JP2012131705A - Group iii nitride semiconductor and substrate for growing group iii nitride semiconductor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor where the dislocation density of the group III nitride semiconductor is further reduced and at the same time the time required for chemical lift-off is greatly shortened when a self-supporting substrate and a semiconductor element are produced.SOLUTION: The group III nitride semiconductor includes a pattern mask with a striped opening on an AlN template substrate where an AlN single crystal layer or a group III nitride single crystal layer including Al is formed at a thickness of 0.005 μm or more and 10 μm or less on the substrate, an AlN template substrate which is a nitrided sapphire substrate or an AlN single crystal substrate, a metal nitride layer formed in the opening and a group III nitride semiconductor layer being formed on the metal nitride layer, wherein the group III nitride semiconductor layer is a continuous film by ELO growth (epitaxial lateral overgrowth) where the metal nitride layer is a nucleus.

Description

  The present invention relates to a group III nitride semiconductor and a group III nitride semiconductor growth substrate. More specifically, the present invention relates to a method for reducing the dislocation density of a group III nitride semiconductor, an efficient method for separating a grown crystal layer from a base substrate, and a free-standing substrate or semiconductor device.

  Group III nitride semiconductors have been put to practical use as materials for manufacturing optical devices such as light-emitting devices and electronic devices, and are attracting attention for applications in areas that could not be covered by conventional semiconductor materials. .

In manufacturing these devices, a group III nitride semiconductor layer is usually epitaxially grown on a substrate crystal. In the case of Si, GaAs, and the like, a wafer having a large diameter and a low defect density is industrially manufactured as the substrate crystal, and a lattice-matched device is manufactured. However, in the case of a group III nitride semiconductor, since there is no high-quality and inexpensive homoepitaxial substrate, a different type substrate having a different lattice constant or thermal expansion coefficient, such as a sapphire substrate, must be substituted. Therefore, a dislocation density of about 10 ^{9 to} 10 ¹⁰ / cm ² is usually introduced into the group III nitride semiconductor crystal grown on the sapphire substrate.

  In the case of a blue LED (Light Emitting Diode), high-efficiency light emission is realized specifically even under the high dislocation density, but in this case, the composition fluctuation of In in the light-emitting layer is fortunate. It turns out. However, a blue-violet laser having a light emission wavelength of 405 nm used as a light source for next-generation DVDs is operated with a current injection density that is orders of magnitude higher than that of the LED. In addition, there is a problem of deterioration of life in which the luminous efficiency is rapidly reduced. In addition, in the light emitting element in the ultraviolet region, the amount of In added is limited due to the mixed crystal composition, and the problem of efficiency and life reduction due to dislocation that becomes a non-emission center occurs in the short wavelength element. Furthermore, even in bipolar electronic device elements, the presence of dislocations causes problems such as an increase in leakage current and deterioration in element characteristics. Therefore, reduction of the dislocation density has become a major issue (Non-Patent Document 1).

  On the other hand, in order to improve the characteristics of the various devices, for example, to increase output, it is necessary to improve heat dissipation. In particular, it will be an important issue in the future for LEDs and high-frequency / high-power devices for lighting and car headlamps. That is, it is necessary to efficiently dissipate the generated heat while improving the efficiency in the operating part and reducing the amount of heat generated. For the former, crystal defects are reduced and the device structure is optimized. For the latter, the device structure is also optimized, the substrate is thinned by grinding, and the crystal layer is separated from the low thermal conductivity substrate to conduct high heat. There are measures such as switching to a more efficient substrate, or using a substrate with high thermal conductivity.

  Typical thermal conductivity of a semiconductor substrate material at room temperature is 150 W / mK (Si), 50 W / mK (GaAs), 42 W / mK (sapphire), 450 W / mK (SiC), and usually a group III Since a sapphire substrate used as a nitride semiconductor has low thermal conductivity, a method of separating a crystal layer grown from a sapphire substrate by a laser lift-off method has been proposed as the above-mentioned countermeasure. Moreover, if GaN (230 W / mK) or AlN (330 W / mK) having a good thermal conductivity can be used as a substrate, it is expected to be advantageous in terms of heat dissipation as well as the effect of reducing crystal defects. There is a problem that a high-quality and inexpensive substrate does not exist (Non-Patent Documents 2 and 3).

Regarding the reduction of the dislocation density of the group III nitride semiconductor crystal grown on the sapphire substrate, improvement of the group III nitride buffer layer, penetration from the underlying substrate by lateral growth on the insulating film called ELO (Epitaxial Lateral Overflow) Dislocation propagation suppression, group III nitride seed layer is arranged on the top of the convex part of the concavo-convex processed substrate called PENDEO epitaxy method, and the growth of the hollow from the side in the lateral direction suppresses the propagation of threading dislocation from the base substrate. Proposed. Further, in GaN, dislocations disappear due to the reaction between dislocations as the crystal layer progresses, and the dislocation density decreases. Therefore, HVPE (Hideride Vapor) capable of high-speed epitaxy.
A thick film crystal having a low dislocation density has been developed by the Phase Epitaxy method. Since the dislocation density can be reduced to the order of 10 ^{7 to} 10 ⁶ / cm ² when grown to a thickness of about several hundred μm to 1 mm, development and manufacture are made especially for the use of free-standing substrates and template substrates. However, in order to obtain a self-supporting substrate, the GaN is decomposed and separated from the substrate by the laser lift-off method described above, that is, GaN at the interface from the back side of the sapphire substrate is irradiated with a nanosecond pulse of 248 nm excimer laser. In this case, the entire surface cannot be completely peeled off or cracks are generated, so that there are many problems on the yield surface, which is a cause of cost increase (Non-Patent Documents 4 to 7).

  By the way, when the present inventors formed a metal nitride buffer layer of a specific metal type on a sapphire substrate under a predetermined condition, the crystallinity of the GaN single crystal layer grown on the metal nitride buffer layer is the conventional AlN or GaN low-temperature buffer. Has a crystallinity equal to or better than that of GaN on a sapphire substrate using a layer, and the metal nitride buffer layer is selectively chemically etched to separate the underlying sapphire substrate and the growth layer, so that A technique capable of manufacturing a substrate or an individual semiconductor chip is proposed (Patent Documents 1 and 2).

  As described above, the inventors have found a technique that allows selective etching on a sapphire substrate and can be used for the growth of a group III nitride semiconductor crystal, but further reduces crystal defects and separates the underlying substrate and the growth layer by selective etching. Reduction of the time taken for is a problem. That is, regarding crystal defects, further improvement in reliability such as device characteristics and lifetime is desired, and it is necessary to continuously reduce the dislocation density. As shown in Patent Document 1 and Patent Document 2, when the metal nitride buffer layer on the sapphire substrate is CrN, there is an optimum value for crystallinity when the thickness of the metal Cr is 15 to 30 nm, up to about 45 nm. Although a single crystal layer of GaN can be obtained, if it exceeds 50 nm, the crystallinity of the CrN layer after the nitriding treatment is greatly lowered, and the GaN grown thereon becomes mosaic or polycrystalline.

  The time required for chemical lift-off is advantageous when the CrN film thickness is thicker, but this is a trade-off with ensuring crystallinity, and is a problem to be improved particularly in increasing the area of a free-standing substrate. Although the etching rate is affected by the liquid composition, liquid temperature, stirring conditions, etc., it is difficult to express numerical values in general. However, when the Cr film thickness is 20 nm, a chip of 300 μm square is about 10 to 15 minutes, 2 inches. It takes several tens of hours to chemically lift off a self-supporting substrate having a diameter. Although the former is in an allowable range as a process time, it is desired to further improve the productivity by reducing the lead time, and the latter requires a significant time reduction / improvement. When the area is increased, the in-plane distribution of the Cr film thickness tends to increase. Therefore, in order to avoid partial pit generation and polycrystallization, the Cr thickness condition is considered in consideration of the process margin. Is a safety side (center of appropriate conditions or slightly thinner), and it is a problem to maintain and improve crystallinity even with a thicker metal nitride buffer layer. . For applications where the compositional fluctuation of In is fortunate, such as blue LEDs, and the decrease in light emission efficiency due to dislocations can be largely contained, the releasability rather than the dislocation density is regarded as the most important factor if the crystallinity is not inferior. However, there is a big problem that the GaN layer becomes polycrystalline when the Cr layer is thick on the sapphire substrate. Therefore, the present inventors investigated a metal nitride buffer layer on AlN and obtained a result exceeding expectations (Japanese Patent Application No. 2007-221774).

PCT / JP / 2006/306958 PCT / JP / 2006/3259592

Supervised by Kiyoshi Takahashi, edited by Fumio Hasegawa and Akihiko Yoshikawa, “Wide Gap Semiconductor Optical and Electronic Devices”, Morikita Publishing (March 2006) W. S. Wong et al. “Damage-free separation of GaN thin films from sapphire substrates” Appl. Phys. Lett. 72 (1998) P.599 “IMEC improve GaN HEMTs” Compound Semiconductor, October (2005) p. 16 Amano et al., “Effects and Mechanisms of Low Temperature Deposited Layers on Group III Nitride Semiconductor Growth on Sapphire Substrates”, Applied Physics 68 (1999), p. 768 A. Sakai et al. “Defect structure in selective growth GaN films with low threading dislocation density” Appl. Phys. Lett. 71 (1997) p. 2259 K. Linthicum et al. “Pendeoepitaxy of gallium nitride thin films” Appl. Phys. Lett. 75 (1999) p. 196 S. K. Mathis et al., “Modeling of threading dislocation in growing GaN layer”, J. Am. Crystal Growth 231 (2001) P.M. 371

  An object of the present invention is to provide a method for forming a group III nitride semiconductor on a substrate having AlN via a metal nitride buffer layer, and at the same time, further reduce the dislocation density of the group III nitride semiconductor and manufacture a self-supporting substrate. It is an object of the present invention to provide a group III nitride semiconductor capable of significantly reducing the time required for chemical lift-off at the time of manufacturing a semiconductor device.

  According to the present invention, an AlN template substrate in which an AlN single crystal layer or a group III nitride single crystal layer containing Al is formed on a substrate with a thickness of 0.005 μm or more and 10 μm or less, or an AlN template substrate obtained by nitriding a sapphire substrate, Alternatively, an AlN single crystal substrate has a pattern mask having a stripe-shaped opening, a metal nitride layer formed in the opening, and a group III nitride semiconductor layer formed on the metal nitride layer. The group III nitride semiconductor layer is a group III nitride semiconductor which is a continuous film formed by ELO growth using the metal nitride layer as a nucleus.

  In the group III nitride semiconductor, the stripe-shaped opening may be parallel to a <1-100> direction of the AlN template substrate or the AlN single crystal substrate. A metal layer may be provided between the AlN template substrate or the AlN single crystal substrate and the pattern mask.

  Moreover, you may have a location where the continuous film of the said group III nitride semiconductor layer is not formed in a part on said pattern mask.

  According to another aspect of the present invention, there is provided an AlN template substrate or a sapphire substrate in which an AlN single crystal layer or a group III nitride single crystal layer containing Al is formed on a substrate with a thickness of 0.005 μm to 10 μm. A group III nitride comprising a patterned mask having a stripe-shaped opening on a nitrided AlN template substrate or an AlN single crystal substrate, and a metal nitride layer formed in the opening. A substrate for semiconductor growth is provided.

  The inventors of the present invention have found that the above group III nitride semiconductor can give results exceeding expectations.

Taking the case where the first metal is Cr as an example,
(1) When GaN is grown on AlN (0001) by a hydride vapor phase epitaxy (HVPE) method without using a pattern mask, sufficient crystallinity is obtained even when the Cr film thickness is increased to about 300 nm, for example, below a predetermined level. It was possible to grow a GaN layer having a full width at half maximum of the X-ray diffraction peak. In the present invention, by further carrying out ELO growth, the crystallinity improvement effect of one to two digits, that is, the dislocation density reduction effect, was obtained as compared with the case where no pattern mask was used.
(2) Since the thickness of the first metal for obtaining the same crystallinity can be increased compared with the case where no pattern mask is used, for example, the first metal is on AlN (0001). When Cr is 500 nm, Ti is 20 nm as the second metal, and the thickness of SiO _{2 as} the pattern mask is 500 nm, even if the thickness of the layer capable of chemical etching is convenient 1020 nm, the maintenance and improvement of crystallinity and chemical etching are achieved. It has become possible to achieve a significant reduction in the required time.
(3) By devising the shape and dimensions of the pattern mask, a continuous film is formed in the element by ELO growth to reduce the dislocation density, while leaving a portion where the mask is not completely covered between the elements even after the ELO growth. Since the supply path for chemical etching is automatically secured, a process such as element isolation groove processing after the growth becomes unnecessary, and productivity can be improved.
(4) By forming a second metal on the first metal that can be removed at the same time as the mask pattern is formed, the first metal is deposited when the mask material, for example, SiO ₂ is formed by plasma CVD. The formation of a strong oxide film on the surface is prevented, the nitriding treatment of the first metal is uniformly performed, and when the group III nitride layer is subsequently formed using the first metal nitride as a nucleus, it is uniform. Growth is possible.

  Using an AlN template, a sapphire substrate with nitrided surface, or an AlN single crystal substrate, a low dislocation density group III compound semiconductor can be mass-produced, and chemical lift-off properties are further improved, and a low dislocation density group III nitride A semiconductor free-standing substrate and a semiconductor element can be obtained.

  According to the present invention, in a method of forming a group III nitride semiconductor on a substrate having AlN via a metal nitride buffer layer, the dislocation density of the group III nitride semiconductor is further reduced, and at the same time, the self-standing substrate manufacturing is performed. There is provided a group III nitride semiconductor capable of significantly reducing the time required for chemical lift-off at the time of manufacturing a semiconductor device.

It is explanatory drawing which shows the example of the manufacturing process of this invention. On the Cr layer is a graph showing an XPS spectrum of the Cr layer surface after dissolving and removing the SiO ₂ film of the sample was deposited SiO ₂ film with buffered hydrofluoric acid in the plasma CVD method. The XPS spectrum of the Cr layer surface after dissolving and removing the SiO ₂ and Ti layers of the sample in which the SiO ₂ film was formed by plasma CVD on the Cr layer continuously on the Cr layer was formed with buffered hydrofluoric acid. It is a graph to show. The XPS spectrum of the Cr layer surface after dissolving and removing the SiO ₂ and Ti layers of the sample in which the SiO ₂ film was formed by plasma CVD on the Cr layer continuously on the Cr layer was deposited with buffered hydrofluoric acid. It is a graph to show. With and without SiO ₂ film thickness and a second metal layer (Ti), it is an explanatory view showing the effect on the facet formation state in the GaN initial growth stage. It is explanatory drawing of the growth process from facet growth to V groove | channel row | line | column pit embedding, and planarization growth. (A) It is a graph which shows the comparison with and without a pattern mask of the relationship between the average film thickness of Cr layer, and the half value width of the XRD (0002) diffraction peak of a GaN layer. (B) It is a graph which shows the comparison with and without a pattern mask of the relationship between the average film thickness of Cr layer, and the half value width of the XRD (11-20) diffraction peak of a GaN layer. (A) It is a graph which shows the dependence with and without a pattern mask about the half value width of the (0002) diffraction peak of a base AlN layer, and the half value width of the (0002) diffraction peak of a GaN layer. (B) It is a graph which shows the dependence with and without a pattern mask about the half value width of the (11-20) diffraction peak of a base AlN layer, and the half value width of the (11-20) diffraction peak of a GaN layer. It is explanatory drawing, such as an azimuth | direction and a dimension, about an element formation area and an element isolation mask.

  Hereinafter, an embodiment of the present invention will be described with reference to FIG. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

  A metal nitride is used as a buffer layer for forming a group III nitride semiconductor layer, a manufacturing process in the case of manufacturing a group III nitride semiconductor layer and an element by ELO growth will be briefly shown, and then the best embodiment will be described. Note that here, the semiconductor layer includes a single layer or a stacked state.

First, a first metal layer 3 having a predetermined thickness is formed on a substrate 1 having a growth base layer 2 by sputtering or vacuum vapor deposition, and then a second metal layer 4 is continuously formed. Continuous film formation with thickness. Here, the continuous film formation is to have a plurality of sputtering targets or evaporation sources in the film forming apparatus, and when the film formation of the first metal layer 3 is completed and the second metal layer 4 is formed, This means that the film is continuously formed without opening to the atmosphere. Thereby, the surface of the first metal layer 3 is protected by the second metal layer 4 in a state where a natural oxide film is not formed. Next, the SiO ₂ film 5 is formed by plasma CVD using, for example, silane gas as the Si source and N ₂ O gas as the oxygen source at a substrate temperature of 350 ° C.

Next, a photoresist is spin-coated on the SiO ₂ film 5, resist pre-baking, exposure and development are performed to form a resist pattern 6, and an SiO ₂ mask material (SiO ₂ film 5) exposed to the opening 6 ′ is formed. Etching with a hydrofluoric acid-containing etchant, for example, buffered hydrofluoric acid or dilute hydrofluoric acid. When the etching of the SiO ₂ film 5 is completed, the second metal layer 4 is also etched to expose the surface of the first metal layer 3 in the opening 6 ′. Finally, by removing and cleaning the photoresist (resist pattern 6), a substrate on which a mask pattern film for ELO growth is formed is prepared.

  Next, it is introduced into a group III nitride semiconductor growth apparatus, for example, an HVPE growth apparatus, and temperature rise is started in a high purity hydrogen or nitrogen gas atmosphere. Start supplying nitrogen hydride such as ammonia gas or hydrazine gas from a predetermined temperature, that is, near the temperature at which the metal used starts to cause a nitriding reaction, further raise the temperature to the nitriding temperature, and perform nitriding for a predetermined time at that temperature, The first metal layer 3 exposed in the mask opening is converted into a metal nitride buffer layer 7 for forming a group III nitride semiconductor layer. Usually, when forming a group III nitride semiconductor layer 7 on a sapphire substrate, SiC substrate, or Si substrate, a low temperature buffer layer of a group III nitride semiconductor is formed, but this method is not necessary.

Next, the growth temperature of the group III nitride semiconductor is adjusted, the supply of the group III source gas is started, and the film formation is started. In the initial stage of growth, the group III nitride semiconductor layer 8 is selectively grown using the first metal nitride layer 7 (metal nitride buffer layer) as a nucleus. Here, the selective growth means that the group III nitride semiconductor layer 8 is grown on the first metal nitride layer 7 without being grown on the mask portion 5 such as SiO ₂ . If the growth layer (Group III nitride semiconductor layer) grows beyond the thickness of the mask film, the growth temperature / flow rate ratio is set to facet formation, and the dislocation propagating over the mask opening is terminated at the facet side. Alternatively, the dislocation density is reduced by bending. The SiO _{2 as a} pattern mask is also grown in the lateral direction while maintaining the facet plane, and if the grown crystals are combined, the deposition temperature and supply gas are set so that the V-groove and pit are buried and flat growth occurs. The seed / flow rate ratio is appropriately changed, and cooling is started when the target film formation is completed. When the temperature reaches a predetermined temperature during cooling, the supply of ammonia gas or hydrazine gas is stopped, cooling is performed in a high-purity hydrogen or nitrogen gas atmosphere, and the growth process is terminated.

As an example of the manufacture of a group III nitride semiconductor and a group III nitride semiconductor free-standing substrate or semiconductor element, a substrate 1 in which an AlN single crystal layer is provided as an underlayer 2 on a sapphire substrate (Al ₂ O ₃ ) ( Hereinafter, an AlN template substrate) was used. In addition to the sapphire substrate, a substrate that can be applied according to a desired semiconductor, such as a SiC substrate or a Si substrate, is used, and a substrate in which an AlN single crystal layer is provided as a base layer 2 on the SiC substrate, the Si substrate, or the like. It can be used as an AlN template substrate. Further, an AlN single crystal substrate may be used (hereinafter also referred to as a base substrate). Alternatively, a substrate obtained by nitriding the surface of the sapphire substrate and converting it to AlN may be used. In addition to AlN, as a layer having a small lattice mismatch ratio with a group III nitride semiconductor, a group III nitride (Alrich-) of AlGaN or a group III main element of Al (containing 50% or more of Al) is used. It is also possible to select BAlGaInN). In this example, an AlN template substrate in which an AlN single crystal layer was formed to a thickness of about 1 μm on the sapphire (0001) surface by MOCVD was used. The half width of XRD of the AlN template substrate was about 100 sec for (0002) diffraction, and the half width of (11-20) diffraction was about 1200 sec to 1400 sec.

  As the predetermined first metal layer 3 formed on the AlN template substrate, metal nitridation for growing the group III nitride semiconductor layer 8 at the stage of nitridation by nitrogen hydride such as ammonia gas or hydrazine gas is used. It is necessary to satisfy the conditions as the physical buffer layer 7. Specifically, at the stage of nitriding, it is in a state of being aligned in a predetermined direction rather than in a random direction with respect to the direction perpendicular to the surface of the underlying layer 2 or the underlying substrate, and twisted in the plane of the underlying layer or the underlying substrate. It is necessary that there is no situation. In other words, it is meaningless to simply align in the direction perpendicular to the base, and the in-plane domain rotation fluctuation must be suppressed. On the AlN (0001) c plane, the metal nitride has a rock salt type or hexagonal crystal structure, and the direction perpendicular to the base is the <111> direction in the former, the <0001> direction in the latter, and with respect to the plane of the base In the former case, the base of the triangle must be parallel to the a-axis direction in the AlN (0001) plane. Preferably, the atomic spacing is close to the lattice constant of the a axis in the AlN (0001) plane, and furthermore, it has heat resistance at the growth temperature of the group III nitride semiconductor, and is less likely to cause mutual diffusion or alloying. The thermal expansion coefficient is preferably close. The above are the requirements necessary for improving the crystallinity of the group III nitride semiconductor crystal.

  Further, when the underlying layer 2 or the underlying substrate and the group III nitride semiconductor layer 8 are separated by the chemical lift-off method, the group III nitride semiconductor layer and the bonding metal or alloy used for transfer are not damaged. The existence of a chemical solution for selectively chemically etching the metal nitride layer 7 that is a buffer layer is also an important selection requirement. At the same time, it is also important that the etching solution is not etched or has a sufficient etching selectivity when forming the pattern mask.

  As the first metal layer 3 that satisfies them, Cr, Sc, V, and Nb are preferable. At least one of these is selected and used in the form of a single layer, a multilayer film, an alloy, or the like. These metals have a rock salt type crystal structure after nitriding. Most preferred is Cr, and CrN can be selectively etched without damaging the group III nitride semiconductor 8, Au—Sn alloy solder, and Au—Au junctions with perchloric acid or nitric acid and 2 ceric ammonium nitrate solution. It is. Since ScN, VN, and NbN have a slow etching rate of only hydrofluoric acid, a mixed solution to which nitric acid is added may be used.

The second metal layer 4 formed on the first metal layer 3 needs to be etched with an etching solution or the like when forming a pattern mask with a mask material 5 such as SiO ₂ and is grown. It is a requirement that heat resistance at the time temperature is sufficient, diffusion is difficult to occur, and adhesion between the first metal layer 3 and the mask material 5 is excellent, and Ti, Hf, Zr are good, At least one of these is selected and used in the form of a single layer, a multilayer film, an alloy film, or the like. Any metal can be completely removed with buffered hydrofluoric acid or diluted hydrofluoric acid solution used for chemically etching SiO ₂ or the like.

  As a method for forming the first metal layer 3 and the second metal layer 4 on an AlN template substrate (or a substrate obtained by nitriding the surface of a sapphire substrate and converting it to an AlN layer, or an AlN single crystal substrate), sputtering is used. Method or vacuum evaporation method is used. The first metal layer is formed in a predetermined average thickness, that is, in the range of 4 nm to 500 nm. This is because when the average film thickness is preferably 30 nm to 500 nm, the time required for chemical lift-off can be shortened. When the average film thickness is less than 4 nm, the exposure ratio of the underlying AlN surface is high after the nitriding treatment, and growth starts from both the AlN underlayer 2 and the metal nitride microcrystals at the start of the growth of the group III nitride semiconductor layer. As a result, the effect of improving the crystallinity is small, and the direct contact ratio between the group III nitride semiconductor layer 8 and the AlN underlayer 2 is increased. When chemical lift-off is performed later, it is difficult for the etchant to penetrate and separation becomes difficult. Because. Further, when the thickness exceeds 500 nm, the nitriding time becomes longer, the productivity is remarkably lowered, and the driving force for solid phase epitaxial growth from the AlN underlayer 2 is lowered. This is because the crystallinity of the group III nitride semiconductor layer 8 formed on the III nitride semiconductor layer 8 formed on the III nitride semiconductor layer 8 is not sufficient. .

By providing the second metal layer 4 continuously to the first metal layer 3, the oxidation of the first metal layer 3 in the atmosphere and the oxidation in the plasma CVD are suppressed, and then partially exposed by etching. Then, the surface of the first metal layer 3 that is nitrided and becomes the growth surface of the group III nitride semiconductor layer 8 can be kept clean. The effect of inserting the second metal layer 4 between the first metal layer 3 and the SiO ₂ mask material 5 is shown in FIGS. FIG. 2 shows X-ray photoelectron spectroscopy of the oxidation state of the Cr surface after the SiO ₂ mask material 5 is deposited to 100 nm by direct plasma CVD on the Cr layer as the first metal layer 3 and then the SiO ₂ film is removed with buffered hydrofluoric acid ( It is the result evaluated by the XPS method. Shown here are Cr2p3 / 2 and Cr2p1 / 2 spectra, each consisting of two peaks. The high energy side shows the state of metal Cr, and the low energy side shows the state of oxidized Cr. FIG. 3 shows a sample in which a SiO ₂ film is similarly formed by plasma CVD after forming a Ti layer of 10 nm continuously as a second metal layer 4 on the Cr layer. It is a XPS spectrum of the Cr surface at the time of removing ₂ and Ti layer. From these comparisons, it can be seen that the latter can largely avoid oxidation when forming the SiO ₂ film by the plasma CVD method.

FIG. 4 shows the results when the thickness of the Ti layer is 2 nm among the conditions shown in FIG. 3. Although the degree of oxidation on the Cr surface is less than that when the SiO ₂ film is formed directly on the Cr surface, oxidation is avoided. I understand that I couldn't. Therefore, the second metal layer is formed in a predetermined average thickness, that is, in the range of 5 nm to 20 nm. As shown in FIGS. 2 to 4, when the thickness is less than 5 nm, the first metal surface is partially exposed, or there is a portion where the film thickness is locally thin. Therefore, plasma CVD is performed on the second metal layer. This is because there is a high risk of oxidizing the first metal surface when a mask material such as SiO _{2 is formed by the} method. When the average film thickness exceeds 20 nm, when the second metal layer is etched, an undercut of the mask material such as SiO ₂ under the resist and an undercut of the second metal layer itself under the SiO ₂ This is because the dimensional accuracy deteriorates and the pattern mask peels off.

After the first metal layer 3 and the second metal layer 4 are formed, the SiO ₂ film 5 is formed to a thickness of 100 nm to 1000 nm at a substrate temperature of about 350 ° C. by plasma CVD. If the thickness is less than 100 nm, fine pinholes remain, the metal layer under the mask locally undergoes nitriding reaction, volume expansion, deformation of the mask material, cracks, etc. In addition to this, when the growth layer and the base substrate are separated, that is, when the chemical lift-off occurs, the permeability of the etching solution from the side surface is reduced, and the effect of shortening the etching time is diminished. When the film thickness of SiO ₂ exceeds 1000 nm, the undercut under the resist becomes large due to wet etching when forming the pattern mask. When the pattern interval is narrow, for example, 2 μm, the SiO ₂ immediately under the resist is etched, and the resist is peeled off during the etching, making it difficult to form a uniform mask pattern over the entire surface of the substrate. It is likely to occur. Also if SiO ₂ film is thick, the supply of the reaction gas source gas into the openings becomes uneven, since the group III nitride semiconductor layer at the initial growth stage there is a case where uniformly difficult to grow, the SiO ₂ The film thickness is preferably in the range of 100 nm to 500 nm.

In addition, at the stage of starting the growth of the group III nitride semiconductor layer 8, it is necessary to have the selectivity that the nitride 7 of the first metal layer is used as a nucleus and the growth does not start on the mask, and heat resistance at the growth temperature is required. gender, (simultaneous removal of the second metal layer) patterning ease of photolithographically like, SiO ₂ or SiON is good for overall surface.

After forming SiO ₂ as the mask material 5, a photoresist is spin-coated, and after pre-baking, exposure, development, and rinsing are performed to form a pattern mask 6 having an opening 6 ′ in the resist.

Next, the SiO ₂ and the second metal layer 4 exposed to the opening 6 ′ are removed by etching with buffered hydrofluoric acid or a diluted hydrofluoric acid solution. Next, the resist is removed using acetone, a resist stripping solution, etc., and cleaning and drying are performed to form a SiO ₂ pattern mask.

The substrate on which the SiO ₂ pattern mask is formed and the first metal layer 3 is exposed in the opening of the mask is introduced into a group III nitride semiconductor layer growth apparatus, and high purity hydrogen or nitrogen or He, Ar gas is used. The temperature is raised in a simple substance or mixed gas atmosphere, and supply of, for example, high-purity ammonia gas is started at a temperature slightly lower than the temperature at which the first metal layer 3 starts nitriding. The ammonia gas is supplied in the form of a mixed gas using the gas as a carrier gas. The maximum temperature of nitriding is defined as the nitriding temperature, and the holding time at that temperature is defined as the nitriding time.

  Since the nitriding reaction is slow when the temperature is low, it is necessary to take a long processing time. When the temperature is high, the time is short. In addition, it is necessary to control the crystal structure, orientation, and in-plane domain rotation fluctuation suppressed state as a metal nitride buffer by the rearrangement of atoms by the driving force of solid phase epitaxial growth from the underlayer 2. Hereinafter, referring to an example of the HVPE method, when the diameter of the reaction tube is about φ80 mm, the flow rate of ammonia gas is about 1000 sccm. When the first metal layer 3 is Cr, the supply of ammonia gas is started at a temperature of about 600 ° C. nitriding temperature. The temperature rising rate of the furnace is about 30 ° C./minute, the nitriding temperature is preferably 900 ° C. or more and 1200 ° C. or less, and the nitriding time is preferably 1 minute or more and 90 minutes or less. The nitriding time may be adjusted within this range as appropriate in a short time when the film thickness of the metal is thin and long when it is thick. When AlN is the underlayer 2, since the driving force for solid phase epitaxial growth is larger than that of the sapphire substrate, good results can be obtained in a short time at a temperature lower than the nitriding temperature and nitriding time on the sapphire substrate.

After nitriding the first metal layer 3 exposed in the pattern mask opening, the substrate temperature is adjusted to a temperature at which the group III nitride semiconductor initial growth layer is grown. When the group III nitride semiconductor layer 8 is GaN, the temperature is adjusted to 900 ° C. In this case, the flow rate of the carrier gas is appropriately changed in order to set the V / III ratio and the growth rate. When preparation for starting the growth is completed, a hydrochloric acid gas is started to flow along with the carrier gas from the upstream side of the metal Ga heated to 850 ° C. to generate a GaCl-containing source gas. The generated GaCl-containing source gas is mixed with an ammonia mixed gas in the vicinity of the substrate, supplied to the substrate surface, and crystal growth of GaN is started with the metal nitride layer 7 of the first metal layer exposed at the opening as a nucleus. Let At this time, so-called selective growth is performed in which no growth of GaN occurs on the SiO ₂ film 5. The flow rate of hydrochloric acid gas is 80 sccm, and growth is performed for 5 minutes, for example. Next, in order to perform facet growth, the substrate temperature is raised to 1020 to 1040 ° C., for example, for 10 minutes. In this case, while maintaining the facet surface, if the lateral growth is performed so as to cover the SiO ₂ film 5 which is the mask material and the GaN crystal is united at the center of the mask, the V groove and pits are buried. In order to planarize the substrate, for example, the substrate temperature is further increased to about 1060 to 1080 ° C. and the growth is continued. At that time, it is preferable to appropriately adjust the gas flow rate and the V / III ratio. When the desired growth thickness is reached, the supply of hydrochloric acid gas is stopped and cooling is started. The supply of ammonia gas is stopped when the substrate temperature reaches 600 ° C. or lower, and cooling is performed in a nitrogen atmosphere. After cooling to a temperature where it can be taken out, the substrate is taken out of the apparatus and the growth is finished.

5, film formation and the case of inserting a second metal layer 4 between the SiO ₂ film 5 according to the first metal layer 3 and the plasma CVD method, an SiO ₂ film 5 directly on the first metal layer 3 In both cases, the comparison of the initial growth process when forming the group III nitride semiconductor layer 8 by changing the film thickness of SiO ₂ is shown. In this case, the first metal layer 3 is Cr, the average thickness is 20 nm, the second metal layer 4 is Ti, the average film thickness is 0, 10, 20 nm, and the SiO ₂ film 5 has a film thickness of 300, 500 nm. The group III nitride semiconductor layer 8 is GaN, and the growth is based on the HVPE method. The pattern mask for ELO growth was striped, and the dimensions of the mask part and the opening part were 10 μm. The stripe direction was parallel to the crystal orientation <1-100> direction of the AlN substrate 2. First, when the SiO ₂ mask thickness is the same, the case where Ti, which is the second metal layer 4, is inserted in comparison with the case where SiO ₂ is directly formed on the Cr, which is the first metal layer 3. It can be seen that the {11-22} facet formation is clearly good. Second, regarding the thickness dependence of SiO ₂ , it can be seen that the facet formation is better in the former when comparing 300 nm and 500 nm. When SiO ₂ is 500 nm, the facet itself is hardly formed when the second metal layer is not inserted, but the facet is formed well when Ti is inserted. As described above, by providing the second metal layer 4, surface oxidation of the first metal layer 3 is avoided, and the crystallinity of the first metal layer after nitriding is improved. It can be seen that the crystallinity of the group III nitride semiconductor layer 8 is improved, and the effect is great.

Next, in facet growth in the initial stage of growth, at the center of the mask, as shown in FIG. 6, the crystals are merged to form a V groove array or pit array, and then the growth temperature is increased or V Crystal growth was performed so as to flatten the outermost surface by changing the / III ratio. The average film thickness of the grown GaN layer was about 30 μm. In order to evaluate the dislocation density of the obtained crystal, etching was performed in hot phosphoric acid at 210 ° C. for 3 minutes, and the pit density corresponding to the dislocation was evaluated, and 1.5 × 10 ⁷ / cm ² was obtained. The result to say was obtained. The value was found to have an effect of reducing the dislocation density close to an order of magnitude compared to 1.0 × 10 ⁸ / cm ² which is normally achieved in the case of almost the same GaN thickness. Further, since not only the first metal layer 3 but also the second metal layer 4 and the SiO ₂ layer 5 capable of chemical etching are interposed, chemical etching from the side surface is possible as compared with the case of only the first metal layer 3. Since the liquid can be supplied efficiently, the chemical lift-off time can be greatly shortened.

Next, the thickness of Ti that is the second metal layer 4 is 10 nm, the thickness of the SiO ₂ film 5 is 300 nm, and the average film thickness of Cr that is the first metal layer 3 is 25 nm, 100 nm, 300 nm, and 500 nm. The relationship between the thickness of the layer and the crystallinity of the group III nitride semiconductor layer 8 was examined. The SiO ₂ pattern mask was striped, the mask width and the opening width were 10 μm each, and the <1-100> direction of the underlying AlN (0001) single crystal layer 2 was matched with the stripe direction. The nitriding temperature and nitriding time of the Cr layer were adjusted between 1050 and 1080 ° C. and 3 to 60 minutes according to the film thickness of the Cr layer. The group III nitride semiconductor layer 8 is GaN, and was grown with an average film thickness of 30 μm by the method described above. The crystallinity of the obtained GaN layer was evaluated by the half width (FWHM) of (0002) and (11-20) diffraction peaks of X-ray diffraction (XRD), and compared with the case without a pattern mask. FIG. 7a shows the result of comparison of (0002) diffraction and FIG. 7b shows the result of comparison of (11-20) diffraction. The average film thickness of the Cr layer as the first metal layer 3 has a tendency that the half-value width increases as the film thickness increases in the range of a predetermined film thickness (4 nm) or more, as in the case where there is no pattern mask. Compared with the average film thickness of the same Cr layer, it can be seen that the half-value widths of both diffraction peaks are greatly reduced as compared with the case without the pattern mask. When there was no Cr layer and GaN was formed directly on the AlN underlayer, the half width of the (11-20) diffraction peak was 1364 arcsec, but when there was a Cr layer and no pattern mask, Cr Although the improvement effect was recognized up to the average film thickness of the layer of about 300 nm, the improvement effect was further increased even with the average film thickness of 500 nm when the pattern mask was provided. Although the crystallinity of the metal nitride layer 7 after the nitriding treatment is lowered by increasing the thickness of the Cr layer, the crystallinity improving effect by ELO growth can be exceeded. It is thought to be due to things.

  Whether the emphasis on crystallinity or the emphasis on productivity improvement by shortening the chemical lift-off time depends on the nitride semiconductor to be manufactured, so the average thickness of the first metal layer 3 is suitably in the range of 4 to 500 nm. Set it. If importance is placed on shortening the chemical lift-off time, a thicker thickness may be set.

  Next, the correspondence relationship between the crystallinity of the AlN underlayer to be used and the crystallinity of the formed group III nitride crystal layer 8 was examined, and compared with the case where there was no mask pattern. For comparison, the AlN underlayer used is an AlN (0001) template substrate formed on the sapphire substrate (0001) surface and a substrate on which the surface of the sapphire substrate is nitrided to form an AlN layer. The thickness of the AlN layer was in the range of 0.005 to 12.5 μm, and the XRD half width of the AlN layer was in the range of 50 to 600 sec for (0002) diffraction and in the range of 550 to 3500 sec for (11-20) diffraction. .

After forming a Cr film having an average thickness of 35 nm as the first metal layer 3 on the substrate 1 having AlN as the underlayer 2 by sputtering, Ti having an average thickness of 10 nm is continuously formed as the second metal layer 4. Filmed. Next, a 300 nm thick SiO ₂ film mask 5 was formed by plasma CVD, and then resist spin coating, exposure, development, and rinse cleaning were performed to form a resist pattern 6. Next, the SiO ₂ portion 5 exposed in the opening and the Ti layer, which is the second metal layer 4 immediately below, are removed by etching with buffered hydrofluoric acid or dilute hydrofluoric acid solution, and the SiO ₂ mask opening is covered with the first metal layer 3. A pattern mask forming substrate in which the surface of a certain Cr layer was exposed was prepared. The width of the mask part and the width of the opening part were each 10 μm, and a stripe pattern parallel to the crystal orientation <1-100> of the underlying AlN (0001) substrate was formed. Thereafter, the metal nitride layer 7 was formed under the growth conditions described above, and a GaN layer was formed to a thickness of about 30 μm as the group III nitride crystal layer 8.

  The crystallinity of the obtained GaN layer was evaluated by the half width of (0002) and (11-20) XRD diffraction peaks. FIG. 8a shows the relationship of the half-value width of the GaN layer to the half-value width of the (0002) diffraction peak of the underlying AlN layer, which is an index of c-axis fluctuation. As the half width of the used AlN underlayer increases, the half width of the grown GaN layer tends to increase. In order to reduce the fluctuation of the C axis, it is preferable to use an AlN undersubstrate having a narrow half width. However, in the case where there is a mask pattern, it was possible to make it narrower than the half width of the AlN underlayer used. On the other hand, FIG. 8b shows the result of (11-20) diffraction, which is an index of in-plane domain rotation. The Cr nitride layer relaxes the rotation domain of the AlN underlayer, and the rotation of the GaN crystal grown thereon. Domains are greatly reduced. When the mask pattern is used, threading dislocations can be further suppressed as compared with the case where the mask pattern is not used. Therefore, when the half width of the used AlN underlayer is up to 3000 sec, there is no problem in crystallinity in actual semiconductor device manufacturing. I understood. As described above, the AlN underlayer used has a thickness of 0.005 μm to 10 μm, and the AlN layer has X-ray diffraction half widths of (0002) and (11-20) of 500 sec and 3000 sec, respectively. The crystallinity of the group III nitride semiconductor layer using the mask can be improved to a sufficiently usable state at a practical level.

  When the pattern mask is used, the crystallinity can be greatly improved as described above. Therefore, there is no problem when the AlN layer is as thin as 0.005 μm, but satisfies the above half width or less. Can be used. However, when the thickness of the AlN layer exceeds 10 μm, the productivity of manufacturing the AlN template is lowered, so that the thickness is preferably 10 μm or less.

  Further, as an application of the present invention, in the element forming part, the element forming part is grown in the lateral direction so as to cover the pattern mask for the purpose of improving the crystallinity, and the crystals are combined to form a continuous flat film. Although the group III nitride semiconductor layer partially covers the pattern mask, if the pattern mask is not covered with a continuous film even after the growth is completed, the crystallinity of each semiconductor element is improved simultaneously. Chemical lift-off in a chip state is possible, and element isolation becomes easy.

  In this case, the distance to cover the mask from the opening varies depending on the facet growth during ELO growth, lateral growth, V groove row / pit embedding, thickness at the end of growth, etc. What is necessary is just to set suitably the dimension of the mask part width | variety of an inner pattern mask, the opening part width | variety, and the mask width dimension of an element isolation part. However, the mask width Ld and the element isolation mask width Ls of the element formation portion must satisfy at least Ld <Ls, and preferably 3Ld ≦ Ls. Further, the stripe direction of the pattern mask of the element forming portion on the AlN (0001) is preferably parallel to the <1-100> direction, and the element side in the case of a square element is parallel to the <1-100> direction. The mask width for element isolation is parallel to <1-100> rather than the mask width Ls <11-20> parallel to <11-20>. It is preferable to increase the mask width Ls <1-100>.

  Hereinafter, a self-standing substrate obtained by separating the group III nitride semiconductor and the group III nitride semiconductor layer described in the above paragraph from the base substrate by chemical etching, a semiconductor element, and the separated group III nitride semiconductor as a self-standing substrate The elements used and examples thereof will be described.

Example 1
An AlN (0001) template on a 2-inch sapphire substrate with an AlN thickness of 1.0 μm, an XRD (0002) diffraction half width of about 100 sec, and a (11-20) diffraction half width of about 1200 to 1400 sec is used. The average thickness of the Cr layer as the first metal layer was 35 nm, and the average thickness of the Ti layer as the second metal layer was continuously formed by a 10 nm sputtering method. Next, after forming a SiO ₂ film to a thickness of 300 nm by plasma CVD, the mask width and the opening width are each 10 μm in the above-described pattern mask process, and a stripe pattern parallel to the <1-100> direction of the underlying AlN layer A mask was formed. Next, it was introduced into an HVPE apparatus, nitriding temperature was 1070 ° C., nitriding time was 5 minutes, and Cr exposed to the opening was nitrided to form a CrN layer. The substrate temperature is lowered to 900 ° C., selective growth of GaN crystal is performed for 5 minutes using CrN exposed in the opening as a nucleus, the growth is interrupted once, the substrate temperature is increased to 1040 ° C., and then facet growth and between masks are performed. The growth of crystal coalescence and embedding start was performed for 10 minutes. Next, the substrate temperature was raised to 1080 ° C., and burying / planarization growth was performed for 15 minutes to conveniently grow a GaN layer of about 30 μm. The obtained crystals had very good crystallinity, with half widths of XRD (0002) and (11-20) diffraction peaks of 78 sec and 90 sec, respectively. After putting a scribe line in a 300 μm square, the Ti layer and the SiO ₂ layer were etched by immersing in buffered hydrofluoric acid at room temperature for 2 minutes. Separately, when the etching progress was examined by changing the etching elapsed time, the Ti layer was dissolved first, so the etching solution was supplied to that part, and the etching in the thickness direction of SiO ₂ progressed not only from the side but also from the middle Therefore, Ti and SiO ₂ are completed within 2 minutes. Next, after cleaning with pure water, the Cr layer located immediately below the mask and the CrN layer in the opening were etched with a ceric ammonium nitrate etching solution at 80 ° C., and the etching was completed in about 4 minutes. Compared with the case where the layers can be separated and there is no pattern mask, the total etching time can be shortened and the crystallinity is greatly improved.

(Example 2)
In contrast to Example 1, the same urban GaN layer was grown under the conditions except that the average thickness of the Cr layer as the first metal layer was 100 nm, the nitriding temperature was 1100 ° C., and the nitriding time was 10 minutes. The half widths of XRD (0002) and (11-20) diffraction peaks of the obtained crystals were good at 110 sec and 190 sec, respectively. Compared to the case of a Cr layer having the same average film thickness and no mask pattern, the XRD half-value width was reduced to half or less, and the crystallinity was greatly improved. When a scribe line was put in a 300 μm square and etching was performed with a ceric ammonium nitrate-based etching solution at 80 ° C., the etching of the Cr layer and the CrN layer was completed in about 3 minutes. Subsequently, when the Ti layer and the SiO ₂ layer were etched with buffered hydrofluoric acid, the etching was completed within 90 seconds.

(Example 3)
Compared to Example 1, the growth process was the same except that the GaN growth thickness was 550 μm. In this case, since the purpose was to obtain a self-supporting substrate, the Cr, CrN, Ti, and SiO ₂ layers were etched from the side surface of the substrate without inserting a scribe line. First, it was immersed in buffered hydrofluoric acid to etch the Ti layer and SiO ₂ . In this etching solution, Ti has a higher etching rate than SiO ₂ and is dissolved in advance, so that SiO ₂ is etched not only from the side but also from the surface where Ti is dissolved. In order to increase the permeability of the etching solution, etching was performed with the aid of ultrasonic waves. As a result, the Ti and SiO ₂ layers on the entire surface of the substrate were completely dissolved in about 4 hours. Next, pure water ultrasonic rinse cleaning was performed to remove the etching solution, and then vacuum heating and drying were once performed for about 10 minutes so that pure water did not remain in the tunnel portion formed by etching of Ti and SiO ₂ . Next, when the Cr and CrN layers were etched with a ceric ammonium nitrate solution at 80 ° C., the dissolution was completely completed in about 1 hour, the underlying AlN template substrate and the GaN growth layer could be separated, and a GaN free-standing substrate could be obtained. It was. As a result of evaluating the crystallinity of the obtained GaN free-standing substrate with the half-value widths of XRD (0002) and (11-20) diffraction peaks, they were very good at 42 sec and 48 sec, respectively.

Example 4
The thickness of the Cr layer was 500 nm, and a Ti layer was continuously formed by a 20 nm sputtering method. Next, a 300 nm film is formed by plasma CVD. Thereafter, the same conditions as in Example 1 were used until the GaN growth was completed. As a result of evaluating the crystallinity of the obtained GaN layer by the half width of the XRD (0002) and (11-20) diffraction peaks, they were 390 sec and 852 sec, respectively. In this case, even if the thickness of the Cr layer is increased, it has sufficient crystallinity for InGaN-based LED applications, and the chemical lift property is good, so that the effect on productivity is great.

(Example 5)
In order to make the group III nitride crystal layer separated for each element at the end of the growth, a pattern mask having an opening just under the element formation region as shown in FIG. 9 was prepared. The element size was 1 mm square, and the element formation region was alternately formed by striped openings and mask parts parallel to the <1-100> direction of the AlN (0001) base. Both the opening width and the mask width Ld were 10 μm. Assuming that a GaN layer is grown to 30 μm by the HVPE method, the element isolation mask width Ls <1-100> in the <1-100> direction of the element and the element isolation mask width in the <11-20> direction of the element The growth test was conducted with Ls <11-20> being 20, 30, and 50 μm. A GaN layer was grown by the method shown in Example 1 except that the pattern mask shape was different. As a result, when the element isolation mask width in the <11-20> direction is 20 μm, the growth film is continuous between adjacent elements. However, when the width is 30 μm, the width of 5 to 10 μm is approximately the center position of the isolation mask. On the top, GaN did not grow and the adjacent elements were separated. Further, even in the case of 50 μm width, there was an ungrown region having a width of 25 μm or more, and the adjacent element was separated. On the other hand, adjacent elements were separated from each other regardless of whether the element isolation mask width in the <1-100> direction was 20, 30, or 50 μm.

(Comparative Example 1)
Compared to Example 1, there was no pattern mask. The AlN (0001) layer on the sapphire substrate having an AlN template with a thickness of 1.0 μm having an XRD (0002) diffraction half width of about 100 sec and an (11-20) diffraction half width of about 1200 sec to 1400 sec was used. . After forming a Cr layer on the AlN (0001) surface with an average layer thickness of 35 nm (that is, without a pattern mask), the CrN layer was introduced into the HVPE apparatus and the nitriding temperature was 1095 ° C. and the nitriding time was 1 minute. The GaN layer was grown to 12 μm. The obtained crystal had a half width of XRD (0002) diffraction of 121 sec and a width of half of (11-20)) of 210 sec, which was inferior to that of Example 1. When a CrN layer was etched with a ceric ammonium nitrate etchant at 80 ° C. with a scribe line in a 300 μm square, the etching was completed and the GaN layer was separated in about 8 minutes. (From Japanese Patent Application No. 2007-221774 including the present inventor).

(Comparative Example 2)
A Cr film was formed on a sapphire (0001) substrate by a sputtering method, a nitriding treatment was performed at a nitriding temperature of 1080 ° C. for 30 minutes, and then GaN was grown. The initial Cr average layer thickness is preferably 10 to 40 nm, and if it is less than 10 nm, the crystallinity is deteriorated, and if it is 50 nm or more, the CrN layer and the GaN grown thereon are mosaic or polycrystalline (the present invention). (From Japanese Patent Application No. 2006-272321). Further, the half width of (0002) diffraction is about 240 sec to 560 sec, and the half width of (10-11) or (11-20) diffraction is about 370 sec to 650 sec. The half width is 6 to 8 times. The upper limit film thickness of the Cr layer from which a single crystal film is obtained is also about 1/10 that of the present application.

As is clear from Examples 1 to 5 and the comparative example, Cr, which is the first metal, and Ti, which is the second metal, are continuously formed on AlN, and the opening of the SiO ₂ pattern mask is formed. This method, which removes the Ti layer during the etching of the portion and nitrides the exposed Cr as a selective growth nucleus at the start of group III growth and performs ELO growth, is significantly more crystalline than the comparative example. Improvements have been made.

  Furthermore, the second metal layer and mask material can also contribute to the separation of the base substrate and the group III nitride crystal by chemical etching, making significant contributions such as improving crystallinity and improving productivity by reducing chemical lift-off time. I am doing.

  While the present invention has been described in detail with specific examples in the embodiments and examples, the present invention is not limited to the above-described embodiments and examples and does not depart from the scope of the present invention. All changes and modifications are possible within the scope. If the purpose of preventing the surface oxidation of the first metal layer is achieved, the first metal layer may be nitrided before the second metal film is formed, or the resist pattern is first applied and lifted off. good. Various orders of manufacturing methods can be studied.

  The present invention can be applied to the manufacture of group III nitride semiconductors.

1 ... substrate 2 ... underlying layer 3 ... first metal layer 4 ... second metal layer 5 ... mask material (mask portion · SiO ₂ film)
6 ... resist pattern 6 '... opening 7 ... metal nitride layer (metal nitride buffer layer)
8 ... Group III nitride semiconductor layer

Claims (5)

On an AlN template substrate formed by forming an AlN single crystal layer or a group III nitride single crystal layer containing Al with a thickness of 0.005 μm to 10 μm on the substrate, or an AlN template substrate obtained by nitriding a sapphire substrate, or an AlN single crystal substrate In addition,
A pattern mask having stripe-shaped openings;
A metal nitride layer formed in the opening;
A group III nitride semiconductor layer formed on the metal nitride layer;
The group III nitride semiconductor layer is a group III nitride semiconductor, which is a continuous film formed by ELO growth using the metal nitride layer as a nucleus. 2. The group III nitride semiconductor according to claim 1, wherein the stripe-shaped opening is parallel to a <1-100> direction of the AlN template substrate or the AlN single crystal substrate. The group III nitride semiconductor according to claim 1 or 2, further comprising a metal layer between the AlN template substrate or the AlN single crystal substrate and the pattern mask. The group III nitride semiconductor according to any one of claims 1 to 3, wherein a part of the pattern mask has a portion where a continuous film of the group III nitride semiconductor layer is not formed. On an AlN template substrate formed by forming an AlN single crystal layer or a group III nitride single crystal layer containing Al with a thickness of 0.005 μm to 10 μm on the substrate, or an AlN template substrate obtained by nitriding a sapphire substrate, or an AlN single crystal substrate In addition,
A pattern mask having stripe-shaped openings;
A group III nitride semiconductor growth substrate comprising: a metal nitride layer formed in the opening.