JP5014217B2 - Group III nitride semiconductor and method of manufacturing the same - Google Patents

Group III nitride semiconductor and method of manufacturing the same Download PDF

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JP5014217B2
JP5014217B2 JP2008070186A JP2008070186A JP5014217B2 JP 5014217 B2 JP5014217 B2 JP 5014217B2 JP 2008070186 A JP2008070186 A JP 2008070186A JP 2008070186 A JP2008070186 A JP 2008070186A JP 5014217 B2 JP5014217 B2 JP 5014217B2
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隆一 鳥羽
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Dowa Electronics Materials Co Ltd
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本発明はIII族窒化物半導体に関する。詳しくは、III族窒化物半導体の転位密度の低減と成長結晶層の下地基板からの効率的な分離方法及び自立基板もしくは半導体素子に関する。   The present invention relates to a group III nitride semiconductor. More specifically, the present invention relates to a method for reducing the dislocation density of a group III nitride semiconductor, an efficient method for separating a grown crystal layer from a base substrate, and a free-standing substrate or semiconductor device.

III族窒化物半導体は、発光デバイスなどの光デバイス及び電子デバイスなどを製造する為の材料として実用化がなされ、さらには従来の半導体材料でカバーできなかった領域への適用などで注目されている。   Group III nitride semiconductors have been put to practical use as materials for manufacturing optical devices such as light-emitting devices and electronic devices, and are attracting attention for applications in areas that could not be covered by conventional semiconductor materials. .

それらのデバイスを製造するにあたり、通常基板結晶上にIII族窒化物半導体層のエピタキシャル成長を実施している。ＳｉやＧａＡｓなどの場合、前記基板結晶として大口径で低欠陥密度なウエハが工業的に製造されており、格子整合系のデバイス製造がなされている。しかしながらIII族窒化物半導体の場合、良質で安価なホモエピタキシャル用基板が存在しない為、通常サファイア基板など格子定数や熱膨張係数などが異なる異種基板で代用せざるをえないのが現状である。その為、サファイア基板上に成長したIII族窒化物半導体結晶には通常転位密度で109乃至1010／cm2程度導入されてしまう。 In manufacturing these devices, a group III nitride semiconductor layer is usually epitaxially grown on a substrate crystal. In the case of Si, GaAs, and the like, a wafer having a large diameter and a low defect density is industrially manufactured as the substrate crystal, and a lattice-matched device is manufactured. However, in the case of a group III nitride semiconductor, since there is no high-quality and inexpensive homoepitaxial substrate, a different type substrate having a different lattice constant or thermal expansion coefficient, such as a sapphire substrate, must be substituted. Therefore, a dislocation density of about 10 9 to 10 10 / cm 2 is usually introduced into the group III nitride semiconductor crystal grown on the sapphire substrate.

青色ＬＥＤ(Light Emitting Diode)の場合、特異的に前記高転位密度な状況下においても高効率な発光が実現されているが、この場合発光層中のＩｎの組成揺らぎが幸いしている事が判明している。しかしながら次世代ＤＶＤ用光源として用いられる発光波長405nmの青紫レーザにおいては前記ＬＥＤに比べ桁違いに高い電流注入密度で動作させる為、発光ストライプ中に存在し非発光中心となる転位が増殖してしまい、発光効率が急速に低下してしまうという寿命劣化問題がある。また、紫外領域の発光素子においては混晶組成の都合上Ｉｎの添加量に制限があり、短波長素子ほど非発光中心となる転位による効率・寿命低下の問題が生じている。さらに、バイポーラ型の電子デバイス素子においても転位の存在でリーク電流の増加や素子特性の劣化などが問題となっている。したがって、転位密度の低減が大きな課題となっている（非特許文献１）。   In the case of a blue LED (Light Emitting Diode), high-efficiency light emission is realized even under the condition of the high dislocation density specifically, but in this case, the composition fluctuation of In in the light-emitting layer is fortunate. It turns out. However, a blue-violet laser with a light emission wavelength of 405 nm used as a light source for next-generation DVDs is operated with a current injection density that is orders of magnitude higher than that of the LED, so that dislocations existing in the light-emitting stripe and serving as non-light-emitting centers proliferate. In addition, there is a problem of deterioration of life in which the luminous efficiency is rapidly reduced. In addition, in the light emitting element in the ultraviolet region, the amount of In added is limited due to the mixed crystal composition, and the problem of efficiency and life reduction due to dislocation that becomes a non-emission center occurs in the short wavelength element. Furthermore, even in bipolar electronic device elements, the presence of dislocations causes problems such as an increase in leakage current and deterioration in element characteristics. Therefore, reduction of the dislocation density has become a major issue (Non-Patent Document 1).

一方、前記各種デバイスの特性向上、例えば高出力化の為には放熱性の向上などをはかる必要がある。特に照明用途や車のヘッドランプ用途のＬＥＤや高周波・ハイパワーデバイスにおいては今後の重要検討課題となる。すなわち動作部での効率を向上し発熱量を低減すると伴に、生じる発熱は効率良く放散させる必要がある。前者に対しては結晶欠陥の低減や素子構造の適正化、後者に対しては同じく素子構造の適正化や下地基板の研削による薄片化、低熱伝導率な基板から結晶層を分離して高熱伝導率な基板に移し変える、あるいは熱伝導率の高い基板を用いるなどの対策がある。   On the other hand, in order to improve the characteristics of the various devices, for example, to increase output, it is necessary to improve heat dissipation. In particular, it will be an important issue in the future for LEDs and high-frequency / high-power devices for lighting and car headlamps. That is, it is necessary to efficiently dissipate the generated heat while improving the efficiency in the operating part and reducing the amount of heat generated. For the former, crystal defects are reduced and the device structure is optimized. For the latter, the device structure is also optimized, the substrate is thinned by grinding, and the crystal layer is separated from the low thermal conductivity substrate to conduct high heat. There are measures such as switching to a more efficient substrate, or using a substrate with high thermal conductivity.

代表的な半導体用基板材料の室温付近での熱伝導率は、150W／mＫ（Ｓｉ）、50W／ｍＫ（ＧａＡｓ）、42W／ｍＫ（サファイア）、450W／ｍＫ（ＳｉＣ）であり、通常III族窒化物半導体として用いるサファイア基板は熱伝導率が低い為、前記の対策としてレーザリフトオフ法でサファイア基板から成長した結晶層を分離する方法が提案されている。また、熱伝導率の良好なＧａＮ（230Ｗ／ｍＫ）やＡｌＮ（330Ｗ／ｍＫ）を基板として用いる事ができれば結晶欠陥の低減効果と同時に放熱上も有利となる事が期待されるが、現状は良質で安価な基板が存在しないという問題がある（非特許文献２、３）。   Typical semiconductor substrate materials have thermal conductivities near room temperature of 150 W / mK (Si), 50 W / mK (GaAs), 42 W / mK (sapphire), and 450 W / mK (SiC), usually a group III Since a sapphire substrate used as a nitride semiconductor has low thermal conductivity, a method of separating a crystal layer grown from a sapphire substrate by a laser lift-off method has been proposed as the above-mentioned countermeasure. In addition, if GaN (230 W / mK) or AlN (330 W / mK) with good thermal conductivity can be used as a substrate, it is expected to be advantageous in terms of heat dissipation as well as the effect of reducing crystal defects. There is a problem that a high-quality and inexpensive substrate does not exist (Non-Patent Documents 2 and 3).

サファイア基板上に成長するIII族窒化物半導体結晶の転位密度の低減については、III族窒化物バッファ層の改良、ＥＬＯ（Epitaxial Lateral Overgtowth)と称する絶縁膜上の横方向成長による下地基板からの貫通転位の伝播抑制、ＰＥＮＤＥＯエピタキシー法と称する凹凸加工基板の凸部上面にIII族窒化物種層を配置し、その側面から中空を横方向に成長することで下地基板からの貫通転位の伝播抑制などが提案されている。また、ＧａＮでは結晶層の進行とともに転位同士の反応によって転位の消滅が起こり転位密度が低下するので、高速エピタキシーが可能なＨＶＰＥ（Ｈｉｄｒｉｄｅ
Ｖａｐｏｒ Ｐｈａｓｅ Ｅｐｉｔａｘｉｙ）法で低転位密度な厚膜結晶の開発がなされている。数百μｍないし1ｍｍ程度の厚みまで成長すると転位密度が107乃至106／ｃｍ2の桁まで低減できるので、特に自立基板やテンプレート基板用途をターゲットとし開発製造がなされている。ただし、自立基板を得る為には前記に示したレーザリフトオフ法、すなわちサファイア基板裏面側から界面のＧａＮを248nmのエキシマレーザのナノ秒パルス照射でＧａＮを分解し基板と分離させている。この場合、全面を完全に剥離できなかったり、クラックが発生するなど歩留面での課題も多いためコストアップ要因となっている（非特許文献４〜７）。 Regarding the reduction of dislocation density of III-nitride semiconductor crystals grown on sapphire substrates, the improvement of III-nitride buffer layer, penetration from the underlying substrate by lateral growth on an insulating film called ELO (Epitaxial Lateral Overgtowth) Dislocation propagation suppression, group III nitride seed layer is arranged on the top of the convex part of the concavo-convex processed substrate called PENDEO epitaxy method, and the growth of the hollow from the side in the lateral direction suppresses the propagation of threading dislocation from the base substrate. Proposed. Further, in GaN, dislocations disappear due to the reaction between dislocations as the crystal layer progresses, and the dislocation density decreases. Therefore, HVPE (Hideride) capable of high-speed epitaxy.
A thick film crystal having a low dislocation density has been developed by the Vapor Phase Epitaxy method. Since the dislocation density can be reduced to the order of 10 7 to 10 6 / cm 2 when grown to a thickness of about several hundred μm to 1 mm, development and manufacture are particularly targeted for freestanding substrates and template substrates. However, in order to obtain a self-supporting substrate, the GaN is decomposed and separated from the substrate by the laser lift-off method described above, that is, GaN at the interface from the back side of the sapphire substrate is irradiated with a nanosecond pulse of 248 nm excimer laser. In this case, the entire surface cannot be completely peeled off or cracks are generated, so that there are many problems on the yield surface, which is a cause of cost increase (Non-Patent Documents 4 to 7).

ところで、本発明者らはサファイア基板上に特定の金属種の金属窒化物バッファー層を所定の条件で形成した場合その上に成長したＧａＮ単結晶層の結晶性が、従来のＡｌＮあるいはＧａＮ低温バッファー層を用いたサファイア基板上のＧａＮの結晶性と比べて同等もしくは良好な結晶性を有し、かつ金属窒化物バッファー層を選択的に化学エッチングして下地サファイア基板と成長層を分離し、自立基板もしくは個別半導体チップが製造できる技術を提案している（特許文献１、２）。   By the way, when the present inventors formed a metal nitride buffer layer of a specific metal type on a sapphire substrate under a predetermined condition, the crystallinity of the GaN single crystal layer grown on the layer is the same as that of a conventional AlN or GaN low-temperature buffer. Has a crystallinity equal to or better than the crystallinity of GaN on the sapphire substrate using the layer, and selectively etches the metal nitride buffer layer to separate the underlying sapphire substrate and the growth layer, thereby self-supporting A technique capable of manufacturing a substrate or an individual semiconductor chip is proposed (Patent Documents 1 and 2).

前記のごとく、サファイア基板上に選択エッチングが可能で、III族窒化物半導体結晶の成長に供することのできる手法を見出したが、結晶欠陥の更なる低減及び選択エッチングによる下地基板と成長層の分離にかかる時間短縮が課題として挙げられる。すなわち、結晶欠陥に関しては素子特性や寿命などの信頼性の更なる向上が望まれ、継続的に転位密度を下げていく必要がある。特許文献1ならびに特許文献2に示したようにサファイア基板上の金属窒化物バッファー層がＣｒＮの場合、金属Ｃｒの膜厚が15乃至30nｍの場合に結晶性についての最適値が有り、45nｍ程度まではＧａＮの単結晶層を得ることができるももの、50nｍを越えると窒化処理後のＣｒＮ層の結晶性が大幅に低下し、その上に成長したＧａＮはモザイク状乃至多結晶化してしまう。   As described above, the inventors have found a technique that allows selective etching on a sapphire substrate and can be used for the growth of a group III nitride semiconductor crystal, but further reduces crystal defects and separates the underlying substrate and the growth layer by selective etching. Reduction of the time taken for is a problem. That is, regarding crystal defects, further improvement in reliability such as device characteristics and lifetime is desired, and it is necessary to continuously reduce the dislocation density. As shown in Patent Document 1 and Patent Document 2, when the metal nitride buffer layer on the sapphire substrate is CrN, there is an optimum value for crystallinity when the film thickness of the metal Cr is 15 to 30 nm, up to about 45 nm. Although a single crystal layer of GaN can be obtained, if it exceeds 50 nm, the crystallinity of the CrN layer after nitriding is greatly lowered, and the GaN grown thereon becomes mosaic or polycrystalline.

ケミカルリフトオフの所要時間はＣｒＮ膜厚が厚いほうが有利であるが、結晶性の確保とのトレードオフであり、特に自立基板の大面積化においては改善すべき課題である。エッチング速度は、液組成や液温、攪拌条件などに影響を受ける為一概に数値表記するのは難しいが、Ｃｒ成膜厚みが20nmの場合、300μｍ角のチップでは10〜15分程度、2インチ口径の自立基板をケミカルリフトオフする場合には数十時間を要する。前者についてはプロセス時間として許容できる範囲ではあるが、更にリードタイム短縮による生産性向上が望まれる、また後者については大幅な時間短縮・改善を要する。大面積化の際には、成膜するＣｒ膜厚の面内分布が大きくなる傾向にあるため、部分的なピット発生や多結晶化を回避する為に、プロセスマージンを考慮してＣｒ厚み条件は安全サイド（適正条件の中心乃至若干薄め）に設定することになってしまう点が問題であり、より厚い金属窒化物バッファー層であっても結晶性の維持向上を実現することが課題である。青色LEDのように、Inの組成ゆらぎが幸いして転位による発光効率の低下を大幅に封じ込めることができる用途については、結晶性が劣悪とならなければむしろ転位密度よりも剥離性を最重要視する場合もあるが、サファイア基板上ではCr層が厚い場合GaN層が多結晶化してしまうと言う大きな課題が有る。そこで本発明者らは、AlN上の金属窒化物バッファー層について調査し、予想を超える結果を得た（特願２００７−２２１７７４）。   The time required for chemical lift-off is advantageous when the CrN film thickness is thicker, but this is a trade-off with ensuring crystallinity, and is a problem to be improved particularly in increasing the area of a free-standing substrate. The etching rate is affected by the liquid composition, liquid temperature, stirring conditions, etc., so it is difficult to express numerical values. However, if the Cr film thickness is 20 nm, the chip of 300 μm square is about 10-15 minutes, 2 inches. It takes several tens of hours to chemically lift off a self-supporting substrate having a diameter. Although the former is in an allowable range as a process time, it is desired to further improve the productivity by reducing the lead time, and the latter requires a significant time reduction / improvement. When the area is increased, the in-plane distribution of the Cr film thickness tends to increase. Therefore, in order to avoid partial pit generation and polycrystallization, the Cr thickness condition is considered in consideration of the process margin. However, the problem is that the crystallinity can be maintained and improved even with a thicker metal nitride buffer layer. . For blue LEDs, where the compositional fluctuation of In is fortunate and the decrease in light emission efficiency due to dislocations can be largely contained, if the crystallinity is not inferior, the peelability is more important than the dislocation density. However, on the sapphire substrate, there is a big problem that if the Cr layer is thick, the GaN layer becomes polycrystalline. Therefore, the present inventors investigated a metal nitride buffer layer on AlN, and obtained a result exceeding expectations (Japanese Patent Application No. 2007-221774).

高橋清監修、長谷川文夫・吉川明彦編著「ワイドギャップ半導体光・電子デバイス」森北出版（2006年3月）Supervised by Kiyoshi Takahashi, edited by Fumio Hasegawa and Akihiko Yoshikawa, “Wide Gap Semiconductor Optical and Electronic Devices”, Morikita Publishing (March 2006) Ｗ．Ｓ．Ｗｏｎｇら「Ｄａｍａｇｅ-ｆｒｅｅ ｓｅｐａｒａｔｉｏｎ ｏｆ ＧａＮ ｔｈｉｎ ｆｉｌｍｓ ｆｒｏｍ ｓａｐｐｈｉｒｅ ｓｕｂｓｔｒａｔｅｓ」Ａｐｐｌ．Ｐｈｙｓ． Ｌｅｔｔ．７２（1998）Ｐ.599W. S. Wong et al. “Damage-free separation of GaN thin films from sapphire substrates” Appl. Phys. Lett. 72 (1998) P.599 「ＩＭＥＣ ｉｍｐｒｏｖｅｓ ＧａＮ ＨＥＭＴｓ」Ｃｏｍｐｏｕｎｄ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ， Ｏｃｔｏｂｅｒ（2005）Ｐ．16“IMEC improve GaN HEMTs” Compound Semiconductor, October (2005) p. 16 天野ら「サファイア基板上III族窒化物半導体成長における低温堆積層の効果と機構」応用物理６８（1999）Ｐ．768Amano et al., “Effects and Mechanisms of Low Temperature Deposited Layers on Group III Nitride Semiconductor Growth on Sapphire Substrates”, Applied Physics 68 (1999), p. 768 Ａ．Ｓａｋａｉら「Ｄｅｆｅｃｔ ｓｔｒｕｃｔｕｒｅ ｉｎ ｓｅｌｅｃｔｉｖｅｌｙ ｇｒｏｗｎ ＧａＮｆｉｌｍｓ ｗｉｔｈ ｌｏｗ ｔｈｒｅａｄｉｎｇ ｄｉｓｌｏｃａｔｉｏｎ ｄｅｎｓｉｔｙ」Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．７１（1997）Ｐ．2259A. Sakai et al. “Defect structure in selective growth GaN films with low threading dislocation density” Appl. Phys. Lett. 71 (1997) p. 2259 Ｋ．Ｌｉｎｔｈｉｃｕｍら「Ｐｅｎｄｅｏｅｐｉｔａｘｙ ｏｆ ｇａｌｌｉｕｍ ｎｉｔｒｉｄｅ ｔｈｉｎ ｆｉｌｍｓ」Ａｐｐｌ．Ｐｈｙｓ．Ｌｅｔｔ．７５（1999）Ｐ．196K. Linthicum et al. “Pendeoepitaxy of gallium nitride thin films” Appl. Phys. Lett. 75 (1999) p. 196 Ｓ．Ｋ．Ｍａｔｈｉｓら「Ｍｏｄｅｒｉｎｇ ｏｆ ｔｈｒｅａｄｉｎｇ ｄｉｓｌｏｃａｔｉｏｎ ｉｎ ｇｒｏｗｉｎｇ ＧａＮ ｌａｙｅｒ」Ｊ．Ｃｒｙｓｔａｌ Ｇｒｏｗｔｈ ２３１（2001）Ｐ．371S. K. Mathis et al., “Modeling of threading dislocation in growing GaN layer”, J. Am. Crystal Growth 231 (2001) P.M. 371 ＰＣＴ／ＪＰ／２００６／３０６９５８PCT / JP / 2006/306958 ＰＣＴ／ＪＰ／２００６／３２５９９２PCT / JP / 2006/3259592

本発明の目的は、AlNを有する基板上に金属窒化物バッファー層を介してIII族窒化物半導体を成膜する方法において、III族窒化物半導体の転位密度の更なる低減と同時に、自立基板製造時および半導体素子製造時のケミカルリフトオフ所要時間の大幅な短縮が可能な手法を提供することにある。   It is an object of the present invention to produce a group III nitride semiconductor film on a substrate having AlN via a metal nitride buffer layer, and at the same time to further reduce the dislocation density of the group III nitride semiconductor and manufacture a self-supporting substrate. It is an object of the present invention to provide a technique capable of greatly reducing the time required for chemical lift-off at the time of manufacturing a semiconductor device.

本発明によれば、基板上にＡｌＮ単結晶層またはＡｌを含むIII族窒化物単結晶層を０．００５μm以上１０μm以下の厚みで形成したAlNテンプレート基板又はサファイア基板を窒化処理したAlNテンプレート基板、もしくはＡｌＮ単結晶基板上に、金属層を成膜する工程と、該金属層の上に開口部を有するパターンマスク膜を形成する工程と、マスク開口部に露呈した部位の金属層をアンモニア混合ガス雰囲気中で加熱処理を行い金属窒化層を形成する工程と、該金属窒化物層を核としてIII族窒化物半導体層を成膜する工程を有することを特徴とする、III族窒化物半導体の製造方法が提供される。なお、AlNテンプレート基板として、例えばサファイア、SiC、Siのいずれかからなる基板上にAlN単結晶層を０．００５μm以上１０μm以下の厚みで形成したAlNテンプレート基板を用いても良い。   According to the present invention, an AlN template substrate in which an AlN single crystal layer or a group III nitride single crystal layer containing Al is formed on a substrate with a thickness of 0.005 μm or more and 10 μm or less, or an AlN template substrate obtained by nitriding a sapphire substrate, Alternatively, a step of forming a metal layer on an AlN single crystal substrate, a step of forming a pattern mask film having an opening on the metal layer, and a metal layer at a portion exposed to the mask opening are mixed with ammonia. A method for producing a group III nitride semiconductor, comprising: a step of forming a metal nitride layer by performing a heat treatment in an atmosphere; and a step of forming a group III nitride semiconductor layer using the metal nitride layer as a nucleus. A method is provided. As the AlN template substrate, for example, an AlN template substrate in which an AlN single crystal layer is formed with a thickness of 0.005 μm or more and 10 μm or less on a substrate made of any of sapphire, SiC, and Si may be used.

この製造方法において、更に、成膜されたIII族窒化物半導体層を前記ＡｌＮテンプレート基板もしくはＡｌＮ単結晶基板と分離する工程を有しても良い。なお、分離したIII族窒化物半導体層により、III族窒化物半導体の自立基板を得ることができ、更に、当該自立基板を用いて半導体素子を形成することができる。また、前記金属層は、金属窒化物を形成するための第一の金属層と、第一の金属層上に成膜され、マスク材成膜時に第一の金属層表面の酸化を防止するとともにマスク開口部を形成する工程でマスク材と同時に除去可能な第二の金属層からなり、第一の金属層がCr（クロム）、Sc（スカンジウム）、V（バナジウム），Nb（ニオブ）から選択された少なくとも1種類以上を含む単層膜・多層膜・合金膜であり、第二の金属層がTi（チタン）、Zr（ジルコニウム）、Hf（ハフニウム）から選択された少なくとも1種類以上を含む、単層膜・多層膜・合金膜で構成されても良い。この場合、第一の金属層と第二の金属層は連続して成膜されても良い。また、前記第一の金属層の窒化前の平均膜厚が例えば４〜５００nmの範囲であり、前記第二の金属層の平均厚さが例えば５〜２０nmの範囲である。   The manufacturing method may further include a step of separating the formed group III nitride semiconductor layer from the AlN template substrate or the AlN single crystal substrate. Note that a separated group III nitride semiconductor layer can provide a freestanding substrate of a group III nitride semiconductor, and a semiconductor element can be formed using the freestanding substrate. The metal layer is formed on the first metal layer for forming the metal nitride and the first metal layer, and prevents oxidation of the surface of the first metal layer when forming the mask material. It consists of a second metal layer that can be removed simultaneously with the mask material in the process of forming the mask opening, and the first metal layer is selected from Cr (chromium), Sc (scandium), V (vanadium), and Nb (niobium) Single layer film / multilayer film / alloy film including at least one selected from the above, and the second metal layer includes at least one selected from Ti (titanium), Zr (zirconium), and Hf (hafnium) Alternatively, it may be composed of a single layer film, a multilayer film, or an alloy film. In this case, the first metal layer and the second metal layer may be continuously formed. The average thickness of the first metal layer before nitriding is, for example, in the range of 4 to 500 nm, and the average thickness of the second metal layer is in the range of, for example, 5 to 20 nm.

また、前記パターンマスク膜がSiO2もしくはSiONから構成されても良い。かかるパターンマスク膜は、フッ酸含有エッチング液でエッチングすることができる。また、前記パターンマスク膜が、プラズマ化学気相堆積（PCVD）法、蒸着法、反応性スパッタ法、熱化学気層堆積（LPCVD）法のいずれかで形成され、膜厚が１００〜１０００nmの範囲であっても良い。
また、前記アンモニアガス雰囲気での金属層の加熱窒化温度が９００〜１２００℃の範囲であり、窒化時間が1分以上９０分以下であっても良い。
また、前記AlNテンプレート基板の（０００２）X線ロッキングカーブの半値幅が５００秒以下、（１１−２０）の半値幅が３０００秒以下であっても良い。 The pattern mask film may be made of SiO 2 or SiON. Such a pattern mask film can be etched with a hydrofluoric acid-containing etchant. The pattern mask film is formed by any one of a plasma chemical vapor deposition (PCVD) method, a vapor deposition method, a reactive sputtering method, and a thermal chemical vapor deposition (LPCVD) method, and has a thickness in the range of 100 to 1000 nm. It may be.
Further, the heating nitriding temperature of the metal layer in the ammonia gas atmosphere may be in a range of 900 to 1200 ° C., and the nitriding time may be 1 minute or more and 90 minutes or less.
The half width of the (0002) X-ray rocking curve of the AlN template substrate may be 500 seconds or less, and the half width of (11-20) may be 3000 seconds or less.

また、本発明によれば、上記製造方法によって製造されたIII族窒化物半導体が提供される。また、前記素子を形成するにあたり、素子内のマスクパターン形状と素子間を分離するためのマスク形状が異なるマスク幅・形状で構成されていても良い。   Moreover, according to this invention, the group III nitride semiconductor manufactured by the said manufacturing method is provided. In forming the element, the mask pattern shape in the element and the mask shape for separating the elements may be different in mask width and shape.

本発明者らは、上記手段を取ることにより、予想を超える結果が得られることを見出した。   The present inventors have found that by taking the above-mentioned measures, results exceeding expectations can be obtained.

第一の金属がCrの場合を例にとって述べると、
（１）パターンマスクを用いずにAlN(0001)上にGaNをハイドライドベーパーフェーズエピタキシー（HVPE）法で成長した場合、Crの膜厚は３００ｎｍ程度まで厚くしても充分な結晶性、例えば所定以下のX線回折ピークの半値幅を有するGaN層を成長することができた。本発明では更にELO成長を実施する事で、パターンマスクを用いない場合に比べ、さらに1〜２桁の結晶性改善効果、即ち転位密度低減効果が得られた。
（２）同一の結晶性を得るための第一の金属の厚みはパターンマスクを用いない場合に比べて厚くする事が可能となった為、たとえばAlN(0001)上に第一の金属であるCrを５００ｎｍ、第二の金属としてTiを２０ｎｍとし、パターンマスクであるSiO2の厚みを５００ｎｍとした場合、化学エッチングが可能な層の膜厚が都合１０２０ｎｍとしても結晶性の維持向上とケミカルエッチングの所要時間の大幅短縮の両立が可能となった。
（３）パターンマスク形状・寸法を工夫することにより、素子内はELO成長で連続膜を形成し転位密度を低減しつつ、素子間はELO成長後もマスクが完全に被覆しない箇所を残すため、化学エッチングの供給経路が自動的に確保されるため、成長後に素子分離溝加工などの工程が不要となり、生産性も向上させることができる。
（４）第一の金属の上に、マスクパターン形成時に同時に除去可能な第二の金属を成膜する事によって、マスク材たとえばプラズマCVD法でSiO2を成膜する際に第一の金属の表面に強固な酸化膜が形成される事が防止され、第一の金属の窒化処理が均一に実施され、引き続き第一の金属窒化物を核としてIII族窒化物層を形成する際に均一な成長が可能となる。 Taking the case where the first metal is Cr as an example,
(1) When GaN is grown by hydride vapor phase epitaxy (HVPE) method on AlN (0001) without using a pattern mask, the crystallinity is sufficient even if the Cr film thickness is increased to about 300 nm, for example, below a predetermined level. A GaN layer with a full width at half maximum of the X-ray diffraction peak can be grown. In the present invention, by further carrying out ELO growth, the crystallinity improvement effect of one to two digits, that is, the dislocation density reduction effect, was obtained as compared with the case where no pattern mask was used.
(2) Since the thickness of the first metal for obtaining the same crystallinity can be increased compared to the case where no pattern mask is used, for example, the first metal is on AlN (0001). When Cr is 500 nm, Ti as the second metal is 20 nm, and the thickness of SiO2 as the pattern mask is 500 nm, even if the thickness of the layer capable of chemical etching is 1020 nm, the improvement in crystallinity and chemical etching It has become possible to reduce the required time significantly.
(3) By devising the shape and dimensions of the pattern mask, a continuous film is formed in the device by ELO growth to reduce the dislocation density, while leaving a portion where the mask is not completely covered even after the ELO growth. Since the supply path for chemical etching is automatically secured, a process such as element isolation groove processing after the growth becomes unnecessary, and productivity can be improved.
(4) By forming a second metal on the first metal that can be removed at the same time as the mask pattern is formed, the surface of the first metal when forming a mask material, for example, SiO2 by plasma CVD. Formation of a strong oxide film, uniform nitriding of the first metal, and subsequent uniform growth when forming a group III nitride layer with the first metal nitride as the nucleus Is possible.

AlNテンプレートまたは表面を窒化したサファイア基板あるいはAlN単結晶基板を用いて、低転位密度のIII族化合物半導体が大量生産可能となるとともに、ケミカルリフトオフ性が更に向上し、低転位密度なIII族窒化物半導体の自立基板、半導体素子を得ることが可能となる。 Using AlN templates, sapphire substrates with nitrided surfaces, or AlN single crystal substrates, low dislocation density group III compound semiconductors can be mass-produced, and chemical lift-off properties are further improved, with low dislocation density group III nitrides. A semiconductor free-standing substrate and a semiconductor element can be obtained.

以下、本発明の実施の形態を、図１を参照にして説明する。なお、本明細書及び図面において、実質的に同一の機能構成を有する構成要素については、同一の符号を付することにより重複説明を省略する。   Hereinafter, an embodiment of the present invention will be described with reference to FIG. In addition, in this specification and drawing, about the component which has the substantially same function structure, duplication description is abbreviate | omitted by attaching | subjecting the same code | symbol.

金属窒化物をIII族窒化物半導体層形成のためのバッファ層とし、ELO成長よってIII族窒化物半導体層ならびに素子を製造する場合の製造工程を簡単に示し、次いで最良の実施形態について説明する。なお、ここで半導体層とは単層または積層された状態を含む。   A metal nitride is used as a buffer layer for forming a group III nitride semiconductor layer, and a manufacturing process in the case of manufacturing a group III nitride semiconductor layer and an element by ELO growth will be briefly described, and then the best embodiment will be described. Note that here, the semiconductor layer includes a single layer or a stacked state.

まず初めに成長用の下地層２を有する基板１上に所定の金属をスパッタリング法や真空蒸着法などで所定厚みで第一の金属層３を成膜し、引続き第二の金属層４を所定厚みで連続成膜する。ここで連続成膜とは、成膜装置中に複数のスパッタリングターゲットもしくは蒸発源を有する事で、第一の金属層３の成膜が終了して第二の金属層４を成膜するにあたって、大気開放はせずに引続き成膜すると言う意味である。それにより、第一の金属層３の表面は、自然酸化膜が形成されない状態で第二の金属層４に保護される。次いでプラズマCVD法で、例えばSi源としてシランガス、酸素源としてN2Oガスを用い、基板温度３５０℃でSiO２膜５を成膜する。   First, a first metal layer 3 having a predetermined thickness is formed on a substrate 1 having a growth base layer 2 by sputtering or vacuum vapor deposition, and then a second metal layer 4 is continuously formed. Continuous film formation with thickness. Here, the continuous film formation is to have a plurality of sputtering targets or evaporation sources in the film forming apparatus, and when the film formation of the first metal layer 3 is completed and the second metal layer 4 is formed, This means that the film is continuously formed without opening to the atmosphere. Thereby, the surface of the first metal layer 3 is protected by the second metal layer 4 in a state where a natural oxide film is not formed. Next, the SiO 2 film 5 is formed by plasma CVD using, for example, silane gas as the Si source and N 2 O gas as the oxygen source at a substrate temperature of 350 ° C.

次いで、SiO２膜５上にフォトレジストをスピン塗布し、レジストのプリベーク、露光、現像を行い、レジストパターン６を形成し、開口部６’に露呈したSiO2マスク材（SiO２膜５）をフッ酸含有エッチング液、例えばバッファードフッ酸やフッ酸希釈液でエッチングする。SiO2膜５のエッチングが完了したならば、引続き第二の金属層４もエッチングし、開口部６’に第一の金属層３の表面を露呈させる。最後に、フォトレジスト（レジストパターン６）を除去・洗浄することで、ELO成長用のマスクパターン膜が形成された基板が準備された状態となる。   Next, a photoresist is spin-coated on the SiO 2 film 5, the resist is pre-baked, exposed and developed to form a resist pattern 6, and the SiO 2 mask material (SiO 2 film 5) exposed in the opening 6 ′ contains hydrofluoric acid. Etching is performed with an etching solution such as buffered hydrofluoric acid or dilute hydrofluoric acid. When the etching of the SiO2 film 5 is completed, the second metal layer 4 is also etched to expose the surface of the first metal layer 3 in the opening 6 '. Finally, the photoresist (resist pattern 6) is removed and washed to prepare a substrate on which a mask pattern film for ELO growth is formed.

次いで、III族窒化物半導体成長装置、例えばHVPE成長装置に導入し高純度水素もしくは窒素ガス雰囲気中で昇温を開始する。所定の温度、すなわち用いる金属が窒化反応を生じる始める温度付近から窒素水素化物例えばアンモニアガスやヒドラジンガスの供給を開始し、さらに窒化処理温度まで昇温しその温度で所定時間窒化処理を実施し、マスク開口部に露呈する第一の金属層３を、III族窒化物半導体層を成膜するための金属窒化物バッファ層７に転化させる。通常サファイア基板、SiC基板、Si基板上にIII族窒化物半導体層７を成膜する場合には、III族窒化物半導体の低温バッファ層を形成するが、本方式ではその必要は無い。   Next, it is introduced into a group III nitride semiconductor growth apparatus, for example, an HVPE growth apparatus, and temperature rise is started in a high purity hydrogen or nitrogen gas atmosphere. Start supplying nitrogen hydride such as ammonia gas or hydrazine gas from a predetermined temperature, that is, near the temperature at which the metal used starts to cause a nitriding reaction, further raise the temperature to the nitriding temperature, and perform nitriding for a predetermined time at that temperature, The first metal layer 3 exposed in the mask opening is converted into a metal nitride buffer layer 7 for forming a group III nitride semiconductor layer. Usually, when forming a group III nitride semiconductor layer 7 on a sapphire substrate, SiC substrate, or Si substrate, a low temperature buffer layer of a group III nitride semiconductor is formed, but this method is not necessary.

次いで、III族窒化物半導体の成長温度に調整し、III族原料ガスの供給を開始して成膜を開始する。成長初期は第一の金属窒化物層７（金属窒化物バッファ層）を核として、III族窒化物半導体層８を選択的に成長させる。ここで選択成長とは、SiO2などのマスク部５には成長させず、第一の金属窒化物層７上にIII族窒化物半導体層８を成長させることを意味する。成長層（III族窒化物半導体層を）がマスク膜厚み以上に成長したならば、ファセット形成がなされる成長温度・流量比に設定し、マスク開口部上に伝播する転位をファセット側面で終端・もしくはベンディングさせることで転位密度を低減させる。パターンマスクであるSiO2上もファセット面を維持しつつ横方向成長させ、成長結晶同士が合体したならば、V溝部やピット部が埋め込まれて平坦成長となるように、成膜温度や供給ガス種・流量比などを適宜変更し、目的の成膜が終了した段階で冷却を開始する。冷却途中の所定温度に至ったならば、アンモニアガスやヒドラジンガスの供給を停止し、高純度水素または窒素ガス雰囲気中で冷却を行い成長工程を終了する。   Next, the growth temperature of the group III nitride semiconductor is adjusted, the supply of the group III source gas is started, and the film formation is started. In the initial stage of growth, the group III nitride semiconductor layer 8 is selectively grown using the first metal nitride layer 7 (metal nitride buffer layer) as a nucleus. Here, the selective growth means that the group III nitride semiconductor layer 8 is grown on the first metal nitride layer 7 without being grown on the mask portion 5 such as SiO 2. If the growth layer (Group III nitride semiconductor layer) grows beyond the thickness of the mask film, the growth temperature / flow rate ratio is set to facet formation, and the dislocation propagating over the mask opening is terminated at the facet side. Alternatively, the dislocation density is reduced by bending. The growth temperature and supply gas type are also adjusted so that the V-groove part and pit part are buried and flat growth is achieved if the growth crystal grows laterally while maintaining the facet plane on the SiO2 pattern mask. -Change the flow rate ratio etc. as appropriate, and start cooling when the target film formation is completed. When the temperature reaches a predetermined temperature during cooling, the supply of ammonia gas or hydrazine gas is stopped, cooling is performed in a high-purity hydrogen or nitrogen gas atmosphere, and the growth process is terminated.

III族窒化物半導体、およびIII族窒化物半導体の自立基板または半導体素子の製造の一例として、サファイア基板（Ａｌ２Ｏ３）の上に、下地層２としてＡｌＮ単結晶層を設けた基板１（以降、ＡｌＮテンプレート基板という）を用いた。前記サファイア基板のほかに、ＳｉＣ基板、Ｓｉ基板など、所望半導体に応じて適用可能な基板を用い、当該ＳｉＣ基板、Ｓｉ基板などの上に、下地層２としてＡｌＮ単結晶層を設けた基板を、ＡｌＮテンプレート基板として用いることが出来る。さらにはＡｌＮ単結晶基板を用いても良い（以下、下地基板とも言う）。また、サファイア基板表面を窒化処理しAlNに転化した基板を用いても良い。また、ＡｌＮ以外にIII族窒化物半導体との間の格子不整合の割合が小さい層として、ＡｌＧａＮ、またはIII族の主元素がＡｌ（Ａｌを50％以上含む）のIII族窒化物（Ａｌｒｉｃｈ-ＢＡｌＧａＩｎＮ）を選択することも可能である。本実施例では、サファイア（0001）面上にMOCVD法によってAlN単結晶層を約１μm成膜したAlNテンプレート基板を用いた。AlNテンプレート基板のXRDの半値幅は（0002）回折では約100sec、（11−20）回折の半値幅は約1200sec乃至1400secのものを用いた。 As an example of the manufacture of a group III nitride semiconductor and a group III nitride semiconductor free-standing substrate or semiconductor element, a substrate 1 in which an AlN single crystal layer is provided as an underlayer 2 on a sapphire substrate (Al 2 O 3 ) ( Hereinafter, an AlN template substrate) was used. In addition to the sapphire substrate, a substrate that can be applied according to a desired semiconductor, such as a SiC substrate or a Si substrate, is used, and a substrate in which an AlN single crystal layer is provided as a base layer 2 on the SiC substrate, the Si substrate, or the like. It can be used as an AlN template substrate. Further, an AlN single crystal substrate may be used (hereinafter also referred to as a base substrate). Further, a substrate obtained by nitriding the surface of the sapphire substrate and converting it to AlN may be used. Further, as a layer having a small lattice mismatch ratio with the group III nitride semiconductor other than AlN, a group III nitride (Alrich-) of AlGaN or a group III main element of Al (containing 50% or more of Al) is used. It is also possible to select BAlGaInN). In this example, an AlN template substrate in which an AlN single crystal layer of about 1 μm was formed on the sapphire (0001) surface by MOCVD was used. The AlN template substrate used had a half-width of XRD of about 100 seconds for (0002) diffraction and a half-width of (11-20) diffraction of about 1200 to 1400 seconds.

AlNテンプレート基板に成膜される所定の第一の金属層３としては、アンモニアガス・ヒドラジンガスなどの窒素水素化物によって窒化された段階で、III族窒化物半導体層８を成長するための金属窒化物バッファ層７としての条件を満たすものである必要がある。具体的には窒化された段階で、下地層２もしくは下地基板面に垂直な方向に対してランダムではなく所定の方位に揃った状態であること、かつ下地層もしくは下地基板の面内に対しねじれの無い状況であることが必要である。すなわち下地に垂直な方向に単に配向するだけでは意味が無く、面内のドメイン回転ゆらぎも抑制されたものでなければならない。AlN(0001)ｃ面上においては金属窒化物が岩塩型もしくは六方晶構造となり、下地に垂直な方向が前者では＜111＞方向、後者では＜0001＞方向となるとともに、下地の面内に対して前者は三角形の底辺が、後者は後者のa軸がAlN(0001)面内のa軸方向に平行となることが必要である。好ましくは原子間隔がAlN（0001）面内のa軸の格子定数に近接するものが良く、更にはIII族窒化物半導体の成長温度において耐熱を有し、相互拡散や合金化どが生じにくいこと、熱膨張係数も近接することが好ましい。以上はIII族窒化物半導体結晶の結晶性を向上するために必要な要件である。   As the predetermined first metal layer 3 formed on the AlN template substrate, metal nitridation for growing the group III nitride semiconductor layer 8 at the stage of nitridation by nitrogen hydride such as ammonia gas or hydrazine gas is used. It is necessary to satisfy the conditions as the physical buffer layer 7. Specifically, at the stage of nitriding, it is in a state of being aligned in a predetermined direction rather than in a random direction with respect to the direction perpendicular to the surface of the underlying layer 2 or the underlying substrate, and twisted in the plane of the underlying layer or the underlying substrate. It is necessary that there is no situation. In other words, it is meaningless to simply align in the direction perpendicular to the base, and the in-plane domain rotation fluctuation must be suppressed. On the AlN (0001) c plane, the metal nitride has a rock salt type or hexagonal structure, and the direction perpendicular to the base is the <111> direction in the former and the <0001> direction in the latter, In the former case, the base of the triangle must be parallel to the a axis direction in the AlN (0001) plane. Preferably, the atomic spacing is close to the a-axis lattice constant in the AlN (0001) plane, and furthermore, it has heat resistance at the growth temperature of the group III nitride semiconductor, and it is difficult for interdiffusion and alloying to occur. The thermal expansion coefficient is preferably close. The above are the requirements necessary for improving the crystallinity of the group III nitride semiconductor crystal.

また、下地層２もしくは下地基板とIII族窒化物半導体層８をケミカルリフトオフ法によって分離する場合には、III族窒化物半導体層および転写用に使用する接合金属または合金にはダメージを与えずに、バッファ層である金属窒化物層７を選択的に化学エッチングする薬液が存在するかも重要な選定要件となる。同時に、パターンマスク形成時のエッチング液に対してはエッチングされない、もしくは充分なエッチング選択比を有する事も重要である。   Further, when the underlying layer 2 or the underlying substrate and the group III nitride semiconductor layer 8 are separated by the chemical lift-off method, the group III nitride semiconductor layer and the bonding metal or alloy used for transfer are not damaged. The existence of a chemical solution for selectively chemically etching the metal nitride layer 7 that is a buffer layer is also an important selection requirement. At the same time, it is also important that the etching solution is not etched or has a sufficient etching selectivity when forming the pattern mask.

それらを満たす第一の金属層３として、Cr、Sc、V、Nbが良く、これらのうち少なくとも1種類以上を選択し、単層、多層膜、合金などの形態で用いる。なお、これらの金属は窒化処理後岩塩型結晶構造となる。最も好ましくはＣｒであり、CrNは過塩素酸もしくは硝酸と硝酸2セリウムアンモニウム溶液がIII族窒化物半導体８ならびにＡｕ−Ｓｎ合金ハンダ、Ａｕ−Ａｕ接合にはダメージを与えること無しに選択エッチングが可能である。ScN、VN、NbNはフッ酸のみのエッチング速度は遅いので硝酸を加えた混合液を用いれば良い。   The first metal layer 3 that satisfies them is preferably Cr, Sc, V, or Nb, and at least one of these is selected and used in the form of a single layer, a multilayer film, an alloy, or the like. These metals have a rock salt type crystal structure after nitriding. Most preferred is Cr, and CrN can be selectively etched without damaging the group III nitride semiconductor 8, Au—Sn alloy solder, and Au—Au joints with perchloric acid or nitric acid and 2 ceric ammonium nitrate solution. It is. Since ScN, VN, and NbN have a slow etching rate of only hydrofluoric acid, a mixed solution containing nitric acid may be used.

第一の金属層３に成膜される第二の金属層４としては、SiO2などのマスク材５でパターンマスクを形成する際のエッチング液等でエッチングされる事が必要で有るとともに、成長時の温度での耐熱性充分で、拡散などが生じにくい事、および第一の金属層３とマスク材５との密着性に優れていることが要件であり、Ti、Hf、Zrが良く、これらのうち少なくとも１種類以上を選択し、単層、多層膜、合金膜などの形態で用いる。いずれの金属とも、SiO2などを化学エッチングする際に用いるバッファードフッ酸や希釈フッ酸溶液で完全に除去できる。   The second metal layer 4 formed on the first metal layer 3 needs to be etched with an etching solution for forming a pattern mask with a mask material 5 such as SiO2, and at the time of growth. It is necessary that the heat resistance at this temperature is sufficient, diffusion is difficult to occur, and the adhesion between the first metal layer 3 and the mask material 5 is excellent, and Ti, Hf, and Zr are good. At least one of them is selected and used in the form of a single layer, a multilayer film, an alloy film or the like. Both metals can be completely removed with buffered hydrofluoric acid or diluted hydrofluoric acid solution used when chemically etching SiO 2 or the like.

AlNテンプレート基板（もしくはサファイア基板表面を窒化処理しAlN層に転化した基板、或はAlN単結晶基板）上への第一の金属層３および第二の金属層４の成膜方法としては、スパッタリング法や真空蒸着法を用いる。第一の金属層は所定の平均厚み、すなわち４ｎｍ〜５００ｎｍの範囲で成膜する。平均膜厚は好ましくは３０ｎｍ〜５００ｎｍであるとケミカルリフトオフ所要時間が短くて済むからである。平均膜厚が４ｎｍ未満の場合、窒化処理後に下地のＡｌＮ表面の露呈比率が高く、III族窒化物半導体層の成長開始時にＡｌＮ下地層２と金属窒化物微結晶の両者から成長が開始されてしまい結晶性の向上効果が少ない点と、III族窒化物半導体層８とＡｌＮ下地層２との直接接触比率が増え、後にケミカルリフトオフを実施する場合にエッチング液が浸透し難く分離が困難となるためである。また５００nmを越えた場合には窒化処理時間が長くなってしまい生産性が著しく低下してしまうこと、ならびにＡｌＮ下地層２からの固相エピタキシャル成長の駆動力が低下するため金属窒化物層７の結晶性が十分でなく、ELO成長による結晶性向上効果をしても悪化分を補えきれず、その上に形成するIII族窒化物半導体層８の結晶性も十分なものが得られないためである。   As a method for forming the first metal layer 3 and the second metal layer 4 on an AlN template substrate (or a substrate obtained by nitriding the surface of a sapphire substrate and converting it to an AlN layer, or an AlN single crystal substrate), sputtering is used. Method or vacuum evaporation method is used. The first metal layer is formed in a predetermined average thickness, that is, in the range of 4 nm to 500 nm. This is because when the average film thickness is preferably 30 nm to 500 nm, the time required for chemical lift-off can be shortened. When the average film thickness is less than 4 nm, the exposure ratio of the underlying AlN surface is high after the nitriding treatment, and growth starts from both the AlN underlayer 2 and the metal nitride microcrystals at the start of the growth of the group III nitride semiconductor layer. As a result, the effect of improving the crystallinity is small, and the direct contact ratio between the group III nitride semiconductor layer 8 and the AlN underlayer 2 is increased. When chemical lift-off is performed later, it is difficult for the etchant to penetrate and separation becomes difficult. Because. Further, when the thickness exceeds 500 nm, the nitriding time becomes long and the productivity is remarkably lowered, and the driving force for solid phase epitaxial growth from the AlN underlayer 2 is lowered. This is because the crystallinity of the group III nitride semiconductor layer 8 formed on the III nitride semiconductor layer 8 formed on the III-nitride semiconductor layer 8 formed thereon cannot be obtained even if the crystallinity is not sufficient, and the effect of improving the crystallinity by ELO growth cannot be compensated. .

第一の金属層３に連続して第二の金属層４を設けることにより、第一の金属層３の大気による酸化およびプラズマCVD内での酸化を抑制し、その後、部分的にエッチングにより露出され、窒化され、III族窒化物半導体層８の成長面となる第一の金属層３の表面を清浄に保つことが可能となる。第二の金属層４を第一の金属層３とSiO2マスク材５との間に挿入することによる効果を図２〜４に示す。図２は第一の金属層３としてのCr層上に直接プラズマCVDでSiO2マスク材５を100ｎｍ成膜した後、バッファードフッ酸でSiO2膜を除去したCr表面の酸化状態をX線光電子分光（XPS)法で評価した結果である。ここで示すのはCr2ｐ3/2ならびにCr2p1/2のスペクトルであり、夫々２つのピークから成り立っている。それぞれ高エネルギー側はメタルCr、低エネルギー側は酸化したCrの状態である事を示している。図３は、Cr層上に連続して第二の金属層４としてTi層を１０ｎｍ成膜した後に、プラズマCVD法でSiO2を同じく１００ｎｍ成膜した試料を、同様にバッファードフッ酸を用いてSiO2およびTi層を除去した場合のCr表面のXPSスペクトルである。これらの比較から、プラズマCVD法でSiO2を成膜する際の酸化を後者は大幅に回避できる事が分かる。   By providing the second metal layer 4 continuously to the first metal layer 3, the oxidation of the first metal layer 3 in the atmosphere and the oxidation in the plasma CVD are suppressed, and then partially exposed by etching. Then, the surface of the first metal layer 3 that is nitrided and becomes the growth surface of the group III nitride semiconductor layer 8 can be kept clean. The effect of inserting the second metal layer 4 between the first metal layer 3 and the SiO2 mask material 5 is shown in FIGS. Fig. 2 shows X-ray photoelectron spectroscopy of the oxidation state of the Cr surface after the SiO2 mask material 5 is deposited 100 nm directly on the Cr layer as the first metal layer 3 by plasma CVD and then the SiO2 film is removed with buffered hydrofluoric acid. It is the result evaluated by (XPS) method. Shown here are Cr2p3 / 2 and Cr2p1 / 2 spectra, each consisting of two peaks. The high energy side shows the state of metal Cr, and the low energy side shows the state of oxidized Cr. FIG. 3 shows a sample in which a Ti layer is continuously formed as a second metal layer 4 on the Cr layer to a thickness of 10 nm, and then a SiO 2 film is similarly formed to a thickness of 100 nm by the plasma CVD method, similarly using buffered hydrofluoric acid. It is an XPS spectrum of the Cr surface when the SiO2 and Ti layers are removed. From these comparisons, it can be seen that the latter can largely avoid oxidation when depositing SiO2 by plasma CVD.

図４は図３に示した条件のうちTi層の厚みを２ｎｍとした場合の結果であり、Cr表面の酸化程度は直接Cr表面にSiO２を成膜した場合よりも少ないものの、酸化を回避できなかった事がわかる。従って第二の金属層は所定の平均厚み、すなわち５ｎｍ〜２０ｎｍの範囲で成膜する。図２〜４で示したように、５ｎｍ未満であると第一の金属表面が一部露呈してしまう、あるいは局所的に膜厚が薄い部分がある為、第二の金属層上にプラズマCVD法でSiO2などのマスク材を成膜する際に、第一の金属表面を酸化させてしまう危険性が高い為である。また、平均膜厚が２０ｎｍを越える場合には、第二の金属層をエッチングする際に、レジスト下のSiO２などのマスク材のアンダーカットおよびSiO2下の第二の金属層自身のアンダーカットが進行してしまうため、寸法精度の悪化が生じたり、パターンマスクが剥離してしまうなどの問題を生じる為である。   FIG. 4 shows the results when the thickness of the Ti layer is 2 nm among the conditions shown in FIG. 3. Although the degree of oxidation of the Cr surface is less than that when the SiO2 film is directly formed on the Cr surface, the oxidation can be avoided. I can see that there wasn't. Therefore, the second metal layer is formed in a predetermined average thickness, that is, in the range of 5 nm to 20 nm. As shown in FIGS. 2 to 4, when the thickness is less than 5 nm, the first metal surface is partially exposed, or there is a portion where the film thickness is locally thin. Therefore, plasma CVD is performed on the second metal layer. This is because there is a high risk of oxidizing the first metal surface when a mask material such as SiO2 is formed by this method. When the average film thickness exceeds 20 nm, when the second metal layer is etched, the undercut of the mask material such as SiO2 under the resist and the undercut of the second metal layer itself under the SiO2 progress. Therefore, problems such as deterioration in dimensional accuracy and peeling of the pattern mask occur.

前記第一の金属層３ならびに第二の金属層４を成膜した後、プラズマCVD法で基板温度３５０℃程度でSiO2膜５を１００ｎｍ〜１０００ｎｍの厚みで成膜する。１００ｎｍ未満の厚みでは微細なピンホールなどが残り、マスク下の金属層が局所的に窒化反応して体積膨張し、マスク材を変形させたり亀裂が入るなど、保護膜的な面で不十分である事に加え、成長層と下地基板の分離、即ちケミカルリフトオフ時に側面からのエッチング液の浸透性が低下し、エッチング時間短縮の効果が薄れる為である。SiO2の膜厚が１０００ｎｍを超える場合、パターンマスク形成時のウエットエッチングでレジスト下のアンダーカットが大きくなる。パターン間隔が例えば２μm間隔のように狭い場合には、レジスト直下のSiO2がエッチングされてしまい、エッチングの途中でレジストの剥離が生じ、基板全面で均一なマスクパターンの形成が困難と言う問題が生じ易い。またSiO2膜厚が厚い場合、開口部への反応ガス・原料ガスの供給が不均一になり、成長初期過程でIII族窒化物半導体層が均一に成長し難い場合がある為、SiO2の膜厚は好ましくは１００ｎｍ〜５００ｎｍの範囲である。   After the first metal layer 3 and the second metal layer 4 are formed, the SiO2 film 5 is formed to a thickness of 100 nm to 1000 nm at a substrate temperature of about 350 [deg.] C. by plasma CVD. If the thickness is less than 100 nm, fine pinholes remain, the metal layer under the mask locally undergoes nitriding reaction, volume expansion, deformation of the mask material, cracks, etc. In addition to this, when the growth layer and the base substrate are separated, that is, when the chemical lift-off occurs, the permeability of the etching solution from the side surface is reduced, and the effect of shortening the etching time is diminished. When the thickness of SiO2 exceeds 1000 nm, the undercut under the resist becomes large due to wet etching when forming the pattern mask. When the pattern interval is narrow, for example, 2 μm, the SiO2 directly under the resist is etched, and the resist is peeled off during the etching, which makes it difficult to form a uniform mask pattern on the entire surface of the substrate. easy. In addition, when the SiO2 film is thick, the supply of reaction gas and source gas to the opening becomes non-uniform, and the group III nitride semiconductor layer may not grow uniformly in the initial growth process. Is preferably in the range of 100 nm to 500 nm.

なお、III族窒化物半導体層８の成長開始段階で、第一の金属層の窒化物７を核として成長し、マスク上では成長が開始しないという選択性が必要であるとともに成長温度での耐熱性、フォトリソグラフでのパターン形成容易さ（第二の金属層の同時除去）など、総合的な面でSiO2もしくはSiONが良い。   In addition, at the stage of starting the growth of the group III nitride semiconductor layer 8, it is necessary to have the selectivity that the nitride 7 of the first metal layer is used as a nucleus and the growth does not start on the mask, and heat resistance at the growth temperature is required. SiO2 or SiON is good in terms of overall characteristics such as operability and ease of pattern formation by photolithography (simultaneous removal of the second metal layer).

前記マスク材５であるSiO2を成膜の後、フォトレジストをスピン塗布し、プレベークの後、露光、現像、リンス洗浄を行い、レジストに開口部６’を有するパターンマスク６を形成する。   After the formation of SiO2 as the mask material 5, a photoresist is spin-coated, and after pre-baking, exposure, development, and rinsing are performed to form a pattern mask 6 having an opening 6 'in the resist.

次いで、バッファードフッ酸や希釈したフッ酸溶液で開口部６’に露呈したSiO2ならびに第二の金属層４をエッチング除去する。次いで、レジストをアセトン、レジスト剥離液などを用いて除去し、洗浄・乾燥を行い、SiO2パターンマスクが形成された状態とする。   Next, the SiO2 exposed to the opening 6 'and the second metal layer 4 are removed by etching with buffered hydrofluoric acid or diluted hydrofluoric acid solution. Next, the resist is removed using acetone, a resist stripping solution, etc., and cleaning and drying are performed to obtain a state in which the SiO2 pattern mask is formed.

前記SiO2パターンマスクが形成され、第一の金属層３がマスクの開口部に露出された基板を、III族窒化物半導体層の成長装置に導入し高純度水素または窒素あるいはHe、Arガスの単体もしくは混合ガス雰囲気中で昇温し、第一の金属層３が窒化を開始する温度よりも若干低い温度から例えば高純度アンモニアガスの供給を開始する。アンモニアガスは前記ガスをキャリアガスとして混合ガスの状態で供給する。窒化処理の最高温度を窒化温度、その温度での保持時間を窒化時間と定義する。   The substrate on which the SiO2 pattern mask is formed and the first metal layer 3 is exposed at the opening of the mask is introduced into a group III nitride semiconductor layer growth apparatus, and a single unit of high-purity hydrogen, nitrogen, He, or Ar gas Alternatively, the temperature is raised in a mixed gas atmosphere, and for example, the supply of high-purity ammonia gas is started at a temperature slightly lower than the temperature at which the first metal layer 3 starts nitriding. The ammonia gas is supplied in the form of a mixed gas using the gas as a carrier gas. The maximum temperature of nitriding is defined as the nitriding temperature, and the holding time at that temperature is defined as the nitriding time.

温度が低い場合、窒化反応が遅い為、処理時間を長くとる必要があり、高温の場合には、時間を短時間とする。それだけでなく下地層２からの固相エピタキシャル成長の駆動力によって、原子の再配列によって金属窒化物バッファとして結晶構造、配向、面内のドメイン回転揺らぎの抑制された状態を制御する必要が有る。以下HVPE法の例で言うと、反応管口径が約φ80ｍｍの場合アンモニアガスの流量は1000sccm程度で行う。第一の金属層３がCrの場合、窒化温度約600℃の温度からアンモニアガスの供給を開始する。炉の昇温速度は約30℃／分であり、窒化温度としては900℃以上1200℃以下の温度で、窒化時間としては1分以上90分以下が好ましい。窒化時間に関しては金属の膜厚が薄い場合には短時間、厚い場合には長めに適宜この範囲内で調整すれば良い。AlNが下地層２の場合、サファイア基板に比べ固相エピタキシャル成長の駆動力が大きい為、サファイア基板上での窒化処理温度、窒化時間よりも低温側でかつ短時間で良好な結果が得られる。   Since the nitriding reaction is slow when the temperature is low, it is necessary to take a long processing time. When the temperature is high, the time is short. In addition, it is necessary to control the crystal structure, orientation, and in-plane domain rotation fluctuation suppressed state as a metal nitride buffer by the rearrangement of atoms by the driving force of solid phase epitaxial growth from the underlayer 2. In the following example of the HVPE method, when the reaction tube diameter is about φ80 mm, the flow rate of ammonia gas is about 1000 sccm. When the first metal layer 3 is Cr, the supply of ammonia gas is started at a temperature of about 600 ° C. for nitriding. The heating rate of the furnace is about 30 ° C./minute, the nitriding temperature is preferably 900 ° C. or higher and 1200 ° C. or lower, and the nitriding time is preferably 1 minute or longer and 90 minutes or shorter. The nitriding time may be adjusted within this range as appropriate in a short time when the film thickness of the metal is thin and long when it is thick. When AlN is the underlayer 2, since the driving force for solid phase epitaxial growth is larger than that of the sapphire substrate, good results can be obtained in a short time at a temperature lower than the nitriding temperature and nitriding time on the sapphire substrate.

パターンマスク開口部に露呈した第一の金属層３を窒化処理した後、III族窒化物半導体初期成長層を成長する温度に基板温度を調整する。III族窒化物半導体層８がGaNの場合９００℃に調整する。この場合、キャリアガスの流量は、V／III比や成長速度設定の為に適宜条件を変更する。成長開始準備が整ったならば、850℃に加熱した金属Gaの上流側からキャリアガスと伴に塩酸ガスを流し始め、GaCl含有原料ガスを生成する。生成されたGaCl含有原料ガスを基板近傍でアンモニア混合ガスと混合して、基板表面に供給し、開口部に露呈した第一の金属層の金属窒化物層７を核としてGaNの結晶成長を開始させる。この時、SiO2膜５上にはGaNの成長が生じないと言う、所謂選択成長がなされる。塩酸ガスの流量は80sccmとし例えば5分間の成長を行う。次いでファセット成長を実施するため、基板温度を１０２０乃至１０４０℃まで昇温し、例えば１０分間の成長を行う。この場合、ファセット面を維持しつつ、マスク材であるSiO2膜５を覆うように横方向成長させマスク中央部でGaN結晶が合体した状況に到ったならば、V溝やピットを埋め込んで平坦化させるため、例えば基板温度をさらに１０６０乃至１０８０℃程度まで昇温して成長を継続する。その際、ガス流量やV/III比も適宜調整するのが好ましい。所望の成長厚みとなった段階で塩酸ガスの供給を停止し、冷却を開始する。アンモニアガスの供給は基板温度が600℃以下となった段階で停止し、窒素雰囲気で冷却を行う。取り出し可能な温度まで冷却した後、基板を装置から取り出して成長を終了する。   After nitriding the first metal layer 3 exposed in the pattern mask opening, the substrate temperature is adjusted to a temperature at which the group III nitride semiconductor initial growth layer is grown. When the group III nitride semiconductor layer 8 is GaN, the temperature is adjusted to 900 ° C. In this case, the flow rate of the carrier gas is appropriately changed in order to set the V / III ratio and the growth rate. When preparation for starting growth is completed, a hydrochloric acid gas is started to flow along with the carrier gas from the upstream side of the metallic Ga heated to 850 ° C. to generate a GaCl-containing source gas. The generated GaCl-containing source gas is mixed with an ammonia mixed gas in the vicinity of the substrate, supplied to the substrate surface, and crystal growth of GaN starts with the metal nitride layer 7 of the first metal layer exposed at the opening as a nucleus. Let At this time, so-called selective growth is performed in which no growth of GaN occurs on the SiO 2 film 5. The flow rate of hydrochloric acid gas is 80 sccm, and growth is performed for 5 minutes, for example. Next, in order to perform facet growth, the substrate temperature is raised to 1020 to 1040 ° C., for example, for 10 minutes. In this case, while maintaining the facet surface, if the lateral growth is performed so as to cover the SiO2 film 5 which is the mask material and the GaN crystal is united at the center of the mask, the V groove and pits are buried and flattened. In order to achieve this, for example, the substrate temperature is further raised to about 1060 to 1080 ° C. and the growth is continued. At that time, it is preferable to appropriately adjust the gas flow rate and the V / III ratio. When the desired growth thickness is reached, the supply of hydrochloric acid gas is stopped and cooling is started. The supply of ammonia gas is stopped when the substrate temperature reaches 600 ° C. or lower, and cooling is performed in a nitrogen atmosphere. After cooling to a temperature where it can be taken out, the substrate is taken out of the apparatus and the growth is finished.

図５は、第一の金属層３とプラズマCVD法によるSiO2膜５との間に第二の金属層４を挿入した場合と、第一の金属層３に直接SiO２膜５を成膜した場合の両者につき、SiO2の膜厚を変えてIII族窒化物半導体層８を成膜する際の、成長初期過程の比較を示したものである。この場合、第一の金属層３がCrで平均厚みは２0ｎｍあり、第二の金属層４がTiで平均膜厚は０、１０，２０ｎｍであり、SiO2膜５の膜厚は３００、５００ｎｍであり、III族窒化物半導体層８はGaNであり、成長はHVPE法によった。ELO成長用のパターンマスクはストライプ状とし、マスク部および開口部の寸法は夫々１０μｍとした。また、ストライプの方向はAlN下地２の結晶方位＜１−１００＞方向と平行とした。第一に、SiO2マスク厚みが同じ場合には第二の金属層４であるTiを挿入した場合のほうが直接第一の金属層３であるCr上に直接SiO2を成膜した場合に比べ、{１１−２２}ファセット形成状況が明らかに良好である事が分かる。第二にSiO2の厚み依存性では、３００ｎｍと５００ｎｍの比較では、前者の方がファセット形成状況が良好で有ることが分かる。SiO２が５００ｎｍの場合、第二の金属層を挿入しない場合、ファセットそのもの形成が殆どなされないが、Tiを挿入した場合にはファセットが良好に形成される事が分かる。以上より、第二の金属層４を設けることにより、第一の金属層３の表面酸化が回避され、第一の金属層の窒化後の結晶性を良好にするため、それを核として成膜する際のIII族窒化物半導体層８の結晶性が良好となるものと考えられ、その効果が大きいことが分かる。   FIG. 5 shows the case where the second metal layer 4 is inserted between the first metal layer 3 and the SiO 2 film 5 by the plasma CVD method, and the case where the SiO 2 film 5 is directly formed on the first metal layer 3. In both cases, a comparison of the initial growth process when forming the group III nitride semiconductor layer 8 by changing the film thickness of SiO 2 is shown. In this case, the first metal layer 3 is Cr and the average thickness is 20 nm, the second metal layer 4 is Ti and the average film thickness is 0, 10, 20 nm, and the SiO2 film 5 has a film thickness of 300 and 500 nm. The group III nitride semiconductor layer 8 is GaN, and the growth is based on the HVPE method. The pattern mask for ELO growth was striped, and the dimensions of the mask part and the opening part were 10 μm. The stripe direction was parallel to the crystal orientation <1-100> direction of the AlN substrate 2. First, when the SiO2 mask thickness is the same, when the Ti, which is the second metal layer 4, is inserted, compared to the case where the SiO2 is directly formed on the Cr, which is the first metal layer 3, { 11-22} It can be seen that the facet formation is clearly good. Secondly, regarding the thickness dependence of SiO2, it can be seen that the facet formation is better in the former when comparing 300 nm and 500 nm. When SiO2 is 500 nm, the facet itself is hardly formed when the second metal layer is not inserted, but the facet is formed well when Ti is inserted. As described above, by providing the second metal layer 4, surface oxidation of the first metal layer 3 is avoided, and the crystallinity of the first metal layer after nitriding is improved. It can be seen that the crystallinity of the group III nitride semiconductor layer 8 is improved, and the effect is great.

次に、成長初期過程のファセット成長でマスク中央において、図６に示すように結晶間が合体しV溝列もしくはピット列を形成した後、これらを埋め込ませるために、成長温度を上昇させるあるいはV/III比を変更するなどの手法により、最表面が平坦化するように結晶成長を行った。成長したGaN層の平均膜厚は約３０μｍであった。得られた結晶の転位密度を評価する為に、２１０℃の熱リン酸中で３分のエッチングを実施し、転位に対応したピット密度を評価したところ、１．５×１０7／ｃｍ２と言う結果が得られた。その値は、ほぼ同一のGaN厚みの場合で通常達成されている１．０×１０８／ｃｍ２に比べ一桁近い転位密度低減効果を有することが分かった。また、第一の金属層３だけでなく、化学エッチングが可能な第二の金属層４ならびにSiO2層５を介在させたため、第一の金属層３だけの場合に比べ、側面からの化学エッチング液の供給が効率的に実施できるようになったなので、ケミカルリフトオフ時間の大幅な短縮が可能となる。 Next, in facet growth in the initial stage of growth, at the center of the mask, as shown in FIG. 6, the crystals are merged to form a V groove array or pit array, and then the growth temperature is increased or V Crystal growth was performed so as to flatten the outermost surface by changing the / III ratio. The average film thickness of the grown GaN layer was about 30 μm. In order to evaluate the dislocation density of the obtained crystal, etching was performed in hot phosphoric acid at 210 ° C. for 3 minutes, and the pit density corresponding to the dislocation was evaluated to be 1.5 × 10 7 / cm 2. Results were obtained. The value was found to have an effect of reducing the dislocation density by almost an order of magnitude compared to 1.0 × 10 8 / cm 2 that is normally achieved in the case of almost the same GaN thickness. Further, since not only the first metal layer 3 but also the second metal layer 4 and the SiO2 layer 5 capable of chemical etching are interposed, the chemical etching liquid from the side surface is compared with the case of only the first metal layer 3. As a result, the chemical lift-off time can be greatly shortened.

次に第二の金属層４であるTiの厚みを１０ｎｍ、SiO2膜５の厚みを３００ｎｍとし、第一の金属層３であるCrの平均膜厚を２５ｎｍ、１００ｎｍ、３００ｎｍ、５００ｎｍとして、Cr層の厚みとIII族窒化物半導体層８の結晶性との関係を調べた。SiO2のパターンマスクはストライプ状で、マスク幅・開口部幅は各々１０μｍとし、下地AlN（０００１）単結晶層２の＜１−１００＞方向とストライプ方向を一致させた。Cr層の窒化温度および窒化時間は、Cr層の膜厚に応じて１０５０〜１０８０℃、３〜６０分の間で調整した。III族窒化物半導体層８はGaNであり、前述の方法により平均膜厚３０μmの成長を行った。得られたGaN層の結晶性をX線回折（XRD)の（０００２）、（１１−２０）回折ピークの半値幅（FWHM)で評価し、パターンマスクが無い場合との比較を行った。図７aは（０００２）回折、図７bは（１１−２０）回折の結果を比較した結果（図中▲で示したものが、パターンマスク有り）である。第一の金属層３であるCr層の平均膜厚は所定の膜厚（4ｎｍ）以上の範囲では膜厚が厚くなるに従い、半値幅は増加する傾向はパターンマスクが無い場合と同様で有るが、同じCr層の平均膜厚で比較すると、パターンマスクが無い場合に比べ、両回折ピークの半値幅は大幅に低減された事が分かる。Cr層が無く、直接AlN下地層上にGaNを成膜した場合には、（１１−２０）回折ピークの半値幅は１３６４arcsecで有ったが、Cr層があり、パターンマスクが無い場合はCr層の平均膜厚が３００ｎｍ程度までは改善効果が認められたが、パターンマスク有りの場合、５００ｎｍの平均膜厚においてもさらにそれ以上の改善効果が認められた。これは、Cr層を厚くする事で窒化処理後の金属窒化物層７の結晶性が、薄い場合に比べて低下してしまうものの、ELO成長による結晶性改善効果がそれを上回る事が出来た事によるものと考えられる。   Next, the thickness of Ti which is the second metal layer 4 is 10 nm, the thickness of the SiO2 film 5 is 300 nm, and the average film thickness of Cr which is the first metal layer 3 is 25 nm, 100 nm, 300 nm and 500 nm. And the crystallinity of the group III nitride semiconductor layer 8 were investigated. The SiO2 pattern mask was striped, the mask width and the opening width were each 10 μm, and the <1-100> direction of the underlying AlN (0001) single crystal layer 2 was matched with the stripe direction. The nitriding temperature and nitriding time of the Cr layer were adjusted between 1050 and 1080 ° C. and 3 to 60 minutes depending on the film thickness of the Cr layer. The group III nitride semiconductor layer 8 is GaN, and was grown with an average film thickness of 30 μm by the method described above. The crystallinity of the obtained GaN layer was evaluated by the half width (FWHM) of (0002) and (11-20) diffraction peaks of X-ray diffraction (XRD), and compared with the case without a pattern mask. FIG. 7a shows the result of comparison of (0002) diffraction and FIG. 7b shows the result of comparison of (11-20) diffraction. The average film thickness of the Cr layer as the first metal layer 3 has a tendency that the half-value width increases as the film thickness increases in the range of a predetermined film thickness (4 nm) or more, as in the case where there is no pattern mask. Compared with the average film thickness of the same Cr layer, it can be seen that the half-value widths of both diffraction peaks were significantly reduced as compared to the case without the pattern mask. When there was no Cr layer and GaN was formed directly on the AlN underlayer, the half width of the (11-20) diffraction peak was 1364 arcsec, but when there was a Cr layer and no pattern mask, Cr Although the improvement effect was recognized up to the average film thickness of the layer of about 300 nm, the improvement effect was further increased even with the average film thickness of 500 nm when the pattern mask was provided. Although the crystallinity of the metal nitride layer 7 after the nitriding treatment is lowered by increasing the thickness of the Cr layer, the crystallinity improving effect by ELO growth can be exceeded. It is thought to be due to things.

結晶性を最重視する或は、ケミカルリフトオフ時間の短縮による生産性向上を重視するかは、製造する窒化物半導体により異なるため、第一の金属層３の平均厚みは４〜５００ｎｍの範囲で適宜設定すれば良い。ケミカルリフトオフ時間の短縮を重視する場合は厚く設定すればよい。   Whether the emphasis on crystallinity or the emphasis on productivity improvement by shortening the chemical lift-off time depends on the nitride semiconductor to be manufactured, so the average thickness of the first metal layer 3 is suitably in the range of 4 to 500 nm. Set it. If importance is placed on shortening the chemical lift-off time, a thicker thickness may be set.

次に、使用するAlN下地層の結晶性と成膜したIII族窒化物結晶層８の結晶性との対応関係を調べ、マスクパターンが無い場合との比較を行った。比較のため、用いたAlN下地層は全てサファイア基板（０００１）面上に成膜したAlN（０００１）テンプレート基板およびサファイア基板表面を窒化処理してAlN層を形成した基板である。AlN層の厚みは０．００５から１２．５μｍの範囲であり、AlN層のXRD半値幅は（０００２）回折で５０から６００secの範囲、（１１−２０）回折では５５０から３５００secの範囲であった。   Next, the correspondence between the crystallinity of the AlN underlayer to be used and the crystallinity of the formed group III nitride crystal layer 8 was examined and compared with the case where there was no mask pattern. For comparison, the AlN underlayer used is an AlN (0001) template substrate formed on the sapphire substrate (0001) surface and a substrate on which the surface of the sapphire substrate is nitrided to form an AlN layer. The thickness of the AlN layer was in the range of 0.005 to 12.5 μm, and the XRD half width of the AlN layer was in the range of 50 to 600 seconds for (0002) diffraction and in the range of 550 to 3500 seconds for (11-20) diffraction. .

下地層２としてAlNを有する基板１上にスパッタリング法により第一の金属層３として平均膜厚３５ｎｍのCrを成膜の後、連続して第二の金属層４として平均厚み１０ｎｍのTiを成膜した。次いでプラズマCVD法により、３００ｎｍ厚みのSiO2膜マスク５を成膜の後、レジストスピン塗布、露光、現像、リンス洗浄を行いレジストパターン６を形成した。次いで、開口部に露出するSiO２部５ならびに直下の第二の金属層４であるTi層をバッファードフッ酸や希釈フッ酸溶液でエッチング除去し、SiO2マスク開口部に第一の金属層３であるCr層の表面が露呈された状態のパターンマスク形成基板を準備した。マスク部の幅ならびに開口部の幅がおのおの１０μｍで、下地AlN（０００１）基板の結晶方位＜１−１００＞に平行なストレイプパターンとした。以下、前述で示した成長条件で金属窒化物層７を形成し、III 族窒化物結晶層８としてGaN層を約３０μｍ成膜した。   A Cr film having an average film thickness of 35 nm is formed as a first metal layer 3 on a substrate 1 having AlN as an underlayer 2 by sputtering, and then Ti having an average thickness of 10 nm is formed as a second metal layer 4 continuously. Filmed. Next, a 300 nm thick SiO2 film mask 5 was formed by plasma CVD, and then resist spin coating, exposure, development, and rinse cleaning were performed to form a resist pattern 6. Next, the SiO 2 portion 5 exposed in the opening and the Ti layer, which is the second metal layer 4 immediately below, are removed by etching with buffered hydrofluoric acid or dilute hydrofluoric acid solution, and the first metal layer 3 is formed in the SiO 2 mask opening. A pattern mask forming substrate in which the surface of a certain Cr layer was exposed was prepared. The width of the mask part and the width of the opening part were each 10 μm, and the stripe pattern was parallel to the crystal orientation <1-100> of the underlying AlN (0001) substrate. Thereafter, the metal nitride layer 7 was formed under the above-described growth conditions, and a GaN layer of about 30 μm was formed as the group III nitride crystal layer 8.

得られたGaN層の結晶性を（０００２）および（１１−２０）XRD回折ピークの半値幅で評価した。図８aはｃ軸の揺らぎの指標である下地AlN層の（０００２）回折ピークの半値幅に対するGaN層の半値幅の関係を示したものである。用いたAlN下地層の半値幅の増加に伴い、成長したGaN層の半値幅は増加する傾向にあり、C軸の揺らぎを低減するためには、半値幅の狭いAlN下地基板を用いるのが好ましいが、マスクパターン有りの場合には用いたAlN下地層の半値幅よりも狭くすることが可能であった。一方、図８ｂは面内のドメイン回転の指標である（１１−２０）回折の結果であるが、AlN下地層の回転ドメインをCr窒化物層が緩和し、その上に成長したGaN結晶の回転ドメインは大幅に低減される。マスクパターンを用いた場合には、用いない場合に比べ貫通転位が更に抑制できる為、用いたAlN下地層の半値幅が３０００secまでは、実際の半導体素子製造において、問題の無い結晶性となる事が分かった。以上より、用いるAlN下地層の厚みが0.005μｍから10μｍで、AlN層のX線回折の半値幅が（０００２）、（１１−２０）がそれぞれ５００sec、３０００sec以下のものを用いる事によって、パターンマスクを用いたIII族窒化物半導体層の結晶性は実用レベルで充分に使用可能な状況まで向上できる。   The crystallinity of the obtained GaN layer was evaluated by the half width of (0002) and (11-20) XRD diffraction peaks. FIG. 8a shows the relationship of the half width of the GaN layer to the half width of the (0002) diffraction peak of the underlying AlN layer, which is an index of c-axis fluctuation. As the full width at half maximum of the AlN underlayer used increases, the full width at half maximum of the grown GaN layer tends to increase, and in order to reduce the fluctuation of the C axis, it is preferable to use an AlN undersubstrate with a narrow half width. However, in the case of having a mask pattern, it was possible to make it smaller than the half width of the AlN underlayer used. On the other hand, FIG. 8b shows the result of (11-20) diffraction, which is an index of in-plane domain rotation. The Cr nitride layer relaxes the rotation domain of the AlN underlayer, and the rotation of the GaN crystal grown thereon. Domains are greatly reduced. When the mask pattern is used, threading dislocations can be further suppressed as compared with the case where the mask pattern is not used. Therefore, when the half width of the used AlN underlayer is up to 3000 sec, crystallinity having no problem is produced in actual semiconductor element manufacturing. I understood. As described above, the pattern mask can be obtained by using the AlN underlayer having a thickness of 0.005 μm to 10 μm and the AlN layer having X-ray diffraction half widths of (0002) and (11-20) of 500 sec and 3000 sec, respectively. The crystallinity of the group III nitride semiconductor layer using can be improved to a sufficiently usable state at a practical level.

なお、パターンマスクを用いた場合、前述のように結晶性の大幅な向上が可能となる為、AlN層の厚みが０．００５μｍと極めて薄くとも、上記の半値幅以下を満たす場合には問題なく使用できる。ただし、AlN層の厚みが１０μｍを越える場合はAlNテンプレート製造の生産性が低下してしまうので、１０μｍ以下が好ましい。   When a pattern mask is used, the crystallinity can be greatly improved as described above. Therefore, there is no problem if the AlN layer is extremely thin, 0.005 μm, but satisfies the above half width or less. Can be used. However, when the thickness of the AlN layer exceeds 10 μm, the productivity of manufacturing the AlN template is lowered, so that the thickness is preferably 10 μm or less.

さらに、本発明の応用として、素子形成部においては結晶性向上を目的としパターンマスクを覆うように横方向成長させ結晶間同士が合体して連続平坦膜となるようにしつつ、素子間分離部においてはIII族窒化物半導体層が部分的にパターンマスクを覆うものの、成長終了後もパターンマスク上が連続膜で覆われない状況とすれば、個々の半導体素子の結晶性を向上するのと同時に、チップ状態でのケミカルリフトオフが可能となり、素子分離が容易になる。   Further, as an application of the present invention, in the element forming part, the element forming part is grown in the lateral direction so as to cover the pattern mask for the purpose of improving the crystallinity, and the crystals are combined to form a continuous flat film. Although the group III nitride semiconductor layer partially covers the pattern mask, if the pattern mask is not covered with a continuous film even after the growth is completed, the crystallinity of each semiconductor element is improved simultaneously. Chemical lift-off in a chip state is possible, and element isolation becomes easy.

この場合、ELO成長時のファセット成長、横方向成長ならびにV溝列・ピットの埋め込み、成長終了時の厚みなどで開口部からマスク上を覆う距離が異なるため、個々の素子のサイズに合わせて素子内パターンマスクのマスク部幅・開口部幅の寸法や、素子分離部のマスク幅寸法は適宜設定すれば良い。ただし、素子形成部のマスク幅Ldと素子間分離マスク幅Lsは最低限Ld＜Lsを満たす必要があり、３Ld≦Lsであることが好ましい。さらにはAlN（０００１）上の素子形成部のパターンマスクのストライプ方向は＜１−１００＞方向に平行であることが好ましく、四角形の素子の場合の素子の辺は＜１−１００＞方向に平行のものとそれに垂直な＜１１−２０＞方向に平行であり、素子分離用のマスク幅は＜１１−２０＞に平行なマスク幅Lｓ＜１１−２０＞よりも、＜１−１００＞に平行なマスク幅Lｓ＜１−１００＞を大きくとるのが好ましい。   In this case, the distance to cover the mask from the opening varies depending on the facet growth during ELO growth, lateral growth, V-groove row / pit embedding, thickness at the end of growth, etc. What is necessary is just to set suitably the dimension of the mask part width | variety of an inner pattern mask, the opening part width | variety, and the mask width dimension of an element isolation part. However, the mask width Ld and the element isolation mask width Ls of the element formation portion need to satisfy Ld <Ls at a minimum, and preferably 3Ld ≦ Ls. Further, the stripe direction of the pattern mask of the element formation portion on AlN (0001) is preferably parallel to the <1-100> direction, and the side of the element in the case of a square element is parallel to the <1-100> direction. The mask width for element isolation is parallel to <1-100> rather than the mask width Ls <11-20> parallel to <11-20>. It is preferable to increase the mask width Ls <1-100>.

以下、上記段落で説明したIII族窒化物半導体およびIII族窒化物半導体層を化学エッチングで下地基板から分離してえられる自立基板、半導体素子、ならびに分離されたIII族窒化物半導体を自立基板として用いた素子とその実施例につき説明する。   Hereinafter, a self-standing substrate obtained by separating the group III nitride semiconductor and the group III nitride semiconductor layer described in the above paragraph from the base substrate by chemical etching, a semiconductor element, and the separated group III nitride semiconductor as a self-standing substrate The elements used and examples thereof will be described.

（実施例１）
２インチのサファイア基板上のAlN（０００１）テンプレートのAlN厚みが１．０μｍ、XRD（０００２）回折の半値幅が約１００sec、（１１−２０）回折の半値幅が約１２００から１４００secのものを用い、第一の金属層であるCr層の平均厚みが３５ｎｍ、第二の金属層であるTi層の平均厚みを１０ｎｍスパッタリング法で連続成膜した。次いでプラズマCVD法により、SiO2膜を３００ｎｍ成膜の後、前述のパターンマスク工程でマスク幅・開口部幅が各々１０μｍとし、下地AlN層の＜１−１００＞方向に平行なストライプ状のパターンマスクを形成した。次いでHVPE装置に導入し窒化処理温度１０７０℃、窒化処理時間を５分として開口部に露呈するCrを窒化しCrN層を形成した。９００℃に基板温度を降下させ、開口部に露呈するCrNを核としてGaN結晶の選択成長を５分間実施し、一度成長を中断して１０４０℃まで基板温度を上昇後、ファセット成長ならびにマスク間の結晶合体、埋め込み開始の成長を１０分間行った。次いで基板温度を１０８０℃まで上昇させて、埋め込み・平坦化成長を１５分間実施し都合約３０μｍのGaN層を成長した。得られた結晶のXRD（０００２）、（１１−２０）回折ピークの半値幅は夫々７８sec、９０secと結晶性は非常に良好であった。３００μｍ角にスクライブ線を入れた後、室温のバッファードフッ酸中に２分間浸漬し、Ti層ならびにSiO2層をエッチングした。別途、エッチング経過時間を変えてエッチング進行状況を調べたところ、Ti層が先に溶解するためその部分にエッチング液が供給され、側面からだけでなく途中からはSiO2の厚み方向のエッチングが進行するため、Ti、およびSiO2は2分以内で完了する。次いで、純水で洗浄した後、８０℃の硝酸２セリウムアンモニウム系エッチング液でマスク直下に位置していたCr層ならびに開口部のCrN層をエッチングしたところ、約４分でエッチングが完了してGaN層が分離でき、パターンマスクが無い場合に比べ、トータルのエッチング時間が短縮できるとともに、結晶性は大幅に向上した。 Example 1
The AlN thickness of the AlN (0001) template on a 2-inch sapphire substrate is 1.0 μm, the half width of XRD (0002) diffraction is about 100 sec, and the half width of (11-20) diffraction is about 1200 to 1400 sec. The average thickness of the Cr layer as the first metal layer was 35 nm, and the average thickness of the Ti layer as the second metal layer was continuously formed by a 10 nm sputtering method. Next, after forming a 300 nm SiO 2 film by plasma CVD, the mask width and the opening width are each 10 μm in the pattern mask process described above, and a striped pattern mask parallel to the <1-100> direction of the underlying AlN layer Formed. Next, it was introduced into an HVPE apparatus, and the CrN layer was formed by nitriding Cr exposed to the opening with a nitriding temperature of 1070 ° C. and a nitriding time of 5 minutes. The substrate temperature is lowered to 900 ° C., selective growth of GaN crystal is performed for 5 minutes using CrN exposed in the opening as a nucleus, the growth is interrupted once, the substrate temperature is raised to 1040 ° C., and then facet growth and between masks The growth of crystal coalescence and embedding start was performed for 10 minutes. Next, the substrate temperature was raised to 1080 ° C., and burying / planarization growth was performed for 15 minutes to conveniently grow a GaN layer of about 30 μm. The obtained crystals had very good crystallinity, with half widths of XRD (0002) and (11-20) diffraction peaks of 78 sec and 90 sec, respectively. After a scribe line was put in a 300 μm square, the Ti layer and the SiO 2 layer were etched by dipping in buffered hydrofluoric acid at room temperature for 2 minutes. Separately, when the etching progress was examined by changing the etching elapsed time, the Ti layer was dissolved first, so the etching solution was supplied to that part, and the etching in the thickness direction of SiO2 progressed not only from the side but also from the middle Therefore, Ti and SiO2 are completed within 2 minutes. Next, after cleaning with pure water, the Cr layer located immediately below the mask and the CrN layer in the opening were etched with an 80 ° C. dicerium ammonium nitrate etching solution, and the etching was completed in about 4 minutes. Compared with the case where the layers can be separated and there is no pattern mask, the total etching time can be shortened and the crystallinity is greatly improved.

（実施例２）
実施例１に対し、第一の金属層であるCr層の平均厚みを１００ｎｍとし、窒化処理温度を１１００℃、窒化処理時間を１０分としたこと以外の条件を同一としGaN層を成長した。得られた結晶のXRD（０００２）、（１１−２０）回折ピークの半値幅はそれぞれ１１０sec、１９０secと良好であった。同じ平均膜厚のCr層でマスクパターンが無い場合に比べ、XRD半値幅が半分以下まで低減し、結晶性は大幅に向上した。３００μｍ角にスクライブ線を入れて、８０℃の硝酸２セリウムアンモニウム系エッチング液でエッチングしたところ、約３分でCr層ならびにCrN層のエッチングが完了した。引続きTi層およびSiO2層をバッファードフッ酸でエッチングしたところ、９０秒以内でエッチングが完了した。 (Example 2)
A GaN layer was grown under the same conditions as in Example 1 except that the average thickness of the Cr layer as the first metal layer was 100 nm, the nitriding temperature was 1100 ° C., and the nitriding time was 10 minutes. The half widths of XRD (0002) and (11-20) diffraction peaks of the obtained crystals were good at 110 sec and 190 sec, respectively. Compared to the Cr layer with the same average film thickness and no mask pattern, the XRD half-width was reduced to less than half and the crystallinity was greatly improved. When a scribe line was inserted into a 300 μm square and etched with an 80 ° C. 2 ceric ammonium nitrate etching solution, the etching of the Cr layer and the CrN layer was completed in about 3 minutes. Subsequently, when the Ti layer and the SiO2 layer were etched with buffered hydrofluoric acid, the etching was completed within 90 seconds.

（実施例３）
実施例1に対し、GaN成長厚みを５５０μｍとしたこと以外成長過程までは同じとした。この場合、自立基板を得ることを目的としたため、スクライブ線は入れずに基板側面からCr、CrN、Ti、SiO2層のエッチングを行った。まず、バッファードフッ酸中に浸漬し、Ti層ならびにSiO2をエッチングした。本エッチング液ではTiのほうがSiO2よりもエッチング速度が速く先行して溶解して行くため、SiO2は側面からだけでなくTiの溶解した面からのエッチングが進行する。エッチング液の浸透性を高める為、超音波でアシストしてエッチングを行ったところ、基板全面のTi、SiO2層は約４時間で溶解完了した。次いで、純水超音波リンス洗浄を行いエッチング液を除去した後、一旦真空加熱乾燥を１０分程度行いTiおよびSiO2のエッチングで形成されたトンネル部に純水が残らないようにした。次に８０℃の硝酸２セリウムアンモニウム液でCrおよびCrN層のエッチングしたところ約1時間で完全に溶解が完了し、下地AlNテンプレート基板とGaN成長層が分離でき、GaN自立基板を得る事ができた。得られたGaN自立基板の結晶性をXRD（０００２）、（１１−２０）回折ピークの半値幅で評価した結果、夫々４２sec、４８secと極めて良好であった。 (Example 3)
Compared to Example 1, the growth process was the same except that the GaN growth thickness was 550 μm. In this case, since the purpose was to obtain a self-supporting substrate, the Cr, CrN, Ti, and SiO2 layers were etched from the side surface of the substrate without inserting scribe lines. First, it was immersed in buffered hydrofluoric acid to etch the Ti layer and SiO2. In this etching solution, Ti has a higher etching rate than SiO 2 and dissolves in advance, so that SiO 2 is etched not only from the side but also from the surface where Ti is dissolved. In order to increase the permeability of the etching solution, etching was performed with the assistance of ultrasonic waves, and the Ti and SiO2 layers on the entire surface of the substrate were completely dissolved in about 4 hours. Next, pure water ultrasonic rinse cleaning was performed to remove the etching solution, and then vacuum heating and drying were performed for about 10 minutes, so that pure water did not remain in the tunnel portion formed by etching of Ti and SiO2. Next, when the Cr and CrN layers were etched with a ceric ammonium nitrate solution at 80 ° C., the dissolution was completely completed in about 1 hour. The underlying AlN template substrate and the GaN growth layer could be separated, and a GaN free-standing substrate could be obtained. It was. As a result of evaluating the crystallinity of the obtained GaN free-standing substrate with the half widths of XRD (0002) and (11-20) diffraction peaks, they were very good at 42 sec and 48 sec, respectively.

（実施例４）
Cr層の厚みを５００ｎｍとし、連続してTi層を２０ｎｍスパッタリング法で成膜した。次いで、プラズマCVD法により３００ｎｍ成膜した。以降、GaN成長終了まで実施例１と同じ条件とした。得られたGaN層の結晶性をXRD（０００２）、（１１−２０）回折ピークの半値幅で評価した結果、それぞれ３９０sec、８５２secであった。この場合、Cr層の厚みを厚くしてもInGaN系LED用途としては充分な結晶性を有し、ケミカルリフト性が良好なため、生産性面での効果が大きい。 Example 4
The thickness of the Cr layer was 500 nm, and a Ti layer was continuously formed by a 20 nm sputtering method. Next, a 300 nm film was formed by plasma CVD. Thereafter, the same conditions as in Example 1 were used until the GaN growth was completed. As a result of evaluating the crystallinity of the obtained GaN layer by the half width of the XRD (0002) and (11-20) diffraction peaks, they were 390 sec and 852 sec, respectively. In this case, even if the thickness of the Cr layer is increased, it has sufficient crystallinity for InGaN-based LED applications and good chemical lift properties, so that it is highly effective in terms of productivity.

（実施例５）
成長終了段階でIII族窒化物結晶層が、素子毎に分離した状態とするため、図９に示すような素子形成領域の直下のみに開口部を有するパターンマスクを準備した。素子寸法は1ｍｍ□であり、素子形成領域はAlN（０００１）下地の＜１−１００＞方向に平行なストライプ状の開口部・マスク部を交互にくりかえした。開口部幅・マスク幅Lｄとも１０μｍとした。HVPE法でのGaN層を３０μｍ成長することを想定し、素子の＜1−１００＞方向の素子分離用マスク幅Ls<1-100>ならびに素子の＜１１−２０＞方向の素子分離用マスク幅Ls<11-20>ともに２０、３０、５０μｍとして成長試験を実施した。パターンマスク形状が異なること以外は実施例１に示した方法でGaN層の成長を行った。その結果、＜１１−２０＞方向の素子分離用マスク幅が２０μmの場合、隣接素子間で成長膜が連続してしまったが、３０μｍ幅では分離マスクのほぼ中央位置で幅５〜１０μｍはマスク上にGaNは成長しておらず隣接素子間が分離された状態であった。また５０μｍ幅の場合にも、２５μｍ以上の幅の未成長領域があり、隣接素子間は分離された状態が実現された。一方、＜１−１００＞方向の素子分離用マスク幅が２０、３０，５０μmのいずれの場合でも、隣接素子間が分離された状態であった。 (Example 5)
In order to make the group III nitride crystal layer separated for each element at the end of the growth, a pattern mask having an opening just under the element formation region as shown in FIG. 9 was prepared. The element size was 1 mm □, and the element formation region was formed by alternately repeating striped openings and mask portions parallel to the <1-100> direction of the AlN (0001) base. Both the opening width and the mask width Ld were 10 μm. Assuming that the GaN layer is grown to 30 μm by the HVPE method, the element isolation mask width Ls <1-100> in the <1-100> direction of the element and the element isolation mask width in the <11-20> direction of the element The growth test was conducted for Ls <11-20> at 20, 30, and 50 μm. A GaN layer was grown by the method shown in Example 1 except that the pattern mask shape was different. As a result, when the element isolation mask width in the <11-20> direction is 20 μm, the growth film is continuous between adjacent elements. However, when the width is 30 μm, the width of 5 to 10 μm is approximately the center position of the isolation mask. On the top, GaN did not grow and the adjacent elements were separated. Further, even in the case of 50 μm width, there was an ungrown region having a width of 25 μm or more, and the adjacent element was separated. On the other hand, adjacent elements were separated from each other regardless of whether the element isolation mask width in the <1-100> direction was 20, 30, or 50 μm.

（比較例１）
実施例１に対して、パターンマスクが無い状態で比較した。サファイア基板上のAlN（０００１）層の厚みが１．０μｍのAlNテンプレートのXRD（０００２）回折の半値幅が約１００sec、（１１−２０）回折の半値幅が約１２００sec乃至１４００secのものを用いた。AlN（０００１）面上にCr層を平均層厚３５nm成膜し後（即ちパターンマスク無しで）、HVPE装置に導入し窒化処理温度が１０９５℃、窒化時間が1分としてCｒN層を形成した後、GaN層を12μｍ成長した。得られた結晶のXRD（０００２）回折の半値幅は１２１sec、（１１−２０）)回折の半値幅は２１０secと結晶性は実施例１よりも劣った。３００μm角にスクライブ線を入れて、８０℃の硝酸２セリウムアンモニウム系エッチング液でCrN層をエッチングしたところ、約８分でエッチングが完了しGaN層が分離できたが、実施例１のほうが短時間であった（本発明者を含む特願２００７−２２１７７４より）。 (Comparative Example 1)
Compared to Example 1, there was no pattern mask. An AlN template having a thickness of 1.0 μm on the sapphire substrate having an XRD (0002) diffraction half width of about 100 sec and an (11-20) diffraction half width of about 1200 sec to 1400 sec was used. . After forming a Cr layer on the AlN (0001) surface with an average layer thickness of 35 nm (that is, without a pattern mask), the CrN layer was introduced into the HVPE apparatus and the nitriding temperature was 1095 ° C. and the nitriding time was 1 minute. The GaN layer was grown to 12 μm. The obtained crystal had an XRD (0002) diffraction half-width of 121 sec and a (11-20)) diffraction half-width of 210 sec. The crystallinity was inferior to that of Example 1. When a CrN layer was etched with a cerium nitrate-based etchant at 80 ° C. with a scribe line at 300 μm square, the etching was completed and the GaN layer was separated in about 8 minutes. (From Japanese Patent Application No. 2007-221774 including the present inventor).

（比較例２）
サファイア（0001）基板上にCrをスパッタリング法で成膜させ窒化温度1080℃で30分の窒化処理を行った後、GaN成長を行った。初期のCr平均層厚は１０〜４０nmが好ましく、１０nm未満では結晶性の悪化が見られ、５０nm以上ではCrN層およびその上に成長させるGaNは、モザイク状ないし多結晶化してしまった（本発明者を含む特願２００６−２７２３２１より）。また、（０００２）回折の半値幅は２４０sec乃至５６０sec程度、また（１０−１１）もしくは（１１−２０）回折での半値幅は３７０sec乃至６５０sec程度の範囲であり、最良のものでも実施例の約６乃至８倍の半値幅である。単結晶膜が得られるCr層の上限膜厚も本願に比べ1／１０程度である。 (Comparative Example 2)
After Cr was deposited on a sapphire (0001) substrate by a sputtering method and a nitriding treatment was performed at a nitriding temperature of 1080 ° C. for 30 minutes, GaN was grown. The initial Cr average layer thickness is preferably 10 to 40 nm. When the thickness is less than 10 nm, the crystallinity is deteriorated. When the thickness is 50 nm or more, the CrN layer and the GaN grown thereon are mosaic-like or polycrystalline. (From Japanese Patent Application No. 2006-272321). Further, the half width of (0002) diffraction is about 240 sec to 560 sec, and the half width of (10-11) or (11-20) diffraction is about 370 sec to 650 sec. The half width is 6 to 8 times. The upper limit thickness of the Cr layer from which a single crystal film can be obtained is also about 1/10 that of the present application.

実施例１〜５及び比較例から明らかなように、AlN上に第一の金属であるCrと、その上に第二の金属であるTiを連続して成膜し、SiO2パターンマスクの開口部のエッチングの際にTi層を除去し、露呈したCｒを窒化処理したCrNをIII族成長開始時の選択成長核として用い、ELO成長を行う本方式は、比較例に比べ大幅な結晶性の向上がなされている。   As is apparent from Examples 1 to 5 and the comparative example, Cr, which is the first metal, and Ti, which is the second metal, are continuously formed on AlN, and the opening of the SiO2 pattern mask. This method, which removes the Ti layer during etching and nitridizes the exposed Cr as a selective growth nucleus at the start of group III growth and performs ELO growth, greatly improves the crystallinity compared to the comparative example Has been made.

さらには、第二の金属層およびマスク材も下地基板とIII族窒化物結晶の化学エッチングによる分離に寄与させることができ、結晶性の向上とケミカルリフトオフ時間の短縮による生産性向上など多大なる貢献をしている。   Furthermore, the second metal layer and mask material can also contribute to the separation of the base substrate and the group III nitride crystal by chemical etching, making significant contributions such as improving crystallinity and improving productivity by reducing chemical lift-off time. I am doing.

以上、実施の形態および実施例において具体例を示しながら本発明を詳細に説明したが、本発明は上記発明の実施の形態および実施例に限定されるものではなく、本発明の範疇を逸脱しない範囲であらゆる変更や変形が可能である。第一の金属層の表面酸化を防止するという目的を果たせば、第二の金属の成膜前に第一の金属層を窒化してもよく、レジストパターンを先に付与してリフトオフしても良い。製造方法の順番は種々検討できる。   While the present invention has been described in detail with specific examples in the embodiments and examples, the present invention is not limited to the above-described embodiments and examples and does not depart from the scope of the present invention. All changes and modifications are possible within the scope. If the purpose of preventing the surface oxidation of the first metal layer is achieved, the first metal layer may be nitrided before the second metal film is formed, or the resist pattern is first applied and lifted off. good. Various orders of manufacturing methods can be studied.

本発明は、III族窒化物半導体の製造に適用できる。   The present invention can be applied to the manufacture of group III nitride semiconductors.

本発明の製造工程の例を示す説明図である。It is explanatory drawing which shows the example of the manufacturing process of this invention. Cr層上にプラズマCVD法でSiO2膜を成膜した試料のSiO2膜をバッファードフッ酸で溶解除去した後のCr層表面のXPSスペクトルを示すグラフである。4 is a graph showing an XPS spectrum on the surface of a Cr layer after dissolving and removing the SiO2 film of a sample in which a SiO2 film is formed on the Cr layer by a plasma CVD method with buffered hydrofluoric acid. Cr層上に連続してTi層を１０ｎｍ成膜した上にプラズマCVD法でSiO2膜を成膜した試料のSiO2およびTi層をバッファードフッ酸で溶解除去した後のCr層表面のXPSスペクトルを示すグラフである。The XPS spectrum of the Cr layer surface after dissolving and removing the SiO2 and Ti layers of the sample in which the Ti layer was continuously formed on the Cr layer by 10 nm and the SiO2 film was formed by plasma CVD using buffered hydrofluoric acid It is a graph to show. Cr層上に連続してTi層を２ｎｍ成膜した上にプラズマCVD法でSiO2膜を成膜した試料のSiO2およびTi層をバッファードフッ酸で溶解除去した後のCr層表面のXPSスペクトルを示すグラフである。An XPS spectrum of the Cr layer surface after dissolving and removing the SiO2 and Ti layers with a buffered hydrofluoric acid sample after depositing a 2 nm Ti layer continuously on the Cr layer and then depositing the SiO2 film by the plasma CVD method It is a graph to show. SiO2膜厚ならびに第二の金属層（Ti)の有無による、GaN成長初期過程でのファセット形成状態に与える影響を示した説明図である。It is explanatory drawing which showed the influence which it has on the facet formation state in the initial stage of GaN growth by the presence or absence of SiO2 film thickness and the 2nd metal layer (Ti). ファセット成長からV溝列・ピット埋め込み、平坦化成長に到る成長過程の説明図である。It is explanatory drawing of the growth process from facet growth to V groove | channel row | line | column pit embedding, and planarization growth. （a）Cr層の平均膜厚とGaN層のXRD（０００２）回折ピークの半値幅の関係の、パターンマスク有りと無しの場合の比較を示すグラフである。（b）Cr層の平均膜厚とGaN層のXRD（１１−２０）回折ピークの半値幅の関係の、パターンマスク有りと無しの場合の比較を示すグラフである。(A) It is a graph which shows the comparison with and without a pattern mask of the relationship between the average film thickness of Cr layer, and the half value width of the XRD (0002) diffraction peak of a GaN layer. (B) It is a graph which shows the comparison with and without a pattern mask of the relationship between the average film thickness of Cr layer, and the half value width of the XRD (11-20) diffraction peak of a GaN layer. （a）下地AlN層の（０００２）回折ピークの半値幅とGaN層の（０００２）回折ピークの半値幅について、パターンマスク有りと無しの場合の依存性を示すグラフである。（b）下地AlN層の（１１−２０）回折ピークの半値幅とGaN層の（１１−２０）回折ピークの半値幅について、パターンマスク有りと無しの場合の依存性を示すグラフである。(A) It is a graph which shows the dependence with and without a pattern mask about the half value width of the (0002) diffraction peak of a base AlN layer, and the half value width of the (0002) diffraction peak of a GaN layer. (B) It is a graph which shows the dependence with and without a pattern mask about the half value width of the (11-20) diffraction peak of a base AlN layer, and the half value width of the (11-20) diffraction peak of a GaN layer. 素子形成領域と素子分離用マスクについて方位や寸法などの説明図である。It is explanatory drawing, such as an azimuth | direction and a dimension, about an element formation area and an element isolation mask.

Claims (9)

基板上にＡｌＮ単結晶層またはＡｌを含むIII族窒化物単結晶層を０．００５μm以上１０μm以下の厚みで形成したAlNテンプレート基板又はサファイア基板を窒化処理したAlNテンプレート基板、もしくはＡｌＮ単結晶基板上に、金属層を成膜する工程と、該金属層の上に開口部を有するパターンマスク膜を形成する工程と、マスク開口部に露呈した部位の金属層をアンモニア混合ガス雰囲気中で加熱処理を行い金属窒化物層を形成する工程と、該金属窒化物層を核としてIII族窒化物半導体層を成膜する工程を有することを特徴とする、III族窒化物半導体の製造方法。 On an AlN template substrate formed by forming an AlN single crystal layer or a group III nitride single crystal layer containing Al with a thickness of 0.005 μm to 10 μm on the substrate, or an AlN template substrate obtained by nitriding a sapphire substrate, or an AlN single crystal substrate In addition, a step of forming a metal layer, a step of forming a pattern mask film having an opening on the metal layer, and a heat treatment of the metal layer exposed at the mask opening in an ammonia mixed gas atmosphere And a step of forming a metal nitride layer, and a step of forming a group III nitride semiconductor layer using the metal nitride layer as a nucleus. 更に、成膜されたIII族窒化物半導体層を、前記ＡｌＮテンプレート基板もしくはＡｌＮ単結晶基板と分離する工程を有することを特徴とする、請求項１に記載のIII族窒化物半導体の製造方法。 The method for manufacturing a group III nitride semiconductor according to claim 1, further comprising a step of separating the formed group III nitride semiconductor layer from the AlN template substrate or the AlN single crystal substrate. 前記金属層は、金属窒化物を形成するための第一の金属層と、第一の金属層上に成膜され、マスク材成膜時に第一の金属層表面の酸化を防止するとともにマスク開口部を形成する工程でマスク材と同時に除去可能な第二の金属層からなり、第一の金属層がCr、Sc、V，Nbから選択された少なくとも1種類以上を含む単層膜・多層膜・合金膜であり、第二の金属層がTi、Zr、Hfから選択された少なくとも1種類以上を含む、単層膜・多層膜・合金膜で構成されることを特徴とする、請求項１または２に記載のIII族窒化物半導体の製造方法。 The metal layer is formed on the first metal layer and the first metal layer for forming the metal nitride, and prevents the oxidation of the surface of the first metal layer when the mask material is formed and the mask opening. A single layer film / multilayer film comprising a second metal layer that can be removed simultaneously with the mask material in the step of forming the first portion, wherein the first metal layer includes at least one selected from Cr, Sc, V, and Nb The alloy film, wherein the second metal layer is composed of a single layer film, a multilayer film, or an alloy film containing at least one selected from Ti, Zr, and Hf. Or a method for producing a group III nitride semiconductor as described in 2 above. 第一の金属層と第二の金属層は連続して成膜されることを特徴とする、請求項３に記載のIII族窒化物半導体の製造方法。 4. The method for producing a group III nitride semiconductor according to claim 3, wherein the first metal layer and the second metal layer are continuously formed. 前記第一の金属層の窒化前の平均膜厚が４〜５００nmの範囲であり、前記第二の金属層の平均厚さが５〜２０nmの範囲であることを特徴とする、請求項３または４に記載のIII族窒化物半導体の製造方法。 The average thickness of the first metal layer before nitriding is in the range of 4 to 500 nm, and the average thickness of the second metal layer is in the range of 5 to 20 nm. 5. A method for producing a group III nitride semiconductor according to 4. 前記パターンマスク膜がSiO2もしくはSiONから構成されることを特徴とする、請求項１〜５のいずれかに記載のIII族窒化物半導体の製造方法。 The method for producing a group III nitride semiconductor according to claim 1, wherein the pattern mask film is made of SiO 2 or SiON. 前記パターンマスク膜が、プラズマ化学気相堆積（PCVD）法、蒸着法、反応性スパッタ法、熱化学気層堆積（LPCVD）法のいずれかで形成され、膜厚が１００〜１０００nmの範囲であることを特徴とする、請求項１〜６のいずれかに記載のIII族窒化物半導体の製造方法。   The pattern mask film is formed by any one of a plasma chemical vapor deposition (PCVD) method, a vapor deposition method, a reactive sputtering method, and a thermal chemical vapor deposition (LPCVD) method, and has a thickness in the range of 100 to 1000 nm. The method for producing a group III nitride semiconductor according to any one of claims 1 to 6, wherein: 前記アンモニアガス雰囲気での金属層の加熱窒化温度が９００〜１２００℃の範囲であり、窒化時間が1分以上９０分以下であることを特徴とする、請求項１〜７のいずれかに記載のIII族窒化物半導体の製造方法。   The heating nitriding temperature of the metal layer in the ammonia gas atmosphere is in a range of 900 to 1200 ° C, and the nitriding time is 1 minute or more and 90 minutes or less, according to any one of claims 1 to 7, A method for producing a group III nitride semiconductor. 前記AlNテンプレート基板の（０００２）X線ロッキングカーブの半値幅が５００秒以下、（１１−２０）の半値幅が３０００秒以下であることを特徴とする、請求項１〜８のいずれかに記載のIII族窒化物半導体の製造方法。
The half width of the (0002) X-ray rocking curve of the AlN template substrate is 500 seconds or less, and the half width of (11-20) is 3000 seconds or less. A method for producing a group III nitride semiconductor.
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