JP2012124367A - Oxide insulator film, oxide semiconductor thin film transistor element, and method of manufacturing the same - Google Patents
Oxide insulator film, oxide semiconductor thin film transistor element, and method of manufacturing the same Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 84
- 239000010408 film Substances 0.000 title claims abstract description 58
- 239000010409 thin film Substances 0.000 title claims abstract description 26
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 239000012212 insulator Substances 0.000 title abstract description 6
- 239000000463 material Substances 0.000 claims abstract description 39
- 238000002161 passivation Methods 0.000 claims abstract description 25
- 125000004430 oxygen atom Chemical group O* 0.000 claims abstract description 23
- 125000004432 carbon atom Chemical group C* 0.000 claims abstract description 15
- 239000010410 layer Substances 0.000 claims description 107
- 238000000034 method Methods 0.000 claims description 34
- 239000011241 protective layer Substances 0.000 claims description 33
- 238000004544 sputter deposition Methods 0.000 claims description 32
- 239000007789 gas Substances 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 11
- 229910052799 carbon Inorganic materials 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims 2
- 238000009413 insulation Methods 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 229910007541 Zn O Inorganic materials 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 239000013077 target material Substances 0.000 description 5
- 239000000470 constituent Substances 0.000 description 4
- 238000009751 slip forming Methods 0.000 description 4
- 150000001721 carbon Chemical group 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000011109 contamination Methods 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 229910001882 dioxygen Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- 229920001621 AMOLED Polymers 0.000 description 1
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
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- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
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- 238000004904 shortening Methods 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N zinc oxide Inorganic materials [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
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- H01L29/76—Unipolar devices, e.g. field effect transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
Description
本発明は、酸化物絶縁膜と、酸化物絶縁膜を用いた酸化物半導体薄膜トランジスタ素子およびその製造方法に関する。 The present invention relates to an oxide insulating film, an oxide semiconductor thin film transistor element using the oxide insulating film, and a manufacturing method thereof.
従来、エッチストッパ層を持つボトムゲート／トップコンタクト構造の薄膜トランジスタ素子の製造方法として、次の工程を経るものがあった（例えば、非特許文献１及び２参照）。
Conventionally, as a method of manufacturing a thin film transistor element having a bottom gate / top contact structure having an etch stopper layer, there has been a method through the following steps (for example, see Non-Patent
まず、ガラス基板上の、フォトリソグラフィ法により形成されたゲート電極上に、ゲート絶縁層としてシリコン酸化膜あるいはシリコン窒化膜をプラズマ化学気相成長蒸着法（ＰＥ−ＣＶＤ）を使って形成する。 First, a silicon oxide film or a silicon nitride film is formed as a gate insulating layer on a glass substrate by a photolithography method using a plasma chemical vapor deposition method (PE-CVD).
続いて、ターゲット材料としてＩｎ−Ｇａ−Ｚｎ−Ｏ（組成比１：１：１：４）を用い、スパッタ装置内でＡｒガスに加えて適量の酸素ガスを混ぜながら、ゲート絶縁層上に酸化物半導体層を形成する。その上にチャンネル保護層を形成するため、スパッタ装置から基板を取り出しＰＥ−ＣＶＤ法によりシリコン酸化膜あるいはシリコン窒化膜のいずれかを成膜する。 Subsequently, In—Ga—Zn—O (composition ratio 1: 1: 1: 4) is used as a target material, and oxidation is performed on the gate insulating layer while mixing an appropriate amount of oxygen gas in addition to Ar gas in the sputtering apparatus. A physical semiconductor layer is formed. In order to form a channel protective layer thereon, the substrate is taken out from the sputtering apparatus and either a silicon oxide film or a silicon nitride film is formed by PE-CVD.
そして、前記酸化物半導体層、並びにチャンネル保護層を所定の形状に加工した後、薄膜トランジスタのソース／ドレイン電極を形成する。 Then, after processing the oxide semiconductor layer and the channel protective layer into predetermined shapes, source / drain electrodes of the thin film transistor are formed.
続いて、パッシベーション層として、シリコン酸化膜あるいはシリコン窒化膜のいずれかをＰＥ−ＣＶＤ法によって成膜する。 Subsequently, either a silicon oxide film or a silicon nitride film is formed as a passivation layer by a PE-CVD method.
最後に、必要に応じて所定のコンタクトホ−ルをフォトリソグラフィ法で形成する。 Finally, a predetermined contact hole is formed by photolithography as necessary.
しかしながら、上述した従来の薄膜トランジスタ素子の製造方法においては、次のような問題点があった。 However, the above-described conventional method for manufacturing a thin film transistor device has the following problems.
ＰｒＯｂ１．ゲート絶縁層やチャンネル保護層、パッシベーション層に使われているシリコン酸化膜あるいはシリコン窒化膜のいずれかを形成するためには、高価なプラズマ化学気相成長蒸着（ＰＥ−ＣＶＤ）装置や高価な半導体用特殊ガス（ＳｉＨ4）が必要である。 PrOb1. In order to form either a silicon oxide film or a silicon nitride film used for a gate insulating layer, a channel protective layer, or a passivation layer, an expensive plasma chemical vapor deposition (PE-CVD) apparatus or an expensive semiconductor is used. Special gas (SiH 4 ) is required.
ＰｒＯｂ２．ＰＥ−ＣＶＤ法で形成されたシリコン酸化膜あるいはシリコン窒化膜の代わりに、酸化物半導体層に使われている同一酸化物材料でゲート絶縁層やチャンネル保護層、パッシベーション層を形成できることが望まれているが、従来のＡｒガスに加えて酸素ガスを添加する成膜方法では、シリコン酸化膜やシリコン窒化膜に匹敵する高抵抗化が実現できない。 PrOb2. It is desirable to be able to form a gate insulating layer, a channel protective layer, and a passivation layer with the same oxide material used for the oxide semiconductor layer instead of the silicon oxide film or silicon nitride film formed by PE-CVD. However, the conventional film formation method in which oxygen gas is added in addition to Ar gas cannot achieve high resistance comparable to silicon oxide films or silicon nitride films.
ＰｒＯｂ３．ＰＥ−ＣＶＤ法によりゲート絶縁層を形成後、酸化物半導体層はスパッタ装置を使うためＰＥ−ＣＶＤ装置から基板を取り出さなければならない。また、チャンネル保護層をＰＥ−ＣＶＤ法で形成するためにはスパッタ装置を使って酸化物半導体層を形成した後、装置から基板を取り出さなければならない。 PrOb3. After forming the gate insulating layer by the PE-CVD method, the oxide semiconductor layer must be taken out of the PE-CVD apparatus in order to use a sputtering apparatus. In order to form the channel protective layer by the PE-CVD method, the substrate must be taken out from the device after forming the oxide semiconductor layer using a sputtering device.
したがって、このような工程を経ると、ゲート絶縁層と酸化物半導体層の界面、または、酸化物半導体層とチャンネル保護層の界面が汚染されることに加えて工程が長くなることで、無駄なコストが発生する。 Therefore, through such a process, in addition to the contamination of the interface between the gate insulating layer and the oxide semiconductor layer or the interface between the oxide semiconductor layer and the channel protective layer, the process becomes longer, which is useless. There is a cost.
上述した従来の薄膜トランジスタ素子の製造方法における問題点の発生原因は次の点が掲げられる。 The cause of the problem in the above-described conventional method for manufacturing a thin film transistor element is as follows.
Ｃａｕｓｅ１．ゲート絶縁層やチャンネル保護層、パッシベーション層に使われているシリコン酸化膜あるいはシリコン窒化膜を形成する手段として、ＰＥ−ＣＶＤ法に代わる技術が無かった。 Cause1. As a means for forming a silicon oxide film or a silicon nitride film used for a gate insulating layer, a channel protective layer, and a passivation layer, there has been no technique replacing the PE-CVD method.
Ｃａｕｓｅ２．半導体層に使われている酸化物材料の固有抵抗値は、酸素原子を増やせば、固有抵抗値が高くなり絶縁性を呈するようになる。しかしながら、酸素量だけを増やして形成したいわゆる酸化物絶縁層は、トランジスタ素子の絶縁層に使うのにその抵抗が低すぎる。 Cause2. The specific resistance value of the oxide material used for the semiconductor layer increases the specific resistance value and exhibits insulating properties when the number of oxygen atoms is increased. However, a so-called oxide insulating layer formed by increasing only the amount of oxygen has too low a resistance to be used for an insulating layer of a transistor element.
Ｃａｕｓｅ３．ゲート絶縁層やチャンネル保護層、パッシベーション層に使われているシリコン酸化膜あるいはシリコン窒化膜は、スパッタリング法で成膜すると、充分な絶縁性が得られない。そのため、ゲート絶縁層やチャンネル保護層、パッシベーション層はＰＥ−ＣＶＤ法を用いて形成せざるを得ない。従って、スパッタ装置とＰＥ−ＣＶＤ装置間の基板の移動は避けられない。 Cause3. If a silicon oxide film or silicon nitride film used for a gate insulating layer, a channel protective layer, or a passivation layer is formed by sputtering, sufficient insulation cannot be obtained. Therefore, the gate insulating layer, the channel protective layer, and the passivation layer must be formed using the PE-CVD method. Therefore, the movement of the substrate between the sputtering apparatus and the PE-CVD apparatus is inevitable.
本発明は、上記のような課題を解決するためになされたものであり、酸素原子に加えて炭素原子を添加することで、酸化物半導体膜に比べて２桁以上高い固有抵抗値を持った酸化物絶縁膜を提供することができ、適量の酸素原子を含有した酸化物半導体材料を半導体層に、酸素原子に加えて適量の炭素原子を含有した酸化物絶縁層材料をゲート絶縁層、チャンネル保護層、パッシベーション層に使った酸化物絶縁膜と、酸化物絶縁膜を用いた酸化物半導体薄膜トランジスタ素子およびその製造方法を得ることを目的とする。 The present invention has been made in order to solve the above-described problems. By adding a carbon atom in addition to an oxygen atom, the specific resistance value is higher by two digits or more than that of an oxide semiconductor film. An oxide insulating film can be provided, an oxide semiconductor material containing an appropriate amount of oxygen atoms in a semiconductor layer, an oxide insulating layer material containing an appropriate amount of carbon atoms in addition to oxygen atoms as a gate insulating layer, a channel It is an object to obtain an oxide insulating film used for a protective layer and a passivation layer, an oxide semiconductor thin film transistor element using the oxide insulating film, and a method for manufacturing the same.
本発明に係る酸化物絶縁膜は、酸化物半導体層中に、酸素原子に加えて、炭素原子を添加して形成したことを特徴とする。 The oxide insulating film according to the present invention is formed by adding carbon atoms in addition to oxygen atoms in an oxide semiconductor layer.
また、本発明に係る酸化物半導体薄膜トランジスタ素子は、酸化物材料がチャンネル半導体層に使われる酸化物半導体薄膜トランジスタ素子であって、前記記載の酸化物絶縁膜は、前記チャンネル半導体層に使われる酸化物材料と同一材料からなり、ゲート絶縁層、チャンネル保護層、パッシベーション層のいずれかまたはすべてに用いたことを特徴とする。 The oxide semiconductor thin film transistor device according to the present invention is an oxide semiconductor thin film transistor device in which an oxide material is used for a channel semiconductor layer, and the oxide insulating film is an oxide used for the channel semiconductor layer. It is made of the same material as the material, and is used for any or all of the gate insulating layer, the channel protective layer, and the passivation layer.
さらに、本発明に係る酸化物半導体薄膜トランジスタ素子の製造方法は、基板上にゲート電極を形成する工程と、酸化物半導体ターゲットを用い、スパッタリング法でゲート絶縁層、半導体層、チャンネル保護層を連続して成膜する工程と、アニーリング処理を行う工程と、前記チャンネル保護層を所定の形状に加工する工程と、前記半導体層を所定の形状に加工する工程と、前記パタ−ニングされるチャンネル保護層及び半導体層上にソース／ドレイン電極を形成する工程と、前記ソース／ドレイン電極を含んだ基板の全面にパッシベーション層を成膜する工程と、前記ソース／ドレイン電極の表面が所定部分露出するようにパッシベーション層をエッチングして コンタクトホ−ルを形成する工程とを順次実行することを特徴とする。ここで、前記ゲート絶縁層及び前記チャンネル保護層、そして前記パッシベーション層の成膜工程は、酸化物半導体層中に酸素原子に加えて炭素原子を添加することを特徴とする。 Furthermore, the method for manufacturing an oxide semiconductor thin film transistor device according to the present invention includes a step of forming a gate electrode on a substrate and an oxide semiconductor target, and a gate insulating layer, a semiconductor layer, and a channel protective layer are continuously formed by sputtering. Forming a film, performing an annealing process, processing the channel protective layer into a predetermined shape, processing the semiconductor layer into a predetermined shape, and the patterned channel protective layer And forming a source / drain electrode on the semiconductor layer, forming a passivation layer on the entire surface of the substrate including the source / drain electrode, and exposing a predetermined portion of the surface of the source / drain electrode. The step of etching the passivation layer to form a contact hole is sequentially performed. Here, the gate insulating layer, the channel protective layer, and the passivation layer are formed by adding carbon atoms in addition to oxygen atoms in the oxide semiconductor layer.
本発明によれば、酸素原子に加えて炭素原子を添加することで、酸化物半導体膜に比べて２桁以上高い固有抵抗値を持った酸化物絶縁膜を提供することができ、適量の酸素原子を含有した酸化物半導体材料を半導体層に、酸素原子に加えて適量の炭素原子を含有した酸化物絶縁層材料をゲート絶縁層、チャンネル保護層、パッシベーション層に使った酸化物半導体薄膜トランジスタ素子を得るようにしたものである。従って、同一ターゲット材料と同一スパッタ装置、あるいは同一チャンバーだけで必要なトランジスタ構成材料が形成できることで、トランジスタ素子の材料コストやプロセスコストが削減できる。 According to the present invention, by adding carbon atoms in addition to oxygen atoms, it is possible to provide an oxide insulating film having a specific resistance that is two orders of magnitude higher than that of an oxide semiconductor film. An oxide semiconductor thin film transistor element using an oxide semiconductor material containing atoms as a semiconductor layer and an oxide insulating layer material containing an appropriate amount of carbon atoms in addition to oxygen atoms as a gate insulating layer, a channel protective layer, and a passivation layer. It ’s what you get. Therefore, the necessary transistor constituent material can be formed only with the same target material and the same sputtering apparatus or the same chamber, so that the material cost and process cost of the transistor element can be reduced.
まず、本発明の要旨について説明する。
Ｉｎ−Ｇａ−Ｚｎ−Ｏに代表されるいわゆる酸化物半導体材料の固有抵抗値は、含有する酸素原子で制御することができる。含有酸素原子を減らせば、固有抵抗値は低くなり、酸化物の物性は半導体から導体に近づく。
First, the gist of the present invention will be described.
The specific resistance value of a so-called oxide semiconductor material typified by In—Ga—Zn—O can be controlled by oxygen atoms contained. If the oxygen atom content is reduced, the specific resistance value decreases, and the physical properties of the oxide approach the conductor from the semiconductor.
一方、酸素原子を増やせば、固有抵抗値が高くなり、半導体、さらには絶縁体になる。すなわち、同じ半導体材料を使いながら、半導体層や絶縁層あるいは導体層を自由に作ることができる。しかしながら、酸素量を増やして形成した酸化物絶縁層をトランジスタ素子の絶縁層に使うには、その固有抵抗値が低すぎる。 On the other hand, increasing the number of oxygen atoms increases the specific resistance value, resulting in a semiconductor and further an insulator. That is, a semiconductor layer, an insulating layer, or a conductor layer can be freely formed while using the same semiconductor material. However, in order to use the oxide insulating layer formed by increasing the amount of oxygen as the insulating layer of the transistor element, the specific resistance value is too low.
本発明は、酸素原子に加えて、炭素原子を添加することで、２桁以上高い固有抵抗値を持った「酸化物絶縁膜」を提供する。 The present invention provides an “oxide insulating film” having a specific resistance value that is two orders of magnitude higher by adding carbon atoms in addition to oxygen atoms.
また、本発明は、適量の酸素原子を含有した酸化物半導体材料を半導体層に、酸素原子に加えて適量の炭素原子を含有した「酸化物絶縁層材料」を、ゲート絶縁層、チャンネル保護層、パッシベーション層に使った酸化物半導体薄膜トランジスタ素子を提供する。 The present invention also provides an oxide semiconductor material containing an appropriate amount of oxygen atoms in a semiconductor layer, an “oxide insulating layer material” containing an appropriate amount of carbon atoms in addition to oxygen atoms, a gate insulating layer, a channel protective layer. An oxide semiconductor thin film transistor device used for a passivation layer is provided.
以下、具体的な実施の形態について説明する。
まず、酸化物半導体膜の高抵抗技術について説明する。
本発明においては、Ｉｎ−Ｇａ−Ｚｎ−Ｏに代表されるいわゆる酸化物半導体材料に酸素原子に加えて、炭素原子を添加することで、２桁以上高い固有抵抗値を持った「酸化物絶縁膜」を形成することが可能になる。
Hereinafter, specific embodiments will be described.
First, a high resistance technique for an oxide semiconductor film will be described.
In the present invention, by adding a carbon atom in addition to an oxygen atom to a so-called oxide semiconductor material typified by In—Ga—Zn—O, an “oxide insulation” having a specific resistance value higher by two digits or more. It is possible to form a “film”.
図１は、本発明に係る酸化物半導体膜の高抵抗化技術を説明するためのガス流量比（Ｏ2／（Ａｒ＋Ｏ2））対固有抵抗値の関係を示す特性図である。 FIG. 1 is a characteristic diagram showing the relationship between a gas flow rate ratio (O 2 / (Ar + O 2 )) and a specific resistance value for explaining a technique for increasing the resistance of an oxide semiconductor film according to the present invention.
図１に示すように、Ｉｎ−Ｇａ−Ｚｎ−Ｏ膜の固有抵抗値に対し、当該Ｉｎ−Ｇａ−Ｚｎ−Ｏ膜の酸化物半導体材料に酸素原子に加えて、ガス流量比で１％の炭素原子を添加することで、点線の円内に示す特性のように、２桁以上高い固有抵抗値を持った「酸化物絶縁膜」を形成することができる。さらに、添加される炭素原子が、１％から５％の範囲では、１％添加とほぼ同じ固有抵抗値（エラーバーの範囲内）を持つことが確認された。また、本発明を実証するに使用したスパッタ装置では、炭素量が１％未満と５％を超える範囲は流量制御が難しくデータを取るに至らなかった。 As shown in FIG. 1, with respect to the resistivity of the In—Ga—Zn—O film, in addition to oxygen atoms in the oxide semiconductor material of the In—Ga—Zn—O film, a gas flow rate ratio of 1% By adding carbon atoms, an “oxide insulating film” having a specific resistance value that is two orders of magnitude higher can be formed as shown by the characteristics shown in the dotted circle. Further, it was confirmed that when the added carbon atom is in the range of 1% to 5%, it has almost the same specific resistance value (within the error bar) as that of 1% addition. Further, in the sputtering apparatus used for demonstrating the present invention, it was difficult to control the flow rate in the range where the carbon content was less than 1% and more than 5%, and data could not be obtained.
従って、適量の酸素原子を含有した酸化物半導体材料を半導体層に、酸素原子に加えて適量の炭素原子を含有した「酸化物絶縁層材料」を、ゲート絶縁層、チャンネル保護層、パッシベーション層に使った酸化物半導体薄膜トランジスタ素子を作製することができる。 Therefore, an oxide semiconductor material containing an appropriate amount of oxygen atoms is applied to the semiconductor layer, and an “oxide insulating layer material” containing an appropriate amount of carbon atoms in addition to the oxygen atoms is applied to the gate insulating layer, channel protective layer, and passivation layer. The used oxide semiconductor thin film transistor element can be manufactured.
次に、高抵抗酸化物絶縁膜を使った薄膜トランジスタ素子およびその製造方法について説明する。本発明においては、同一酸化物材料（スパッタターゲット）を使いながら、スパッタリング法による成膜中の反応ガスを変えるだけで、半導体層や絶縁層の作り分けが可能になる。そして、同一ターゲット材料と同一スパッタ装置あるいは同一チャンバーだけで必要なトランジスタ構成材料が形成できることで、トランジスタ素子の材料コストやプロセスコストが削減できる。 Next, a thin film transistor element using a high resistance oxide insulating film and a manufacturing method thereof will be described. In the present invention, a semiconductor layer and an insulating layer can be separately formed by changing the reaction gas during film formation by sputtering while using the same oxide material (sputter target). Further, since the necessary transistor constituent material can be formed only with the same target material and the same sputtering apparatus or the same chamber, the material cost and process cost of the transistor element can be reduced.
エッチストッパ層を持つボトムゲート／トップコンタクト構造の例を参照して、図２及び図３の工程順に従って本発明に係る酸化物半導体薄膜トランジスタ素子の製造方法について説明する。 With reference to an example of a bottom gate / top contact structure having an etch stopper layer, a method of manufacturing an oxide semiconductor thin film transistor device according to the present invention will be described in the order of steps shown in FIGS.
まず、下記条件の下で、図２（Ａ）に示すように、ガラス基板１上にスパッタ装置を用いＭｏ膜を成膜しフォトリソグラフィ法によりゲート電極２を形成する。
First, as shown in FIG. 2A, a Mo film is formed on a
・Ｍｏ厚さ：５０〜１００ｎｍ
・ＤＣスパッタ電力：５００Ｗ
・スパッタリングガス／流量：Ａｒ／３０ｓｃｃｍ
・チャンバー内ワ−キング圧力：３〜５ｍＴｏｒｒ
・ Mo thickness: 50-100nm
・ DC sputtering power: 500W
・ Sputtering gas / flow rate: Ar / 30 sccm
・ Working pressure in the chamber: 3-5 mTorr
次に、下記成膜条件の下で、図２（Ｂ）に示すように、酸化物半導体ターゲットを用い、スパッタリング法で、ゲート絶縁層３、半導体層４、チャンネル保護層５を連続で成膜する。
Next, as shown in FIG. 2B, the
ゲート絶縁層３／チャンネル保護層５の成膜条件
・厚さ：１５０〜２００ｎｍ（ゲート絶縁膜３）
５０〜１００ｎｍ（チャンネル保護層５）
・ＤＣスパッタ電力：１５０Ｗ
・総スパッタリングガス流量：５０ｓｃｃｍ（Ａｒ＋Ｏ2＋Ｃ）
・Ｏ2濃度：１〜２０％
・Ｃ濃度：１〜５％
・チャンバー内ワ−キング圧力：５〜７ｍＴｏｒｒ
Film formation conditions of
50 to 100 nm (channel protective layer 5)
・ DC sputtering power: 150W
・ Total sputtering gas flow rate: 50 sccm (Ar + O 2 + C)
・ O 2 concentration: 1-20%
・ C concentration: 1-5%
・ Working pressure in the chamber: 5-7 mTorr
半導体層４の成膜条件
・厚さ：３０〜５０ｎｍ
・ＤＣスパッタ電力：１５０Ｗ
・総スパッタリングガス流量：５０ｓｃｃｍ（Ａｒ＋Ｏ2）
・Ｏ2濃度：１〜２０％
・チャンバー内ワ−キング圧力：３〜５ｍＴｏｒｒ
Deposition conditions of semiconductor layer 4-Thickness: 30-50 nm
・ DC sputtering power: 150W
・ Total sputtering gas flow rate: 50 sccm (Ar + O 2 )
・ O 2 concentration: 1-20%
・ Working pressure in the chamber: 3-5 mTorr
図２（Ｂ）のＡ部に示すように、ゲート絶縁層３、半導体層４、チャンネル保護層５を連続成膜したため各々層間の汚染やプロセス短縮ができる。また、同一ターゲット材料と同一スパッタ装置で必要なトランジスタ構成材料が形成できることで、トランジスタ素子の材料コストやプロセスコストが削減できる。
As shown in part A of FIG. 2B, since the
次に、下記条件の下で、図２（Ｃ）に示すように、アニーリング処理を行う。
・温度：３５０℃
・時間：１ｈｒ
・雰囲気：空気
Next, as shown in FIG. 2C, an annealing process is performed under the following conditions.
・ Temperature: 350 ℃
・ Time: 1 hr
・ Atmosphere: Air
次に、図２（Ｄ）に示すように、チャンネル保護層５を、ウェトエッチング法あるいはドライエッチング法により所定の形状に加工（パタ−ニング）する。
Next, as shown in FIG. 2D, the channel
チャンネル保護層５の加工は次の工程を経ることになる。
チャンネル保護層５上にポジレジスト塗布→露光→現像→チャンネル保護層５のエッチング→ポジレジストの剥離
図２（Ｄ）には、エッチストッパ層によりパタ−ニングされたチャンネル保護層５を示している。
The processing of the channel
Application of positive resist on the channel
次に、図３（Ａ）に示すように、半導体層４をウェトエッチング法あるいはドライエッチング法により所定の形状に加工（パタ−ニング）する。
Next, as shown in FIG. 3A, the
半導体層４の加工は次の工程を経ることになる。
半導体層４上にポジレジスト塗布→露光→現像→半導体層４のエッチング→ポジレジストの剥離
図３（Ａ）には、パタ−ニングされた半導体層４を示している。
The
Application of positive resist on the
次に、下記条件の下で、図３（Ｂ）に示すように、スパッタ装置を用いＭｏ膜を成膜後、フォトリソグラフィ法によりソース／ドレイン電極６を形成する。
Ｍｏ厚さ：１００〜１５０ｎｍ
ＤＣスパッタ電力：５００Ｗ
スパッタリングガス／流量：Ａｒ／３０ｓｃｃｍ
チャンバー内ワ−キング圧力：３〜５ｍＴｏｒｒ
Next, as shown in FIG. 3B, a source / drain electrode 6 is formed by photolithography after forming a Mo film using a sputtering apparatus under the following conditions.
Mo thickness: 100-150 nm
DC sputtering power: 500W
Sputtering gas / flow rate: Ar / 30 sccm
Working pressure in chamber: 3-5 mTorr
Ｍｏ膜の加工は次の工程を経ることになる。
Ｍｏ膜上にポジレジスト塗布→露光→現像→Ｍｏ膜のエッチング→ポジレジストの剥離
The processing of the Mo film goes through the following steps.
Application of positive resist on Mo film → Exposure → Development → Etching of Mo film → Stripping of positive resist
次に、下記成膜条件の下で、図３（Ｃ）に示すように、スパッタリング法を用いパッシベーション層７を成膜する。
パッシベーション層７の成膜条件
厚さ：４００〜５００ｎｍ
ＤＣスパッタ電力：１５０Ｗ
総スパッタリングガス流量：５０ｓｃｃｍ（Ａｒ＋Ｏ2＋Ｃ）
Ｏ2濃度：１〜２０％
Ｃ濃度：１〜５％
チャンバー内ワ−キング圧力：５〜７ｍＴｏｒｒ
Next, as shown in FIG. 3C, a passivation layer 7 is formed using a sputtering method under the following film formation conditions.
Film formation conditions for the passivation layer 7 Thickness: 400 to 500 nm
DC sputtering power: 150W
Total sputtering gas flow rate: 50 sccm (Ar + O 2 + C)
O 2 concentration: 1-20%
C concentration: 1 to 5%
Working pressure in chamber: 5-7 mTorr
最後に、図３（Ｄ）に示すように、ソース／ドレイン電極６の表面が所定部分露出するようにパッシベーション層７をフォトリソグラフィ法によりエッチングしてコンタクトホ−ル8を形成する。
Finally, as shown in FIG. 3D, the passivation layer 7 is etched by photolithography so that a predetermined portion of the surface of the source / drain electrode 6 is exposed to form a
なお、上記実施の形態では、半導体層４に使われる酸化物材料と同一材料で、ゲート絶縁層３、チャンネル保護層５、パッシベーション層７を形成するものであるが、少なくともいずれか１つに用いて形成しても良い。
In the above embodiment, the
従って、本発明によれば、Ｉｎ−Ｇａ−Ｚｎ−Ｏに代表される酸化物材料を使いながら、スパッタリング法による成膜中の反応ガスを変えるだけで、酸化物材料を半導体層や絶縁層に作り分けることができる。 Therefore, according to the present invention, by using an oxide material typified by In-Ga-Zn-O, the oxide material can be turned into a semiconductor layer or an insulating layer only by changing a reaction gas during film formation by sputtering. Can be made separately.
その結果、同一ターゲット材料と同一スパッタ装置、あるいは同一チャンバーだけで必要なトランジスタ構成材料が形成できることで、トランジスタ素子の材料コストやプロセスコストが削減できる。また、従来のａ−Ｓｉ／ＴＦＴ工程に比べて高価なプラズマ化学気相成長蒸着法（ＰＥ−ＣＶＤ）装置や高価な半導体ガス（ＳｉＨ4）が不要になる。 As a result, a necessary transistor constituent material can be formed only by the same target material and the same sputtering apparatus or the same chamber, so that the material cost and process cost of the transistor element can be reduced. Further, an expensive plasma chemical vapor deposition (PE-CVD) apparatus and an expensive semiconductor gas (SiH 4 ) are not required as compared with the conventional a-Si / TFT process.
また、スパッタ装置内で必要な半導体層、ならびに絶縁層を連続して形成できるため、不連続成膜で問題になる水や二酸化炭素などによる界面の汚染を皆無にできる。また、基板の装置間搬送が不要であり、工程短縮が実現する。 Further, since necessary semiconductor layers and insulating layers can be continuously formed in the sputtering apparatus, contamination of the interface due to water, carbon dioxide, etc., which becomes a problem in discontinuous film formation, can be eliminated. In addition, it is not necessary to transfer the substrate between apparatuses, and the process can be shortened.
また、半導体層も絶縁層も、基本材料はＩｎ−Ｇａ−Ｚｎ−Ｏで構成されるため、膨張係数や格子定数で代表される、いわゆる「物理定数」がほぼ等しい。このことは、本質的にストレス（圧縮や引っ張り）の少ない薄膜トランジスタ構造を実現でき、電気的に信頼性の高い、特性の安定したＴＦＴが実現する。 Further, since the basic material of both the semiconductor layer and the insulating layer is composed of In—Ga—Zn—O, so-called “physical constants” represented by expansion coefficients and lattice constants are almost equal. This essentially realizes a thin film transistor structure with little stress (compression or tension), and an electrically reliable TFT with stable characteristics is realized.
以上のように、本発明によれば、安価で信頼性に優れた酸化物薄膜トランジスタを提供できる。 As described above, according to the present invention, an oxide thin film transistor that is inexpensive and excellent in reliability can be provided.
１ ガラス基板、２ ゲート電極、３ ゲート絶縁層、４ 半導体層、５ チャンネル保護層、６ ソース／ドレイン電極、７ パッシベーション層、８ コンタクトホ−ル。 1 glass substrate, 2 gate electrode, 3 gate insulating layer, 4 semiconductor layer, 5 channel protective layer, 6 source / drain electrode, 7 passivation layer, 8 contact hole.
Claims (5)
前記炭素原子は、スパッタリング時のガス流量比で、１％から５％の範囲で添加されることを特徴とする酸化物絶縁膜。 The oxide insulating film according to claim 1,
The oxide insulating film according to claim 1, wherein the carbon atom is added in a range of 1% to 5% in a gas flow rate ratio during sputtering.
請求項１または２に記載の酸化物絶縁膜は、前記チャンネル半導体層に使われる酸化物材料と同一材料でなり、ゲート絶縁層、チャンネル保護層、パッシベーション層のいずれかまたはすべてに用いたことを特徴とする酸化物半導体薄膜トランジスタ素子。 An oxide semiconductor thin film transistor device in which an oxide material is used for a channel semiconductor layer,
The oxide insulating film according to claim 1 or 2 is made of the same material as the oxide material used for the channel semiconductor layer, and is used for any or all of the gate insulating layer, the channel protective layer, and the passivation layer. An oxide semiconductor thin film transistor element.
酸化物半導体ターゲットを用い、スパッタリング法でゲート絶縁層、半導体層、チャンネル保護層を連続して成膜する工程と、
アニーリング処理を行う工程と、
前記チャンネル保護層を所定の形状にパタ−ニングする工程と、
前記半導体層を所定の形状にパタ−ニングする工程と、
前記パタ−ニングされるチャンネル保護層及び半導体層上にソース／ドレイン電極を形成する工程と、
前記ソース／ドレイン電極を含んだ基板の全面にパッシベーション層を成膜する工程と、
前記ソース／ドレイン電極の表面が所定部分露出するようにパッシベーション層をエッチングしてコンタクトホ−ルを形成する工程と
を順次実行し、
前記ゲート絶縁層及び前記チャンネル保護層、前記パッシベーション層の成膜工程は、酸化物半導体層中に酸素原子に加えて炭素原子を添加することを特徴とする酸化物半導体薄膜トランジスタ素子の製造方法。 Forming a gate electrode on the substrate;
Using an oxide semiconductor target, a step of continuously forming a gate insulating layer, a semiconductor layer, and a channel protective layer by a sputtering method;
An annealing process;
Patterning the channel protective layer into a predetermined shape;
Patterning the semiconductor layer into a predetermined shape;
Forming source / drain electrodes on the patterned channel protection layer and semiconductor layer;
Forming a passivation layer on the entire surface of the substrate including the source / drain electrodes;
Sequentially performing a step of etching the passivation layer so that a predetermined portion of the surface of the source / drain electrode is exposed to form a contact hole,
The method of manufacturing an oxide semiconductor thin film transistor element, wherein the gate insulating layer, the channel protective layer, and the passivation layer are formed by adding carbon atoms in addition to oxygen atoms in the oxide semiconductor layer.
前記炭素原子は、スパッタリング時のガス流量比で、１％から５％の範囲で添加されることを特徴とする酸化物半導体薄膜トランジスタ素子の製造方法。 In the manufacturing method of the oxide semiconductor thin film transistor element according to claim 4,
The method for manufacturing an oxide semiconductor thin film transistor element, wherein the carbon atom is added in a gas flow rate ratio of 1% to 5% during sputtering.
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| JP4377139B2 (en) * | 2003-02-19 | 2009-12-02 | 株式会社 日立ディスプレイズ | Display device |
| JP2007109918A (en) * | 2005-10-14 | 2007-04-26 | Toppan Printing Co Ltd | Transistor and its manufacturing method |
| JP5128792B2 (en) * | 2006-08-31 | 2013-01-23 | 財団法人高知県産業振興センター | Thin film transistor manufacturing method |
| JP4852400B2 (en) * | 2006-11-27 | 2012-01-11 | シャープ株式会社 | Semiconductor memory device, semiconductor device, display device, liquid crystal display device, and receiver |
| KR20100023151A (en) * | 2008-08-21 | 2010-03-04 | 삼성모바일디스플레이주식회사 | Thin film transistor and fabricating method thereof |
| US8367486B2 (en) * | 2009-02-05 | 2013-02-05 | Semiconductor Energy Laboratory Co., Ltd. | Transistor and method for manufacturing the transistor |
| JP2010219114A (en) * | 2009-03-13 | 2010-09-30 | Tokyo Institute Of Technology | Carbon electrode, method for manufacturing the same, organic transistor and method for manufacturing the same |
-
2010
- 2010-12-09 JP JP2010274707A patent/JP2012124367A/en active Pending
-
2011
- 2011-12-07 KR KR1020110130041A patent/KR101970548B1/en active IP Right Grant
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9508866B1 (en) | 2013-07-05 | 2016-11-29 | Joled Inc. | Thin-film transistor element, method for manufacturing same, and display device |
Also Published As
| Publication number | Publication date |
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| KR20120064626A (en) | 2012-06-19 |
| KR101970548B1 (en) | 2019-04-19 |
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