JP2012124313A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for manufacturing a semiconductor device having excellent characteristics in a better manufacturing process.SOLUTION: A method is provided, which includes steps of: covering a first region 1As over a conductive film, forming a mask film with an opening of a second region 1Ad adjacent to the first region, implanting impurity ions into the conductive film, and forming a gate electrode GE1 in a region including a boundary between the first region and second region by selectively removing the conductive film. The method further includes steps of heat-treating, forming a side wall oxide film 7 on a side wall of the gate electrode, forming a drain region in a semiconductor substrate below an end of the gate electrode at a second region side, and forming a source region in the semiconductor substrate below an end of the gate electrode at a first region side. Such a process can increase a bird's beak portion 7d at a drain region side, and decrease a bird's beak portion at a source region side. Accordingly this can ease a GIDL, reduce an off-leak current, and increase an on-state current.

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and more particularly, to a semiconductor device having a MISFET and a technique effective when applied to the manufacture thereof.

  Currently, development for improving the characteristics of transistors is being actively conducted. For example, in order to improve the operation speed of the transistor, the gate length is miniaturized. However, the junction leakage current such as GIDL (Gate-Induced Drain Leakage) increases with the miniaturization of the gate length. Various techniques have been studied in order to reduce such leakage current.

  For example, in Patent Document 1 below, gate oxidation in the vicinity of the drain (13) is performed by performing isotropic oxide film etching using a resist formed so as to expose only the drain side of the gate electrode (12) as a mask. A technique is disclosed in which the gate oxide film is selectively thickened by forming a relatively thick so-called gate bird's beak only in the vicinity of the drain (13) by slightly etching the film and performing reoxidation. In addition, the code | symbol described in the following patent document 1 is shown in a parenthesis.

JP-A-4-246862

  The inventor is considering reducing the off-leakage current caused by the GIDL.

  However, as described later, when the bird's beak is formed on both sides of the gate electrode to reduce the off-leakage current due to the GIDL, there is a problem that the on-current is reduced.

  Therefore, it is desirable to have a MISFET (semiconductor device) configuration that can reduce the off-leakage current and improve the on-current.

  Various devices can be conceived for the MISFET structure for increasing the on-current, but it is desirable to manufacture the MISFET having the above-mentioned favorable characteristics while avoiding an increase in the number of masks and a complicated process.

  Therefore, an object of the present invention is to provide a technique capable of improving the characteristics of a semiconductor device.

  Another object of the present invention is to provide a method of manufacturing a semiconductor device that manufactures a semiconductor device having good characteristics in a better manufacturing process.

  The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  Among the inventions disclosed in the present application, a method for manufacturing a semiconductor device shown in a representative embodiment includes a step of forming an insulating film on a semiconductor substrate and a step of forming a conductive film on the insulating film. And having. A step of forming a mask film formed on the conductive film, the mask film covering the first region of the conductive film and having an open second region adjacent to the first region; Implanting impurity ions into the conductive film through a mask film, and selectively removing the conductive film, thereby forming a gate electrode in a region including a boundary between the first region and the second region. Forming. A step of forming an oxide film on a side wall of the gate electrode; and forming a drain region in the semiconductor substrate located below an end of the gate electrode on the second region side; and Forming a source region in the semiconductor substrate located below the end of the electrode on the first region side.

  Among the inventions disclosed in this application, a method for manufacturing a semiconductor device shown in a typical embodiment forms an insulating film on a semiconductor substrate having a first element formation region and a second element formation region. And a step of forming a conductive film on the insulating film. Further, the mask film is disposed on the conductive film, covers a first region of the conductive film located in the first element formation region, and opens a second region adjacent to the first region. And a step of forming a mask film having an opening in the second element formation region, and a step of implanting impurity ions into the conductive film through the mask film. Furthermore, by selectively removing the conductive film, a first gate electrode is formed in a region including a boundary between the first region and the second region in the first element formation region, and the second element Forming a second gate electrode in the element formation region. Further, a heat treatment is performed to form an oxide film on the sidewalls of the first gate electrode and the second gate electrode, and a first conductivity type impurity region in the semiconductor substrate on both sides of the first gate electrode. Forming a pair and forming a second conductivity type impurity region pair in the semiconductor substrate on both sides of the second gate electrode.

  Among the inventions disclosed in the present application, a semiconductor device shown in a representative embodiment includes a first gate electrode disposed on a semiconductor substrate via a first gate insulating film, and both sides of the first gate electrode. A first field effect transistor having a source region and a drain region disposed in the semiconductor substrate. A second electric field comprising: a second gate electrode disposed on the semiconductor substrate via a second gate insulating film; and an impurity region pair disposed in the semiconductor substrate on both sides of the second gate electrode. Has an effect transistor. Of the first gate insulating film under the first gate electrode, the film thickness at the end on the drain region side is the end of the first gate insulating film under the first gate electrode on the source region side. The film thickness of the end portions on both sides of the second gate electrode in the second gate insulating film below the second gate electrode is larger than the film thickness of the first gate insulating film. It is larger than the film thickness at the end on the region side.

  Among the inventions disclosed in the present application, according to the semiconductor device described in the following representative embodiment, the characteristics of the semiconductor device can be improved.

  In addition, among the inventions disclosed in the present application, according to the method for manufacturing a semiconductor device shown in the following representative embodiment, a semiconductor device having good characteristics can be manufactured in a better manufacturing process.

7 is a fragmentary cross-sectional view showing the manufacturing process of the semiconductor device of First Embodiment; FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 1 during the manufacturing process of the semiconductor device; FIG. 3 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 2 in the manufacturing process of the semiconductor device; FIG. 4 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 3 in the manufacturing process of the semiconductor device; FIG. 5 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 4 during the manufacturing process of the semiconductor device; FIG. 6 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 5 during the manufacturing process of the semiconductor device; FIG. 7 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 6 in the manufacturing process of the semiconductor device; FIG. 8 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 7 in the manufacturing process of the semiconductor device; FIG. 9 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 8 in the manufacturing process of the semiconductor device; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 9 in the manufacturing process of the semiconductor device; FIG. 11 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 10 in the manufacturing process of the semiconductor device; FIG. 12 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 11 in the manufacturing process of the semiconductor device; FIG. 13 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 12 in the manufacturing process of the semiconductor device; FIG. 14 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 13 in the manufacturing process of the semiconductor device; FIG. 15 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1, which is subsequent to FIG. 14 in the manufacturing process of the semiconductor device; 2 is a cross-sectional view showing the shapes of a gate electrode and a sidewall oxide film of a MISFET (Qn1 or Qp1) according to the first embodiment. FIG. It is sectional drawing which shows the shape of the gate electrode and side wall oxide film of MISFET of a comparative example. 2 is a cross-sectional view showing the shapes of a gate electrode and a sidewall oxide film of a MISFET (Qn1 or Qp1) according to the first embodiment. FIG. It is sectional drawing which shows the shape of the gate electrode and side wall oxide film of MISFET of a comparative example. 2 is a cross-sectional view showing the shapes of a gate electrode and a sidewall oxide film of a MISFET (Qn1 or Qp1) according to the first embodiment. FIG. 2 is a cross-sectional view showing the shapes of a gate electrode and a sidewall oxide film of a MISFET (Qn1 or Qp1) according to the first embodiment. FIG. 2 is a cross-sectional view showing the shapes of a gate electrode and a sidewall oxide film of a MISFET (Qn1 or Qp1) according to the first embodiment. FIG. 2 is a plan view showing a configuration of MISFETs (Qn1 and Qp1) of the first embodiment and a configuration of MISFETs (Qn and Qp) of a comparative example. FIG. FIG. 24 is a plan view corresponding to the mask formation region of (PR1) in FIG. FIG. 24 is a plan view corresponding to the mask formation region of (PR2) of FIG. FIG. 24 is a plan view corresponding to the mask formation region of (PR3) of FIG. FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 2; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 3; FIG. 10 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 3; FIG. 10 is a main-portion cross-sectional view showing the configuration of the semiconductor device of Embodiment 5; FIG. 25 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device of Embodiment 5; FIG. 33 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 32; FIG. 34 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 33 in the manufacturing process of the semiconductor device; FIG. 35 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 34 and during the manufacturing process of the semiconductor device; FIG. 36 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 35 in the manufacturing process of the semiconductor device; FIG. 37 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 36 in the manufacturing process of the semiconductor device; FIG. 38 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 37 in the manufacturing process of the semiconductor device; FIG. 39 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 38 in the manufacturing process of the semiconductor device; FIG. 40 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 39 in the manufacturing process of the semiconductor device; FIG. 41 is a main-portion cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 5, which is subsequent to FIG. 40 during the manufacturing process of the semiconductor device;

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Furthermore, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same or related reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. 1 to 15 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

[Description of structure]
First, a characteristic configuration of the semiconductor device of the present embodiment will be described with reference to FIG. 14 which is one of main part sectional views showing a manufacturing process of the semiconductor device of the present embodiment.

  As shown in FIG. 14, the semiconductor device according to the present embodiment includes an n-channel type MISFET (Metal Insulator Semiconductor Field Effect Transistor) Qn1 disposed in a first nMIS region 1A of a silicon substrate (semiconductor substrate) 1. And a p-channel type MISFET Qp1 disposed in the first pMIS region 1B of the silicon substrate 1. Furthermore, the semiconductor device of the present embodiment has an n-channel type MISFET Qn2 arranged in the second nMIS region 1C of the silicon substrate 1 and a p-channel type MISFET Qp2 arranged in the second pMIS region 1D of the silicon substrate 1. is doing.

  The gate electrodes (GE1 to GE4) of the four MISFETs Qn1, Qn2, Qp1 and Qp2 are made of polycrystalline silicon, and impurity ions are implanted to prevent depletion of the gate electrodes (GE1 to GE4). . Specifically, the gate electrodes GE1 and GE3 of the n-channel type MISFETs Qn1 and Qn2 contain n-type impurities (for example, phosphorus or arsenic). The gate electrodes GE2 and GE4 of the p-channel type MISFETs Qp1 and Qp2 contain p-type impurities (for example, boron).

The n-channel type MISFET Qn1 includes a gate electrode GE1 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs, semiconductors disposed in the silicon substrate 1 on both sides of the gate electrode GE1). Region, diffusion layer, source / drain region). This impurity region is constituted by n ⁺ type semiconductor regions S1 and D1 and an n ⁻ type semiconductor region EX1. Among the impurity regions, the n ⁺ type semiconductor region S1 side becomes a source region, and the n ⁺ type semiconductor region D1 side becomes a drain region.

Here, in the n-channel MISFET Qn1, the bottom of the gate electrode GE1 on the drain region (n ⁺ -type semiconductor region D1) side is rounded. In other words, a bird's beak portion 7d is formed at the bottom of the sidewall oxide film 7 on the drain region side. Thus, the thickness of the end portion on the drain region (n ⁺ -type semiconductor region D1) side of the gate insulating film (silicon oxide film 3 and bird's beak portion 7d) under the gate electrode GE1 is set to the gate insulation under the gate electrode GE1. Of the film, the thickness is larger than the film thickness of the end portion on the source region (n ⁺ -type semiconductor region S1) side. The relationship between these film thicknesses will be described in detail later with reference to FIG.

  As described above, by increasing the thickness of the gate insulating film at the end on the drain region side, GIDL (Gate Induced Drain Leakage) can be relaxed and off-leakage current (Ioff) can be reduced. Further, the on-current (Ion) can be increased by reducing the thickness of the gate insulating film at the end on the source region side. That is, the Ioff / Ion characteristic can be improved.

The p-channel type MISFET Qp1 includes a gate electrode GE2 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs) disposed in the silicon substrate 1 on both sides of the gate electrode GE2. , Semiconductor region, diffusion layer, source / drain region). This impurity region is constituted by p ⁺ type semiconductor regions S2 and D2 and a p ⁻ type semiconductor region EX2. Among the impurity regions, the p ⁺ type semiconductor region S2 side becomes a source region, and the p ⁺ type semiconductor region D2 side becomes a drain region.

Here, in the p-channel type MISFET Qp1, the bottom of the gate electrode GE2 on the drain region (p ⁺ -type semiconductor region D2) side is rounded. In other words, a bird's beak portion 7d is formed at the bottom of the sidewall oxide film 7 on the drain region side. As a result, the thickness of the end portion on the drain region (p ⁺ -type semiconductor region D2) side of the gate insulating film (silicon oxide film 3 and bird's beak portion 7d) under the gate electrode GE2 is equal to the gate insulating film under the gate electrode GE1. Of the film, the thickness is larger than the film thickness of the end portion on the source region (p ⁺ -type semiconductor region S2) side. The relationship between these film thicknesses will be described in detail later with reference to FIG.

  In this way, by increasing the thickness of the gate insulating film at the end on the drain region side, GIDL can be relaxed and off-leakage current (Ioff) can be reduced. Further, the on-current (Ion) can be increased by reducing the thickness of the gate insulating film at the end on the source region side. That is, the Ioff / Ion characteristic can be improved.

On the other hand, the n-channel type MISFET Qn2 includes a gate electrode GE3 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs) disposed in the silicon substrate 1 on both sides of the gate electrode GE3. , Semiconductor region, diffusion layer, source / drain region). This impurity region is constituted by an n ⁺ type semiconductor region SD3 and an n ⁻ type semiconductor region EX3. The n-channel type MISFET Qn2 is driven so that a current flows bidirectionally between the impurity region pair. Therefore, in the n ⁺ type semiconductor region SD3, one may be a source region and the other may be a drain region, and one may be a drain region and the other may be a source region.

  Here, in the n-channel MISFET Qn2, the bottoms on both sides of the gate electrode GE3 are rounded. In other words, bird's beak portions 7sd are formed at the bottoms of the sidewall oxide films 7 on both sides of the gate electrode GE3.

  Thus, by increasing the film thickness of the gate insulating film on both sides of the gate electrode GE3, the off-leak current can be reduced regardless of which impurity region is the drain region.

The p-channel type MISFET Qp2 includes a gate electrode GE4 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs) disposed in the silicon substrate 1 on both sides of the gate electrode GE4. , Semiconductor region, diffusion layer, source / drain region). This impurity region is constituted by a p ⁺ type semiconductor region SD4 and a p ⁻ type semiconductor region EX4. The p-channel type MISFET Qp2 is driven such that a current flows bidirectionally between the impurity region pair. Accordingly, one of the p ⁺ type semiconductor regions SD4 may be a source region and the other may be a drain region, and one may be a drain region and the other may be a source region.

  Here, in the p-channel type MISFET Qp2, the bottoms on both sides of the gate electrode GE4 are rounded. In other words, bird's beak portions 7sd are formed at the bottoms of the sidewall oxide films 7 on both sides of the gate electrode GE4.

  As described above, by increasing the thickness of the gate insulating film on both sides of the gate electrode GE4, the off-leak current can be reduced regardless of which impurity region is the drain region.

  In FIG. 14, only one MISFET is shown in each region (1A to 1D), but it goes without saying that a plurality of MISFETs can be formed in each region.

[Production method explanation]
Next, the method for manufacturing the semiconductor device of the present embodiment will be described with reference to FIGS. 1 to 15 and the configuration of the semiconductor device will be further clarified.

  First, as shown in FIG. 1, a silicon substrate 1 is prepared as a semiconductor substrate (semiconductor wafer). Specifically, for example, a silicon substrate 1 made of p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared. A semiconductor substrate other than the silicon substrate 1 may be used.

  The silicon substrate 1 has a first nMIS region 1A in which an n-channel type MISFET Qn1 is formed and a first pMIS region 1B in which a p-channel type MISFET Qp1 is formed. The silicon substrate 1 further has a second nMIS region 1C in which the n-channel type MISFET Qn2 is formed and a second pMIS region 1D in which the p-channel type MISFET Qp2 is formed.

  As described above, the n-channel MISFET Qn1 and the p-channel MISFET Qp1 are elements that are driven so that a source region and a drain region are fixed and current (electrons, holes) flows only in one direction. In other words, in circuit design, it is an element used as a constituent element of a predetermined circuit at a location where a current flows only in one direction.

  On the other hand, the n-channel MISFET Qn2 and the p-channel MISFET Qp2 are elements that are driven so that current (electrons, holes) flows in both directions. In other words, in circuit design, it is an element used as a component of a predetermined circuit at a location where current flows bidirectionally.

  After the silicon substrate 1 is prepared, an element isolation region 2 is formed on the main surface of the silicon substrate 1. For example, by forming element isolation trenches surrounding the first nMIS region 1A, the first pMIS region 1B, the second nMIS region 1C, and the second pMIS region 1D in the silicon substrate 1, and embedding an insulating film in the element isolation trenches. Then, the element isolation region 2 is formed (see FIG. 23). Such an element isolation method is called an STI (Shallow Trench Isolation) method. In addition, the element isolation region 2 may be formed using a LOCOS (Local Oxidization of Silicon) method or the like. Note that a region surrounded by the element isolation region 2 is called an “active region”.

  Next, the p-type well PW1 is formed in the first nMIS region 1A of the silicon substrate 1, the n-type well NW1 is formed in the first pMIS region 1B of the silicon substrate 1, the p-type well PW2 is formed in the second nMIS region 1C of the silicon substrate 1, and the silicon substrate 1 is formed. The n-type well NW2 is formed in the second pMIS region 1D. The p-type wells PW1 and PW2 and the n-type wells NW1 and NW2 can be formed by ion implantation using a photoresist film (not shown in FIG. 1) as an ion implantation blocking mask (FIG. 23 ( PW) and (NW) column).

  Next, after cleaning (cleaning) the surface of the silicon substrate 1 by, for example, wet etching using a hydrofluoric acid (HF) aqueous solution, as shown in FIG. 2, the surface of the silicon substrate 1, that is, the p-type well PW1, A silicon oxide film 3 is formed on the surfaces of PW2 and n-type wells NW1 and NW2. The silicon oxide film 3 is a film constituting a gate insulating film, and can be formed by, for example, a thermal oxidation method. The silicon oxide film 3 may be formed using a CVD (Chemical Vapor Deposition) method or the like. Further, instead of the silicon oxide film 3, another insulating film such as a silicon nitride film may be used.

  Next, as shown in FIG. 3, a polycrystalline silicon film (polysilicon film) 4 is formed on the silicon oxide film 3 as a conductive film with a film thickness of about 50 to 150 nm by using, for example, a CVD method. Note that an amorphous silicon film (amorphous silicon film) may be formed and subjected to heat treatment to be polycrystallized.

  Next, a photoresist film is applied on the main surface of the silicon substrate 1, that is, on the polycrystalline silicon film 4, and the photoresist film is exposed and developed. The film thickness of the photoresist film is, for example, about 410 nm.

  As a result, as shown in FIG. 4, the first region 1Bs of the second nMIS region 1C, the first nMIS region 1A, and the first pMIS region 1B is covered, and the second region 1Bd of the second pMIS region 1D and the first pMIS region 1B is opened. A resist film (mask film, resist film, resist pattern) PR1 is formed. That is, the second pMIS region 1D of the polycrystalline silicon film 4 and the second region 1Bd of the first pMIS region 1B are exposed.

Next, as shown in FIG. 5, p-type impurities (for example, boron) are ion-implanted into the polycrystalline silicon film 4 using the photoresist film PR1 as a mask. As an implantation condition, for example, boron is implanted at an energy of 3 keV and at a concentration of about 2E15 / cm ² . Note that 2E15 represents 2 × 10 ¹⁵ . Thereby, as shown in FIG. 6, p-type impurities are implanted into the polycrystalline silicon film 4 in the second pMIS region 1D and the second region 1Bd of the first pMIS region 1B. In FIG. 6, the state in which impurities (impurity ions) are implanted is schematically shown by dots. Next, the photoresist film PR1 is removed by ashing or the like, and cleaning (for example, APM cleaning or HPM cleaning) is performed. APM cleaning refers to ammonia hydrogen peroxide cleaning, and HPM cleaning refers to hydrochloric hydrogen peroxide cleaning.

  Next, a photoresist film is applied on the main surface of the silicon substrate 1, that is, on the polycrystalline silicon film 4, and the photoresist film is exposed and developed. The film thickness of the photoresist film is, for example, about 410 nm.

  As a result, as shown in FIG. 7, the first region 1As of the second pMIS region 1D, the first pMIS region 1B, and the first nMIS region 1A is covered, and the second region 1Ad of the second nMIS region 1C and the first nMIS region 1A is opened. A resist film PR2 is formed.

Next, as shown in FIG. 8, n-type impurities (for example, phosphorus or arsenic) are ion-implanted into the polycrystalline silicon film 4 using the photoresist film PR2 as a mask. As the implantation conditions, for example, phosphorus is implanted at a concentration of about 6E15 / cm ² at an energy of 10 keV. As a result, as shown in FIG. 9, n-type impurities are implanted into the polycrystalline silicon film 4 in the second region 1Ad of the second nMIS region 1C and the first nMIS region 1A. Also in FIG. 9, the state in which impurities are implanted is schematically shown by dots. Next, the photoresist film PR2 is removed by ashing or the like, and cleaning (for example, APM cleaning or HPM cleaning) is performed.

  By the above ion implantation process, impurities are not implanted into the polycrystalline silicon film 4 in the first region 1As of the first nMIS region 1A and the first region 1Bs of the first pMIS region 1B, and other regions (for example, the first nMIS An n-type or p-type impurity is implanted into the polycrystalline silicon film 4 in the second region 1Ad of the region 1A, the second region 1Bd of the first pMIS region 1B, the second nMIS region 1C, and the second pMIS region 1D). A state is reached (see FIG. 9).

  Next, annealing treatment (activation annealing, heat treatment) for activating the implanted n-type or p-type impurities is performed. For example, RTA (Rapid Thermal Anneal) is performed at 900 ° C. for about 10 seconds. Thereby, the n-type or p-type impurity in the polycrystalline silicon film 4 is diffused and activated (FIG. 10). Due to the diffusion of the impurities during the annealing process, the impurities are diffused in the polycrystalline silicon film 4 also in the first region 1As of the first nMIS region 1A and the first region 1Bs of the first pMIS region 1B where no impurity has been implanted. Thereby, as shown in FIG. 10, in the first nMIS region 1A, the impurity concentration in the polycrystalline silicon film 4 is reduced so that the impurity concentration decreases in the order of the second region 1Ad, the boundary region, and the first region 1As. (Gradient) occurs. The boundary region means a boundary portion between the first region 1As and the second region 1Ad and a region in the vicinity thereof. Further, in the first pMIS region 1B, the concentration of the impurity concentration is generated in the polycrystalline silicon film 4 so that the impurity concentration decreases in the order of the second region 1Bd, the boundary region, and the first region 1Bs. The boundary region means a boundary portion between the first region 1Bs and the second region 1Bd and a region in the vicinity thereof. In the present embodiment, the boundary portion substantially coincides with the central portion of the region where the gate electrode is to be formed. For example, the gate electrodes (GE1, GE2) have a substantially rectangular shape with a short side L extending in the first direction (x direction) and a long side W extending in the second direction (y direction) intersecting the first direction. It is. That is, the gate length is L and the gate width is W. In this case, the boundary extends in the gate width direction (y direction) at the center (L / 2 position, c) in the gate length direction (x direction) of the region where the gate electrode is to be formed (FIG. 23). (See the left figure).

  Next, a photoresist film having a BARC (Bottom Anti Reflective Coating, antireflection layer, not shown) as a lower layer is formed on the polycrystalline silicon film 4. Next, the photoresist film PR3 is formed by exposing and developing the upper photoresist film. The film thickness of the photoresist film PR3 is, for example, about 780 nm. As shown in FIG. 11, the photoresist film PR3 is left in a region where the gate electrodes (GE1 to GE4) are to be formed. For example, a photoresist film PR3 is formed in the middle portion of the second nMIS region 1C and also in the middle portion of the second pMIS region 1D. On the other hand, in the first nMIS region 1A, a photoresist film PR3 is formed on the region including the boundary between the first region 1As and the second region 1Ad. Also in the first pMIS region 1B, a photoresist film PR3 is formed on a region including the boundary between the first region 1Bs and the second region 1Bd (see the left diagram in FIG. 23).

  Next, the BARC (not shown) is etched using the photoresist film PR3 as a mask, and then the polycrystalline silicon film 4 is etched (selectively removed), and then the photoresist film PR3 containing BARC is ashed. And cleaning (for example, APM cleaning, HPM cleaning, etc.) is performed. Thereby, as shown in FIG. 12, the gate electrode GE3 made of the polycrystalline silicon film 4 doped with the n-type impurity is formed in the second nMIS region 1C, and the p-type impurity is doped in the second pMIS region 1D. A gate electrode GE4 made of the polycrystalline silicon film 4 is formed. In addition, a gate electrode GE1 made of a polycrystalline silicon film 4 doped with n-type impurities is formed in the first nMIS region 1A, and a gate made of a polycrystalline silicon film 4 doped with p-type impurities in the first pMIS region 1B. Electrode GE2 is formed. Here, in the gate electrodes GE1 and GE2, the above-described concentration of the impurity concentration is maintained. That is, in the gate electrode GE1, the n-type impurity concentration at the end on the second region 1Ad side is high, and the n-type impurity concentration is low from the boundary portion to the end on the first region 1As side. Further, in the gate electrode GE2, the concentration of the p-type impurity at the end portion on the second region 1Bd side is high, and the concentration of the p-type impurity is low from the boundary portion to the end portion on the first region 1Bs side.

  As described above, by doping the gate electrodes GE1 to GE4 with impurities, the depletion of the gate electrodes GE1 to GE4 can be reduced, and the characteristics of the MISFET can be improved.

Next, as shown in FIG. 13, heat treatment is performed in an oxidizing atmosphere to form a sidewall oxide film 7 on the sidewalls of the gate electrodes (GE1 to GE4). That is, the sidewall oxide film 7 is formed using a thermal oxidation method. As film formation conditions, for example, in an atmosphere of 100% oxygen (O ₂ ), after crystallization at 650 ° C. for 30 seconds, RTO (Rapid Thermal Oxidation) at 800 ° C. for about 200 seconds is performed and about 2 nm. A sidewall oxide film 7 having a thickness of 5 is formed. This film thickness is the film thickness in the gate length direction (x direction) at the intermediate portion in the thickness direction (z direction) of the gate electrodes (GE1 to GE4) (the x direction and the z direction are shown in the left of FIG. (See figure).

  Here, among the gate electrodes GE1 to GE4, so-called bird's beaks are formed in the sidewall oxide film 7 on both sides of the gate electrode GE3, on both sides of GE4, on the second region 1Ad side of GE1, and on the second region 1Bd side of GE4. Part (7d, 7sd) is generated. Therefore, the thickness of the gate insulating film (the thickness of the side wall oxide film 7) is large on both sides of these gate electrodes GE3, on both sides of GE4, on the second region 1Ad side of GE1, and on the second region 1Bd side of GE4. Become. This is because the higher the impurity concentration, the easier the oxidation, and the thick bird's beak portions (7d, 7sd) are formed in the region having a high impurity concentration in the gate electrode.

  The shape of the bird's beak portion (7d, 7sd) of the sidewall oxide film 7 will be described in detail later.

Next, as shown in FIG. 14, an n ⁻ type semiconductor region (n ⁻ type extension region) EX1 is formed in regions on both sides of the gate electrode GE1 of the p type well PW1 in the first nMIS region 1A. In addition, ap ⁻ type semiconductor region (p ⁻ type extension region) EX2 is formed in regions on both sides of the gate electrode GE2 of the n type well NW1 in the first pMIS region 1B. In addition, n ⁻ type semiconductor regions (n ⁻ type extension regions) EX3 are formed in regions on both sides of the gate electrode GE3 of the p type well PW2 in the second nMIS region 1C. In addition, ap ⁻ type semiconductor region (p ⁻ type extension region) EX4 is formed in regions on both sides of the gate electrode GE4 of the n type well NW2 in the second pMIS region 1D.

The n ⁻ type semiconductor regions EX1 and EX3 are formed, for example, by ion-implanting n-type impurities (for example, phosphorus or arsenic) into the first nMIS region 1A and the second nMIS region 1C using the gate electrodes GE1 and CE3 as a mask. By this step, n ⁻ type semiconductor regions EX1 and EX3 are formed in alignment with the gate electrodes GE1 and GE3, respectively. The p ⁻ type semiconductor regions EX2 and EX4 are formed, for example, by ion-implanting p-type impurities (for example, boron) into the first pMIS region 1B and the second pMIS region 1D using the gate electrodes GE2 and GE4 as a mask. Through this step, p ⁻ type semiconductor regions EX2 and EX4 are formed in alignment with the gate electrodes GE2 and GE4.

  Next, on the main surface of the silicon substrate 1, as an insulating film, for example, a silicon nitride film is deposited with a film thickness of about 10 to 40 nm by a CVD method. By this step, the gate electrodes GE1 to GE4 are covered with the silicon nitride film.

  Next, the silicon nitride film is anisotropically etched (etched back) to form sidewalls (sidewall insulating films, sidewall spacers) SW made of a silicon nitride film on the respective sidewalls of the gate electrodes GE1 to GE4.

Next, n ⁺ type semiconductor regions D1 and S1 are formed in regions on both sides of the gate electrode GE1 and the sidewall SW. Further, p ⁺ type semiconductor regions D2 and S2 are formed in regions on both sides of the gate electrode GE2 and the sidewall SW. In addition, n ⁺ type semiconductor regions SD3 are formed in regions on both sides of the gate electrode GE3 and the sidewall SW. In addition, ap ⁺ type semiconductor region SD4 is formed in regions on both sides of the gate electrode GE4 and the sidewall SW.

The n ⁺ type semiconductor regions D1, S1, and SD3 are formed by ion-implanting n-type impurities (for example, phosphorus or arsenic) into the first nMIS region 1A and the second nMIS region 1C. At this time, since the gate electrode GE1 and the sidewall SW on the sidewall function as an ion implantation blocking mask, the n ⁺ type semiconductor regions D1, S1, and SD3 are formed in alignment with the gate electrode GE1 and the sidewall SW. . The p ⁺ type semiconductor regions D2, S2, and SD4 are formed by ion-implanting p-type impurities (for example, boron) into the first pMIS region 1B and the second pMIS region 1D. At this time, since the gate electrode GE2 and the sidewall SW on the sidewall function as an ion implantation blocking mask, the p ⁺ type semiconductor regions D2, S2, and SD4 are formed in alignment with the gate electrode GE2 and the sidewall SW. .

After ion implantation, annealing treatment (activation annealing, heat treatment) for activating the introduced impurities is performed. For example, spike annealing at about 900 to 1100 ° C. is performed. This activates impurities in the n ⁻ type semiconductor regions EX1 and EX3, the p ⁻ type semiconductor regions EX2 and EX4, the n ⁺ type semiconductor regions D1, S1 and SD3, and the p ⁺ type semiconductor regions D2, S2 and SD4. Can do.

  Through the above steps, n-channel type MISFETs Qn1, Qn2 and p-channel type MISFETs Qp1, Qp2 having impurity regions (impurity region pairs, semiconductor regions, diffusion layers, source / drain regions) having an LDD (Lightly doped Drain) structure are formed. . Thereafter, as shown in FIG. 15, an interlayer insulating film 32 and a plug PG are formed.

  Note that in the MISFET, the “source / drain region” means “a region to be a source region or a drain region”.

The n-channel MISFET Qn2 is a MISFET that is driven so that carriers (in this case, electrons e) flow in both directions. The n ⁺ type semiconductor region SD3 and the n ⁻ type semiconductor region EX3 constituting the impurity region function as a source region or a drain region. The p-channel type MISFET Qp2 is also a MISFET that is driven so that carriers (holes h in this case) flow in both directions. The p ⁺ type semiconductor region SD4 and the p ⁻ type semiconductor region EX4 constituting the impurity region function as a source region or a drain region.

On the other hand, as described above, the n-channel MISFET Qn1 is a MISFET that is driven so that carriers (in this case, electrons e) flow only in one direction. That is, in FIG. 14, the MISFET is driven such that electrons e flow from the n ⁺ type semiconductor region S1 on the first region 1As side to the n ⁺ type semiconductor region D1 on the second region 1Ad side. Note that the direction in which the current flows is opposite to the direction in which the electrons e flow. Therefore, the impurity region of the n-channel type MISFET Qn1 is composed of the n ⁺ type semiconductor regions S1 and D1 and the n ⁻ type semiconductor region EX1. Among the impurity regions, the n ⁺ type semiconductor region S1 and the n ⁻ type semiconductor region EX1 side on the first region 1As side are the source regions, and the n ⁺ type semiconductor region D1 and the n ⁻ type semiconductor region EX1 side on the second region 1Ad side are the source regions. It becomes a drain region. In other words, the n ⁺ type semiconductor region S1 and the n ⁻ type semiconductor region EX1 side on the first region 1As side are the source regions, and the n ⁺ type semiconductor region D1 and the n ⁻ type semiconductor region EX1 side on the second region 1Ad side are the drain regions. As described above, the circuit is connected to another circuit or element by a plug (PG) or a wiring described later.

The p-channel type MISFET Qp1 is a MISFET that is driven so that carriers (in this case, holes h) flow only in one direction. That is, in FIG. 14, the MISFET is driven so that the hole h flows from the p ⁺ type semiconductor region S2 on the first region 1Bs side to the p ⁺ type semiconductor region D2 on the second region 1Bd side. The direction in which the current flows is the same as the direction in which the hole h flows. Therefore, the impurity region of the p-channel type MISFET Qp1 is constituted by the p ⁺ type semiconductor regions S2 and D2 and the p ⁻ type semiconductor region EX2. Among the impurity regions, the p ⁺ type semiconductor region S2 and the p ⁻ type semiconductor region EX2 side on the first region 1Bs side are the source regions, and the p ⁺ type semiconductor region D2 and the p ⁻ type semiconductor region EX2 side on the second region 1Bd side are the source regions. It becomes a drain region. In other words, the p ⁺ type semiconductor region S2 and the p ⁻ type semiconductor region EX2 side on the first region 1Bs side become the source region, and the p ⁺ type semiconductor region D2 and the p ⁻ type semiconductor region EX2 side on the second region 1Bd side become the drain region. As described above, the circuit is connected to another circuit or element by a plug (PG) or a wiring described later.

  Thus, in this embodiment, in the MISFETs (Qn1, Qp1) driven in one direction, the impurity concentration on the drain region side of the gate electrodes (GE1, GE2) is increased, and the impurity concentration on the source region side is increased. Lower. Thus, the bird's beak portion 7d on the drain region side is enlarged and the bird's beak portion 7s on the source region side is reduced (bird's beak portion 7s) by utilizing the difference in oxidation rate (oxidation rate, oxidation rate, and ease of oxidation). Including the case where is not formed). Thus, by increasing the film thickness of the gate insulating film (silicon oxide film 3 and bird's beak portion 7d) at the end on the drain region side, GIDL can be relaxed and off-leakage current can be reduced. In addition, the on-current can be increased by reducing the thickness of the gate insulating film at the end portion on the source region side.

  Hereinafter, the above effect will be described in detail with reference to FIGS. 16, 18, 20, 20, and 22 are cross-sectional views showing the shapes of the gate electrode and the sidewall oxide film of the MISFET (Qn1 or Qp1) of the present embodiment. 17 and 19 are cross-sectional views showing the shapes of the gate electrode and the sidewall oxide film of the MISFET of the comparative example.

  When the sidewall oxide film 7 is formed by thermal oxidation after the concentration (gradient) is generated in the impurities in the gate electrodes (GE1, GE2) as in the present embodiment, as shown in FIG. The bird's beak portion 7d on the higher density side becomes larger.

  On the other hand, in the case of the comparative example shown in FIG. 17, bird's beaks 7d are formed on both sides (source region (S) side and drain region (D) side) of the gate electrode GE. In the case of the comparative example, the photoresist film PR1 is not formed in the first region 1Bs of the first pMIS region 1B shown in FIG. 4, but p-type impurities are implanted into the entire first pMIS region 1B, and the first nMIS region shown in FIG. This means that the photoresist film PR2 is not formed in the first region 1As of 1A and an n-type impurity is implanted into the entire first nMIS region 1A. In this case, the impurity concentration on the source region (S) side also increases, and a relatively large bird's beak portion 7d is also formed on the source region (S) side. Therefore, in the MISFET (Qn1, Qp1) driven in one direction, a relatively large bird's beak portion 7d is formed also on the source region (S) side, and the on-current is reduced.

  Next, the shape of the bird's beak part (7d, 7sd) of the sidewall oxide film 7 will be described. In the present embodiment, the shape of the bottom of the gate electrodes (GE1, GE2) (the shape of the bird's beak portion 7d) can be approximated, for example, as a round shape. That is, the shape of the portion where the polycrystalline silicon film 4 is in contact with the silicon oxide film which is a bird's beak can be approximated as a part of a circle at the side end portion of the bottom of the gate electrode. In this case, as shown in FIG. 18, it can be approximated as a round shape with a radius rd on the drain region (D) side where the impurity concentration is high, and is not rounded on the source region (S) side. On the other hand, in the comparative example, as shown in FIG. 19, not only the drain region (D) side but also the source region (S) side is rounded with a radius rd.

  In the above embodiment, the bird's beak portion is not formed on the source region (S) side (FIGS. 14, 16, 18, etc.). However, in the thermal oxidation process, the gate electrode ( Since the source region (S) side of GE1, GE2) is also exposed, the bird's beak portion 7s may be formed also on the source region (S) side. Such a case is shown in FIG. 20, FIG. 21, and FIG. Thus, even if the bird's beak portion 7s is formed on the source region (S) side, the size thereof is smaller than that of the bird's beak portion 7d on the drain region (D) side. For example, as shown in FIG. 20, the bottom of the gate electrode (GE1, GE2) on the source region (S) side may have a round shape with a radius rs (<rd). For example, in this case, as shown in FIG. 21, the thickness of the sidewall oxide film 7 (bird's beak portion 7d) at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side is T1d. In other words, T1d is a length from the upper surface of the gate insulating film (silicon oxide film 3) to the side wall portion of the gate electrode (GE1, GE2) until the sidewall oxide film 7 starts to be formed almost uniformly in the drain region (D). It can be said. Further, the thickness of the sidewall oxide film 7 (bird's beak portion 7s) at the bottom of the gate electrode (GE1, GE2) on the source region (S) side is T1s. In other words, T1s is from the upper surface of the gate insulating film (silicon oxide film 3) on the source region (S) side until the side wall oxide film 7 starts to be formed almost uniformly on the side wall portions of the gate electrodes (GE1, GE2). It can be called length. At this time, these are in a relationship of T1d> T1s. Therefore, when the thickness of the silicon oxide film 3 is T3, the thickness of the gate insulating film at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side is T3 + T1d. The film thickness of the gate insulating film at the bottom of the gate electrode (GE1, GE2) on the source region (S) side is T3 + T1s. Also in these cases, the relationship of T3 + T1d> T3 + T1s is established. This relationship can be said for both the n-channel MISFET Qn1 and the p-channel MISFET Qp1.

  Thus, by increasing the thickness (T3 + T1d) of the gate insulating film at the end on the drain region (D) side, GIDL can be relaxed and off-leakage current can be reduced. In addition, the on-current can be increased by reducing the thickness (T3 + T1s) of the gate insulating film at the end on the source region (S) side.

  On the other hand, in the case of the comparative example shown in FIG. 17, since the thickness of the gate insulating film at the end on the source region (S) side (≈T3 + T1d) is large, the on-current decreases.

  In FIG. 21 and the like, the shape of the bottom of the gate electrode (GE1, GE2) is approximated as a round shape, but the shape is not limited to this shape, and may be various shapes. For example, as shown in FIG. 22, the shape of the bottom of the gate electrodes (GE1, GE2) may be a tapered shape.

  Also in this case, the gate oxide film 7 (bird's beak portion 7d) at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side has a thickness (or from the upper surface of the gate insulating film (silicon oxide film 3) to the gate. Let T1d be the length until the sidewall oxide film 7 starts to be formed almost uniformly on the sidewalls of the electrodes (GE1, GE2). Then, the gate insulating film (silicon oxide film 3 on the source region (S) side of the side wall oxide film 7 (bird's beak portion 7 s) on the bottom side of the gate electrode (GE1, GE2) on the source region (S) side. ) From the top surface of the gate electrode (GE1, GE2) to the side wall portion of the gate electrode (GE1, GE2) until the sidewall oxide film 7 starts to be formed almost uniformly) is defined as T1s. These have a relationship of T1d> T1s. Accordingly, when the film thickness T3 of the silicon oxide film 3 is set, the film thickness of the gate insulating film at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side is T3 + T1d. The film thickness of the gate insulating film at the bottom of the gate electrode (GE1, GE2) on the source region (S) side is T3 + T1s. Also in these cases, the relationship of T3 + T1d> T3 + T1s is established.

  Thus, the shape of the bird's beak portion 7d may be any shape as long as the thickness of the gate insulating film at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side gradually decreases from T3 + T1d to T3. It is not limited to the round shape or the tapered shape. The bird's beak portion 7s has a shape in which the thickness of the gate insulating film at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side gradually decreases from T3 + T1s (<T3 + T1d) to T3. Well, it is not limited to the round shape or the tapered shape. Further, the bird's beak portion 7s is not formed, that is, T1s may be 0 (zero).

  As described above in detail, in the present embodiment, the characteristics of the MISFETs (Qn1, Qp1) can be improved.

  Furthermore, in the present embodiment, the MISFETs (Qn1, Qp1) having the above-mentioned good characteristics are formed with the same number of masks (photoresist film forming process, patterning process) as the manufacturing process for forming the MISFET of the comparative example. can do.

  Hereinafter, the number of masks will be described with reference to FIGS. FIG. 23 is a plan view showing the configuration of the MISFETs (Qn1 and Qp1) of the present embodiment and the configuration of the MISFETs (Qn and Qp) of the comparative example. In addition, the columns of (STI), (PW), (NW), (PR1), (PR2), and (PR3) are for forming a mask (exposure original plate, mask film, photoresist film) in the following steps. Indicates the area. 24 to 26 are plan views corresponding to the mask formation regions of (PR1), (PR2), and (PR3) of FIG. 23, respectively. 24 to 26, the mask formation region is indicated by dots. 23 to 26, the left side of the drawing shows the case of the present embodiment, and the right side shows the case of the comparative example. In the plan view, the description of the sidewall oxide film 7 is omitted.

  That is, in this embodiment, a mask is formed in the region shown in the column (STI) in FIG. For example, in forming the device isolation trench in the above manufacturing process, the active region is covered with a mask film, and the device isolation trench is formed around the active region. Thereafter, an element isolation region 2 is formed by embedding an insulating film in the element isolation trench.

  In the manufacturing process, when the p-type well PW1 and the n-type well NW1 are formed, a mask is formed in the regions shown in the columns (PW) and (NW) in FIG.

  Further, when the n-type impurity is implanted when the impurity ions are implanted into the polycrystalline silicon film 4 described above, a mask is formed in the column (PR1) in FIG. 23 and the region shown in FIG. 24 (FIG. 4). See also). Further, when the p-type impurity is implanted, a mask is formed in the column (PR2) in FIG. 23 and the region shown in FIG. 25 (see also FIG. 7).

  Further, in the process of forming the gate electrodes GE1 and GE2 (etching process of the polycrystalline silicon film 4), a mask is formed in the column (PR3) in FIG. 23 and the region shown in FIG. 26 (see also FIG. 11). ).

  On the other hand, in the comparative example, as shown on the right side of FIG. 23, in the columns of (PR1) and (PR2), only the mask formation regions are different and the number of masks is the same.

  As described above, according to the present embodiment, it is possible to increase the thickness of the bird's beak portion 7d on the drain region side and reduce the thickness of the bird's beak portion 7s on the source region side without increasing the number of masks. Therefore, the MISFETs (Qn1, Qp1) having good characteristics can be easily formed at low cost and in a short process.

  In addition, in the present embodiment, in the MISFETs (Qn2, Qp2) that are driven so that carriers flow in both directions, the bottoms of the sidewall oxide films 7 on both sides of the gate electrodes (GE3, GE4) are relatively thick. Since the bird's beak portion 7sd is formed, the off-leak current can be reduced regardless of which impurity region is the drain region. Here, when Tsd is the thickness of the bird's beak portion 7sd (the thickness of the sidewall oxide film 7 at the bottom on both sides of the gate electrodes (GE3, GE4)), Tsd≈T1d, and the relationship of Tsd> T1s is established. In this case, the thickness of the gate insulating film at the bottoms on both sides of the gate electrodes (GE3, GE4) is T3 + Tsd. As described above, since the MISFET structure is optimized according to the required function, the characteristics of the entire circuit (device) can be improved.

  After the formation of the MISFETs (Qn1, Qn2, Qp1, Qp2), as described above, the interlayer insulating film 32 and the plug PG are formed. An example of the process after the formation of the MISFET will be described below (see FIG. 15).

After the formation of the MISFET, the surface of the silicon substrate 1 is cleaned, and then the gate electrodes GE1 to GE4, n ⁺ type semiconductor regions D1, S1, SD3, and p ⁺ type semiconductor regions D2, S2, SD4 as necessary. On top of this, a metal silicide layer 23 is formed by a salicide (Salicide: Self Aligned Silicide) technique.

  Next, as the interlayer insulating film 32, for example, silicon oxide is deposited using a CVD method or the like, and then the surface of the interlayer insulating film 32 is planarized using a CMP (Chemical Mechanical Polishing) method or the like.

Next, a plug (connection conductor portion) PG is formed on the n ⁺ type semiconductor regions D1, S1, SD3 and the p ⁺ type semiconductor regions D2, S2, SD4. In order to form the plug PG, first, for example, the contact hole CNT is formed by etching the interlayer insulating film 32. Next, after depositing a barrier conductor film (not shown) on the interlayer insulating film 32 including the inside (on the bottom and side walls), a main conductor film made of a tungsten film or the like is deposited on the barrier conductor film, Unnecessary main conductor films and barrier conductor films on the interlayer insulating film 32 are removed by a CMP method or an etch back method. A plug PG may be formed on the gate electrodes GE1 to GE4.

  Next, although not shown, a stopper insulating film and an interlayer insulating film are sequentially formed on the interlayer insulating film 32 including the plug PG. Next, a first layer wiring (not shown) is formed using a single damascene method or the like. For example, after patterning the interlayer insulating film, the stopper insulating film is etched to form wiring grooves. Next, a barrier conductor film and a seed layer are formed on the interlayer insulating film including the inside of the wiring trench. Next, after a metal plating film is formed on the seed layer using an electrolytic plating method or the like, the metal plating film, the seed layer, and the barrier metal film in regions other than the wiring trench are removed by the CMP method, whereby the first layer The wiring is formed. Thereafter, the second and subsequent wirings are formed by a dual damascene method or the like, but the description thereof is omitted here. Further, the wiring is not limited to damascene wiring, and can be formed by patterning a conductive film for wiring.

  Furthermore, after forming a protective film or the like on the uppermost layer wiring, the silicon substrate 1 is cut (divided) by dicing or the like to form a plurality of semiconductor devices (semiconductor chips).

According to the study of the present inventor, when the sidewall oxide film 7 having a thickness of about 3 nm is formed by dry oxidation for about 15 minutes at 800 ° C. in an atmosphere of 100% oxygen (O ₂ ), the drain region side The gate insulating film thickness (T3 + T1d) was about 5 nm. Thus, the bird's beak part (7d) was confirmed on the drain region side.

  In dry oxidation, since the crystallization process and the sidewall oxidation process are performed simultaneously, the processing time is longer than that of the aforementioned RTO.

  In the present embodiment, the oxidation method is not limited as long as the bird's beak portion is formed in the side wall oxidation step. Of course, in the side wall oxidation step of the above embodiment, the crystallization treatment and RTO are performed. Alternatively, dry oxidation may be performed, or the RTO processing time may be extended to be about several minutes.

[Circuit explanation]
The circuit configuration to which the MISFET (Qn1, Qp1) and MISFET (Qn2, Qp2) are applied is not limited, but can be applied to, for example, an I / O buffer (Input / Output Buffer) circuit. In particular, it can be applied to general-purpose I / O circuits, PLL (Phase locked Loop) circuits, MSC (Master Stop Control) circuits, and the like.

  In addition to an I / O buffer, the present invention can be applied to an ESD (ElectroStatic Discharge) protection circuit, a booster circuit, and the like.

  For example, as a logic circuit constituting the above circuit, for example, in an inverter, the current direction is fixed, so the above MISFET (Qn1, Qp1) is used. On the other hand, for example, the MISFET (Qn2, Qp2) is used as an element for transferring a bidirectional signal from the A circuit to the B circuit and from the B circuit to the A circuit.

(Embodiment 2)
In the first embodiment, the boundary between the first region 1As and the second region 1Ad is provided at the center in the gate length direction of the region where the gate electrode is to be formed (see FIGS. 5 and 8). The boundary portion may be provided closer to the source region than the central portion of the region where the gate electrode is to be formed.

  27 and 28 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. Note that the steps prior to the step of forming the photoresist film PR1 are the same as those in the first embodiment, and a description thereof will be omitted.

  In the present embodiment, as shown in FIG. 27, the second region 1Bd of the first pMIS region 1B is set wide. That is, in the first pMIS region 1B, the boundary between the first region 1Bs and the second region 1Bd is located on the source region side (in the drawing) from the central portion (c) in the gate length direction (x direction) of the region where the gate electrode is to be formed. A photoresist film PR1 is formed so as to be positioned on the right side. Thereafter, using the photoresist film PR1 as a mask, p-type impurities are ion-implanted into the polycrystalline silicon film 4 to remove the photoresist film PR1.

  In the present embodiment, as shown in FIG. 28, the second region 1Ad of the first nMIS region 1A is set wide. That is, in the first nMIS region 1A, the boundary between the first region 1As and the second region 1Ad is located on the source region side (in the drawing) from the center (c) in the gate length direction (x direction) of the region where the gate electrode is to be formed. A photoresist film PR2 is formed so as to be positioned on the right side). Thereafter, n-type impurities are ion-implanted into the polycrystalline silicon film 4 using the photoresist film PR2 as a mask to remove the photoresist film PR2. Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  According to the present embodiment, since the first region (1Ad, 1Bd) is enlarged, the amount of impurity ions to be implanted can be increased, and depletion of the gate electrodes (GE1, GE2) can be effectively reduced. Can do. Further, since the photoresist films (PR1, PR2) exist at the end portions (first regions 1As, 1Bs) on the source region side of the gate electrodes (GE1, GE2), it is possible to prevent impurity ions from being implanted into the regions. The bird's beak (7s) on the source region side can be reduced.

  As described above, by appropriately adjusting the position of the photoresist film PR1, it is possible to optimize the thickness of the bird's beak (7s) on the source region side and the prevention of depletion of the gate electrode.

(Embodiment 3)
In the first embodiment, the first regions 1As and 1Bs are covered with the photoresist films (PR1 and PR2) so that impurity ions are not implanted into the regions (see FIGS. 5 and 8). A narrow slit Sp may be provided in the photoresist films (PR1, PR2) in the first regions 1As, 1Bs.

  29 and 30 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment. Note that the steps prior to the step of forming the photoresist film PR1 are the same as those in the first embodiment, and a description thereof will be omitted.

  In the present embodiment, as shown in FIG. 29, in the first region 1Bs of the first pMIS region 1B, a slit Sp (opening, space) is provided in the photoresist film PR1. The slit Sp has a width of WS2 in the gate length direction (x direction), extends in a line shape in the gate width direction (y direction), and is provided in a plurality at intervals WS1. Here, WS1 and WS2 are set equal. The width WS2 of the slit Sp is smaller than the width W1Bd in the gate length direction (x direction) of the second region 1Bd to be opened. Using the photoresist film PR1 as a mask, p-type impurities are ion-implanted into the polycrystalline silicon film 4 to remove the photoresist film PR1.

  In this case, the p-type impurity is implanted not only in the second region 1Bd but also in the first region 1Bs through the slit Sp. The amount of impurity implantation per unit area is the same as the amount through the slit Sp. The first region 1Bs is smaller than the two regions 1Bd.

  In the present embodiment, as shown in FIG. 30, a photoresist film PR2 having a slit Sp is formed in the first region 1As of the first nMIS region 1A. The slit Sp has a width of WS2 in the gate length direction (x direction), extends in a line shape in the gate width direction (y direction), and is provided in a plurality at intervals WS1. Here, WS1 and WS2 are set equal. The width WS2 of the slit Sp is smaller than the width W1Ad in the gate length direction (x direction) of the opened second region 1Ad. Using the photoresist film PR2 as a mask, n-type impurities are ion-implanted into the polycrystalline silicon film 4 to remove the photoresist film PR2.

  In this case, the n-type impurity is implanted not only in the second region 1Ad but also in the first region 1As through the slit Sp. However, the amount of impurity implantation per unit area is equal to the amount through the slit Sp. The first region 1As is smaller than the two regions 1Ad.

  Since the subsequent steps are the same as those in the first embodiment, description thereof is omitted.

  As described above, according to the present embodiment, the impurities are injected into the first regions 1As and 1Bs through the slits Sp, so that the second regions 1Ad and 1Bd pass through the boundary region to the first regions 1As and 1Bs. The drastic change in the impurity concentration of the gate electrode (GE1, GE2) can be effectively reduced. Further, although impurities are implanted into the end portions (first regions 1As, 1Bs) on the source region side of the gate electrodes (GE1, GE2) through the slits Sp, the concentration is lower than that on the end portion on the drain region side. Therefore, the bird's beak (7s) on the source region side can be made smaller than the bird's beak (7d) on the drain region side.

  Note that the width WS1 and the interval WS2 of the plurality of slits Sp may be changed. That is, the width of the slit Sp may be gradually narrowed toward the source region side. By forming in such a manner, the shape of the bird's beak (7s) (the film thickness on the side walls of the gate electrodes (GE1, GE2)) can be finely adjusted.

(Embodiment 4)
In the first to third embodiments, n-type impurities (for example, phosphorus or arsenic) are applied to the gate electrodes GE1 and GE3 of the n-channel type MISFETs Qn1 and Qn2, and the gate electrodes GE2 and GE4 of the p-channel type MISFETs Qp1 and Qp2 are applied. Respectively implanted p-type impurities (for example, boron). In contrast, in the fourth embodiment, in addition to the n-type impurity, the p-type impurity is added to the gate electrodes GE1 and GE3 of the n-channel type MISFETs Qn1 and Qn2, and the gate electrodes GE2 and GE4 of the p-channel type MISFETs Qp1 and Qp2 are added. An n-type impurity is implanted in addition to the p-type impurity. Since p-type impurities and n-type impurities are injected into one gate electrode (GE1, GE3, GE2, GE4), they are electrically neutralized. Therefore, the electrically neutralized impurities in the gate electrode are removed by appropriately adjusting the injection amount of the p-type impurity and the injection amount of the n-type impurity injected into the polycrystalline silicon forming one gate electrode. It is possible to adjust the concentration of the p-type or n-type impurity to a desired value. On the other hand, for example, the gate electrode into which only the n-type impurity is implanted and the n-type impurity concentration of the gate electrode and the n-type impurity and the p-type impurity (injection amount smaller than the n-type impurity) are electrically When the concentration of both n-type impurities except for the neutralized impurities is equal, a larger bird's beak is formed in the latter case. This is because the higher the impurity concentration, the larger the bird's beak, and the impurity concentration when both the n-type impurity and the p-type impurity are implanted is the n-type impurity concentration and the p-type impurity concentration. This is because the impurity concentration becomes higher. That is, when both n-type and p-type impurities are implanted, the n-type and p-type impurities are electrically neutralized, but the amount of n-type and p-type impurities implanted increases, so that the impurity concentration is reduced. As a result, the bird's beak becomes larger in size. When the bird's beak is formed larger, GIDL can be further relaxed. Alternatively, for example, when considering a case where a resistance element is formed using polycrystalline silicon in the same layer as a gate electrode, polycrystalline silicon that forms a resistance element by electrically neutralizing a p-type impurity and an n-type impurity Therefore, the planar element area of the resistor element for obtaining a desired resistance value can be reduced.

  A method of implanting n-type impurities and p-type impurities into the gate electrodes GE1 and GE3 of the n-channel type MISFETs Qn1 and Qn2 will be described below. For example, in the photoresist film covering the second nMIS region 1C and the first nMIS region 1A formed in the step shown in FIG. 4, a slit as described in the third embodiment is provided in a region where p-type impurities are to be implanted. Thereafter, in the step shown in FIG. 5, when the p-type impurity is implanted into the gate electrodes GE2 and GE4 of the p-channel type MISFETs Qp1 and Qp2, the p-type impurity is implanted into the region where the slit is formed. By adjusting the shape of the slit (the width of the slit, the interval at which the slit is provided, etc.), it is possible to inject a desired p-type impurity concentration. Thereafter, as in the first embodiment, a desired amount of n-type impurity may be implanted in the step shown in FIG.

  The method of implanting the n-type impurity and the p-type impurity into the gate electrodes GE2 and GE4 of the p-channel type MISFETs Qn3 and Qn4 is the same as that of the n-type impurities and the p-type impurities into the gate electrodes GE1 and GE3 of the n-channel type MISFETs Qn1 and Qn2. Similar to the injection method. That is, for example, as in the first embodiment, a desired amount of p-type impurity is implanted in the step shown in FIG. After that, in the photoresist film covering the second pMIS region 1D and the first pMIS region 1B formed in the step shown in FIG. 7, a slit as described in the third embodiment is provided in a region where an n-type impurity is to be implanted. Thereafter, in the step shown in FIG. 8, when an n-type impurity is implanted into the gate electrodes GE1 and GE3 of the n-channel type MISFETs Qn1 and Qn2, a desired amount of the n-type impurity is implanted into the region where the slit is formed. do it.

  By adjusting the region where the slit is formed and the shape of the slit, it is possible to separately create a region where the size of the bird's beak portion (the film thickness of the bird's beak portion) is desired to be larger and a region where it is not.

(Embodiment 5)
In the present embodiment, six MISFETs are formed in the IO region (IO) and the core region (Core) (Qn1 to Qn3, Qp1 to Qp3).

  Hereinafter, the configuration and manufacturing method of the semiconductor device of the present embodiment will be described in detail with reference to the drawings. FIG. 31 is a main-portion cross-sectional view showing the configuration of the semiconductor device of the present embodiment. 32 to 41 are main-portion cross-sectional views showing the manufacturing process of the semiconductor device of the present embodiment.

[Description of structure]
First, a characteristic configuration of the semiconductor device of the present embodiment will be described with reference to FIG.

  As shown in FIG. 31, the semiconductor device of the present embodiment includes an n-channel MISFET Qn1 arranged in the first nMIS region 1A in the IO region (IO) of the silicon substrate (semiconductor substrate) 1, and the silicon substrate 1 P-channel type MISFETQp1 disposed in the first pMIS region 1B. In addition, of the IO regions (IO), an n-channel type MISFET Qn2 disposed in the second nMIS region 1C of the silicon substrate 1 and a p-channel type MISFET Qp2 disposed in the second pMIS region 1D of the silicon substrate 1 are included. ing.

  Furthermore, the semiconductor device of the present embodiment is arranged in the n-channel type MISFET Qn3 arranged in the third nMIS region 1E and the third pMIS region 1F in the core region (Core) of the silicon substrate (semiconductor substrate) 1. a p-channel type MISFET Qp3.

  The MISFETs (Qn1, Qn2, Qp1, Qp2) formed in the IO region (IO) have the same configuration as the MISFETs (Qn1, Qn2, Qp1, Qp2) described in the first embodiment. However, for example, these MISFETs are different from the first embodiment in that Qn2, Qn1, Qp2, and Qp1 are arranged in this order from the left side in FIG. 31 (see FIGS. 31 and 14). The MISFETs (Qn1, Qn2, Qp1, Qp2) formed in the IO region (IO) are high breakdown voltage MISFETs, and the MISFETs (Qn3, Qp3) formed in the core region (Core) are low breakdown voltages. MISFET. Therefore, the MISFETs (Qn3, Qp3) formed in the core region (Core) have a shorter gate length than the MISFETs (Qn1, Qn2, Qp1, Qp2) formed in the IO region (IO). The insulating film has a small thickness (see FIG. 31).

  As described in the first embodiment, as a circuit to which the MISFET (Qn1, Qn2, Qp1, Qp2) formed in the IO region (IO) is applied, for example, an I / O buffer circuit can be exemplified. . In particular, the present invention can be applied to general-purpose I / O circuits, PLL circuits, MSC circuits, and the like. In addition to an I / O buffer, the present invention can also be applied to an ESD protection circuit, a booster circuit, and the like. Here, the MISFETs (Qn2, Qp2) are MISFETs driven so that carriers (holes h or electrons e) flow in both directions, and the MISFETs (Qn1, Qp1) are carriers (holes) in only one direction. The MISFET is driven so that h or electrons e) do not flow (see FIG. 31).

  Moreover, as a circuit to which the MISFET (Qn3, Qp3) formed in the core region (Core) is applied, for example, an analog circuit can be exemplified. Here, the MISFETs (Qn3, Qp3) are MISFETs driven so that carriers (holes h or electrons e) flow in both directions.

  The gate electrodes (GE1 to GE6) of the six MISFETs (Qn1 to Qn3, Qp1 to Qp3) are made of polycrystalline silicon, and impurity ions are implanted to prevent depletion of the gate electrodes (GE1 to GE6). Has been. Specifically, the gate electrodes GE1, GE3, and GE5 of the n-channel type MISFETs Qn1 to Qn3 contain n-type impurities (for example, phosphorus or arsenic). The gate electrodes GE2, GE4, and GE6 of the p-channel type MISFETs Qp1 to Qp3 contain p-type impurities (for example, boron).

  First, MISFETs (Qn1, Qn2, Qp1, Qp2) formed in the IO region (IO) will be described.

The n-channel type MISFET Qn1 includes a gate electrode GE1 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs, semiconductors disposed in the silicon substrate 1 on both sides of the gate electrode GE1). Region, diffusion layer, source / drain region). This impurity region is constituted by n ⁺ type semiconductor regions S1 and D1 and an n ⁻ type semiconductor region EX1. Among the impurity regions, the n ⁺ type semiconductor region S1 side becomes a source region, and the n ⁺ type semiconductor region D1 side becomes a drain region.

Here, in the n-channel MISFET Qn1, the bottom of the gate electrode GE1 on the drain region (n ⁺ -type semiconductor region D1) side is rounded. In other words, a bird's beak portion 7d is formed at the bottom of the sidewall oxide film 7 on the drain region side. Thus, the thickness of the end portion on the drain region (n ⁺ -type semiconductor region D1) side of the gate insulating film (silicon oxide film 3 and bird's beak portion 7d) under the gate electrode GE1 is set to the gate insulation under the gate electrode GE1. Of the film, the thickness is larger than the film thickness of the end portion on the source region (n ⁺ -type semiconductor region S1) side. As for the relationship between these film thicknesses, as described with reference to FIG. 21 in the first embodiment, the sidewall oxide film 7 (bird's beak) at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side. When the thickness of the portion 7d) is T1d and the thickness of the sidewall oxide film 7 (bird's beak portion 7s) at the bottom on the source region (S) side is T1s, the relationship is T1d> T1s.

The p-channel type MISFET Qp1 includes a gate electrode GE2 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs) disposed in the silicon substrate 1 on both sides of the gate electrode GE2. , Semiconductor region, diffusion layer, source / drain region). This impurity region is constituted by p ⁺ type semiconductor regions S2 and D2 and a p ⁻ type semiconductor region EX2. Among the impurity regions, the p ⁺ type semiconductor region S2 side becomes a source region, and the p ⁺ type semiconductor region D2 side becomes a drain region.

Here, in the p-channel type MISFET Qp1, the bottom of the gate electrode GE2 on the drain region (p ⁺ -type semiconductor region D2) side is rounded. In other words, a bird's beak portion 7d is formed at the bottom of the sidewall oxide film 7 on the drain region side. As a result, the thickness of the end portion on the drain region (p ⁺ -type semiconductor region D2) side of the gate insulating film (silicon oxide film 3 and bird's beak portion 7d) under the gate electrode GE2 is equal to the gate insulating film under the gate electrode GE1. Of the film, the thickness is larger than the film thickness of the end portion on the source region (p ⁺ -type semiconductor region S2) side. As for the relationship between these film thicknesses, as described with reference to FIG. 21 in the first embodiment, the sidewall oxide film 7 (bird's beak) at the bottom of the gate electrode (GE1, GE2) on the drain region (D) side. When the thickness of the portion 7d) is T1d and the thickness of the sidewall oxide film 7 (bird's beak portion 7s) at the bottom on the source region (S) side is T1s, the relationship is T1d> T1s.

On the other hand, the n-channel type MISFET Qn2 includes a gate electrode GE3 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs) disposed in the silicon substrate 1 on both sides of the gate electrode GE3. , Semiconductor region, diffusion layer, source / drain region). This impurity region is constituted by an n ⁺ type semiconductor region SD3 and an n ⁻ type semiconductor region EX3. The n-channel type MISFET Qn2 is driven so that a current flows bidirectionally between the impurity region pair. Therefore, in the n ⁺ type semiconductor region SD3, one may be a source region and the other may be a drain region, and one may be a drain region and the other may be a source region.

  Here, in the n-channel MISFET Qn2, the bottoms on both sides of the gate electrode GE3 are rounded. In other words, bird's beak portions 7sd are formed at the bottoms of the sidewall oxide films 7 on both sides of the gate electrode GE3. When the thickness of the sidewall oxide film 7 (bird's beak portion 7sd) is T1sd, T1sd is substantially equal to T1d, and therefore, relational expression 1 of T1sd≈T1d> T1s is established.

The p-channel type MISFET Qp2 includes a gate electrode GE4 disposed on the silicon substrate 1 via the silicon oxide film 3, and impurity regions (impurity region pairs) disposed in the silicon substrate 1 on both sides of the gate electrode GE4. , Semiconductor region, diffusion layer, source / drain region). This impurity region is constituted by a p ⁺ type semiconductor region SD4 and a p ⁻ type semiconductor region EX4. The p-channel type MISFET Qp2 is driven such that a current flows bidirectionally between the impurity region pair. Accordingly, one of the p ⁺ type semiconductor regions SD4 may be a source region and the other may be a drain region, and one may be a drain region and the other may be a source region.

  Here, in the p-channel type MISFET Qp2, the bottoms on both sides of the gate electrode GE4 are rounded. In other words, bird's beak portions 7sd are formed at the bottoms of the sidewall oxide films 7 on both sides of the gate electrode GE4. When the thickness of the sidewall oxide film 7 (bird's beak portion 7sd) is T1sd, T1sd is substantially equal to T1d, and therefore, relational expression 1 of T1sd≈T1d> T1s is established.

  Next, MISFETs (Qn3, Qp3) formed in the core region (Core) will be described.

The n-channel type MISFET Qn3 includes a gate electrode GE5 disposed on the silicon substrate 1 via the silicon oxide film 30, and impurity regions (impurity region pairs, semiconductors disposed in the silicon substrate 1 on both sides of the gate electrode GE5). Region, diffusion layer, source / drain region). This impurity region is constituted by an n ⁺ type semiconductor region SD5 and an n ⁻ type semiconductor region EX5. The n-channel type MISFET Qn3 is driven so that a current flows in both directions between the impurity region pair. Therefore, in the n ⁺ type semiconductor region SD5, one may be a source region and the other may be a drain region, and one may be a drain region and the other may be a source region.

  Here, in the n-channel MISFET Qn3, the bottoms on both sides of the gate electrode GE3 are rounded. In other words, bird's beak portions 70sd are formed at the bottoms of the sidewall oxide films 70 on both sides of the gate electrode GE3. When the thickness of the sidewall oxide film 70 (bird's beak portion 70sd) is T10sd, T10sd is smaller than T1d, and therefore, relational expression 2 of T1sd≈T1d> T10sd is established.

The p-channel type MISFET Qp3 includes a gate electrode GE6 disposed on the silicon substrate 1 via a silicon oxide film 30, and impurity regions (impurity region pairs, semiconductors disposed in the silicon substrate 1 on both sides of the gate electrode GE6). Region, diffusion layer, source / drain region). This impurity region is constituted by a p ⁺ type semiconductor region SD6 and a p ⁻ type semiconductor region EX6. The p-channel type MISFET Qp3 is driven so that a current flows in both directions between the impurity region pair. Therefore, one of the p ⁺ type semiconductor regions SD6 may be a source region and the other may be a drain region, and one may be a drain region and the other may be a source region.

  Here, in the p-channel type MISFET Qp3, the bottoms on both sides of the gate electrode GE6 are rounded. In other words, bird's beak portions 70sd are formed at the bottoms of the sidewall oxide films 70 on both sides of the gate electrode GE6. When the thickness of the sidewall oxide film 70 (bird's beak portion 70sd) is T10sd, T10sd is smaller than T1d, and therefore, relational expression 2 of T1sd≈T1d> T10sd is established.

[Production method explanation]
Next, with reference to FIGS. 32 to 31, the manufacturing method of the semiconductor device of the present embodiment will be described, and the configuration of the semiconductor device will be clarified. In addition, the same code | symbol is attached | subjected to the site | part similar to Embodiment 1, and the detailed description of the manufacturing process is abbreviate | omitted.

  First, as shown in FIG. 32, a silicon substrate 1 is prepared as a semiconductor substrate (semiconductor wafer), and an element isolation region 2 is formed on the main surface of the silicon substrate 1. For example, element isolation grooves surrounding the first nMIS region 1A, the first pMIS region 1B, the second nMIS region 1C, the second pMIS region 1D, the third nMIS region 1E, and the third pMIS region 1F are formed on the silicon substrate 1, and the element isolation grooves are formed. An element isolation region 2 is formed by embedding an insulating film inside the substrate.

  Next, the p-type well PW1 is formed in the first nMIS region 1A of the silicon substrate 1, the n-type well NW1 is formed in the first pMIS region 1B of the silicon substrate 1, the p-type well PW2 is formed in the second nMIS region 1C of the silicon substrate 1, and the silicon substrate 1 is formed. An n-type well NW2 is formed in the second pMIS region 1D, a p-type well PW3 is formed in the third nMIS region 1E of the silicon substrate 1, and an n-type well NW3 is formed in the third pMIS region 1F of the silicon substrate 1, respectively.

  Next, after the surface of the silicon substrate 1 is cleaned (washed) by wet etching using a hydrofluoric acid (HF) aqueous solution, for example, the IO region (IO) of the silicon substrate 1, that is, the p-type wells PW1, PW2, and n A silicon oxide film 3 is formed on the surfaces of the type wells NW1 and NW2, and a silicon oxide film 30 is formed on the surfaces of the core regions (Core), that is, the p-type well PW3 and the n-type well NW3. The silicon oxide films 3 and 30 are films constituting a gate insulating film and can be formed by, for example, a thermal oxidation method. For example, when the core region (Core) is thermally oxidized, the IO region (IO) is covered with a mask film, and when the IO region (IO) is thermally oxidized, the core region (Core) is covered with a mask film, Each region is thermally oxidized under different conditions. Through this process, silicon oxide films (3, 30) having different thicknesses can be formed. The film thickness of the silicon oxide film 3 is larger than the film thickness of the silicon oxide film 30. As an example, the film thickness of the silicon oxide film 3 is about 15 nm, and the film thickness of the silicon oxide film 30 is about 3 nm. The silicon oxide films 3 and 30 may be formed using a CVD (Chemical Vapor Deposition) method or the like. Further, instead of the silicon oxide films 3 and 30, other insulating films such as a silicon nitride film may be used.

  Next, as shown in FIG. 33, a polycrystalline silicon film (polysilicon film) 4 is formed as a conductive film on the silicon oxide films 3 and 30 with a film thickness of about 50 to 150 nm using, for example, a CVD method. . Note that an amorphous silicon film (amorphous silicon film) may be formed and subjected to heat treatment to be polycrystallized.

  Next, a photoresist film is applied on the main surface of the silicon substrate 1, that is, on the polycrystalline silicon film 4, and the photoresist film is exposed and developed. The film thickness of the photoresist film is, for example, about 410 nm.

  Thus, the third nMIS region 1E, the second nMIS region 1C, the first nMIS region 1A, and the first region 1Bs of the first pMIS region 1B are covered, and the third pMIS region 1F, the second pMIS region 1D, and the second region 1Bd of the first pMIS region 1B are covered. An opened photoresist film (mask film, resist film, resist pattern) PR1 is formed. That is, the third pMIS region 1F, the second pMIS region 1D, and the second region 1Bd of the first pMIS region 1B of the polycrystalline silicon film 4 are exposed.

Next, a p-type impurity (for example, boron) is ion-implanted into the polycrystalline silicon film 4 using the photoresist film PR1 as a mask. As an implantation condition, for example, boron is implanted at an energy of 3 keV and at a concentration of about 2E15 / cm ² . Note that 2E15 represents 2 × 10 ¹⁵ . As a result, the p-type impurity is implanted into the polycrystalline silicon film 4 in the third pMIS region 1F, the second pMIS region 1D, and the second region 1Bd of the first pMIS region 1B (FIG. 34). In FIG. 34, the state in which impurities (impurity ions) are implanted is schematically shown by dots. Next, the photoresist film PR1 is removed by ashing or the like, and cleaning (for example, APM cleaning or HPM cleaning) is performed.

  Next, a photoresist film is applied on the main surface of the silicon substrate 1, that is, on the polycrystalline silicon film 4, and the photoresist film is exposed and developed. The film thickness of the photoresist film is, for example, about 410 nm.

  Thus, the third pMIS region 1F, the second pMIS region 1D, the first pMIS region 1B and the first region 1As of the first nMIS region 1A are covered, and the third nMIS region 1E, the second nMIS region 1C and the second region 1Ad of the first nMIS region 1A are covered. An opened photoresist film PR2 is formed.

Next, n-type impurities (for example, phosphorus or arsenic) are ion-implanted into the polycrystalline silicon film 4 using the photoresist film PR2 as a mask. As the implantation conditions, for example, phosphorus is implanted at a concentration of about 6E15 / cm ² at an energy of 10 keV. Thereby, as shown in FIG. 35, the n-type impurity is implanted into the polycrystalline silicon film 4 in the third nMIS region 1E, the second nMIS region 1C, and the second region 1Ad of the first nMIS region 1A. Also in FIG. 35, the state in which impurities are implanted is schematically shown by dots. Next, the photoresist film PR2 is removed by ashing or the like, and cleaning (for example, APM cleaning or HPM cleaning) is performed.

  By the ion implantation process described above, impurities are not implanted into the polycrystalline silicon film 4 in the first region 1As of the first nMIS region 1A and the first region 1Bs of the first pMIS region 1B, and the polycrystalline silicon film in the other regions. 4, n-type or p-type impurities are implanted (see FIG. 35). The other regions are the second region 1Ad of the first nMIS region 1A, the second region 1Bd of the first pMIS region 1B, the second nMIS region 1C, the second pMIS region 1D, the third nMIS region 1E, and the third pMIS region 1F. It is.

  Next, annealing treatment (activation annealing, heat treatment) for activating the implanted n-type or p-type impurities is performed. For example, RTA is performed at 900 ° C. for about 10 seconds. As a result, n-type or p-type impurities in the polycrystalline silicon film 4 are diffused and activated (FIG. 36). Due to the diffusion of the impurities during the annealing process, the impurities are diffused in the polycrystalline silicon film 4 also in the first region 1As of the first nMIS region 1A and the first region 1Bs of the first pMIS region 1B where no impurity has been implanted. Thus, as shown in FIG. 36, in the first nMIS region 1A, the impurity concentration in the polycrystalline silicon film 4 is reduced so that the impurity concentration decreases in the order of the second region 1Ad, the boundary region, and the first region 1As. (Gradient) occurs. The boundary region means a boundary portion between the first region 1As and the second region 1Ad and a region in the vicinity thereof. Further, in the first pMIS region 1B, the concentration of the impurity concentration is generated in the polycrystalline silicon film 4 so that the impurity concentration decreases in the order of the second region 1Bd, the boundary region, and the first region 1Bs. The boundary region means a boundary portion between the first region 1Bs and the second region 1Bd and a region in the vicinity thereof. In the present embodiment, the boundary portion substantially coincides with the central portion of the region where the gate electrode is to be formed. For example, the gate electrodes (GE1, GE2) have a substantially rectangular shape with a short side L extending in the first direction (x direction) and a long side W extending in the second direction (y direction) intersecting the first direction. It is. That is, the gate length is L and the gate width is W. In this case, the boundary extends in the gate width direction (y direction) at the center (L / 2 position, c) in the gate length direction (x direction) of the region where the gate electrode is to be formed (FIG. 23). (See the left figure).

  Next, a photoresist film (not shown) having BARC as a lower layer is formed on the polycrystalline silicon film 4. Next, the upper photoresist film is exposed and developed to form a photoresist film. The thickness of this photoresist film is, for example, about 780 nm. This photoresist film is left in the region where the gate electrodes (GE1 to GE6) are to be formed.

  Next, using the photoresist film as a mask, the BARC (not shown) is etched, and then the polycrystalline silicon film 4 is etched (selectively removed), and then the photoresist film containing the BARC is removed by ashing or the like. And cleaning (for example, APM cleaning, HPM cleaning, etc.) is performed. As a result, as shown in FIG. 37, the gate electrode GE5 made of the polycrystalline silicon film 4 doped with the n-type impurity is formed in the third nMIS region 1E, and the p-type impurity is doped in the third pMIS region 1F. A gate electrode GE6 made of the polycrystalline silicon film 4 is formed. A gate electrode GE3 made of a polycrystalline silicon film 4 doped with an n-type impurity is formed in the second nMIS region 1C, and a gate made of a polycrystalline silicon film 4 doped with a p-type impurity in the second pMIS region 1D. Electrode GE4 is formed. In addition, a gate electrode GE1 made of a polycrystalline silicon film 4 doped with n-type impurities is formed in the first nMIS region 1A, and a gate made of a polycrystalline silicon film 4 doped with p-type impurities in the first pMIS region 1B. Electrode GE2 is formed.

  Here, in the gate electrodes GE1 and GE2, the above-described concentration of the impurity concentration is maintained. That is, in the gate electrode GE1, the n-type impurity concentration at the end on the second region 1Ad side is high, and the n-type impurity concentration is low from the boundary portion to the end on the first region 1As side. Further, in the gate electrode GE2, the concentration of the p-type impurity at the end portion on the second region 1Bd side is high, and the concentration of the p-type impurity is low from the boundary portion to the end portion on the first region 1Bs side.

  The gate lengths (L) of the gate electrodes (GE1 to GE4) are substantially equal and larger than the gate lengths of the gate electrodes (GE5, GE6). As an example, the gate length (L) of the gate electrodes (GE1 to GE4) is 1 μm (= 1000 nm), and the gate lengths of the gate electrodes (GE5 and GE6) are 50 nm.

  Thus, by doping the gate electrodes GE1 to GE6 with impurities, the depletion of the gate electrodes GE1 to GE4 can be reduced, and the characteristics of the MISFET can be improved.

Next, as shown in FIG. 38, for example, n-type impurities (for example, phosphorus or arsenic) are ion-implanted into the first nMIS region 1A and the second nMIS region 1C using the gate electrodes GE1 and CE3 as a mask. That is, the first pMIS region 1B, the second pMIS region 1D, the third pMIS region 1F, and the third nMIS region 1E that do not require ion implantation are covered with the photoresist film PR21, and the n ⁻ type semiconductor region EX1, Perform ion implantation for EX3. As the ion implantation conditions, for example, phosphorus is ion-implanted with an energy of 80 keV and a concentration of 2E13 / cm ² . In FIG. 38 and subsequent figures, this ion implantation region is indicated by a cross. In this step, n ⁻ type semiconductor regions EX1 and EX3 are formed by performing an annealing process (heat treatment) described later on the implanted ions.

  Here, as will be described later, n-type impurities (for example, phosphorus or arsenic) are ion-implanted also into the third nMIS region 1E. However, since the ion implantation conditions are different, the ion-implantation is performed by covering with the photoresist film PR21 here. Absent.

Next, with the photoresist film PR21 remaining, heat treatment is performed in an oxidizing atmosphere to form a sidewall oxide film 7 on the sidewalls of the gate electrodes GE3 and GE1. That is, the sidewall oxide film 7 is formed using a thermal oxidation method. As film formation conditions, for example, in an atmosphere of 100% oxygen (O ₂ ), after crystallization at 650 ° C. for 30 seconds, RTO is performed at 800 ° C. for about 200 seconds, and a sidewall having a thickness of about 2 nm is formed. An oxide film 7 is formed. This film thickness is the film thickness in the gate length direction (x direction) at the intermediate portion in the thickness direction (z direction) of the gate electrodes (GE1 to GE4) (the x direction and the z direction are shown in the left of FIG. (See figure).

  Here, so-called bird's beak portions (7d, 7sd) are generated in the sidewall oxide film 7 on both sides of the gate electrode GE3 and the bottom of the GE1 on the second region 1Ad side. Therefore, the film thickness of the gate insulating film (the film thickness of the sidewall oxide film 7) increases on both sides of the gate electrode GE3 and on the bottom of the GE1 on the second region 1Ad side. This is because the higher the impurity concentration, the easier the oxidation, and the thick bird's beak portions (7d, 7sd) are formed in the region having a high impurity concentration in the gate electrode. Thereafter, the photoresist film PR21 is removed.

Next, as shown in FIG. 39, for example, p-type impurities (for example, boron) are ion-implanted into the first pMIS region 1B and the second pMIS region 1D using the gate electrodes GE2 and GE4 as a mask. That is, the first nMIS region 1A, the second nMIS region 1C, the third pMIS region 1F, and the third nMIS region 1E that do not require ion implantation are covered with the photoresist film PR22, and the p ⁻ type semiconductor region EX2, using the photoresist film PR22 as a mask, Perform ion implantation for EX4. As an ion implantation condition, for example, boron is ion-implanted at a concentration of 4E13 / cm ² with an energy of 10 keV. In this step, the implanted ions are subjected to an annealing process (heat treatment) to be described later, whereby p ⁻ type semiconductor regions EX2 and EX4.

  Here, a p-type impurity (for example, boron) is also ion-implanted into the third pMIS region 1F as will be described later. However, since the ion implantation conditions are different, here, the third pMIS region 1F is covered with the photoresist film PR22 and ion implantation is not performed.

Next, with the photoresist film PR22 remaining, heat treatment is performed in an oxidizing atmosphere to form a sidewall oxide film 7 on the sidewalls of the gate electrodes GE4 and GE2. That is, the sidewall oxide film 7 is formed using a thermal oxidation method. As film formation conditions, for example, in an atmosphere of 100% oxygen (O ₂ ), after crystallization at 650 ° C. for 30 seconds, RTO (Rapid Thermal Oxidation) at 800 ° C. for about 200 seconds is performed and about 2 nm. A sidewall oxide film 7 having a thickness of 5 is formed. This film thickness is the film thickness in the gate length direction (x direction) at the intermediate portion in the thickness direction (z direction) of the gate electrodes (GE1 to GE4) (the x direction and the z direction are shown in the left of FIG. (See figure).

  Here, so-called bird's beak portions (7d, 7sd) are generated in the sidewall oxide film 7 on both sides of the gate electrode GE4 and on the bottom of the GE2 on the second region 1Bd side. Therefore, the thickness of the gate insulating film (the thickness of the sidewall oxide film 7) increases on both sides of the gate electrode GE4 and on the bottom of the GE2 on the second region 1Ad side. This is because the higher the impurity concentration, the easier the oxidation, and the thick bird's beak portions (7d, 7sd) are formed in the region having a high impurity concentration in the gate electrode. Thereafter, the photoresist film PR22 is removed.

Next, as shown in FIG. 40, for example, n-type impurities (for example, phosphorus or arsenic) are ion-implanted into the third nMIS region 1E using the gate electrode GE5 as a mask. That is, a region other than the third nMIS region 1E that does not require ion implantation is covered with the photoresist film PR23, and ion implantation for the n ⁻ type semiconductor region EX5 is performed. As an ion implantation condition, for example, arsenic is ion-implanted with an energy of 10 keV and a concentration of 2E14 / cm ² . In this step, the implanted ions are subjected to an annealing process (heat treatment) to be described later, whereby the n ⁻ type semiconductor region EX5 is formed.

Next, with the photoresist film PR23 remaining, heat treatment is performed in an oxidizing atmosphere to form a sidewall oxide film 70 on the sidewall of the gate electrode GE5. That is, the sidewall oxide film 70 is formed using a thermal oxidation method. The film forming conditions are about 2 nm after crystallization treatment at 650 ° C. for 30 seconds in an atmosphere of 100% oxygen (O ₂ ), followed by RTO at about 800 ° C. for about 200 seconds. This film thickness is the film thickness in the gate length direction (x direction) at the intermediate portion in the thickness direction (z direction) of the gate electrode (GE5) (see the left figure of FIG. 23 for the x direction and z direction). ).

  Here, so-called bird's beak portions (70sd) are formed in the sidewall oxide film 70 at the bottoms on both sides of the gate electrode GE5. However, under the film formation conditions of the sidewall oxide film 70, the bird's beak portion 70sd has a very small film thickness, for example, about 0.05 nm. Thereafter, the photoresist film PR23 is removed.

Next, as shown in FIG. 41, for example, p-type impurities (for example, boron) are ion-implanted into the third pMIS region 1F using the gate electrode GE6 as a mask. That is, regions other than the third pMIS region 1F that do not require ion implantation are covered with the photoresist film PR24, and ion implantation for the p ⁻ type semiconductor region EX6 is performed. As ion implantation conditions, for example, boron difluoride is ion-implanted at a concentration of 2E14 / cm ² with an energy of 3 keV. In this step, the implanted ions are subjected to an annealing process (heat treatment) to be described later, whereby the p ⁻ type semiconductor region EX6 is formed.

Next, with the photoresist film PR24 remaining, heat treatment is performed in an oxidizing atmosphere to form a sidewall oxide film 70 on the sidewall of the gate electrode GE6. That is, the sidewall oxide film 70 is formed using a thermal oxidation method. The film forming conditions are about 2 nm after crystallization treatment at 650 ° C. for 30 seconds in an atmosphere of 100% oxygen (O ₂ ), followed by RTO at about 800 ° C. for about 200 seconds. This film thickness is the film thickness in the gate length direction (x direction) at the intermediate portion in the thickness direction (z direction) of the gate electrode (GE6) (see the left figure of FIG. 23 for the x direction and the z direction). ).

  Here, so-called bird's beak portions (70sd) are generated in the sidewall oxide film 70 at the bottoms on both sides of the gate electrode GE6. However, under the conditions for forming the sidewall oxide film 70, the thickness of the bird's beak portion 70sd is extremely small, for example, about 0.04 nm. Thereafter, the photoresist film PR24 is removed.

  By the step of forming the sidewall oxide films 7 and 70, bird's beak portions (7d, 7sd, 70sd) satisfying the above relational expressions 1 and 2 are formed (see FIG. 31).

That is, in the n-channel type MISFET Qn1, the bird's beak portion 7d is formed at the bottom of the sidewall oxide film 7 on the drain region side, and the film thickness of the end portion on the drain region (n ⁺ type semiconductor region D1) side is the gate electrode GE1. Of the lower gate insulating film, the thickness is larger than the film thickness of the end portion on the source region (n ⁺ type semiconductor region S1) side. At this time, the thickness of the bottom sidewall oxide film 7 (bird's beak portion 7d) on the drain region (D) side of the gate electrodes (GE1, GE2) is T1d, and the bottom sidewall oxide film 7 (on the source region (S) side) ( When the film thickness of the bird's beak portion 7s) is T1s, the relationship is T1d> T1s.

Further, in the p-channel type MISFET Qp1, a bird's beak portion 7d is formed at the bottom of the side wall oxide film 7 on the drain region side, and the film thickness of the end portion on the drain region (p ⁺ type semiconductor region D2) side is the gate electrode GE1. Of the lower gate insulating film, the thickness is larger than the film thickness of the end portion on the source region (p ⁺ -type semiconductor region S2) side. At this time, the thickness of the bottom sidewall oxide film 7 (bird's beak portion 7d) on the drain region (D) side of the gate electrodes (GE1, GE2) is T1d, and the bottom sidewall oxide film 7 (on the source region (S) side) ( When the film thickness of the bird's beak portion 7s) is T1s, the relationship is T1d> T1s.

  On the other hand, in the n-channel type MISFET Qn2, a bird's beak portion 7sd is formed at the bottom of the sidewall oxide film 7 on both sides of the gate electrode GE3, and the thickness of the sidewall oxide film 7 (bird's beak portion 7sd) is T1sd. Is substantially equal to T1d, and therefore, relational expression 1 of T1sd≈T1d> T1s holds.

  Further, in the p-channel type MISFET Qp2, a bird's beak portion 7sd is formed at the bottom of the sidewall oxide film 7 on both sides of the gate electrode GE4, and the thickness of the sidewall oxide film 7 (bird's beak portion 7sd) is T1sd. Is substantially equal to T1d, and therefore, relational expression 1 of T1sd≈T1d> T1s holds.

  In the channel type MISFET Qn3, a bird's beak portion 70sd is formed at the bottom of the side wall oxide film 70 on both sides of the gate electrode GE3. When the thickness of the side wall oxide film 70 (bird's beak portion 70sd) is T10sd, T10sd is Therefore, the relational expression 2 of T1sd≈T1d> T10sd is established.

  In the p-channel type MISFET Qp3, a bird's beak portion 70sd is formed at the bottom of the sidewall oxide film 70 on both sides of the gate electrode GE6. When the thickness of the sidewall oxide film 70 (bird's beak portion 70sd) is T10sd, T10sd is Therefore, the relational expression 2 of T1sd≈T1d> T10sd is established.

  The definition of the film thickness of the sidewall oxide films 7, 70 (bird's beak portion, 7d, 7sd, 70sd) is as described in the first embodiment with reference to FIG.

  Thereafter, for example, a silicon nitride film is deposited on the main surface of the silicon substrate 1 with a film thickness of about 10 to 40 nm by a CVD method as an insulating film. By this step, the gate electrodes GE1 to GE6 are covered with the silicon nitride film.

  Next, the silicon nitride film is anisotropically etched (etched back) to form sidewalls (sidewall insulating films, sidewall spacers) SW made of a silicon nitride film on the respective sidewalls of the gate electrodes GE1 to GE6.

Next, ion implantation for forming the n ⁺ -type semiconductor regions D1 and S1 is performed in regions on both sides of the gate electrode GE1 and the sidewall SW. In addition, ion implantation for forming the n ⁺ type semiconductor regions SD3 and SD5 is performed in regions on both sides of the gate electrodes GE3 and GE5 and the sidewall SW. Here, the first to third pMIS regions (1B, 1D, 1F) are covered with a photoresist film (not shown), and ion implantation is simultaneously performed on the first to third nMIS regions (1A, 1C, 1E). I do.

Next, the photoresist film is removed, and ion implantation for forming p ⁺ -type semiconductor regions D2 and S2 is performed in regions on both sides of the gate electrode GE2 and the sidewall SW. Further, ion implantation for forming the n ⁺ -type semiconductor regions SD4 and SD6 is performed in the regions on both sides of the gate electrodes GE4 and GE6 and the sidewall SW. Here, the first to third nMIS regions (1A, 1C, 1E) are covered with a photoresist film (not shown), and ion implantation is simultaneously performed on the first to third pMIS regions (1B, 1D, 1F). I do.

After the ion implantation, annealing treatment (activation annealing, heat treatment) for activating the introduced impurities is performed. For example, spike annealing at about 900 to 1100 ° C. is performed. Thereby, the impurity implanted into each region is diffused and activated. Thereby, the n ⁻ type semiconductor regions EX1, EX3, EX5, the p ⁻ type semiconductor regions EX2, EX4, EX6, the n ⁺ type semiconductor regions D1, S1, SD3, SD5 and the p ⁺ type semiconductor regions D2, S2, SD4, SD6. Can be formed (see FIG. 31).

  Through the above steps, n-channel MISFETs Qn1, Qn2, Qn3 and p-channel MISFETs Qp1, Qp2, Qp3 having impurity regions (impurity region pairs, semiconductor regions, diffusion layers, source / drain regions) having an LDD structure are formed ( FIG. 31). Thereafter, similar to the first embodiment, the interlayer insulating film 32 and the plug PG are formed.

  Thus, also in this embodiment, the same effect as in the first embodiment is obtained. That is, in the MISFETs (Qn1, Qp1) driven in one direction, the impurity concentration on the drain region side of the gate electrodes (GE1, GE2) is increased, and the impurity concentration on the source region side is decreased. Thus, the bird's beak portion 7d on the drain region side is enlarged and the bird's beak portion 7s on the source region side is reduced (bird's beak portion 7s) by utilizing the difference in oxidation rate (oxidation rate, oxidation rate, and ease of oxidation). Including the case where is not formed). Thus, by increasing the film thickness of the gate insulating film (silicon oxide film 3 and bird's beak portion 7d) at the end on the drain region side, GIDL can be relaxed and off-leakage current can be reduced. In addition, the on-current can be increased by reducing the thickness of the gate insulating film at the end portion on the source region side.

Furthermore, in the present embodiment, the ion implantation masks (PR21 to PR24) of the low concentration semiconductor regions (n ⁻ type semiconductor regions EX1, EX3, EX5, p ⁻ type semiconductor regions EX2, EX4, EX6) are used, Side wall oxidation was performed. Thereby, the gate electrode (GE5, GE6) of the MISFET in the core region (Core) and the IO region (IO) without increasing the number of masks (number of exposure original plates) and the mask process (photoresist film forming step). Bird's beaks can be selectively formed on the gate electrodes (GE1 to GE4) of the MISFETs. In other words, the gate electrodes (GE5, GE6) of the MISFET in the core region (Core) and the IO region (IO) without increasing the number of masks (the number of exposure original plates) and the mask process (photoresist film forming step). The side wall oxidation amount and bird's beak amount of the gate electrodes (GE1 to GE4) of the MISFETs can be changed.

  In the present embodiment, the amount of bird's beak with respect to the gate electrode (GE5, GE6) of the MISFET in the core region (Core) is designed to be fine, that is, the gate length is small and the gate insulating film is thin. Can do.

  As described above, regarding the thickness of the bird's beak portion of each MISFET (Qn1 to Qn3, Qp1 to Qp3), T1sd≈T1d> T1s... Relation 1 and T1sd≈T1d> T10sd. Therefore, according to the present embodiment, it is possible to easily form bird's beaks satisfying these relational expressions in a short process.

  In the present embodiment also, the photoresist film described in the second to fourth embodiments may be applied when forming the MISFETs (Qn1, Qn2, Qp1, Qp2) in the IO region (IO). Also, when forming the MISFETs (Qn3, Qp3) in the core region (Core), the impurity concentration in the gate electrodes (GE5, GE6) may be adjusted using the photoresist film described in the fourth embodiment.

  Although the invention made by the present inventor has been specifically described based on the embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to semiconductor devices and semiconductor device manufacturing techniques.

1 silicon substrate 1A first nMIS region 1Ad second region 1As first region 1B first pMIS region 1Bd second region 1Bs first region 1C second nMIS region 1D second pMIS region 1E third nMIS region 1F third pMIS region 2 element isolation region 3 silicon oxide Film 30 Silicon oxide film 4 Polycrystalline silicon film 7 Side wall oxide film 70 Side wall oxide film 7d Bird's beak portion 7s Bird's beak portion 7sd Bird's beak portion 70sd Bird's beak portion 23 Metal silicide layer 32 Interlayer insulating film CNT Contact hole D Drain region D1 n ⁺ type semiconductor region D2 p ⁺ type semiconductor region e Electron EX1, EX3 n ⁻ type semiconductor region EX2, EX4 p ⁻ type semiconductor region EX5 n ⁻ type semiconductor region EX6 p − type semiconductor region GE, GE1, GE2, GE3, GE4 Gate electrode G E5, GE6 Gate electrode h Hole NW1, NW2, NW3 n-type well PG plug PR1, PR2, PR3 photoresist films PR21, PR22, PR23, PR24 photoresist films PW, PW1, PW2, PW3 p-type wells Qn, Qn1, Qn2 Qn3 n-channel MISFET
Qp, Qp1, Qp2, Qp3 p-channel MISFET
rd, rs, rsd radius S source region Sp slit S1 n ⁺ type semiconductor region S2 p ⁺ type semiconductor region SD3, SD5 n ⁺ type semiconductor region SD4, SD6 p ⁺ type semiconductor region SW sidewall T1d film thickness T1s film thickness T1sd film Thickness T10sd Film thickness T3 Film thickness W1Ad, W1Bd, WS1 Width WS2 Interval

Claims (21)

Forming an insulating film on the semiconductor substrate;
Forming a conductive film on the insulating film;
Forming a mask film formed on the conductive film, covering the first region of the conductive film and opening a second region adjacent to the first region;
Implanting impurity ions into the conductive film through the mask film;
Forming a gate electrode in a region including a boundary between the first region and the second region by selectively removing the conductive film;
Applying heat treatment to form an oxide film on the side wall of the gate electrode;
A drain region is formed in the semiconductor substrate located below the end of the gate electrode on the second region side, and in the semiconductor substrate located below the end of the gate electrode on the first region side Forming a source region;
A method for manufacturing a semiconductor device, comprising: The oxide film is formed on the side wall and bottom of the gate electrode on the drain region side, and on the side wall and bottom of the gate electrode on the source region side,
The sum of the film thickness of the oxide film and the insulating film at the bottom on the drain region side is larger than the sum of the film thickness of the oxide film and the insulating film on the bottom on the source region side. A method for manufacturing a semiconductor device according to claim 1. The gate electrode has a predetermined width in a first direction and is formed to extend in a second direction intersecting the first direction;
2. The method of manufacturing a semiconductor device according to claim 1, wherein a boundary between the first region and the second region is located at an intermediate portion of the predetermined width and extends in the second direction. The gate electrode has a predetermined width in a first direction and is formed to extend in a second direction intersecting the first direction;
2. The semiconductor device according to claim 1, wherein a boundary between the first region and the second region is located closer to the source region than an intermediate portion having the predetermined width and extends in the second direction. Production method. The gate electrode has a predetermined width in a first direction and is formed to extend in a second direction intersecting the first direction;
The mask film has a plurality of openings on the first region,
2. The method of manufacturing a semiconductor device according to claim 1, wherein widths of the plurality of openings in the first direction are smaller than widths of the openings in the second region in the first direction.   The method of manufacturing a semiconductor device according to claim 1, wherein the conductive film is a silicon film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity ions are n-type impurity ions.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the impurity ions are p-type impurity ions. Forming an insulating film on a semiconductor substrate having a first element formation region and a second element formation region;
Forming a conductive film on the insulating film;
A mask film disposed on the conductive film, covering a first region of the conductive film located in the first element formation region, and opening a second region adjacent to the first region; A step of forming a mask film having an opening in the second element formation region;
Implanting impurity ions into the conductive film through the mask film;
By selectively removing the conductive film,
Forming a first gate electrode in a region including a boundary between the first region and the second region in the first element formation region, and forming a second gate electrode in the second element formation region;
Applying heat treatment to form an oxide film on the side walls of the first gate electrode and the second gate electrode;
Forming a first conductivity type impurity region pair in the semiconductor substrate on both sides of the first gate electrode and forming a second conductivity type impurity region pair in the semiconductor substrate on both sides of the second gate electrode; When,
A method for manufacturing a semiconductor device, comprising: The oxide film is formed on the side wall and bottom of the first gate electrode on the second region side, and on the side wall and bottom of the first gate electrode on the first region side,
The sum of the film thickness of the oxide film and the insulating film at the bottom on the second region side is larger than the sum of the film thickness of the oxide film and the insulating film on the bottom on the first region side. A method for manufacturing a semiconductor device according to claim 9. The oxide film is formed on a sidewall and a bottom portion of the first gate electrode on the second region side, and on a sidewall and a bottom portion of the first gate electrode on the first region side, and further on both sides of the second gate electrode. Formed on the side wall and bottom of
The sum of the film thickness of the oxide film and the insulating film at the bottom on both sides of the second gate electrode is greater than the sum of the film thickness of the oxide film and the insulating film at the bottom on the first region side, respectively. The method of manufacturing a semiconductor device according to claim 9, wherein the semiconductor device is large. The first conductivity type impurity region pair is a constituent part of a first field effect transistor,
The first field effect transistor is:
Of the first conductivity type impurity region pair, the first impurity region on the second region side of the first gate electrode is a drain,
10. The semiconductor device according to claim 9, wherein the semiconductor device is driven by using, as a source, the first impurity region on the first region side of the first gate electrode in the first conductivity type impurity region pair. Production method. The first conductivity type impurity region pair is a constituent part of a first field effect transistor,
The first field effect transistor is:
Of the first conductivity type impurity region pair, the first impurity region on the second region side of the first gate electrode is a drain,
Of the first conductivity type impurity region pair, the first impurity region on the first region side of the first gate electrode is driven as a source,
The second conductivity type impurity region pair is a constituent part of a second field effect transistor,
The second field effect transistor is:
Driven so that current flows in both directions between the impurity region pair,
10. A method for manufacturing a semiconductor device according to claim 9, wherein: The semiconductor substrate further includes a third element formation region,
The method of manufacturing a semiconductor device according to claim 9, wherein the mask film covers the conductive film located in the third element formation region. A first gate electrode disposed on a semiconductor substrate via a first gate insulating film;
A first field effect transistor having a source region and a drain region disposed in the semiconductor substrate on both sides of the first gate electrode;
A second gate electrode disposed on the semiconductor substrate via a second gate insulating film;
A second field effect transistor having a pair of impurity regions disposed in the semiconductor substrate on both sides of the second gate electrode;
Have
Of the first gate insulating film under the first gate electrode, the film thickness at the end on the drain region side is the end of the first gate insulating film under the first gate electrode on the source region side. Larger than the film thickness of the part,
Of the second gate insulating film under the second gate electrode, the film thickness of the end portions on both sides of the second gate electrode is the film thickness of the end portion on the source region side of the first gate insulating film, respectively. A semiconductor device characterized by being larger than the above. Of the first gate insulating film under the first gate electrode, the film thickness on the drain region side gradually decreases from the end of the first gate electrode on the drain region side,
Of the first gate insulating film under the first gate electrode, the film thickness on the source region side gradually decreases from the end portion on the source region side of the first gate electrode.
The semiconductor device according to claim 15. The bottom surface of the first gate electrode on the drain region side has a curved surface shape,
The bottom surface of the first gate electrode on the source region side has a curved surface shape,
The semiconductor device according to claim 16. The bottom surface of the first gate electrode on the drain region side has a tapered shape,
The bottom surface on the source region side of the first gate electrode has a tapered shape.
The semiconductor device according to claim 16.   16. The semiconductor device according to claim 15, wherein the first gate electrode and the second gate electrode are silicon films.   16. The semiconductor device according to claim 15, wherein the first field effect transistor and the second field effect transistor are n-channel field effect transistors.   16. The semiconductor device according to claim 15, wherein the first field effect transistor and the second field effect transistor are p-channel field effect transistors.

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