JP2012123889A5 - - Google Patents

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Publication number
JP2012123889A5
JP2012123889A5 JP2011168083A JP2011168083A JP2012123889A5 JP 2012123889 A5 JP2012123889 A5 JP 2012123889A5 JP 2011168083 A JP2011168083 A JP 2011168083A JP 2011168083 A JP2011168083 A JP 2011168083A JP 2012123889 A5 JP2012123889 A5 JP 2012123889A5
Authority
JP
Japan
Prior art keywords
refresh
control circuit
signal
memory cell
cell array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2011168083A
Other languages
English (en)
Japanese (ja)
Other versions
JP2012123889A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP2011168083A priority Critical patent/JP2012123889A/ja
Priority claimed from JP2011168083A external-priority patent/JP2012123889A/ja
Priority to US13/287,600 priority patent/US8750067B2/en
Publication of JP2012123889A publication Critical patent/JP2012123889A/ja
Publication of JP2012123889A5 publication Critical patent/JP2012123889A5/ja
Abandoned legal-status Critical Current

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JP2011168083A 2010-11-18 2011-08-01 半導体装置 Abandoned JP2012123889A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2011168083A JP2012123889A (ja) 2010-11-18 2011-08-01 半導体装置
US13/287,600 US8750067B2 (en) 2010-11-18 2011-11-02 Semiconductor device having reset function

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2010257630 2010-11-18
JP2010257630 2010-11-18
JP2011168083A JP2012123889A (ja) 2010-11-18 2011-08-01 半導体装置

Publications (2)

Publication Number Publication Date
JP2012123889A JP2012123889A (ja) 2012-06-28
JP2012123889A5 true JP2012123889A5 (cg-RX-API-DMAC7.html) 2014-10-09

Family

ID=46064278

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2011168083A Abandoned JP2012123889A (ja) 2010-11-18 2011-08-01 半導体装置

Country Status (2)

Country Link
US (1) US8750067B2 (cg-RX-API-DMAC7.html)
JP (1) JP2012123889A (cg-RX-API-DMAC7.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142280B1 (en) 2014-08-06 2015-09-22 Freescale Semiconducotr, Inc. Circuit for configuring external memory
JP6180450B2 (ja) * 2015-02-02 2017-08-16 キヤノン株式会社 制御装置、制御装置の制御方法及びプログラム
KR20160133073A (ko) 2015-05-11 2016-11-22 에스케이하이닉스 주식회사 초기화 동작을 수행하는 반도체장치 및 반도체시스템
KR102373544B1 (ko) * 2015-11-06 2022-03-11 삼성전자주식회사 요청 기반의 리프레쉬를 수행하는 메모리 장치, 메모리 시스템 및 메모리 장치의 동작방법
KR102535182B1 (ko) * 2016-07-27 2023-05-23 에스케이하이닉스 주식회사 반도체 장치
KR20220168520A (ko) * 2021-06-16 2022-12-23 에스케이하이닉스 주식회사 리프레쉬 동작 주기를 조절하는 전자장치

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4246971B2 (ja) * 2002-07-15 2009-04-02 富士通マイクロエレクトロニクス株式会社 半導体メモリ
JP4848564B2 (ja) 2005-09-29 2011-12-28 株式会社ハイニックスセミコンダクター 半導体メモリ装置のリセット制御回路
KR100802074B1 (ko) * 2006-09-08 2008-02-12 주식회사 하이닉스반도체 리프레쉬명령 생성회로를 포함하는 메모리장치 및리프레쉬명령 생성방법.

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