WO2012164986A3 - Semiconductor memory device for pseudo-random number generation - Google Patents

Semiconductor memory device for pseudo-random number generation Download PDF

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Publication number
WO2012164986A3
WO2012164986A3 PCT/JP2012/054497 JP2012054497W WO2012164986A3 WO 2012164986 A3 WO2012164986 A3 WO 2012164986A3 JP 2012054497 W JP2012054497 W JP 2012054497W WO 2012164986 A3 WO2012164986 A3 WO 2012164986A3
Authority
WO
WIPO (PCT)
Prior art keywords
random number
number generation
pseudo
memory device
generation circuit
Prior art date
Application number
PCT/JP2012/054497
Other languages
French (fr)
Other versions
WO2012164986A2 (en
Inventor
Yuji Nagai
Atsushi Inoue
Yoshikazu Takeyama
Original Assignee
Kabushiki Kaisha Toshiba
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kabushiki Kaisha Toshiba filed Critical Kabushiki Kaisha Toshiba
Priority to EP12715448.2A priority Critical patent/EP2715524B1/en
Priority to CN2012800108180A priority patent/CN103403670A/en
Priority to KR1020137022824A priority patent/KR101540875B1/en
Priority to US13/985,436 priority patent/US8976586B2/en
Publication of WO2012164986A2 publication Critical patent/WO2012164986A2/en
Publication of WO2012164986A3 publication Critical patent/WO2012164986A3/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/582—Pseudo-random number generators
    • G06F7/584—Pseudo-random number generators using finite field arithmetic, e.g. using a linear feedback shift register

Abstract

According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a random number generation circuit configured to generate a random number, and a controller configured to control the memory cell array and the random number generation circuit. The random number generation circuit includes a random number control circuit configured to generate a random number parameter based on data which is read out from the memory cell by a generated control parameter, and a pseudo-random number generation circuit configured to generate the random number by using the random number parameter as a seed value.
PCT/JP2012/054497 2011-06-03 2012-02-17 Semiconductor memory device WO2012164986A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP12715448.2A EP2715524B1 (en) 2011-06-03 2012-02-17 Semiconductor memory device
CN2012800108180A CN103403670A (en) 2011-06-03 2012-02-17 Semiconductor memory device for pseudo-random number generation
KR1020137022824A KR101540875B1 (en) 2011-06-03 2012-02-17 Semiconductor memory device for pseudo-random number generation
US13/985,436 US8976586B2 (en) 2011-06-03 2012-02-17 Semiconductor memory device for pseudo-random number generation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2011125282A JP5813380B2 (en) 2011-06-03 2011-06-03 Semiconductor memory device
JP2011-125282 2011-06-03

Publications (2)

Publication Number Publication Date
WO2012164986A2 WO2012164986A2 (en) 2012-12-06
WO2012164986A3 true WO2012164986A3 (en) 2013-03-28

Family

ID=45976988

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2012/054497 WO2012164986A2 (en) 2011-06-03 2012-02-17 Semiconductor memory device

Country Status (7)

Country Link
US (1) US8976586B2 (en)
EP (1) EP2715524B1 (en)
JP (1) JP5813380B2 (en)
KR (1) KR101540875B1 (en)
CN (1) CN103403670A (en)
TW (1) TW201250582A (en)
WO (1) WO2012164986A2 (en)

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Also Published As

Publication number Publication date
EP2715524B1 (en) 2021-01-06
US8976586B2 (en) 2015-03-10
WO2012164986A2 (en) 2012-12-06
KR20130122664A (en) 2013-11-07
CN103403670A (en) 2013-11-20
JP2012252195A (en) 2012-12-20
JP5813380B2 (en) 2015-11-17
EP2715524A2 (en) 2014-04-09
KR101540875B1 (en) 2015-07-30
US20140146607A1 (en) 2014-05-29
TW201250582A (en) 2012-12-16

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