JP2012105522A

JP2012105522A - Switching power supply

Info

Publication number: JP2012105522A
Application number: JP2011039724A
Authority: JP
Inventors: Eiji Nagata; 英士永田
Original assignee: Cosel Co Ltd
Current assignee: Cosel Co Ltd
Priority date: 2010-10-15
Filing date: 2011-02-25
Publication date: 2012-05-31
Anticipated expiration: 2031-02-25
Also published as: JP5783597B2

Abstract

PROBLEM TO BE SOLVED: To protect a synchronous rectifier against increase in an input voltage for sure and also, for that protection, avoid increase in a regenerative current when the power supply stops.SOLUTION: There is included in a switching power supply using a synchronous rectification type flyback converter a synchronous rectification drive circuit 30 which blocks supply to the gate of a synchronous rectification FET 24 of a drive signal generated from a negative polarity induction voltage which develops in a drive coil 18 of an output transformer 12 when a switching FET 20 is turned off, and also reduces a drive signal generated from a positive polarity induction voltage which develops in the drive coil 18 when the switching FET 20 is turned off due to stoppage of the power supply and then, after a prescribed time, turns the synchronous rectification FET 24 off.

Description

本発明は、同期整流型フライバックコンバ−タを用いたスイッチング電源装置に関する。
The present invention relates to a switching power supply device using a synchronous rectification type flyback converter.

従来、この種の同期整流型フライバックコンバ−タを用いたスイッチング電源装置としては、例えば図７に示すものがある。 Conventionally, as a switching power supply device using this type of synchronous rectification type flyback converter, for example, there is the one shown in FIG.

図７において、１００は入力電源であり、出力トランス１１２の１次側には１次コイル１１４が設けられてスイッチングＦＥＴ１２０を直接接続し、２次側には１次側コイル１１４と極性を逆にする２次コイル１１６と駆動コイル（補助コイル）１１８を設けている。 In FIG. 7, reference numeral 100 denotes an input power source. A primary coil 114 is provided on the primary side of the output transformer 112 and is directly connected to the switching FET 120. The polarity is reversed to that of the primary side coil 114 on the secondary side. A secondary coil 116 and a drive coil (auxiliary coil) 118 are provided.

２次コイル１１６と駆動コイル１１８のコイル接続点は２次側同期整流器としての同期整流ＦＥＴ１２４のソ−ス端子Ｓに接続され、そのドレイン端子Ｄは平滑コンデンサ１２６のプラス側に接続されている。駆動コイル１１８の他端は電流制限抵抗１３６を介して同期整流ＦＥＴ１２４のゲ−ト端子Ｇに接続され、同期整流駆動回路を構成している。 A coil connection point between the secondary coil 116 and the drive coil 118 is connected to a source terminal S of a synchronous rectification FET 124 as a secondary side synchronous rectifier, and a drain terminal D thereof is connected to a plus side of the smoothing capacitor 126. The other end of the drive coil 118 is connected to the gate terminal G of the synchronous rectification FET 124 via a current limiting resistor 136 to constitute a synchronous rectification drive circuit.

制御回路１２８は出力電圧Ｖｏを安定化するためのＰＷＭ制御信号を絶縁ドライバ回路１２２に出力し、絶縁ドライバ回路１２２はスイッチングＦＥＴ１２０のゲート端子Ｇとソース端子Ｓ間に制御信号Ｅ１１を出力し、制御信号Ｅ１１がハイレベル（Ｈ）になるとスイッチングＦＥＴ１２０がオンし、制御信号Ｅ１１がローレベル（Ｌ）になるとスイッチングＦＥＴ１２０がオフする。 The control circuit 128 outputs a PWM control signal for stabilizing the output voltage Vo to the insulation driver circuit 122, and the insulation driver circuit 122 outputs a control signal E11 between the gate terminal G and the source terminal S of the switching FET 120 for control. When the signal E11 becomes high level (H), the switching FET 120 is turned on, and when the control signal E11 becomes low level (L), the switching FET 120 is turned off.

図８は従来の同期整流型フライバックコンバータの各部の動作波形を示したタイムチャートであり、図８（Ａ）は制御信号Ｅ１１の電圧波形、図８（Ｂ）はスイッチングＦＥＴ１２０のドレイン・ソース間電圧Ｖｄｓ１１、図８（Ｃ）は１次コイル１１４に発生する電圧、図８（Ｄ）は２次側コイル１１６に発生する電圧、図８（Ｅ）は駆動コイル１１８に発生する電圧、図８（Ｆ）は同期整流ＦＥＴ１２４のゲ−ト・ソース間電圧Ｖｇｓ１２、図８（Ｇ）は同期整流ＦＥＴ１２４のドレイン・ソース間電圧Ｖｄｓ１２、更に図８（Ｈ）は２次コイル１１６に流れる電流を示している。なお、スイッチングＦＥＴ１２０のドレイン・ソース間電圧Ｖｄｓ１１、１次コイル１１４に発生する電圧、２次側コイル１１６に発生する電圧、駆動コイル１１８に発生する電圧と同期整流ＦＥＴ１２４のドレイン・ソース間電圧Ｖｄｓ１２は、スイッチングにより発生するリンギング電圧を含めた概略波形を示している。 FIG. 8 is a time chart showing the operation waveform of each part of the conventional synchronous rectification type flyback converter. FIG. 8A shows the voltage waveform of the control signal E11, and FIG. 8C is a voltage generated in the primary coil 114, FIG. 8D is a voltage generated in the secondary coil 116, FIG. 8E is a voltage generated in the drive coil 118, and FIG. 8F shows the gate-source voltage Vgs12 of the synchronous rectification FET 124, FIG. 8G shows the drain-source voltage Vds12 of the synchronous rectification FET 124, and FIG. 8H shows the current flowing through the secondary coil 116. ing. The drain-source voltage Vds11 of the switching FET 120, the voltage generated in the primary coil 114, the voltage generated in the secondary coil 116, the voltage generated in the drive coil 118, and the drain-source voltage Vds12 of the synchronous rectification FET 124 are FIG. 2 shows a schematic waveform including a ringing voltage generated by switching.

フライバックコンバ−タは１次側のスイッチングＦＥＴ１２０と２次側の同期整流ＦＥＴ１２４が交互にオンとオフを繰り返し、出力トランス１１２のエネルギ−の蓄積と放出を繰り返すことにより１次側から２次側にエネルギ−を伝える。 In the flyback converter, the switching FET 120 on the primary side and the synchronous rectification FET 124 on the secondary side alternately turn on and off alternately, and the energy is stored and released in the output transformer 112, thereby repeating the operation from the primary side to the secondary side. Tell the energy to.

出力トランス１１２にエネルギ−を蓄積するために１次側のスイッチングＦＥＴ１２０をオンしたとき２次側の同期整流ＦＥＴ１２４はオフとなり、出力トランス１１２からエネルギ−を放出するために１次側のスイッチングＦＥＴ１２０をオフしたときは２次側の同期整流ＦＥＴ１２４がオンとなるように駆動される。 When the primary side switching FET 120 is turned on to store energy in the output transformer 112, the secondary side synchronous rectification FET 124 is turned off, and in order to release energy from the output transformer 112, the primary side switching FET 120 is turned off. When turned off, the secondary side synchronous rectification FET 124 is driven to be turned on.

２次側の同期整流ＦＥＴ１２４のオンとオフの制御は以下のように行われる。同期整流ＦＥＴ１２４は、駆動コイル１１８の極性が１次コイル１１４と逆なため、１次側のスイッチングＦＥＴ１２０がオフのときに駆動コイル１１８にプラス極性の電圧が発生し、電流制限抵抗１３６を介して同期整流ＦＥＴ１２４のゲ−ト端子Ｇにゲートバイアス電圧として印加され、スレッショルド電圧を超えることによって同期整流ＦＥＴ１２４がオンする。 On-off control of the secondary side synchronous rectification FET 124 is performed as follows. In the synchronous rectification FET 124, the polarity of the drive coil 118 is opposite to that of the primary coil 114, so that a positive polarity voltage is generated in the drive coil 118 when the primary side switching FET 120 is off, and the current rectifying FET 124 is connected via the current limiting resistor 136. A gate bias voltage is applied to the gate terminal G of the synchronous rectification FET 124, and when the threshold voltage is exceeded, the synchronous rectification FET 124 is turned on.

同期整流ＦＥＴ１２４のゲ−ト端子Ｇに印加されるプラス方向のゲート・ソース間電圧Ｖｇｓ１２は、図８（Ｆ）に示すように、２次コイル１１６の巻数Ｎ２と駆動コイル１１８の巻数Ｎ３及び出力電圧Ｖｏによって
Ｖｇｓ１２＝Ｖｏ×Ｎ３／Ｎ２（１）
で示され、出力電圧Ｖｏに比例した電圧が印加される。ここで出力電圧Ｖｏは制御回路１２８により安定化されているため、同期整流ＦＥＴ１２４のゲ−ト端子Ｇに印加されるプラス電圧は結果的に一定の電圧となる。 As shown in FIG. 8F, the positive gate-source voltage Vgs12 applied to the gate terminal G of the synchronous rectification FET 124 includes the number of turns N2 of the secondary coil 116, the number of turns N3 of the drive coil 118, and the output. Depending on the voltage Vo, Vgs12 = Vo × N3 / N2 (1)
A voltage proportional to the output voltage Vo is applied. Here, since the output voltage Vo is stabilized by the control circuit 128, the plus voltage applied to the gate terminal G of the synchronous rectification FET 124 becomes a constant voltage as a result.

続いて１次側のスイッチングＦＥＴ１２０がオンすると、駆動コイル１１８にマイナス極性の電圧が発生し、電流制限抵抗１３６を介して同期整流ＦＥＴ１２４のゲ−ト端子Ｇにゲートバイアス電圧として印加され、同期整流ＦＥＴ１２４のオン時にゲ−ト端子Ｇに蓄積されていた電荷が引き抜かれ（放電）、スレッショルド電圧を下回ることによりオフする。 Subsequently, when the switching FET 120 on the primary side is turned on, a negative polarity voltage is generated in the drive coil 118 and is applied as a gate bias voltage to the gate terminal G of the synchronous rectification FET 124 via the current limiting resistor 136. When the FET 124 is turned on, the charge accumulated in the gate terminal G is extracted (discharged), and the FET 124 is turned off when it falls below the threshold voltage.

同期整流ＦＥＴ１２４のゲ−ト端子Ｇに印加されるマイナス極性のゲート・ソース間電圧Ｖｇｓ１２は、図８（Ｆ）に示すように、１次コイル１１４の巻数Ｎ１と駆動コイル１１８の巻数Ｎ３及び入力電圧Ｖｉによって決り、
Ｖｇｓ１２＝Ｖｉ×Ｎ３／Ｎ１（２）
で示され、入力電圧Ｖｉに比例した電圧となる。 As shown in FIG. 8F, the negative polarity gate-source voltage Vgs12 applied to the gate terminal G of the synchronous rectification FET 124 includes the number of turns N1 of the primary coil 114, the number of turns N3 of the drive coil 118, and the input. Determined by the voltage Vi,
Vgs12 = Vi × N3 / N1 (2)
The voltage is proportional to the input voltage Vi.

スイッチング電源装置は入力電圧Ｖｉの変動を許容しているため、同期整流ＦＥＴ１２４のゲ−ト端子Ｇに印加されるマイナス極性のゲート・ソース間電圧Ｖｇｓ１２は、入力電圧Ｖｉの変動に応じて変化する。 Since the switching power supply device allows the fluctuation of the input voltage Vi, the negative polarity gate-source voltage Vgs12 applied to the gate terminal G of the synchronous rectification FET 124 changes according to the fluctuation of the input voltage Vi. .

また、同期整流型フライバックコンバ−タを用いた従来のスイッチング電源装置としては、図９に示した様に、平滑コンデンサ１２６のマイナス側に接続される二次コイル端子に、同期整流ＦＥＴ１２４を備えて同期整流駆動回路を構成している例もある。この場合においても動作原理は図７に示したスイッチング電源装置と同様である。
As a conventional switching power supply device using a synchronous rectification type flyback converter, a synchronous rectification FET 124 is provided at the secondary coil terminal connected to the negative side of the smoothing capacitor 126 as shown in FIG. In some cases, a synchronous rectification drive circuit is configured. In this case as well, the operating principle is the same as that of the switching power supply device shown in FIG.

特開２００１−２９２５７０号公報JP 2001-292570 A 特開２００７−３３６６３５号公報JP 2007-336635 A

しかしながら、このような従来の同期整流型フライバックコンバータを用いたスイッチング電源装置にあっては、同期整流ＦＥＴ１２４の駆動回路として、駆動コイル１１８の誘起電圧を電流制限抵抗１３６のみを介してゲート端子Ｇにゲートバイアス電圧として印加して駆動する回路となっていたため、入力電圧Ｖｉに高い電圧が印加された場合に、同期整流ＦＥＴ１２４の破壊につながる恐れがある。 However, in such a switching power supply device using the conventional synchronous rectification type flyback converter, as the drive circuit for the synchronous rectification FET 124, the induced voltage of the drive coil 118 is applied to the gate terminal G only through the current limiting resistor 136. Therefore, when a high voltage is applied to the input voltage Vi, the synchronous rectification FET 124 may be destroyed.

図１０（Ａ）〜（Ｇ）は、図７に示したスイッチング電源装置において、入力電圧Ｖｉに高い電圧が印加された場合の各部の動作波形を示しており、スイッチングＦＥＴ１２０のオンに伴い駆動コイル１１８に高いマイナス極性の電圧が発生し、電流制限抵抗１３６を介して同期整流ＦＥＴ１２４のゲ−ト端子Ｇに前記（２）式で示される高いマイナス電圧が図１０（Ｆ）に示すように印加され、同期整流ＦＥＴ１２４のゲ−ト端子の定格電圧を超え、破壊につながる。 FIGS. 10A to 10G show operation waveforms of respective parts when a high voltage is applied to the input voltage Vi in the switching power supply device shown in FIG. A high negative voltage is generated at 118, and a high negative voltage expressed by the equation (2) is applied to the gate terminal G of the synchronous rectification FET 124 through the current limiting resistor 136 as shown in FIG. This exceeds the rated voltage of the gate terminal of the synchronous rectification FET 124, leading to destruction.

一般的に、同期整流ＦＥＴ１２４のゲ−ト端子定格電圧は２０ボルト程度であり、スイッチング電源装置の入力電圧Ｖｉの下限時に、同期整流ＦＥＴ１２４のマイナス電圧を、例えば５ボルト程度に設定したとしても、入力電圧Ｖｉが４倍となった時点で同期整流ＦＥＴ１２４のゲ−ト端子定格電圧を超えてしまい、破壊してしまう。 Generally, the gate terminal rated voltage of the synchronous rectification FET 124 is about 20 volts, and even when the negative voltage of the synchronous rectification FET 124 is set to about 5 volts at the lower limit of the input voltage Vi of the switching power supply device, When the input voltage Vi is quadrupled, the gate terminal rated voltage of the synchronous rectification FET 124 is exceeded and it is destroyed.

これを防止するため１１図に示すように、同期整流ＦＥＴ１２４のゲ−ト端子Ｇとソ−ス端子Ｓ間に、ゲ−ト端子Ｇ側がカソ−ドとなるようダイオ−ド１４０を挿入接続して逆電圧を印加させないようにする方法があるが、電流制限抵抗１３６の損失が増大してしまい、効率が低下する問題がある。 In order to prevent this, as shown in FIG. 11, a diode 140 is inserted and connected between the gate terminal G and the source terminal S of the synchronous rectification FET 124 so that the gate terminal G side becomes a cathode. However, there is a method of preventing the reverse voltage from being applied, but there is a problem that the loss of the current limiting resistor 136 is increased and the efficiency is lowered.

また従来の同期整流型フライバックコンバータにあっては、同期整流ＦＥＴ１２４の駆動回路として、駆動コイル１１８の誘起電圧を電流制限抵抗１３６のみを介してゲート端子Ｇにゲートバイアス電圧として印加して駆動する回路となっていたため、図１２（Ａ）〜（Ｈ）の動作波形に示すように、フライバックコンバ−タは１次側のスイッチングＦＥＴ１２０がオンの場合、２次側の同期整流ＦＥＴ１２４はオフとなり、オンとオフが逆転した動作であり、時刻ｔ１で電源を停止した場合、駆動回路１２２からの制御信号Ｅ１１がローレベルとなり、１次側のスイッチングＦＥＴ１２０をオフさせた状態で停止する。 In the conventional synchronous rectification type flyback converter, as the drive circuit of the synchronous rectification FET 124, the induced voltage of the drive coil 118 is applied as the gate bias voltage to the gate terminal G only through the current limiting resistor 136 and driven. Since the circuit is a circuit, as shown in the operation waveforms of FIGS. 12A to 12H, in the flyback converter, when the primary side switching FET 120 is on, the secondary side synchronous rectification FET 124 is off. When the power supply is stopped at time t1, the control signal E11 from the drive circuit 122 becomes low level, and the primary side switching FET 120 is turned off.

このとき駆動コイル１１８にはプラス方向の電圧が発生しており、同期整流ＦＥＴ１２４はオンした状態となる。このため同期整流ＦＥＴ１２４と出力トランス１１２の２次コイル１１６が電圧源に接続された状態となり、図１２（Ｈ）に示すように、２次コイル１１６に回生電流が流れ続ける。この状態が続くとトランスコアが励磁され続けることとなるため磁束が増大し、ついにはトランスコアの飽和磁束密度を超え、出力トランス１１２が飽和し、インダクタンスとしての特性がなくなり大電流が流れる。この電流により、同期整流ＦＥＴ１２４の破壊、出力トランス１１２の２次コイル１１６の焼損につながる。 At this time, a positive voltage is generated in the drive coil 118, and the synchronous rectification FET 124 is turned on. Therefore, the synchronous rectification FET 124 and the secondary coil 116 of the output transformer 112 are connected to the voltage source, and the regenerative current continues to flow through the secondary coil 116 as shown in FIG. If this state continues, the transformer core will continue to be excited and the magnetic flux will increase, eventually exceeding the saturation magnetic flux density of the transformer core, the output transformer 112 will be saturated, the characteristic as inductance will be lost, and a large current will flow. This current leads to destruction of the synchronous rectification FET 124 and burning of the secondary coil 116 of the output transformer 112.

これを防ぐために、出力トランス１１２の外形を大きくして、飽和磁束密度を上げる方法があるが、スイッチング電源装置の外形が大きくなってしまう問題点がある。 In order to prevent this, there is a method of increasing the outer shape of the output transformer 112 and increasing the saturation magnetic flux density, but there is a problem that the outer shape of the switching power supply device becomes large.

本発明は、入力電圧の増加に対し同期整流器を確実に保護すると共に電源停止時の回生電流の増加を回避して保護する同期整流型フライバックコンバータを用いたスイッチング電源装置を提供することを目的とする。
An object of the present invention is to provide a switching power supply apparatus using a synchronous rectification type flyback converter that reliably protects a synchronous rectifier against an increase in input voltage and prevents an increase in regenerative current when the power is stopped. And

本発明は、
１次側に設けた１次コイル、１次コイルと逆極性となるように２次側に設けた２次コイル及び駆動コイルを備えた出力トランスと、
出力トランスの１次コイルに直列接続され、制御回路からの制御信号に基づいてオン、オフ制御される１次側スイッチング素子と、
１次側スイッチング素子のオン、オフ制御に対し逆相となるようにオフ、オン制御されて前記２次コイルの誘起電圧を同期整流して平滑コンデンサに出力する２次側同期整流器と、
から成る同期整流型フライバックコンバ−タを用いたスイッチング電源装置に於いて、
駆動コイルの誘起電圧から生成した駆動信号により１次側スイッチング素子のオン、オフ制御に対し逆相となるように２次側同期整流器をオフ、オン制御し、１次側スイッチング素子をオンした場合に駆動コイルに発生する負極性の誘起電圧から生成した駆動信号の２次側同期整流器への供給を阻止すると共に、電源停止により１次側スイッチング素子をオフした場合に駆動コイルに発生する正極性の誘起電圧から生成した同期整流器への駆動信号を減少させて所定時間後に２次側同期整流器をオフする同期整流駆動回路を設けたことを特徴とする。 The present invention
An output transformer including a primary coil provided on the primary side, a secondary coil provided on the secondary side so as to have a polarity opposite to that of the primary coil, and a drive coil;
A primary side switching element connected in series to the primary coil of the output transformer and controlled to be turned on and off based on a control signal from the control circuit;
A secondary-side synchronous rectifier that is off / on-controlled so as to be in opposite phase to the on / off control of the primary-side switching element, synchronously rectifies the induced voltage of the secondary coil, and outputs it to the smoothing capacitor;
In a switching power supply using a synchronous rectification type flyback converter comprising:
When the secondary-side synchronous rectifier is turned off and on so that the primary-side switching element is in the opposite phase to the on-off control of the primary-side switching element by the drive signal generated from the induced voltage of the drive coil, and the primary side switching element is turned on The positive polarity generated in the drive coil when the primary side switching element is turned off by stopping the power supply while preventing the supply of the drive signal generated from the negative induced voltage generated in the drive coil to the secondary side synchronous rectifier. A synchronous rectification drive circuit is provided that reduces the drive signal to the synchronous rectifier generated from the induced voltage of the second and turns off the secondary side synchronous rectifier after a predetermined time.

ここで、２次側同期整流器は同期整流ＦＥＴであり、
同期整流駆動回路は、
駆動コイルの出力端子と同期整流ＦＥＴのゲート端子の間に、正極性の誘起電圧でオンし負極性の誘起電圧でオフするダイオード、正極性の誘起電圧で充電されるコンデンサ及び駆動信号の電流を調整する第１抵抗を直列接続すると共に、同期整流ＦＥＴのゲート端子と駆動コイルのコイル接続点との間に放電用の第２抵抗を接続したゲート回路と、
コンデンサの両端の各々からコイル接続点の間に接続した一対の放電用スイッチング素子と、
制御回路からの制御信号に基づいて、１次側スイッチング素子がオフして駆動コイルに正極性電圧が誘起した場合は一対の放電用スイッチング素子をオフし、１次側スイッチング素子がオフして駆動コイルに負極性電圧が誘起した場合は一対の放電用スイッチング素子をオンして前記ゲート回路のコンデンサを放電リセットする放電リセット回路と、
を設ける。 Here, the secondary side synchronous rectifier is a synchronous rectification FET,
The synchronous rectification drive circuit
Between the output terminal of the drive coil and the gate terminal of the synchronous rectification FET, a diode that is turned on with a positive induced voltage and turned off with a negative induced voltage, a capacitor that is charged with a positive induced voltage, and a drive signal current A gate circuit in which a first resistor to be adjusted is connected in series, and a second resistor for discharge is connected between the gate terminal of the synchronous rectification FET and the coil connection point of the drive coil;
A pair of switching elements for discharging connected between the coil connection points from each of both ends of the capacitor;
Based on the control signal from the control circuit, when the primary side switching element is turned off and a positive voltage is induced in the drive coil, the pair of discharge switching elements are turned off, and the primary side switching element is turned off and driven. A discharge reset circuit that turns on a pair of discharge switching elements to discharge and reset the capacitor of the gate circuit when a negative voltage is induced in the coil;
Is provided.

同期整流駆動回路、ゲート回路、一対の放電用スイッチング素子および放電リセット回路は、前記２次コイルの正極側に設けてもよいし負極側に設けてもよい。 The synchronous rectification drive circuit, the gate circuit, the pair of discharge switching elements, and the discharge reset circuit may be provided on the positive electrode side or the negative electrode side of the secondary coil.

また、同期整流回路は、
駆動コイルの出力端子と同期整流ＦＥＴのゲート端子の間に、正極性の誘起電圧でオンし負極性の誘起電圧でオフするダイオード、正極性の誘起電圧で充電されるコンデンサ及び駆動信号の電流を調整する第１抵抗を直列接続すると共に、同期整流ＦＥＴのゲート端子と駆動コイルのコイル接続点との間に放電用の第２抵抗を接続したゲート回路と、
ダイオード側のコンデンサ端子と駆動コイル接続点の間に接続した放電用スイッチング素子と、
第１抵抗側のコンデンサ端子と駆動コイル接続点の間に接続したダイオードと、
制御回路からの制御信号に基づいて、１次側スイッチング素子がオフして駆動コイルに正極性電圧が誘起した場合は放電用スイッチング素子をオフし、１次側スイッチング素子がオフして駆動コイルに負極性電圧が誘起した場合は放電用スイッチング素子をオンしてゲート回路のコンデンサを放電リセットする放電リセット回路と、
を設けた構成であってもよい。 The synchronous rectifier circuit
Between the output terminal of the drive coil and the gate terminal of the synchronous rectification FET, a diode that is turned on with a positive induced voltage and turned off with a negative induced voltage, a capacitor that is charged with a positive induced voltage, and a drive signal current A gate circuit in which a first resistor to be adjusted is connected in series, and a second resistor for discharge is connected between the gate terminal of the synchronous rectification FET and the coil connection point of the drive coil;
A discharge switching element connected between the capacitor terminal on the diode side and the drive coil connection point;
A diode connected between the capacitor terminal on the first resistance side and the drive coil connection point;
Based on the control signal from the control circuit, when the primary side switching element is turned off and a positive voltage is induced in the driving coil, the discharging switching element is turned off, and the primary side switching element is turned off to turn on the driving coil. A discharge reset circuit that turns on the discharge switching element to reset the discharge of the capacitor of the gate circuit when a negative voltage is induced; and
May be provided.

この場合においても同期整流駆動回路、ゲート回路、一対の放電用スイッチング素子および放電リセット回路は、前記２次コイルの正極側に設けてもよいし負極側に設けてもよい。
Also in this case, the synchronous rectification drive circuit, the gate circuit, the pair of discharge switching elements, and the discharge reset circuit may be provided on the positive electrode side or the negative electrode side of the secondary coil.

本発明によれば、１次側スイッチング素子をオンした場合に駆動コイルに発生する負極性の誘起電圧から生成した駆動信号の２次側同期整流器への供給を阻止するようにしたため、２次側の同期整流器となる同期整流ＦＥＴのゲ−トに逆電圧を印加させずに同期整流が可能であり、入力電圧が高くなっても同期整流ＦＥＴのゲ−ト端子定格電圧を超えることがないため、入力電圧範囲の広いスイッチング電源装置を実現できる。 According to the present invention, since the drive signal generated from the negative induced voltage generated in the drive coil when the primary side switching element is turned on is prevented from being supplied to the secondary side synchronous rectifier, the secondary side Synchronous rectification is possible without applying a reverse voltage to the gate of the synchronous rectification FET that is the synchronous rectifier of the synchronous rectifier, and even if the input voltage increases, the gate terminal rated voltage of the synchronous rectification FET is not exceeded. A switching power supply device with a wide input voltage range can be realized.

また、電源停止により１次側スイッチング素子をオフした場合に駆動コイルに発生する正極性の誘起電圧から生成した駆動信号を減少させて所定時間後に２次側同期整流器をオフするようにしため、同期整流型フライバックコンバ−タを停止する時の回生電流を抑制して出力トランスの飽和を防止し、出力トランスを飽和させないようにトランスサイズを大きくする必要がなくなり、小さな出力トランスを使用することで、スイッチング電源装置の小型化を実現できる。
In addition, in order to reduce the drive signal generated from the positive induced voltage generated in the drive coil when the primary side switching element is turned off due to the power stop and to turn off the secondary side synchronous rectifier after a predetermined time, By suppressing the regenerative current when stopping the rectifying flyback converter, the output transformer is prevented from being saturated, and there is no need to increase the transformer size so that the output transformer is not saturated. The switching power supply device can be downsized.

本発明による同期整流型フライバックコンバータを用いたスイッチング電源装置の実施形態を示した回路図The circuit diagram showing the embodiment of the switching power supply device using the synchronous rectification type flyback converter by the present invention 図１の実施形態における各部の動作波形を示したタイムチャートFIG. 1 is a time chart showing operation waveforms of respective units in the embodiment of FIG. 図１の実施形態における電源停止時の各部の動作波形を示したタイムチャートFIG. 1 is a time chart showing operation waveforms of respective parts when the power is stopped in the embodiment of FIG. 本発明による他の同期整流型フライバックコンバータを用いたスイッチング電源装置の実施形態を示した回路図The circuit diagram which showed the embodiment of the switching power supply device using the other synchronous rectification type flyback converter by this invention 本発明による同期整流型フライバックコンバータを負極側に用いたスイッチング電源装置の実施形態を示した回路図The circuit diagram which showed embodiment of the switching power supply device which used the synchronous rectification type flyback converter by this invention for the negative electrode side 本発明による他の同期整流型フライバックコンバータを負極側に用いたスイッチング電源装置の実施形態を示した回路図The circuit diagram which showed embodiment of the switching power supply device which used the other synchronous rectification type | mold flyback converter by this invention for the negative electrode side 同期整流型フライバックコンバータを用いた従来のスイッチング電源装置を示した回路図A circuit diagram showing a conventional switching power supply using a synchronous rectification type flyback converter 図７の従来回路における各部の動作波形を示したタイムチャートFIG. 7 is a time chart showing operation waveforms of various parts in the conventional circuit. 同期整流型フライバックコンバータを負極側に備えた従来のスイッチング電源装置を示した回路図A circuit diagram showing a conventional switching power supply device equipped with a synchronous rectification type flyback converter on the negative electrode side 図７の従来回路で入力電圧が高くなった場合の各部の動作波形を示したタイムチャートFIG. 7 is a time chart showing operation waveforms of each part when the input voltage becomes high in the conventional circuit of FIG. 同期整流ＦＥＴの破壊防止回路を設けた従来のスイッチング電源装置を示した回路図Circuit diagram showing a conventional switching power supply device provided with a circuit for preventing breakdown of a synchronous rectification FET 図７の従来回路における電源停止時の各部の動作波形を示したタイムチャートFIG. 7 is a time chart showing operation waveforms of respective parts when the power is stopped in the conventional circuit of FIG.

図１は本発明による同期整流型フライバックコンバ−タ（絶縁型）を用いたスイッチング電源装置の実施形態を示した回路図である。 FIG. 1 is a circuit diagram showing an embodiment of a switching power supply device using a synchronous rectification type flyback converter (insulated type) according to the present invention.

図１において、１０は入力電源であり、出力トランス１２の１次側には１次コイル１４が設けられてスイッチング素子としてスイッチングＦＥＴ２０を直接接続し、２次側には１次側コイル１４と極性を逆にする２次コイル１６と駆動コイル（補助コイル）１８を設けている。 In FIG. 1, reference numeral 10 denotes an input power source. A primary coil 14 is provided on the primary side of the output transformer 12, and a switching FET 20 is directly connected as a switching element. A secondary coil 16 and a drive coil (auxiliary coil) 18 that reverse the above are provided.

２次コイル１６と駆動コイル１８のコイル接続点は２次側同期整流器としての同期整流ＦＥＴ２４のソ−ス端子Ｓに接続され、そのドレイン端子Ｄは平滑コンデンサ２６のプラス側に接続されている。駆動コイル１８の他端は同期整流駆動回路３０を介して同期整流ＦＥＴ２４のゲ−ト端子Ｇに接続されている。 A coil connection point between the secondary coil 16 and the drive coil 18 is connected to a source terminal S of a synchronous rectification FET 24 as a secondary side synchronous rectifier, and a drain terminal D thereof is connected to a plus side of the smoothing capacitor 26. The other end of the drive coil 18 is connected to the gate terminal G of the synchronous rectification FET 24 via the synchronous rectification drive circuit 30.

制御回路２８は出力電圧Ｖｏを安定化するためのＰＷＭ制御信号を絶縁ドライブ回路２２に出力し、絶縁ドライブ回路２２はスイッチングＦＥＴ２０のゲート端子Ｇとソース端子Ｓ間に制御信号Ｅ１を出力し、制御信号Ｅ１がハイレベル（Ｈ）になるとスイッチングＦＥＴ２０がオンし、制御信号Ｅ１がローレベル（Ｌ）になるとスイッチングＦＥＴ２０がオフする。絶縁ドライバ回路２２はフォトカプラなどにより１次側と２次側を絶縁分離している。 The control circuit 28 outputs a PWM control signal for stabilizing the output voltage Vo to the insulated drive circuit 22, and the insulated drive circuit 22 outputs a control signal E1 between the gate terminal G and the source terminal S of the switching FET 20 for control. When the signal E1 becomes high level (H), the switching FET 20 is turned on, and when the control signal E1 becomes low level (L), the switching FET 20 is turned off. The insulating driver circuit 22 insulates and separates the primary side and the secondary side by a photocoupler or the like.

同期整流駆動回路３０は、駆動コイル１８の他端と同期整流ＦＥＴ２４のゲ−ト端子Ｇの間に、ダイオード３２、コンデンサ３４及び第１抵抗３６、更に、同期整流ＦＥＴ２４のゲート端子Ｇとソース端子Ｓとの間には第２抵抗３８を直列に接続している。１次側のスイッチングＦＥＴ２０のオフで駆動コイル１８に発生したプラス極性（正極性）の電圧を、第１抵抗３６と第２抵抗３８の抵抗分割に基づくゲートバイアス信号として同期整流ＦＥＴ２４のゲ−ト端子Ｇに印加してオンする。 The synchronous rectification drive circuit 30 includes a diode 32, a capacitor 34 and a first resistor 36 between the other end of the drive coil 18 and the gate terminal G of the synchronous rectification FET 24, and a gate terminal G and a source terminal of the synchronous rectification FET 24. A second resistor 38 is connected in series with S. The positive polarity (positive polarity) voltage generated in the drive coil 18 when the switching FET 20 on the primary side is turned off is used as a gate bias signal based on the resistance division of the first resistor 36 and the second resistor 38 to gate the synchronous rectifier FET 24. Applied to terminal G and turned on.

ここで、ダイオード３２は駆動コイル１８の他端にダイオ−ド３２のアノ−ド端子を接続し、カソ−ド端子はコンデンサ３４の一端に接続しており、１次側のスイッチングＦＥＴ２０のオンで駆動コイル１８に発生したマイナス極性（負極性）の電圧に基づくゲートバイアス信号の同期整流ＦＥＴ２４のゲ−ト端子Ｇに対する印加を阻止する。 Here, the diode 32 is connected to the anode terminal of the diode 32 at the other end of the driving coil 18, and the cathode terminal is connected to one end of the capacitor 34. When the switching FET 20 on the primary side is turned on. Application of the gate bias signal based on the negative polarity (negative polarity) voltage generated in the drive coil 18 to the gate terminal G of the synchronous rectification FET 24 is blocked.

コンデンサ３４は、１次側のスイッチングＦＥＴ２０のオフで駆動コイル１８に発生したプラス極性（正極性）の電圧により充電される。第１抵抗から同期整流ＦＥＴ２４のゲ−ト端子Ｇ電流が流れる。第２抵抗は、駆動コイル１８の他端に、第１抵抗と直列接続されることにより、駆動コイル１８で発生した電圧を抵抗分割してスイッチングＦＥＴ２４のゲート端子Ｇに印加している。また、第１抵抗と第２抵抗は直列接続されているから、コンデンサ３４に流れ込む電荷量を制限し、コンデンサ３４に電荷が溜まるにつれて徐々に電流が減少する。即ち、コンデンサ３４の容量と同期整流ＦＥＴ２４の寄生容量及び第１抵抗３６と第２抵抗３８を加えた抵抗値で決まる時定数に従って減少する。このため、同期整流ＦＥＴ２４のゲ−ト端子Ｇに印加されるゲートバイアス電圧は、電流の減少と共に減衰する。 The capacitor 34 is charged by a positive polarity (positive polarity) voltage generated in the drive coil 18 when the primary side switching FET 20 is turned off. The gate terminal G current of the synchronous rectification FET 24 flows from the first resistor. The second resistor is connected to the other end of the drive coil 18 in series with the first resistor, so that the voltage generated in the drive coil 18 is divided by resistance and applied to the gate terminal G of the switching FET 24. Further, since the first resistor and the second resistor are connected in series, the amount of charge flowing into the capacitor 34 is limited, and the current gradually decreases as the charge accumulates in the capacitor 34. That is, the capacitance decreases according to a time constant determined by the capacitance of the capacitor 34, the parasitic capacitance of the synchronous rectification FET 24, and the resistance value including the first resistor 36 and the second resistor 38. For this reason, the gate bias voltage applied to the gate terminal G of the synchronous rectification FET 24 attenuates as the current decreases.

コンデンサ３４の両端のそれぞれには一対の放電用スイッチング素子としての放電用ＦＥＴ４０，４２のドレイン端子Ｄが接続され、それぞれのソ−ス端子Ｓは２次コイル１６と駆動コイル１８のコイル接続点に接続している。放電用ＦＥＴ４０，４２のゲ−ト端子Ｇには絶縁型の放電リセット回路４４からの制御信号Ｅ２が与えられている。 The drain terminals D of discharge FETs 40 and 42 as a pair of discharge switching elements are connected to both ends of the capacitor 34, and the source terminals S are connected to the coil connection points of the secondary coil 16 and the drive coil 18. Connected. A control signal E2 from an insulating discharge reset circuit 44 is applied to the gate terminals G of the discharge FETs 40 and 42.

放電リセット回路４４は絶縁ドライブ回路２２からの制御信号Ｅ１を入力し、１次側のスイッチングＦＥＴ２０をオンして駆動コイル１８にマイナス極性（負極性）の電圧を発生するタイミングで制御信号Ｅ２を出力して放電用ＦＥＴ４０，４２を同時にオンし、コンデンサ３４の両端を接続する放電回路を形成してコンデンサ３４の電荷を放電リセットし、次の充電に備える。放電リセット回路４４が出力する制御信号Ｅ２は、絶縁ドライブ回路２２の出力する制御信号Ｅ１を微分して正極成分のみを取り出したパルス信号となる。 The discharge reset circuit 44 receives the control signal E1 from the insulated drive circuit 22, turns on the primary side switching FET 20, and outputs the control signal E2 at the timing of generating a negative polarity (negative polarity) voltage in the drive coil 18. Then, the discharge FETs 40 and 42 are simultaneously turned on to form a discharge circuit for connecting both ends of the capacitor 34 to reset the charge of the capacitor 34 to prepare for the next charge. The control signal E2 output from the discharge reset circuit 44 is a pulse signal obtained by differentiating the control signal E1 output from the insulated drive circuit 22 and extracting only the positive electrode component.

次に図１の実施形態の動作を図２に示す各部の動作波形を参照して説明する。ここで図２（Ａ）は制御信号Ｅ１の電圧波形、図２（Ｂ）はスイッチングＦＥＴ２０のドレイン・ソース間電圧Ｖｄｓ１、図２（Ｃ）は１次コイル１４に発生する電圧、図２（Ｄ）は２次側コイル１６に発生する電圧、図２（Ｅ）は駆動コイル１８に発生する電圧、図２（Ｆ）は同期整流ＦＥＴ２４のゲ−ト・ソース間電圧Ｖｇｓ２、図２（Ｇ）は同期整流ＦＥＴ２４のドレイン・ソース間電圧Ｖｄｓ２、図２（Ｈ）は２次コイル１８に流れる電流、更に図２（Ｉ）は放電リセット回路４４から出力する制御信号Ｅ２を示している。 Next, the operation of the embodiment of FIG. 1 will be described with reference to the operation waveforms of the respective parts shown in FIG. 2A shows the voltage waveform of the control signal E1, FIG. 2B shows the drain-source voltage Vds1 of the switching FET 20, FIG. 2C shows the voltage generated in the primary coil 14, and FIG. ) Is a voltage generated in the secondary coil 16, FIG. 2E is a voltage generated in the drive coil 18, FIG. 2F is a gate-source voltage Vgs2 of the synchronous rectification FET 24, and FIG. Is the drain-source voltage Vds2 of the synchronous rectification FET 24, FIG. 2 (H) is the current flowing through the secondary coil 18, and FIG. 2 (I) is the control signal E2 output from the discharge reset circuit 44.

制御回路２８は出力電圧Ｖｏを入力して基準電圧との誤差を検出し、誤差をなくすようなパルス幅を制御したＰＷＭ制御信号を生成して絶縁ドライブ回路２２に出力し、絶縁ドライブ回路２２はフォトカプラなどによる絶縁結合を介して図２（Ａ）に示す制御信号Ｅ１を１次側のスイッチングＦＥＴ２０に出力してハイレベルでオンし、ローレベルでオフするスイッチングを繰り返している。 The control circuit 28 receives the output voltage Vo, detects an error from the reference voltage, generates a PWM control signal with a pulse width controlled so as to eliminate the error, and outputs the PWM control signal to the isolated drive circuit 22. The isolated drive circuit 22 The control signal E1 shown in FIG. 2A is output to the switching FET 20 on the primary side through insulating coupling by a photocoupler or the like, and switching is switched on at a high level and turned off at a low level.

スイッチングＦＥＴ２０のオン、オフに伴って出力トランス１２の１次コイル１４への印加電圧は反転を繰り返す。出力トランス１２の２次コイル１６及び駆動コイル１８の極性は１次コイル１４と反対であるので、１次コイル１４に対し２次コイル１６及び駆動コイル１８の発生電圧は反転する。 The voltage applied to the primary coil 14 of the output transformer 12 repeats inversion as the switching FET 20 is turned on and off. Since the secondary coil 16 and the drive coil 18 of the output transformer 12 are opposite in polarity to the primary coil 14, the voltages generated by the secondary coil 16 and the drive coil 18 are reversed with respect to the primary coil 14.

制御信号Ｅ１がローレベルになると、スイッチングＦＥＴ２０のオフによって駆動コイル１８にプラス極性の電圧が誘起され、同期整流駆動回路３０に設けたダイオ−ド３２、コンデンサ３４及び第１抵抗３６を介して同期整流ＦＥＴ２４のゲ−ト端子Ｇにゲートバイアス電圧が印加され同期整流ＦＥＴ２４がオンとなる。この同期整流ＦＥＴ２４に対するゲ−トバイアス電圧は徐々に低下していくが、制御信号Ｅ１がハイレベルになる前に、同期整流ＦＥＴ２４が動作を停止するスレッショルド電圧Ｖｔｈを下回らないように時定数が調整されている。 When the control signal E1 is at a low level, a positive polarity voltage is induced in the drive coil 18 by turning off the switching FET 20 and is synchronized via the diode 32, the capacitor 34 and the first resistor 36 provided in the synchronous rectification drive circuit 30. A gate bias voltage is applied to the gate terminal G of the rectifying FET 24, and the synchronous rectifying FET 24 is turned on. The gate bias voltage for the synchronous rectification FET 24 gradually decreases, but before the control signal E1 becomes high level, the time constant is adjusted so as not to fall below the threshold voltage Vth at which the synchronous rectification FET 24 stops its operation. ing.

続いて制御信号Ｅ１がハイレベルになると、スイッチングＦＥＴ２０がオンし、出力トランス１２の駆動コイル１８にはマイナス極性の電圧が誘起されるが、同期整流駆動回路３０に設けたダイオ−ド３２への逆方向への電圧印加となるため、同期整流ＦＥＴ２４のゲ−ト端子Ｇへゲートバイアス電圧が印加されない。 Subsequently, when the control signal E1 becomes high level, the switching FET 20 is turned on, and a negative polarity voltage is induced in the drive coil 18 of the output transformer 12, but the voltage to the diode 32 provided in the synchronous rectification drive circuit 30 is increased. Since the voltage is applied in the reverse direction, the gate bias voltage is not applied to the gate terminal G of the synchronous rectification FET 24.

また、制御信号Ｅ１がハイレベルになると同時に、放電リセット制御回路４４から図２（Ｉ）に示す制御信号（パルス信号）Ｅ２が発生し、放電用ＦＥＴ４０及び放電用ＦＥＴ４２を同時にオンし、放電用ＦＥＴ４０が同期整流ＦＥＴ２４のゲ−ト電荷を引き抜きオフ状態とする。放電用ＦＥＴ４２もオンするため、コンデンサ３４に充電していた電荷を放電してリセットする。これにより次に制御信号Ｅ１がローレベルとなった場合に、同期整流駆動回路３０に設けたダイオ−ド３２、コンデンサ３４及び第１抵抗３６を介して同期整流ＦＥＴ２４のゲ−ト端子Ｇにゲートバイアス電圧を印加することが可能となり、同期整流を繰り返すことができる。 At the same time as the control signal E1 becomes high level, a control signal (pulse signal) E2 shown in FIG. 2I is generated from the discharge reset control circuit 44, and the discharge FET 40 and the discharge FET 42 are turned on at the same time. The FET 40 pulls out the gate charge of the synchronous rectification FET 24 and turns it off. Since the discharging FET 42 is also turned on, the charge charged in the capacitor 34 is discharged and reset. As a result, when the control signal E1 next becomes a low level, the gate is connected to the gate terminal G of the synchronous rectification FET 24 via the diode 32, the capacitor 34 and the first resistor 36 provided in the synchronous rectification drive circuit 30. A bias voltage can be applied, and synchronous rectification can be repeated.

このようして同期整流ＦＥＴ２４のゲート端子Ｇに対するマイナス電圧印加を阻止した同期整流動作を行うことで、入力電圧Ｖｉが高くなった時の定格を越えるマイナス電圧の印加による同期整流ＦＥＴ２４の破壊を確実に防止し、広い入力電圧範囲で動作することができる。 Thus, by performing the synchronous rectification operation in which the negative voltage application to the gate terminal G of the synchronous rectification FET 24 is prevented, the destruction of the synchronous rectification FET 24 due to the application of the negative voltage exceeding the rating when the input voltage Vi becomes high is ensured. And can operate over a wide input voltage range.

次に電源を停止した場合の動作を図３の各部の動作波形を参照して説明する。図３にあっては、図２の場合と同様に同期整流動作を実施しており、時刻ｔ１で電源の停止を行ったとすると、絶縁ドライブ回路２２からの制御信号Ｅ１がローレベルになり、１次側のスイッチングＦＥＴ２０がオフ状態となり、このため出力トランス１２の駆動コイル１８にプラス極性の電圧が発生し、同期整流駆動回路３０のダイオード３２、コンデンサ３４及び第１抵抗３６を介して同期整流ＦＥＴ２４のゲ−ト端子Ｇにゲートバイアス電圧が印加され、同期整流ＦＥＴ２４がオン状態となる。 Next, the operation when the power supply is stopped will be described with reference to the operation waveforms of the respective parts in FIG. In FIG. 3, if the synchronous rectification operation is performed in the same manner as in FIG. 2 and the power supply is stopped at time t1, the control signal E1 from the insulated drive circuit 22 goes to the low level. The switching FET 20 on the next side is turned off, so that a positive polarity voltage is generated in the drive coil 18 of the output transformer 12, and the synchronous rectification FET 24 is passed through the diode 32, the capacitor 34 and the first resistor 36 of the synchronous rectification drive circuit 30. A gate bias voltage is applied to the gate terminal G, and the synchronous rectification FET 24 is turned on.

コンデンサ３２及び同期整流ＦＥＴ２４のゲートに充電された電荷は、第１抵抗３６と第２抵抗３８により徐々に放電し、ゲートバイアス電圧は放電と共に減衰し、トランスコアが飽和する前の時刻ｔ２でスレッショルド電圧Ｖｔｈを下回り、同期整流ＦＥＴ２４がオフ状態となる。これにより電源停止状態で出力トランス１２の２次コイル１６に流れる回生電流をカットして出力トランス１２の飽和を防ぐことができ、電源停止後に大電流が流れることを確実に防止できる。 The charges charged in the gates of the capacitor 32 and the synchronous rectification FET 24 are gradually discharged by the first resistor 36 and the second resistor 38, the gate bias voltage is attenuated along with the discharge, and the threshold is reached at time t2 before the transformer core is saturated. The voltage falls below the voltage Vth, and the synchronous rectification FET 24 is turned off. As a result, the regenerative current flowing through the secondary coil 16 of the output transformer 12 can be cut off when the power is stopped to prevent the output transformer 12 from being saturated, and a large current can be reliably prevented from flowing after the power is stopped.

図４は、本発明による他の同期整流駆動回路３１を用いた同期整流型フライバックコンバ−タ（絶縁型）によるスイッチング電源装置の実施形態を示した回路図である。図４に示した同期整流駆動回路３１は、図１に示した同期整流駆動回路３０における一対の放電用ＦＥＴ４０、４２の一方の放電用ＦＥＴ４０を、ダイオード４６（第２）に替えている。 FIG. 4 is a circuit diagram showing an embodiment of a switching power supply device using a synchronous rectification type flyback converter (insulated type) using another synchronous rectification drive circuit 31 according to the present invention. In the synchronous rectification drive circuit 31 shown in FIG. 4, one of the pair of discharge FETs 40 and 42 in the synchronous rectification drive circuit 30 shown in FIG. 1 is replaced with a diode 46 (second).

ダイオード４６（第２）は、コンデンサ３４と第１抵抗３６間にカソ−ド端子を接続し、アノ−ド端子は同期整流ＦＥＴ２４のソース端子に接続して、同期整流ＦＥＴ２４への逆電圧の印加を防止している。 The diode 46 (second) has a cathode terminal connected between the capacitor 34 and the first resistor 36, and the anode terminal is connected to the source terminal of the synchronous rectification FET 24 to apply a reverse voltage to the synchronous rectification FET 24. Is preventing.

ダイオード３２（第１）、コンデンサ３４、第１抵抗３６及び第２抵抗３８を接続したゲート回路は、同期整流駆動回路３０と同様であるが、コンデンサ３４の第１抵抗３６側にのみ、放電用ＦＥＴ４２が接続されている。放電用ＦＥＴ４２のゲート端子Ｄには放電リセット回路４４が接続され、放電リセット回路４４からの制御信号Ｅ２が与えられる。 The gate circuit to which the diode 32 (first), the capacitor 34, the first resistor 36, and the second resistor 38 are connected is the same as that of the synchronous rectification drive circuit 30, but only for the first resistor 36 side of the capacitor 34 for discharging. The FET 42 is connected. A discharge reset circuit 44 is connected to the gate terminal D of the discharge FET 42, and a control signal E2 from the discharge reset circuit 44 is applied.

放電リセット回路４４から与えられる制御信号Ｅ２は、１次側のスイッチングＦＥＴ２０をオンして駆動コイル１８にマイナス極性（負極性）の電圧を発生するタイミングで出力して放電用ＦＥＴ４２をオンして放電回路を形成する。このとき、ダイオード４６（第２）によりスイッチングＦＥＴ２４のゲート端子に逆極性の電圧が印加するのを防止する。放電用ＦＥＴ４２のオンによる放電回路で、コンデンサ３４の電荷を放電リセットし、次の充電に備える。 The control signal E2 given from the discharge reset circuit 44 turns on the primary side switching FET 20 and outputs it to the drive coil 18 at the timing of generating a negative polarity (negative polarity) voltage, and turns on the discharge FET 42 to discharge. Form a circuit. At this time, the diode 46 (second) prevents a reverse polarity voltage from being applied to the gate terminal of the switching FET 24. In the discharge circuit by turning on the discharge FET 42, the charge of the capacitor 34 is discharged and reset to prepare for the next charge.

同期整流動作中に電源を停止した場合は、同期整流駆動回路３０と同様に、絶縁ドライブ回路２２からの制御信号Ｅ１がローレベルとなることで１次側のスイッチングＦＥＴ２０がオフ状態となり、このため出力トランス１２の駆動コイル１８にプラス極性の電圧が発生し、同期整流駆動回路３１のダイオード３２（第１）、コンデンサ３４及び第１抵抗３６を介して同期整流ＦＥＴ２４のゲ−ト端子Ｇにゲートバイアス電圧が印加され、同期整流ＦＥＴ２４がオン状態となる。 When the power supply is stopped during the synchronous rectification operation, similarly to the synchronous rectification drive circuit 30, the control signal E1 from the insulated drive circuit 22 goes to a low level, so that the primary side switching FET 20 is turned off. A positive polarity voltage is generated in the drive coil 18 of the output transformer 12, and the gate is connected to the gate terminal G of the synchronous rectification FET 24 via the diode 32 (first), the capacitor 34, and the first resistor 36 of the synchronous rectification drive circuit 31. A bias voltage is applied, and the synchronous rectification FET 24 is turned on.

コンデンサ３４及び同期整流ＦＥＴ２４のゲートに充電された電荷は、第１抵抗３６と第２抵抗３８により徐々に放電し、ゲートバイアス電圧は放電と共に減衰し、トランスコアが飽和する前にスレッショルド電圧Ｖｔｈを下回り、同期整流ＦＥＴ２４がオフ状態となる。これにより電源停止状態で出力トランス１２の２次コイル１６に流れる回生電流をカットして出力トランス１２の飽和を防ぐことができ、電源停止後に大電流が流れることを確実に防止できる。 The electric charge charged to the capacitor 34 and the gate of the synchronous rectification FET 24 is gradually discharged by the first resistor 36 and the second resistor 38, the gate bias voltage is attenuated together with the discharge, and the threshold voltage Vth is reduced before the transformer core is saturated. The synchronous rectification FET 24 is turned off. As a result, the regenerative current flowing through the secondary coil 16 of the output transformer 12 can be cut off when the power is stopped to prevent the output transformer 12 from being saturated, and a large current can be reliably prevented from flowing after the power is stopped.

図５は、図９に示した平滑コンデンサ１２６のマイナス側に接続される二次コイル端子に、同期整流ＦＥＴ１２４を備えたスイッチング電源装置に、同期整流駆動回路３０を適用したスイッチング電源装置を示している。 FIG. 5 shows a switching power supply device in which the synchronous rectification drive circuit 30 is applied to the switching power supply device having the synchronous rectification FET 124 at the secondary coil terminal connected to the negative side of the smoothing capacitor 126 shown in FIG. Yes.

図５において、２次コイル１６の端子は平滑コンデンサ２６のプラス側に接続され、２次コイル１６の他端子は、スイッチングＦＥＴ２４のドレイン端子Ｄに接続され、スイッチングＦＥＴ２４のソース端子Ｓから平滑コンデンサ２６のマイナス側に接続されている。駆動コイル１８のコイル接続点は、ダイオード３２、コンデンサ３４と第１抵抗３６を介して同期整流ＦＥＴ２４のゲート端子Ｇに接続されている。駆動コイル１８の他端は電流制限抵抗３６を介して同期整流ＦＥＴ２４のソース端子Ｓに接続され、同期整流駆動回路３０を構成している。 In FIG. 5, the terminal of the secondary coil 16 is connected to the plus side of the smoothing capacitor 26, the other terminal of the secondary coil 16 is connected to the drain terminal D of the switching FET 24, and the smoothing capacitor 26 is connected from the source terminal S of the switching FET 24. It is connected to the negative side. The coil connection point of the drive coil 18 is connected to the gate terminal G of the synchronous rectification FET 24 via a diode 32, a capacitor 34 and a first resistor 36. The other end of the drive coil 18 is connected to the source terminal S of the synchronous rectification FET 24 via a current limiting resistor 36 to constitute a synchronous rectification drive circuit 30.

この様な回路構成であっても、電源停止状態で出力トランス１２の２次コイル１６に流れる回生電流をカットして出力トランス１２の飽和を防ぐことができ、電源停止後に大電流が流れることを確実に防止できる。 Even with such a circuit configuration, it is possible to prevent the saturation of the output transformer 12 by cutting the regenerative current flowing in the secondary coil 16 of the output transformer 12 when the power supply is stopped, and that a large current flows after the power supply is stopped. It can be surely prevented.

図６は、図５に示した回路構成に対して、一対の放電用ＦＥＴ４０、４２を用いた同期整流駆動回路３０から、放電用ＦＥＴ４２とダイオード４６（第２）を用いた同期整流駆動回路３１にした図である。この場合においても、図４で説明したと同様の機能と動作が実現でき、電源停止後に大電流が流れることを確実に防止できる。 6 differs from the circuit configuration shown in FIG. 5 in that a synchronous rectification drive circuit 31 using a discharge FET 42 and a diode 46 (second) is changed from a synchronous rectification drive circuit 30 using a pair of discharge FETs 40 and 42. FIG. Even in this case, the same function and operation as described in FIG. 4 can be realized, and it is possible to reliably prevent a large current from flowing after the power supply is stopped.

なお、上記の実施形態にあっては、同期整流型フライバックコンバータを用いたスイッチング電源装置を例にとるものであったが、本発明は同期整流型フライバックコンバータそのものを含むものである。 In the above embodiment, the switching power supply device using the synchronous rectification type flyback converter is taken as an example. However, the present invention includes the synchronous rectification type flyback converter itself.

また上記の実施形態にあっては、絶縁ドライブ回路２２で１次側と２次側を絶縁分離しているが、制御回路２８側で絶縁分離を行っても良い。 Further, in the above embodiment, the primary side and the secondary side are insulated and separated by the insulated drive circuit 22, but the insulation separation may be performed on the control circuit 28 side.

また本発明はその目的と利点を損なうことのない適宜の変形を含み、また上記の実施形態に示した数値による限定は受けない。
The present invention includes appropriate modifications that do not impair the object and advantages thereof, and is not limited by the numerical values shown in the above embodiments.

１０：入力電源
１２：出力トランス
１４：１次コイル
１６：２次コイル
１８：駆動コイル
２０：スイッチングＦＥＴ
２２：絶縁ドライブ回路
２４：同期整流ＦＥＴ
２６：平滑コンデンサ
２８：制御回路
３０、３１：同期整流駆動回路
３２、４６：ダイオード
３４：コンデンサ
３６：第１抵抗
３８：第２抵抗
４０、４２：放電用ＦＥＴ
４４：放電リセット回路 10: input power supply 12: output transformer 14: primary coil 16: secondary coil 18: drive coil 20: switching FET
22: Isolated drive circuit 24: Synchronous rectification FET
26: smoothing capacitor 28: control circuit 30, 31: synchronous rectification drive circuit 32, 46: diode 34: capacitor 36: first resistor 38: second resistor 40, 42: discharge FET
44: Discharge reset circuit

Claims

An output transformer including a primary coil provided on the primary side, a secondary coil provided on the secondary side so as to be opposite in polarity to the primary coil, and a drive coil;
A primary side switching element connected in series to the primary coil of the output transformer and controlled to be turned on and off based on a control signal from a control circuit;
A secondary-side synchronous rectifier that is off / on-controlled so as to be in opposite phase to the on / off control of the primary-side switching element, and that synchronously rectifies the induced voltage of the secondary coil and outputs the same to a smoothing capacitor;
In a switching power supply using a synchronous rectification type flyback converter comprising:
The secondary side synchronous rectifier is controlled to be turned off and on so as to be in reverse phase to the on and off control of the primary side switching element by a drive signal generated from the induced voltage of the drive coil, and the primary side switching element When the switch is turned on, the drive signal generated from the negative induced voltage generated in the drive coil is blocked from being supplied to the secondary side synchronous rectifier, and the drive is performed when the primary side switching element is turned off due to the power stop. A switching device comprising a synchronous rectification drive circuit for reducing a drive signal to the secondary side synchronous rectifier generated from a positive induced voltage generated in the coil and turning off the secondary side synchronous rectifier after a predetermined time. Power supply.

In the switching power supply device according to claim 1,
The secondary side synchronous rectifier is a synchronous rectification FET;
The synchronous rectification driving circuit includes:
Between the output terminal of the drive coil and the gate terminal of the synchronous rectification FET, a diode that is turned on with a positive induced voltage and turned off with a negative induced voltage, a capacitor charged with a positive induced voltage, and the drive signal A gate circuit in which a first resistor that adjusts the current of the second resistor is connected in series, and a second resistor is connected between the gate terminal of the synchronous rectification FET and a coil connection point of the drive coil;
A pair of switching elements connected between the coil connection points from both ends of the capacitor;
Based on a control signal from the control circuit 28, when the primary side switching element is turned off and a positive voltage is induced in the drive coil 18, the pair of discharge switching elements are turned off, and the primary side A discharge reset circuit that turns on the pair of discharge switching elements to discharge and reset a capacitor of the gate circuit when a switching element is turned off and a negative voltage is induced in the drive coil 18;
A switching power supply device comprising:

In the switching power supply device according to claim 2,
A switching power supply apparatus comprising the gate circuit, the pair of discharge switching elements, and a discharge reset circuit constituting the synchronous rectification drive circuit on a positive electrode side of the secondary coil.

In the switching power supply device according to claim 2,
A switching power supply apparatus comprising the gate circuit, the pair of discharge switching elements, and a discharge reset circuit constituting the synchronous rectification drive circuit on a negative electrode side of the secondary coil.

In the switching power supply device according to claim 1,
The secondary side synchronous rectifier is a synchronous rectification FET;
The synchronous rectification driving circuit includes:
Between the output terminal of the drive coil and the gate terminal of the synchronous rectification FET, a first diode that is turned on with a positive induced voltage and turned off with a negative induced voltage, a capacitor charged with a positive induced voltage, and the A gate circuit in which a first resistor for adjusting a current of a drive signal is connected in series and a second resistor is connected between a gate terminal of the synchronous rectification FET and a coil connection point of the drive coil;
A discharge switching element connected between the capacitor terminal on the first diode side and the coil connection point;
A second diode connected between the capacitor terminal on the first resistance side and the coil connection point;
Based on a control signal from the control circuit, when the primary side switching element is turned off and a positive voltage is induced in the drive coil, the discharging switching element is turned off, and the primary side switching element is turned off. When a negative voltage is induced in the drive coil, a discharge reset circuit that turns on the discharge switching element and resets the capacitor of the gate circuit via the discharge switching element;
A switching power supply device comprising:

In the switching power supply device according to claim 5,
A switching power supply apparatus comprising the gate circuit, the discharge switching element, the second diode, and the discharge reset circuit constituting the synchronous rectification drive circuit on a positive electrode side of the secondary coil.

In the switching power supply device according to claim 5,
A switching power supply device comprising: the gate circuit, the discharge switching element, the second diode, and a discharge reset circuit constituting the synchronous rectification drive circuit provided on a negative electrode side of the secondary coil.