JP2000116122A - Power supply device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent simultaneous on-state by providing a forced break circuit at auxiliary coil winding to break a synchronous rectification MOS transistor after a predetermined time elapses after a voltage with a polarity for allowing a synchronous rectification MOS transistor to conduct current is induced. SOLUTION: When a main switching element 12 is changed from current- conduction state to break state, a voltage that is higher than that at a source terminal is applied to the gate terminal of a synchronous rectification MOS transistor 21. As a result, the synchronous rectification MOS transistor 21 conducts current in an opposite direction from the normal case, feeds current from the source terminal to the drain terminal, supplies power to a load by energy being shifted from the source terminal to the drain terminal, and at the same time charges a secondary side rectification smoothing circuit 22. In a switching power supply, a forced break circuit 30 is connected to auxiliary coil winding 43, and the forced break circuit 30 also starts operating when a voltage with a polarity for allowing the synchronous rectification MOS transistor 21 to conduct current is induced in the auxiliary coil winding 43.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a power supply device,
In particular, the present invention relates to a technique for suppressing surge current of a synchronous rectification type switching power supply.

[0002]

2. Description of the Related Art In recent years, a number of synchronous rectification type switching power supplies have been developed which rectify a voltage induced in a secondary winding by utilizing a third quadrant operation of a MOS transistor. Reference numeral 101 in FIG. 2 denotes a conventional switching power supply, which stabilizes a DC voltage applied to an input terminal 161 on the primary side and transfers energy to a secondary side while being insulated by a transformer 104. , Secondary output terminal 1
It is configured to obtain a constant DC voltage from 63.

The switching power supply 101 will be described. A primary winding 141, a secondary winding 142, an auxiliary winding 143, and a voltage detection winding 144 magnetically coupled to each other are provided in the transformer 104.

A primary switching element 112 is connected in series to a primary winding 141, and a primary input terminal 161 is connected to the primary switching element 112.
The DC voltage applied between the first terminal 141 and the ground terminal 162 is applied to the series circuit of the primary winding 141 and the main switching element 112 after the ripple component is removed by the smoothing circuit 111.

The gate terminal of the main switching element 112 is connected to the PWM circuit 116, performs a switching operation at a predetermined frequency, and induces a voltage in the secondary winding 142.

A synchronous rectification MOS transistor (n-channel type MOS transistor) 121 is connected in series to the secondary winding 142. The gate terminal of the synchronous rectification MOS transistor 121 is connected to one end of the auxiliary winding 143. It is connected.

The polarity of the secondary winding 142 and the auxiliary winding 143 is such that a positive voltage is applied to the source terminal of the synchronous rectification MOS transistor 121 by the secondary winding 142 when the main switching element 112 changes from the conductive state to the cutoff state. In addition, the auxiliary winding 143 is configured to apply a positive voltage to the gate terminal of the synchronous rectification MOS transistor 121.

As described above, when the main switching element 121 changes from the conductive state to the cut-off state, a positive voltage is applied to the source terminal and the gate terminal of the synchronous rectification MOS transistor 121 at the same time. The three-quadrant operation is performed, and a current is caused to flow in the direction of the arrow 147 by the voltage induced in the secondary winding 142,
While charging the capacitor in the rectifying and smoothing circuit 122,
A current is supplied from the output terminal 163 to the load.

In this switching power supply 101, a voltage proportional to the voltage generated in the secondary winding 142 appears on the voltage detection winding 144.
The voltage generated at 4 is smoothed by the filter circuit 113 and then divided by the series resistor 114 to generate a sampling voltage V _samp .

The sampling voltage V _samp is input to the error amplifier 115 together with the reference voltage V _ref , and the difference voltage is output to the PWM circuit 116 as an error signal. PW
Since the M circuit 116 changes the ratio between the conduction period and the cutoff period of the main switching element 112 in a direction to reduce the error signal, the output terminal 163 on the secondary side eventually has a magnitude corresponding to the reference voltage _Vref. That is, a constant voltage can be obtained.

Reference numerals 119 and 129 denote snubber circuits on the primary side and the secondary side, respectively.
12 and a surge voltage generated in the synchronous rectification MOS transistor 121 are absorbed as much as possible.

However, in the switching power supply 101 as described above, particularly when the load is light, the capacitor 124 in the rectifying / smoothing circuit 122 is overcharged. As a result, while the main switching element 112 is shut off, Then, the discharge current of the overcharged capacitor 124 flows.

The direction of the discharge current is indicated by reference numeral 148 in FIG.
As shown in the figure, the secondary winding 142 has the opposite direction to the current when the capacitor is charged, and once the discharge current flows, the secondary winding 142 and the auxiliary winding 143 have the synchronous rectification MOS transistor 121 , A voltage having a polarity that causes the current to flow in the forward direction is induced, so that the discharge current cannot be stopped.

As described above, when the main switching element 112 changes from the cut-off state to the conducting state while the discharge current is flowing through the secondary winding 142, the main switching element 112
Large surge currents flow through.

The upper symbol I in the timing chart of FIG.
_Reference numeral ₁₄₁ denotes a current flowing through the primary winding 141 (that is, a current flowing through the main switching element 112), and a lower symbol I ₁₄₂ denotes a current flowing through the secondary winding 142. The symbol T indicates a period during which the synchronous rectification MOS transistor 121 conducts in the forward direction (operates as a transistor) and the overcharged capacitor 124 discharges, in which state the main switching element 112 conducts from the cut-off state. Since the state changes, a surge current 148 is generated.

The surge current 148 as described above causes deterioration of the main switching element 112 and also causes a reduction in efficiency.

[0017]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned disadvantages of the prior art, and an object of the present invention is to provide a technique for preventing the above simultaneous ON.

[0018]

In order to solve the above-mentioned problems, an invention according to claim 1 comprises a primary winding and a secondary winding magnetically coupled to each other, and a main switching device connected in series to the primary winding. An element, a synchronous rectification MOS transistor connected in series to the secondary winding, and an auxiliary winding magnetically coupled to the primary winding and having one end connected to a gate terminal of the synchronous rectification MOS transistor. When the main switching element conducts, at one end of the auxiliary winding,
A voltage to cut off the synchronous rectification MOS transistor is induced, and the synchronous rectification MO is applied to the secondary winding.
The synchronous rectification is connected to one end of the auxiliary winding when the main switching element is switched from the conductive state to the cut-off state when a voltage having a polarity reverse biasing the parasitic diode in the S transistor is induced. A power supply device configured to induce a voltage of a polarity for conducting a MOS transistor and to induce a voltage of a polarity for forward biasing a parasitic diode in the synchronous rectification MOS transistor in the secondary winding. The auxiliary winding is provided with a forced cutoff circuit, and after a voltage having a polarity for conducting the synchronous rectification MOS transistor is induced in the auxiliary winding, the synchronous rectification MOS transistor is cut off after a predetermined time has elapsed. It is characterized by being comprised so that it may be performed.

According to a second aspect of the present invention, in the power supply device according to the first aspect, the forcible shutoff circuit has an auxiliary transistor, and a voltage having a polarity for conducting the synchronous rectification MOS transistor to the auxiliary winding is provided. After the induction, the auxiliary transistor conducts with a delay, and the gate-source voltage of the synchronous rectification MOS transistor is set to be equal to or lower than a threshold voltage.

According to a third aspect of the present invention, in the power supply device according to any one of the first and second aspects, further comprising a PWM circuit, the switching operation of the main switching element is performed by the PWM circuit. The ratio between the conduction period and the interruption period is controlled to be constant, and the output voltage is made constant.

The present invention is configured as described above, and includes a primary winding and a secondary winding magnetically coupled to each other in a transformer. A main switching element is connected in series to the primary winding, and a synchronous rectification MOS transistor is connected in series to the secondary winding.

An auxiliary winding magnetically coupled to the primary winding (and the secondary winding) is disposed in the transformer.
One end is connected to the gate terminal of the synchronous rectification MOS transistor.

FIG. 5 is a sectional view of a MOS transistor 182 used in the synchronous rectification MOS transistor according to the present invention. Here, an n-channel type is shown. Reference numeral 180 denotes an n-type silicon substrate, and n
^An n ⁺ ohmic layer 186 is formed on the back surface side of the ⁻ region 198, and a drain electrode 189 is formed on the surface thereof.

On the opposite side of ohmic layer 186, a deep p
^{A +} diffusion layer 183 and a shallow p ⁻ diffusion layer 184 are formed, and an n ⁺ source diffusion layer 185 is formed in the p ⁺ and p ⁻ diffusion layers 183 and 184. Source diffusion layer 185
And source electrode 190 is formed on p ⁺ diffusion layer 183, while gate oxide film 1 is formed on p ⁻ diffusion layer 188.
88 and the gate electrode 187 are formed in this order.

[0025] voltage higher than the source electrode 190 with the gate electrode 187 is applied, p ^- n diffusion layer 184 surface
A type inversion layer is formed, source diffusion layer 185 and n ⁻ region 198 are connected by the inversion layer, and MOS transistor 182 is rendered conductive.

Between the p ⁺ and p ^- diffusion layers 183, 184 and the n ^- region 198, a pn junction formed by them forms
Although the parasitic diode 181 exists, when the MOS transistor 182 is conductive (when the inversion layer is formed), the polarity for reversely biasing the parasitic diode 181 is provided between the drain electrode 189 and the source electrode 190. Is applied (a high voltage is applied to the drain electrode 189,
When a low voltage is applied to the source electrode 190), the MOS
Transistor 182 conducts in the forward direction, and p ⁻ diffusion layer 18
A current flows from the drain electrode 189 to the source electrode 190 through the inversion layer on the eight surfaces.

When the gate electrode 187 is at the same potential as the source electrode 190, no current flows between the drain electrode 189 and the source electrode 190 because no inversion layer is formed.

Contrary to the above, when the parasitic diode 181 is forward-biased, a current flows through the diode 181 unless the MOS transistor 182 is in a conductive state. Thus, a current flows from the source electrode 190 to the drain electrode 189.

The above operation is called a third quadrant operation. However, since a voltage drop when a current flows through the inversion layer is small,
(The MOS transistor is selected to be about 0.2 V.) During the operation of the third quadrant, the parasitic diode 181 is selected.
No current flows through.

In the power supply device according to the present invention, when the main switching element changes from the cutoff state to the conduction state in the secondary winding,
A voltage for inverting a parasitic diode in the synchronous rectification MOS transistor is induced, and when the conduction state is changed to a cut-off state, a voltage in a direction for forward-biasing the parasitic diode is induced.

On the other hand, the polarity of the auxiliary winding becomes synchronous rectification MO when the main switching element changes from the cut-off state to the conductive state.
When a voltage for turning off the S transistor is induced and the main switching element changes from the conductive state to the cutoff state, a voltage for turning on the synchronous rectification MOS transistor is induced.

Therefore, when the main switching element changes from the cut-off state to the conductive state, the voltage induced in the auxiliary winding causes the synchronous rectification MOS transistor to be in the cut-off state, and no current flows through the secondary winding. Not flowing.

Conversely, when the main switching element changes from the conductive state to the cut-off state, the voltage induced in the auxiliary winding causes the synchronous rectification MOS transistor to operate in the third quadrant.
A current flows with low loss from the source terminal to the drain terminal through the inversion layer without passing through the parasitic diode. The current charges a capacitor provided in the secondary-side rectifying / smoothing circuit.

The auxiliary winding of the power supply device according to the present invention is provided with a forced cutoff circuit. When a voltage having a polarity for conducting the synchronous rectification MOS transistor is induced in the auxiliary winding, the synchronous rectification is performed after a predetermined time has elapsed. The MOS transistor is forcibly shut off.

Therefore, if the synchronous rectification MOS transistor is cut off by the forced cutoff circuit before the main switching element changes from the cutoff state to the conductive state, no surge current is generated.

The synchronous rectification MOS transistor conducts in the forward direction, and the discharge current of the capacitor flows when the energy transferred from the primary winding to the secondary winding is small (light load). When the element is under PWM control (when the ratio between the conduction period and the cut-off period is controlled at a constant frequency), the time from when the synchronous rectification MOS transistor starts the third quadrant operation to when it is forcibly cut off is started. The time can be determined based on the operating frequency of the main switching element.

[0037]

Embodiments of the present invention will be described below with reference to the drawings. Referring to FIG. 1, reference numeral 1 denotes a switching power supply according to an embodiment of the present invention,
have. In the transformer 4, a primary winding 41, a secondary winding 42, and an auxiliary winding 43 magnetically coupled to each other are provided.
And a voltage detection winding 44.

The primary winding 41 has a main switching element 1
2 are connected in series, and the voltage applied to the primary-side input terminal 61 is applied to a series circuit of the primary winding 41 and the main switching element 12 after being smoothed by the primary-side rectifying / smoothing circuit 11. It is configured as follows.

One end of the secondary winding 42 has a synchronous rectification MOS
The source terminal of the transistor 21 is connected, and the drain terminal is connected to the terminal on the high potential side of the rectifying / smoothing circuit 22 on the secondary side. Specifically, the rectifying and smoothing circuit 2
2, a low potential side terminal of the capacitor 24 is connected to a ground line. On the other hand, the other end of the secondary winding 42 is connected to the ground line (low potential side of the secondary-side smoothing circuit 22).

One end of the auxiliary winding 43 is connected to the secondary winding 4
2 and the source terminal of the synchronous rectification MOS transistor 21 are connected to each other.
It is connected to the gate terminal of the OS transistor 21 (via the operation acceleration capacitor 27 and the resistor 26).

When the main switching element 12 performs a switching operation, a voltage is induced in the secondary winding 42 via the primary winding 41. The polarity of the secondary winding 42 is configured to apply a negative voltage (a voltage lower than the ground potential) to the source terminal of the synchronous rectification MOS transistor 21 when the main switching element 12 changes from the cutoff state to the conduction state. ing.

At this time, the parasitic diode in the synchronous rectification MOS transistor 21 is reverse-biased, and a negative voltage is applied to the auxiliary winding 43 at the gate terminal of the synchronous rectification MOS transistor 21. 21 is cut off, and no current flows through the secondary winding 42. During this period, magnetic energy is accumulated in the primary winding 41.

Next, when the main switching element 12 changes from the conductive state to the cutoff state, a voltage for applying a positive voltage to the source terminal of the synchronous rectification MOS transistor 21 is induced in the secondary winding 42. In this case, the synchronous rectification M
The potential of the source terminal of the OS transistor 21 becomes higher than the potential of its drain terminal, and the internal parasitic diode is forward-biased.

As described above, when the main switching element 12 changes from the conductive state to the cutoff state, the voltage induced in the auxiliary winding 43 causes the synchronous rectification MOS transistor 21
A voltage higher than that of the source terminal is applied to the gate terminal, and as a result, the synchronous rectification MOS transistor 21 conducts in a direction opposite to the normal direction (third quadrant operation), and a current flows from the source terminal to the drain terminal. With the energy transferred from the primary winding 41 to the secondary winding 42, power is supplied to the load and the secondary side rectifying / smoothing circuit 22 is charged.

In the switching power supply 1, the auxiliary winding 4
3 is connected to a forced cutoff circuit 30,
Then, when a voltage having a polarity that causes the synchronous rectification MOS transistor 21 to conduct is induced, the forced cutoff circuit 30 also starts operating.

The forced cutoff circuit 30 will be described. The forced cutoff circuit 30 has an auxiliary switch 35 composed of an NPN transistor. The auxiliary switch 35 has an emitter terminal connected to the source terminal of the synchronous rectification MOS transistor 21, and a collector terminal connected to the gate terminal of the synchronous rectification MOS transistor 21 via a current limiting resistor 36.

The base terminal of the auxiliary switch 35 is connected to the emitter terminal via the timing capacitor 34. The base terminal is connected to the auxiliary winding 43 via the timing resistor 33 and the diode 32 connected in series to each other. Is connected to the gate terminal side.

Therefore, the auxiliary winding 43 has a synchronous rectification MOS
When a voltage having a polarity for applying a positive voltage to the gate terminal of the transistor 21 is induced and the synchronous rectification MOS transistor 21 starts the third quadrant operation, the diode 32 is forward-biased, and the current flowing through the diode 32 and the resistor 33 is
Timing capacitor 34 begins to charge.

The magnitude of the charging current is a value determined by the magnitude of the voltage induced in the auxiliary winding 43 and the resistance of the timing resistor 33. _{When the} magnitude exceeds _BE (about 0.7 V at room temperature), the base and emitter of the auxiliary switch 35 are forward-biased, and the auxiliary switch 35 becomes conductive.

When the auxiliary switch 35 is turned on, the voltage at the gate terminal of the synchronous rectification MOS transistor 21 decreases,
When the voltage between the source and the gate becomes equal to or lower than the threshold voltage, the third quadrant operation of the synchronous rectification MOS transistor 21 ends (the synchronous rectification MOS transistor 21 is shut off).

In the forced cutoff circuit 30, the sizes of the timing resistor 33 and the timing capacitor 34 are set such that the auxiliary switch 35 is turned on before the main switching element 12 changes from the cutoff state to the conductive state. Therefore, before the main switching element 12 conducts,
The synchronous rectification MOS transistor 21 shuts off, and as a result,
The main switching element 12 and the synchronous rectification MOS transistor 21 are not simultaneously turned on.

The synchronous rectification MOS
When the main switching element 12 changes from the cut-off state to the conductive state in a state where the transistor 21 is forcibly cut off, a current flows through the primary winding 41. When the main switching element 12 changes from the conductive state to the cutoff state, the secondary winding 4
2, the current is supplied to the rectifying / smoothing circuit 22 and the load.

As described above, by alternately conducting the main switching element 12 and the synchronous rectification MOS transistor 21, energy is transmitted from the primary side to the secondary side. The voltage of the secondary winding 42 is detected by the detection winding 44, divided by the series resistor 14, and a sampling voltage V _samp is generated. Sampling voltage V _{sa mp}
Is input to the error amplifier 15 together with the reference voltage _Vref ,
An error signal indicating the difference between the two voltages is output to the PWM circuit 16.

The PWM circuit 16 changes the ratio between the conduction period and the interruption period of the main switching element 12 in a direction to reduce the input error signal (the switching frequency is maintained at a constant value). As a result, a constant voltage is output from the output terminal 63 of the secondary side rectifier circuit 22.

When a voltage having a polarity that shuts off the synchronous rectification MOS transistor 21 is induced in the auxiliary winding 43, the timing capacitor 34 discharges via the capacitor 31 connected in parallel with the diode 32.
(A resistor may be provided instead of the capacitor 31. Alternatively, a Zener diode may be provided instead of the parallel circuit of the capacitor 31 and the diode 32, and discharging may be performed via the Zener diode.)

As described above, according to the power supply device of the present invention, since the main switching element 12 and the synchronous rectification MOS transistor 21 do not become conductive at the same time,
No surge current occurs.

Although the auxiliary switch 35 is constituted by a bipolar transistor, it may be constituted by a MOS transistor. In the above embodiment, the voltage detection winding 44
Although the secondary-side voltage was indirectly detected by the present invention, the present invention is not limited to this, and the secondary-side voltage is directly fed back to the primary side by using a photocoupler. Is also good.

[0058]

Since no surge current is generated, the main switching element does not deteriorate and the efficiency is increased.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an example of a power supply device of the present invention.

FIG. 2 is a circuit diagram showing an example of a conventional power supply device.

FIG. 3 is a diagram for explaining a surge current of the power supply device.

FIG. 4 is a timing chart for explaining a surge current;

FIG. 5 is a diagram for explaining a third quadrant operation of the synchronous rectification MOS transistor;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Power supply circuit 12 ... Main switching element 16 ... PWM circuit 21 ... Synchronous rectification MOS transistor 30 ... Forced shut-off circuit 35 ... Auxiliary transistor 41 ... Primary winding 42 ... Secondary winding 43 ... Auxiliary winding

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Hiroki Higashi 10-13, Minamimachi, Hanno-shi, Saitama F-term in the Handen Factory of Shindengen Kogyo Co., Ltd. 5H730 AA14 BB43 BB57 DD04 DD41 EE02 EE07 EE14 FD24 FG05

Claims (3)

[Claims] A primary winding and a secondary winding magnetically coupled to each other; a main switching element connected in series to the primary winding; a synchronous rectification MOS transistor connected in series to the secondary winding; Magnetically coupled to the primary winding, one end of the synchronous rectifier MO
An auxiliary winding connected to the gate terminal of the S transistor; and when the main switching element is turned on, a voltage is induced at the one end of the auxiliary winding to shut off the synchronous rectification MOS transistor, The secondary winding is connected so as to induce a voltage having a polarity for reversely biasing a parasitic diode in the synchronous rectification MOS transistor. When the main switching element changes from a conductive state to a cut-off state, the auxiliary winding is turned on. A voltage having a polarity that causes the synchronous rectification MOS transistor to conduct is induced at the one end of the winding, and a voltage having a polarity that forward biases a parasitic diode in the synchronous rectification MOS transistor is applied to the secondary winding. A power supply device configured to be induced, wherein the auxiliary winding is provided with a forced cutoff circuit, and the auxiliary winding is After the voltage of the polarity for turning the serial synchronous rectification MOS transistor is induced, after a predetermined time has elapsed, the power supply device, characterized in that said synchronous rectification MOS transistor is configured to be blocked. 2. The synchronous cut-off circuit has an auxiliary transistor, and after a voltage having a polarity for conducting the synchronous rectification MOS transistor is induced in the auxiliary winding, the auxiliary transistor conducts with a delay and the synchronous rectification is performed. 2. The power supply device according to claim 1, wherein a voltage between a gate and a source of the MOS transistor is set to be equal to or lower than a threshold voltage. 3. The method according to claim 1, further comprising a PWM circuit.
The power supply device according to any one of the above, wherein the PWM circuit controls the switching operation of the main switching element at a constant frequency and controls a ratio between a conduction period and a cutoff period,
The output voltage is configured to be constant.