JP2000134931A - Parallelly operated power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology for stopping the self oscillation action of the secondary side of a power unit which can no longer be operated normally. SOLUTION: A secondary-side circuit B is provided with a protective circuit 30 which controls the voltage of a gate terminal so as not to allow a synchronous rectifier MOS transistor 21 which makes a third quadrant action, to conduct when the source-drain junction of the synchronous rectifier MOS transistor 21 is forward biased (the polarity in which an inner parasitic diode is backward biased). The existence of the protective circuit prevents the self oscillation of the secondary-side circuit B and therefore a plurality of power supply equipments can be parallelly operated with safety.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a power supply device,
In particular, the present invention relates to a synchronous rectification type switching power supply suitable for parallel connection.

[0002]

2. Description of the Related Art In recent years, there has been developed a parallel operation type power supply device in which a synchronous rectification type switching power supply utilizing the third quadrant operation of a MOS transistor is used as a power supply unit, and a plurality of the power supplies are connected in parallel to obtain a large current. ing.

[0003] Reference numeral 101 in FIG. 4 denotes a parallel operation type power supply device, and a plurality of power supply units 102 _{1 to} 102 ₃ are connected in parallel (in FIG. 4, three power supply units are shown). The power supply units 102 _{1 to} 102 ₃ operate in parallel, so that a large current can be extracted from the output terminal 163.

[0004] Each power supply unit 102 ₁ to 102 ₃ includes a transformer 104 ₁ respectively, the primary circuit a ₁ ~a _3, has a secondary circuit b ₁ ~b _3, primary circuit a ₁ ~ A
₃ is an input terminal 161 and a primary side ground terminal 162
And the secondary circuits b _{1 to} b ₃ share the output terminal 163 and the secondary ground terminal 164.

Thus, one power supply unit 1 having the transformer 104, the primary circuit a, and the secondary circuit b
2, the transformer 104 includes a primary winding 141, a secondary winding 142, an auxiliary winding 143, and a voltage detection winding 144 that are magnetically coupled to each other. .

The primary winding 141 has a main switching element 112 connected in series, and a primary-side input terminal 161.
The DC voltage applied between the first terminal 141 and the ground terminal 162 is applied to the series circuit of the primary winding 141 and the main switching element 112 after the ripple component is removed by the smoothing circuit 111.

The gate terminal of the main switching element 112 is connected to a PWM circuit 116. The PWM circuit 116 causes the main switching element 112 to perform a switching operation at a predetermined frequency to induce a voltage in the secondary winding 142. .

A synchronous rectification MO is connected to one end of the secondary winding 142.
The source terminal of an S transistor (here, a case of an n-channel MOS transistor) 121 is connected, the secondary winding 142 and the synchronous rectification MOS transistor 121 are connected in series. The end is connected to the ground terminal 164 on the secondary side.

On the other hand, a synchronous rectification MOS transistor 121
Is connected to one end of the auxiliary winding 143, and the other end of the auxiliary winding 143 is connected to a portion where the secondary winding 142 and the source terminal of the synchronous rectification MOS transistor 121 are connected. ing.

The polarity of the secondary winding 142 is set such that a positive voltage is applied to the source terminal of the synchronous rectification MOS transistor 121 when the main switching element 112 changes from the conductive state to the cutoff state. The auxiliary winding 1
When the polarity of 43 changes from the conduction state to the interruption state,
The setting is such that a positive voltage is applied to the gate terminal of the synchronous rectification MOS transistor 121.

When a positive voltage is applied to the source terminal of the synchronous rectification MOS transistor 121, the parasitic diode in the synchronous rectification MOS transistor 121 is forward-biased. Is applied, the synchronous rectification MOS transistor 121 performs a third quadrant operation to be described later, flows a current from the source terminal to the drain terminal, and charges the secondary-side rectification smoothing circuit 122 connected to the drain terminal. . Since the voltage drop at this time is small, no current flows through the parasitic diode, and the loss is low.

In the power supply unit 102, a voltage proportional to the voltage generated in the secondary winding 142 appears on the voltage detection winding 144, and the voltage is smoothed by the filter circuit 113. , A sampling voltage V according to the magnitude of the output voltage.
_{A samp} has been generated.

The sampling voltage V _samp is input to the error amplifier 115 together with the reference voltage V _ref , and the difference voltage between them is output to the PWM circuit 116 as an error signal. The PWM circuit 116 includes the main switching element 1
12 is changed in a direction to reduce the error signal, so that the output terminal 16 on the secondary side
3, a constant voltage having a magnitude corresponding to the reference voltage _Vref can be obtained.

Reference numerals 119 and 129 denote primary-side and secondary-side snubber circuits for absorbing a surge voltage generated in the main switching element 112 and the synchronous rectification MOS transistor 121 as much as possible.

In the power supply unit 102, the synchronous rectification M
When the potential of the source terminal becomes lower than the potential of the drain terminal while a positive voltage is applied to the gate terminal of the OS transistor 121, the synchronous rectification MOS transistor 121 conducts in the forward direction, and the rectification smoothing circuit 122 Is discharged, and energy may be transmitted in the reverse direction from the secondary side to the primary side.

In the power supply unit of the parallel operation type, since a plurality of power supply units 102 _{1 to} 102 ₃ are connected in parallel, even if one of the power supply units fails, the power supply unit which is operating normally remains connected to the output terminal. Especially in order to maintain the voltage,
The secondary circuit b of the power supply unit in which the primary circuit has been destroyed oscillates by itself, and a current is forced to flow to the primary side.

In this case, the parallel operation type power supply 101 of the prior art cannot stop the self-excited oscillation of the secondary circuit, so that the entire power supply is eventually destroyed or adversely affects other circuits. There is a problem that exerts.

[0018]

SUMMARY OF THE INVENTION The present invention has been made in order to solve the above-mentioned disadvantages of the prior art, and has as its object to perform a self-oscillation operation on the secondary side of a power supply unit that cannot operate normally. It is to provide a technique to be stopped.

[0019]

In order to solve the above-mentioned problems, the invention according to claim 1 comprises a primary winding and a secondary winding which are magnetically coupled to each other, and a main winding connected in series to the primary winding. A switching element, a synchronous rectification MOS transistor connected in series to the secondary winding, and an auxiliary connected magnetically to the primary winding and the secondary winding and having one end connected to a gate terminal of the synchronous rectification MOS transistor. And when the main switching element changes from the cut-off state to the conducting state, the synchronous rectification M
A voltage is induced to cut off the OS transistor, and a voltage having a polarity for reverse-biasing a parasitic diode in the synchronous rectification MOS transistor is induced in the secondary winding, and the main switching element is connected to the secondary winding. When the state changes from the conductive state to the cut-off state, a voltage having a polarity that causes the synchronous rectification MOS transistor to be conductive is induced in the auxiliary winding, and a voltage in the synchronous rectification MOS transistor is generated in the secondary winding. A power supply device in which a voltage having a polarity for forward-biasing a parasitic diode is induced and the synchronous rectification MOS transistor performs a third quadrant operation, wherein a polarity of a voltage difference between the source terminal and the drain terminal is provided. And the polarity is determined by the synchronous rectification MO
When the S transistor is in the direction of conducting in the forward direction, the gate terminal of the synchronous rectification MOS transistor is
A protection circuit for applying a voltage for shutting off the synchronous rectification MOS transistor is provided.

According to a second aspect of the present invention, there are provided a plurality of the power supply units according to the first aspect, wherein each of the power supply units is connected in parallel with a common input terminal and output terminal. Parallel operation type power supply.

First, the operation of the synchronous rectification MOS transistor will be described. FIG. 5 is a cross-sectional structure diagram of a MOS transistor 182 used for the synchronous rectification MOS transistor of the present invention. Here, an n-channel type is shown. Reference numeral 180 denotes an n-type silicon substrate, and an n ⁺ ohmic layer 186 is provided on the back side of the n ⁻ region 198.
Is formed, and a drain electrode 189 is formed on the surface thereof.

On the opposite side of ohmic layer 186, a deep p
^{A +} diffusion layer 183 and a shallow p ⁻ diffusion layer 184 are formed, and an n ⁺ source diffusion layer 185 is formed in the p ⁺ and p ⁻ diffusion layers 183 and 184. Source diffusion layer 185
And source electrode 190 is formed on p ⁺ diffusion layer 183, while gate oxide film 1 is formed on p ⁻ diffusion layer 188.
88 and the gate electrode 187 are formed in this order.

[0023] voltage higher than the source electrode 190 with the gate electrode 187 is applied, p ^- n diffusion layer 184 surface
A type inversion layer is formed, source diffusion layer 185 and n ⁻ region 198 are connected by the inversion layer, and MOS transistor 182 is rendered conductive.

Between the p ⁺ and p ^- diffusion layers 183 and 184 and the n ^- region 198, a pn junction formed by them forms
Although the parasitic diode 181 exists, when the MOS transistor 182 is conductive (when the inversion layer is formed), the polarity for reversely biasing the parasitic diode 181 is provided between the drain electrode 189 and the source electrode 190. Is applied (a high voltage is applied to the drain electrode 189,
When a low voltage is applied to the source electrode 190), the MOS
Transistor 182 conducts in the forward direction, and p ⁻ diffusion layer 18
A current flows from the drain electrode 189 to the source electrode 190 through the inversion layer on the eight surfaces.

When the gate electrode 187 is at the same potential as the source electrode 190, no current flows between the drain electrode 189 and the source electrode 190 because no inversion layer is formed.

Conversely, when the parasitic diode 181 is forward-biased, a current flows through the diode 181 unless the MOS transistor 182 is in a conductive state. Thus, a current flows from the source electrode 190 to the drain electrode 189.

The above operation is called a third quadrant operation, but the voltage drop when a current flows through the inversion layer is small.
(The MOS transistor is selected to be about 0.2 V.) During the operation of the third quadrant, the parasitic diode 181 is selected.
No current flows through.

In the power supply unit of the present invention, when the main switching element changes from the cut-off state to the conductive state, a voltage for reversely biasing the parasitic diode in the synchronous rectification MOS transistor is induced in the secondary winding. When the state is changed to the cutoff state, a voltage is induced in a direction of forward biasing the parasitic diode.

On the other hand, the polarity of the auxiliary winding becomes synchronous rectification MO when the main switching element changes from the cut-off state to the conductive state.
When a voltage for turning off the S transistor is induced and the main switching element changes from the conductive state to the cutoff state, a voltage for turning on the synchronous rectification MOS transistor is induced.

Therefore, when the main switching element changes from the cut-off state to the conductive state, the synchronous rectification MOS transistor is turned off by the voltage induced in the auxiliary winding. At this time, no current flows through the secondary winding.

Conversely, when the main switching element changes from the conductive state to the cutoff state, the voltage induced in the auxiliary winding causes the synchronous rectification MOS transistor to operate in the third quadrant.
A current flows with low loss from the source terminal to the drain terminal through the inversion layer without passing through the parasitic diode. The current charges a capacitor provided in the secondary-side rectifying / smoothing circuit.

The above operation is performed when the power supply unit is operating normally. However, if the primary circuit of one power supply unit is broken while a plurality of power supply units are connected in parallel, the secondary side Output terminal becomes power supply, synchronous rectification MOS
The transistor becomes the main switching element, the secondary side circuit starts self-sustained pulsation, and tries to transfer energy from the secondary side to the primary side.

In the case of self-excited oscillation, the synchronous rectification MOS transistor tends to move in the forward direction. However, in the power supply unit of the present invention, when the drain-source of the synchronous rectification MOS transistor is biased in the forward direction (the internal parasitic diode). Is reverse-biased), the protection circuit controls the gate terminal, and the synchronous rectification MOS transistor is configured not to conduct.

Therefore, the secondary side circuit does not self-oscillate, and failure of one power supply unit does not cause failure of the entire apparatus or other circuits.

[0035]

Embodiments of the present invention will be described below with reference to the drawings. Number 1 in Figure 1 shows a parallel operation type power supply, the plurality of power supply units 2 ₁ to 2 ₃ are connected in parallel (in FIG. 1, three power unit is shown.) by each of the power supply units 2 ₁ to 2 ₃ to the parallel operation is configured to retrieve a large current from the output terminal 63.

[0036] Each power supply unit 2 ₁ to 2 _3, a transformer 4 ₁ respectively, the primary circuit A ₁ to A _3, the secondary circuit B ₁ .about.B
₃ has a primary side circuit A ₁ to A ₃ is an input terminal 6
The first and primary side ground terminals 62 are shared.
Further, the secondary side circuits B _{1 to} B ₃ share the output terminal 63 and the secondary side ground terminal 64.

[0037] The power supply device 2 ₁ to 2 ₃ is the same structure both, among the power supply units 2 ₁ to 2 _3, will be described with reference to FIG. 2 the internal circuit of the power supply unit 2 one. Referring to FIG. 2, in a transformer 4 of the power supply unit 2, a primary winding 41, a secondary winding 42, and an auxiliary winding 4 magnetically coupled to each other are provided.
3. A voltage detection winding 44 is provided.

The primary winding 41 has a main switching element 1
2 are connected in series, and the input terminal 61 of the primary side circuit A is
Is smoothed by the primary-side rectifying / smoothing circuit 11 and then applied to a series circuit of the primary winding 41 and the main switching element 12.

One end of the secondary winding 42 has a synchronous rectification MOS
The source terminal of the transistor (here, the case of an n-channel MOS transistor) 21 is connected, and the other end is connected to the secondary-side ground line (the wiring of the ground terminal 64). The low potential side of the smoothing circuit 22 of the secondary circuit B is connected to the ground line. The drain terminal of the synchronous rectification MOS transistor 21 is directly connected to the terminal on the high potential side of the capacitor 24 in the rectification smoothing circuit 22 on the secondary side.

One end of the auxiliary winding 43 is connected to the secondary winding 4
2 and the source terminal of the synchronous rectification MOS transistor 21 are connected to each other.
The gate terminal of the OS transistor 21 is connected via an operation acceleration capacitor 27 and a resistor 26.

In this power supply device 2, the protection circuit 3
0 is provided. The protection circuit 30 includes an error amplifier 31 and a protection transistor 30.
A rectifying / smoothing circuit including a diode 37 and a capacitor 38 is provided.

The rectifying / smoothing circuit is connected to one end of the auxiliary winding 43 on the gate terminal side, and is configured to half-wave rectify the voltage induced in the auxiliary winding 43 and supply it to the error amplifier 31. Have been. Therefore, at least synchronous rectification M
The error amplifier 31 is also configured to be operable during a period in which the OS transistor 21 can conduct.

The drain terminal of the synchronous rectification MOS transistor 21 (the capacitor 24 in the rectifying / smoothing circuit 22 on the secondary side)
Is divided by a resistor 33 configured by connecting two resistive elements in series, and then input to a non-inverting input terminal of an error amplifier 31. On the other hand, the voltage at the source terminal of the synchronous rectification MOS transistor 21 is input to the inverting input terminal of the error amplifier 31 via the diode 35.

The divided voltage in the resistor 33 is determined by the synchronous rectification MOS
The voltage at the non-inverting input terminal is set to be higher than the voltage at the inverting input terminal when the voltage at the drain terminal of the transistor 21 becomes higher than the voltage at the source terminal.

The protection transistor 32 is composed of an NPN-type bipolar transistor, and its base terminal is connected to the output terminal of the error amplifier 31 via a resistor 36. Therefore, when the voltage of the non-inverting input terminal of the error amplifier 31 becomes higher than the voltage of the inverting input terminal, the protection transistor 32 is turned on.

The emitter terminal of the protection transistor 32 is connected to the ground line (ground terminal 64) on the secondary side, and the collector terminal is connected to the gate terminal of the synchronous rectification MOS transistor 21. With such a connection, when the protection transistor 32 is turned on, the synchronous rectification M
The voltage of the gate terminal of the OS transistor 21 is reduced to the voltage of the emitter terminal (the voltage of the ground line).

When the main switching element 12 performs a switching operation, a voltage is induced in the secondary winding 42 and the auxiliary winding 43 via the primary winding 41. The polarity of the secondary winding 42 is configured to apply a negative voltage (a voltage lower than the ground potential) to the source terminal of the synchronous rectification MOS transistor 21 when the main switching element 12 changes from the cutoff state to the conduction state. The polarity of the auxiliary winding 43 is configured so that a negative voltage (a voltage lower than the source terminal) is applied to the gate terminal of the synchronous rectification MOS transistor 21 in that case.

Therefore, in the above case (when the main switching element 12 changes from the cut-off state to the conductive state), the voltage induced in the secondary winding 42 causes a forward bias between the drain and source of the synchronous rectification MOS transistor 21. However, since the synchronous rectification MOS transistor 21 is cut off by the auxiliary winding 43, no current flows through the secondary winding 42.
During this period, magnetic energy is accumulated in the primary winding 41.

Next, when the main switching element 12 changes from the conductive state to the cut-off state, a voltage for applying a positive voltage to the source terminal of the synchronous rectification MOS transistor 21 is induced in the secondary winding 42. In this state, the potential of the source terminal of the synchronous rectification MOS transistor 21 becomes higher than the potential of its drain terminal, and the internal parasitic diode is forward-biased.

At this time, the synchronous rectification M
Although a voltage having a polarity for applying a positive voltage to the gate terminal of the OS transistor 21 is induced, the voltage of the non-inverting input terminal of the error amplifier 31 is lower than the voltage of the inverting input terminal. Therefore, the positive voltage induced in the auxiliary winding 43 is a synchronous rectification MOS
The voltage is applied to the gate terminal of the transistor 21 as it is, and as a result, the synchronous rectification MOS transistor 21 conducts in a direction opposite to the normal direction (third quadrant operation). By this third quadrant operation, the energy stored in the primary winding 41 is
2 and the synchronous rectification MO
A current flows from the source terminal of the S transistor 21 to the drain terminal. This current supplies power to the load and charges the secondary side rectifying and smoothing circuit 22.

As described above, the switching operation of the main switching element 12 is performed, and the synchronous rectification MOS transistor 21 performs the third quadrant operation during the cutoff period of the main switching element 12, so that energy is transmitted from the primary side to the secondary side. It is supposed to be. The voltage appearing on the secondary winding 42 appears on the detection winding 44 at a predetermined ratio, and the voltage is divided by the series resistor 14 to obtain a sampling voltage V _samp.
Has been generated. Then, the sampling voltage V
_{The samp} is input to the error amplifier 15 together with the reference voltage _Vref , and an error signal indicating the difference between the two voltages is input to the PWM circuit 16.
Is output to

The PWM circuit 16 includes the main switching element 1
The ratio between the conduction period and the interruption period of the second signal is changed in a direction to reduce the input error signal (the switching frequency is maintained at a constant value). As a result, a constant voltage is output from the output terminal 63 of the secondary side rectifier circuit 22.

[0053] or more in a state where it is the operation power supply unit 2 ₁ to 2 ₃ in the case where the power supply unit 2 is operating normally are operated in parallel, the main switching element 12 is broken in one power supply 2 Then, when the source-drain is short-circuited, the secondary circuit B starts the same self-oscillation operation as the one circuit of the RCC power supply, and the output terminal 63 is used as a power supply to supply a current to the secondary winding 42. Try to shed.

When the synchronous rectification MOS transistor 21 performs a self-excited oscillation operation, the synchronous rectification MOS transistor 2
In the state where the voltage of the drain terminal is higher than the voltage of the source terminal, a voltage higher than that of the source terminal is applied to the gate terminal, and the synchronous rectification MOS transistor 21 needs to conduct in the forward direction. In this configuration, when the voltage at the drain terminal becomes higher than the voltage at the source terminal, the error amplifier 31 turns on the protection transistor 32.

Therefore, even when a voltage having a polarity for conducting the synchronous rectification MOS transistor 21 is induced in the auxiliary winding 43 in a state where the voltage of the drain terminal is higher than that of the source terminal, the protection transistor 32 is made conductive. Since the voltage at the gate terminal is reduced, the synchronous rectification MOS transistor 21 does not conduct in the forward direction. Therefore, in the power supply unit 2, the secondary circuit B does not oscillate by itself.

Reference numeral 28 denotes a synchronous rectification MOS transistor 2 similar to the power supply unit 102 of the prior art.
1 and the main switch element 12 are simultaneously prevented from conducting, and when the primary circuit A and the secondary circuit B are operating normally, the main switch element 1
2 is switched from the cut-off state to the conductive state before the synchronous rectification MO
The S transistor 21 is turned off.

Reference numerals 19 and 29 denote primary and secondary snubber circuits for absorbing a surge voltage generated in the main switching element 12 and the synchronous rectification MOS transistor 21 as much as possible.

As described above, according to the power supply device of the present invention, when the primary circuit A is broken, the synchronous rectification M
The OS transistor 21 does not conduct in the forward direction,
A failure of one power supply unit 2 does not cause a failure of another power supply unit or a failure of another device.

Although the protection switch 32 is constituted by an NPN-type bipolar transistor, it may be constituted by a PNP-type bipolar transistor. Further, it may be constituted by a MOS transistor. The synchronous rectification MOS transistor 21 is not limited to the n-channel type MOS transistor, but may be a p-channel type.

Furthermore, in the above-described embodiment, the voltage on the secondary side is indirectly detected by the voltage detection winding 44, but the present invention is not limited to this. The voltage on the secondary side may be directly fed back to the primary side.

[0061]

According to the present invention, when the primary circuit is destroyed, the operation of the secondary circuit is reliably stopped, which is safe.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an example of a power supply device of the present invention.

FIG. 2 is a circuit diagram of an example of a power supply unit according to the present invention.

FIG. 3 is a diagram illustrating a power supply unit according to the related art.

FIG. 4 is a block diagram of a power supply device using the power supply unit.

FIG. 5 is a diagram for explaining a third quadrant operation of the synchronous rectification MOS transistor;

[Explanation of symbols]

1 ...... the power supply circuit 2, 2 _{1, 2} 2, 2 ₃ ...... power unit 12 ...... main switching element 16 ...... PWM circuit 21 ...... synchronous rectification MOS transistor 30 ...... protection circuit 35 ...... auxiliary transistor 41 ...... Primary winding 42 Secondary winding 43 Auxiliary winding

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Hiroki Higashi 10-13, Minamimachi, Hanno-shi, Saitama F-term in the Handen Factory of Shindengen Kogyo Co., Ltd. 5H730 AA20 AS01 BB25 BB43 BB57 BB84 DD04 DD41 EE02 EE08 EE13 EE65 EE72 FD21 FG01 XX04 XX13 XX24 XX28 XX33 XX42

Claims (2)

[Claims] A primary winding and a secondary winding magnetically coupled to each other; a main switching element connected in series to the primary winding; a synchronous rectification MOS transistor connected in series to the secondary winding; An auxiliary winding magnetically coupled to the primary winding and the secondary winding, one end of which is connected to a gate terminal of the synchronous rectification MOS transistor; and the main switching element changes from a cutoff state to a conduction state. Sometimes, a voltage is induced at the one end of the auxiliary winding to shut off the synchronous rectification MOS transistor, and a voltage having a polarity that reverse-biases a parasitic diode in the synchronous rectification MOS transistor is applied to the secondary winding. When the main switching element changes from the conductive state to the cutoff state, the synchronous rectifying MOS transistor is connected to the auxiliary winding. With the voltage of polarity for turning the motor is induced,
A power supply device, wherein a voltage having a polarity for inducing a forward bias to a parasitic diode in the synchronous rectification MOS transistor is induced in the secondary winding, and the synchronous rectification MOS transistor operates in a third quadrant. Detecting the polarity of the voltage difference between the source terminal and the drain terminal, and when the polarity is a direction in which the synchronous rectification MOS transistor is conducted in the forward direction, a gate terminal of the synchronous rectification MOS transistor; Synchronous rectification MO
A power supply device provided with a protection circuit for applying a voltage for shutting off an S transistor. 2. A parallel operation type power supply device comprising a plurality of power supply devices according to claim 1, wherein each of the power supply devices is connected in parallel with common input terminals and output terminals.