JP2012084806A - Mounting semiconductor device and manufacturing method thereof - Google Patents

Mounting semiconductor device and manufacturing method thereof Download PDF

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JP2012084806A
JP2012084806A JP2010231736A JP2010231736A JP2012084806A JP 2012084806 A JP2012084806 A JP 2012084806A JP 2010231736 A JP2010231736 A JP 2010231736A JP 2010231736 A JP2010231736 A JP 2010231736A JP 2012084806 A JP2012084806 A JP 2012084806A
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Prior art keywords
die pad
lead
sealing body
land
resin sealing
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Inventor
Hiroshi Hattori
博 服部
Kenji Kobayashi
賢司 小林
Yoshihiro Sato
義広 佐藤
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Fujitsu Semiconductor Ltd
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Fujitsu Semiconductor Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector

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  • Lead Frames For Integrated Circuits (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a mounting semiconductor device in which confirmation of solder wetting is easy.SOLUTION: In a mounting semiconductor device, using a mounting substrate having a die pad attaching land and a lead attaching land, and a lead frame in which the die pad is positioned lower than the inner part of the lead, an extention extended continuous from the die pad to near an end of a bottom of a resin sealing body and a part formed on the die pad attaching land corresponding to the extention extended further outside are formed, and a semiconductor chip mounted to the lead frame is sealed by the resin sealing body, and a semiconductor package in which the die pad and the extention are exposed on the bottom of the resin sealing body is mounted on the mounting substrate by soldering, and a solder layer reaches the bottom end of the resin sealing body, forming a protrusion which enables a visual inspection.

Description

本発明の実施例は、実装半導体装置とその製造方法に関する。   Embodiments of the present invention relate to a mounted semiconductor device and a method for manufacturing the same.

量産性に富み、コスト低減が可能になる封止形態の半導体装置として、樹脂封止型半導体装置が知られている。樹脂封止型半導体装置は、一般的に、半導体チップを搭載するダイパッド(タブないしアイランド)、ダイパッドを支持する吊りリード、半導体チップの電極を外部に導出するためのリードを有するリードフレームを用いる。   2. Description of the Related Art Resin-encapsulated semiconductor devices are known as encapsulated semiconductor devices that are rich in mass productivity and can reduce costs. In general, a resin-encapsulated semiconductor device uses a lead frame having a die pad (tab or island) for mounting a semiconductor chip, a suspension lead for supporting the die pad, and a lead for leading an electrode of the semiconductor chip to the outside.

リードフレームのダイパッド上に半導体チップをダイボンドし、半導体チップ上のボンディングパッドをリードフレームのインナリードにワイヤボンディングし、半導体チップを覆って封止樹脂をモールドし、樹脂封止体から突出するリードを曲げ加工すると共にタイバーないしダム、枠等を切断して半導体パッケージとする。ワイヤボンディングを容易にするために、リードフレームのダイパッドをインナリードより沈み込んだ構成とし、半導体チップの上面とインナリードの上面を合わせる構成も知られている。   The semiconductor chip is die-bonded on the die pad of the lead frame, the bonding pad on the semiconductor chip is wire-bonded to the inner lead of the lead frame, the sealing resin is molded over the semiconductor chip, and the lead protruding from the resin sealing body is formed. The semiconductor package is made by bending and cutting tie bars, dams, frames, and the like. In order to facilitate wire bonding, a configuration in which the die pad of the lead frame is submerged from the inner lead and the upper surface of the semiconductor chip is aligned with the upper surface of the inner lead is also known.

封止部(パッケージ)内に組み込まれる半導体チップで発生する熱を速やかに封止部の外側に放散することも望まれる。半導体チップを搭載したリードフレームを利用して効率的に放熱を行う構成が提案されている。   It is also desired to quickly dissipate heat generated in the semiconductor chip incorporated in the sealing portion (package) to the outside of the sealing portion. A configuration for efficiently radiating heat using a lead frame on which a semiconductor chip is mounted has been proposed.

特開平6−268142号は、ダイパッドをリードより沈めて、チップ上面をリードとほぼ同一高さとし、チップ、ダイパッド、リード内側部分を包み込むように樹脂封止体でモールドし、封止体外側のリード外側部分をダイパッド底面より下方にクランク状(所謂ガルウイング状)に折り曲げて実装基盤に半田付けする構成において、ダイパッドのサポートバー(吊りリード)を幅広にしてリードと共に実装基盤上に延在させ、放熱性を向上する構成を開示する。   In JP-A-6-268142, the die pad is submerged from the lead, the top surface of the chip is made almost the same height as the lead, and is molded with a resin sealing body so as to enclose the chip, the die pad, and the inner part of the lead. In the configuration where the outer part is bent downward from the bottom of the die pad into a crank shape (so-called gull wing shape) and soldered to the mounting board, the support bar (hanging lead) of the die pad is widened and extended on the mounting board together with the lead to dissipate heat. A configuration for improving the performance is disclosed.

半導体チップを固定した支持板(タブ)の裏面(下面)を封止部の裏面(底面)に露出させる構造が知られている。リード外側部分は折り曲げて、例えばダイパッドと同一高さとする。リードを実装基盤の配線に半田付けすると共に、半導体パッケージの底面に露出したダイパッドを実装基盤上の熱拡散パッドに半田付けする。   A structure is known in which the back surface (lower surface) of a support plate (tab) to which a semiconductor chip is fixed is exposed to the back surface (bottom surface) of a sealing portion. The lead outer portion is bent to have the same height as the die pad, for example. The lead is soldered to the wiring of the mounting substrate, and the die pad exposed on the bottom surface of the semiconductor package is soldered to the thermal diffusion pad on the mounting substrate.

特開2004−235217号は、樹脂封止体底面に露出したダイパッド、樹脂封止体側面からガルウイング状に延在するリードを実装基盤上に半田付けする構造において、ダイパッドのチップを搭載するタブ部分を封止樹脂中に突出する形状とし、さらに封止樹脂中に鋸歯状に食い込む凸部をダイパッドに設けて熱変形を抑制し、チップとダイパッド間の剥離を防止するタブ露出型半導体装置を記載する。   Japanese Patent Application Laid-Open No. 2004-235217 discloses a tab portion on which a die pad chip is mounted in a structure in which a die pad exposed on the bottom surface of a resin sealing body and a lead extending in a gull wing shape from the side surface of the resin sealing body are soldered onto a mounting substrate. A tab-exposed semiconductor device that has a shape that protrudes into the sealing resin and further has a convex portion that cuts into the sealing resin in a saw-tooth shape to suppress thermal deformation and prevent peeling between the chip and the die pad. To do.

特開2003−224239号は、リードを一旦上方に折り曲げ、ワイヤより上方で外側に折り曲げ、リード上端面とダイパッド底面とが樹脂封止体表面と裏面に露出するように樹脂体でモールドし、上下を反転して実装基盤にリード先端を半田付けする構成を記載する。ダイパッドは上方(実装基盤と逆側)に露出され、放熱性を向上する。ダイパッドの吊りリード外側部分をリードと同一レベルに折り曲げ、実装面積を増大させたノンリード型半導体装置を記載する。樹脂封止体の裏面(実装面)に凹部を形成し、ゴミが発生しても収容できるようにする。   Japanese Patent Application Laid-Open No. 2003-224239 temporarily folds the lead upward, then folds it outward above the wire, and molds it with a resin body so that the upper end surface of the lead and the bottom surface of the die pad are exposed on the surface and back surface of the resin sealing body. A configuration is described in which the tip of the lead is soldered to the mounting substrate by inverting. The die pad is exposed upward (on the opposite side to the mounting substrate), improving heat dissipation. A non-lead type semiconductor device is described in which the outer portion of the suspension lead of the die pad is bent to the same level as the lead to increase the mounting area. A recess is formed on the back surface (mounting surface) of the resin sealing body so that it can be accommodated even if dust is generated.

特許第4351150号(WO2003/005475)は、ダイパッド(タブ)、タブ吊りリード、リード先端部の下面が同一平面上に位置し、タブ上面に複数の回路を含むチップを接着し、信号電極、電源電極などと共に一部の回路のグランド電極はリードにワイヤボンドし、残りの回路のグランド電極はタブにワイヤボンドし、樹脂封止体により片面モールドする際、樹脂封止体の下面をタブ、タブ吊りリード、リードの下面より引き上げて、実装面を突出させるノンリード型半導体装置を記載する。   In Japanese Patent No. 4351150 (WO2003 / 005475), a die pad (tab), a tab suspension lead, and a lower surface of a lead tip are located on the same plane, and a chip including a plurality of circuits is bonded to the upper surface of the tab. The ground electrodes of some circuits are wire-bonded to the leads together with the electrodes, etc., and the ground electrodes of the remaining circuits are wire-bonded to the tabs. A suspension lead and a non-lead type semiconductor device in which the mounting surface protrudes from the lower surface of the lead are described.

特開平6−268142号公報JP-A-6-268142 特開2004−235217号公報JP 2004-235217 A 特開2003−224239号公報JP 2003-224239 A 特許第4351150号公報Japanese Patent No. 4351150

樹脂封止体外側に導出されたリードの先端と共に樹脂封止体底面に露出したダイパッドを実装基盤に半田付けする構成において、半田の濡れ性確認が容易な実装半導体装置を提供する。   Provided is a mounting semiconductor device in which solder wettability can be easily confirmed in a configuration in which a die pad exposed to the bottom surface of a resin sealing body together with the tip of a lead led out to the outside of the resin sealing body is soldered to a mounting substrate.

実施例によれば、
表面にダイパッド接着用ランド、リード接続用ランドを有する実装基板と、
ダイパッドがリードの内側部分の存在する平面より沈んだ構成のリードフレームと、前記ダイパッド上にダイボンディングされた半導体チップと、前記半導体チップと前記リードの内側部分との間を接続するワイヤと、樹脂封止体とを含み、前記樹脂封止体底面に前記ダイパッドが露出し、前記リードの外側部分が前記樹脂封止体外側で折り曲げられ、前記ダイパッドと略同一平面の接続領域を形成する半導体パッケージと、
前記リードの接続領域を前記リード接続用ランドに接続し、前記ダイパッドを前記ダイパッド接続用ランドに接着する半田層と、
を含み、
前記半導体パッケージが、前記ダイパッドに連続して前記樹脂封止体底面端部近くまで延在する延長部を含み、
前記ダイパッド接続用ランドが、前記ダイパッドに対応する部分と、前記延長部に対応する部分とを有し、前記延長部に対応する部分は前記樹脂封止体底面端部外側に達し、前記ダイパッド接続用ランドの、延長部に対応する部分と前記延長部との間の前記半田層は、前記樹脂封止体底面端部に達し、はみ出す部分を形成する、
実装半導体装置
が提供される。
According to the example,
A mounting substrate having a die pad bonding land and a lead connection land on the surface;
A lead frame having a die pad sinking from a plane on which an inner portion of the lead exists, a semiconductor chip die-bonded on the die pad, a wire connecting the semiconductor chip and the inner portion of the lead, and a resin A semiconductor package including a sealing body, wherein the die pad is exposed on a bottom surface of the resin sealing body, and an outer portion of the lead is bent outside the resin sealing body to form a connection region substantially flush with the die pad. When,
A solder layer for connecting the lead connection region to the lead connection land, and bonding the die pad to the die pad connection land;
Including
The semiconductor package includes an extension that extends to the bottom of the bottom of the resin sealing body continuously to the die pad,
The die pad connection land has a portion corresponding to the die pad and a portion corresponding to the extension portion, and the portion corresponding to the extension portion reaches the outside of the bottom end portion of the resin sealing body, and the die pad connection The solder layer between the portion corresponding to the extension portion and the extension portion of the land for use reaches the bottom end portion of the resin sealing body and forms a protruding portion.
A mounted semiconductor device is provided.

X線を用いることなく、目視で半田濡れ性を確認できる。   The solder wettability can be confirmed visually without using X-rays.

と、When, 図1A,1Bは、第1の実施例による実装半導体装置を概略的に示す断面図及びその半導体パッケージの裏面図、図1C〜1Eは、半導体パッケージの裏面図、実装基盤の平面図、実装基板上に半導体パッケージを実装した状態の平面図である。1A and 1B are a cross-sectional view schematically showing a mounting semiconductor device according to the first embodiment and a back view of the semiconductor package, and FIGS. 1C to 1E are back views of the semiconductor package, a plan view of a mounting base, and a mounting substrate. It is a top view of the state which mounted the semiconductor package on it. 図2A〜2Cは、第2の実施例による、半導体パッケージの裏面図、実装基盤の平面図、実装基板上に半導体パッケージを実装した状態の平面図である。2A to 2C are a rear view of a semiconductor package, a plan view of a mounting substrate, and a plan view of a state in which the semiconductor package is mounted on a mounting substrate according to a second embodiment. 図3A,3Bは、変形例による半導体パッケージの裏面図である。3A and 3B are rear views of a semiconductor package according to a modification. と、When, 図4A〜4Iは、第2の実施例による実装半導体装置の製造方法の主要工程を示す断面図である。4A to 4I are cross-sectional views showing main steps of a method for manufacturing a mounted semiconductor device according to the second embodiment. 図5A,5Bは第2の実施例に用いることのできるリードフレームを概略的に示す平面図、断面図、図5Cは第1の実施例に用いることのできるリードフレームを概略的に示す平面図である。5A and 5B are a plan view and a cross-sectional view schematically showing a lead frame that can be used in the second embodiment, and FIG. 5C is a plan view schematically showing a lead frame that can be used in the first embodiment. It is.

樹脂封止体の底面にダイパッドが露出し、樹脂封止体の側面からリードが外側に導出され、下方に折り曲げられた半導体パッケージが実装基盤に半田付けで固定される実装半導体装置において、ダイパッドと実装基盤の対応ランドとの間の半田濡れ性は放熱性に大きな影響を及ぼす。高い放熱性が必要な半導体装置においては、半田濡れ性を確保することが必要である。ダイパッドはプラスチックパッケージの中央部に位置し、実装後ダイパッドと対応ランドとの間の半田層は外部から目視することはできないので、パッケージと実装基盤間の半田の濡れ性は、X線で観察している。   In the mounting semiconductor device in which the die pad is exposed on the bottom surface of the resin sealing body, the leads are led out from the side surface of the resin sealing body, and the semiconductor package bent downward is fixed to the mounting base by soldering. Solder wettability with the corresponding land on the mounting board has a significant effect on heat dissipation. In a semiconductor device that requires high heat dissipation, it is necessary to ensure solder wettability. The die pad is located at the center of the plastic package, and the solder layer between the die pad and the corresponding land after mounting cannot be seen from the outside, so the solder wettability between the package and the mounting board is observed with X-rays. ing.

但し、半導体装置の中にはX線を照射できないものもある。実装基盤が両面実装の場合、半田の濡れ領域が重なる部分についてはX線による半田の濡れ性確認ができない。X線以外の半田濡れ性確認方法が望まれる。   However, some semiconductor devices cannot be irradiated with X-rays. When the mounting substrate is a double-sided mounting, the solder wettability cannot be confirmed by X-ray at the portion where the solder wet regions overlap. A solder wettability confirmation method other than X-rays is desired.

本発明者らは、パッケージに露出するダイパッドと実装基盤の対応ランドを一部外側に延長して半田がパッケージ端まではみ出るようにして、半田濡れ性を目視で確認することを検討した。   The inventors of the present invention studied to visually confirm the solder wettability by extending the die pad exposed to the package and the corresponding land of the mounting substrate partially outward so that the solder protrudes to the package end.

図1A,1Bは、第1の実施例の概略を示す実装半導体装置の断面図およびその半導体パッケージの裏面図である。図1Aは、図1B中のIA−IA線に沿う断面図である。   1A and 1B are a cross-sectional view of a mounting semiconductor device and a rear view of the semiconductor package showing an outline of the first embodiment. 1A is a cross-sectional view taken along line IA-IA in FIG. 1B.

図1Aに示すように、半導体パッケージ10の裏面に露出したダイパッド11は、樹脂封止体7の端部近くまで延在する延長部12に連続する。半導体チップ1は、Agペースト等の導電性接着剤3によりダイパッド11に固着される。ボンディングワイヤ5は、半導体チップ1上の電極(ボンディングパッド)をリードに接続すると共に、必要に応じてチップ上の接地電極をダイパッド11に接続する。   As shown in FIG. 1A, the die pad 11 exposed on the back surface of the semiconductor package 10 continues to the extension portion 12 extending to the vicinity of the end portion of the resin sealing body 7. The semiconductor chip 1 is fixed to the die pad 11 with a conductive adhesive 3 such as an Ag paste. The bonding wire 5 connects an electrode (bonding pad) on the semiconductor chip 1 to a lead, and connects a ground electrode on the chip to the die pad 11 as necessary.

図1Bに示すように、樹脂封止体7は、裏面にダイパッド11及びその上下左右の辺中央部から4方向に延在する延長部12を露出して、半導体チップをモールドして半導体パッケージを形成する。本構成では、延長部12は矩形半導体パッケージの2辺に平行である(他の2辺には直交する)。一般的には、半導体パッケージの2辺に沿う方向に配置される。リード13は、ダイパッド11より引き上げられた面上で樹脂封止体7の厚さの中央部から外側に導出されている。実装基盤20は、図1Aにおいて4層配線で例示された多層配線を有するガラスエポキシ樹脂基盤であり、最上配線層には、リード接続用ランドと共にダイパッド11及びその延長部12に対応し、延長部12より外方にまで延在し、半導体パッケージ10の端部外に達するパッケージマウント用ランド22を有する。ランド22の下方には放熱用ビア導電体23が形成されている。   As shown in FIG. 1B, the resin encapsulant 7 exposes the die pad 11 and the extension 12 extending in four directions from the center of the upper, lower, left and right sides on the back surface, and molds the semiconductor chip to mold the semiconductor package. Form. In this configuration, the extension portion 12 is parallel to two sides of the rectangular semiconductor package (perpendicular to the other two sides). Generally, it arrange | positions in the direction in alignment with 2 sides of a semiconductor package. The lead 13 is led out from the center of the thickness of the resin sealing body 7 on the surface pulled up from the die pad 11. The mounting substrate 20 is a glass epoxy resin substrate having a multilayer wiring exemplified by the four-layer wiring in FIG. 1A, and the uppermost wiring layer corresponds to the die pad 11 and its extension part 12 together with the lead connection land, and the extension part. 12 has a package mounting land 22 that extends outward from 12 and reaches the outside of the end of the semiconductor package 10. A heat radiating via conductor 23 is formed below the land 22.

半導体パッケージ10を実装基盤20に半田層17によって接続し、実装半導体装置30が形成される。半導体パッケージ10のダイパッド11及びその延長部12と実装基盤のランド22とに接合する半田層17は、端面が半導体パッケージ10外にはみ出し、露出する。観察者35は半導体パッケージ10縁部を目視で観察することにより、半田の濡れ性を確認できる。   The semiconductor package 10 is connected to the mounting substrate 20 by the solder layer 17 to form a mounting semiconductor device 30. The solder layer 17 bonded to the die pad 11 and its extension 12 of the semiconductor package 10 and the land 22 of the mounting substrate has an end surface protruding outside the semiconductor package 10 and exposed. The observer 35 can confirm the wettability of the solder by visually observing the edge of the semiconductor package 10.

図1C,1D,1Eは、半導体パッケージ10の裏面、実装基盤20の表面、これらを接続した実装半導体装置の上面の関係を概略的に示す平面図である。図1Cは、図1Bを概略的に示した図であり、実質的な相違はない。   1C, 1D, and 1E are plan views schematically showing the relationship between the back surface of the semiconductor package 10, the surface of the mounting substrate 20, and the top surface of the mounting semiconductor device to which these are connected. FIG. 1C schematically shows FIG. 1B, and there is no substantial difference.

図1Dに示すように、実装基盤20の表面配線層には、ダイパッド及び延長部接着用のランド22及びリード接続用ランド23が配置されている。リード接続用ランド23は多層配線を介して、実装基盤裏面の配線に接続される。   As shown in FIG. 1D, a die pad and an extension bonding land 22 and a lead connection land 23 are arranged on the surface wiring layer of the mounting substrate 20. The lead connection land 23 is connected to the wiring on the back surface of the mounting substrate through multilayer wiring.

図1Eに示すように、リード13をリード接続用ランド23に半田層で接続すると共に、ダイパッド及び延長部を対応するランド22に半田層で接続する。半田層は溶融して、ダイパッド11、延長部12及びランド22を濡らし、半導体パッケージ10端部に達する。樹脂封止体底面端部に達した半田層17が、一部外側にはみ出す。半導体パッケージ10端部の半田はみ出し部32を目視することにより、半田の濡れ性を確認できる。   As shown in FIG. 1E, the lead 13 is connected to the lead connection land 23 with a solder layer, and the die pad and the extension are connected to the corresponding land 22 with a solder layer. The solder layer melts to wet the die pad 11, the extension 12, and the land 22, and reaches the end of the semiconductor package 10. A part of the solder layer 17 reaching the bottom end of the resin sealing body protrudes outward. By visually observing the solder protrusion 32 at the end of the semiconductor package 10, the wettability of the solder can be confirmed.

ダイパッド及び対応するランドを外側に延長し、その間に形成される半田層が樹脂封止体底面端部に達し、一部はみ出す構成とすることにより、半田濡れ性を目視で確認できる他、接着面積の増大により接着強度が増加し、増加した接着面積に基づき、熱抵抗が低下し、放熱性が向上する。   By extending the die pad and the corresponding land to the outside, the solder layer formed between them reaches the bottom end of the resin encapsulant and partially protrudes, so that the solder wettability can be confirmed visually, and the bonding area The increase in adhesion increases the adhesive strength, and based on the increased adhesion area, the thermal resistance decreases and the heat dissipation improves.

なお、ダイパッドの延長部が半導体パッケージの外辺に平行な配置を示したが、ダイパッドの延長部は種々の形態を取り得る。   In addition, although the extension part of the die pad has been arranged parallel to the outer side of the semiconductor package, the extension part of the die pad can take various forms.

図2A,2B,2Cは、ダイパッド11の延長部12を、半導体パッケージの対角位置にある頂部を結ぶ方向(対角方向と呼ぶ)に沿って形成した例を示す。実装基盤20のダイパッド、延長部対応ランド22の形状も、対応して、対角方向に延在する領域を有する。半導体パッケージ10を実装基盤20上に接続した時に半田層17がはみ出し、はみ出し部32を形成するのは、延長部12に対応して半導体パッケージ10の対角方向縁部となる。   2A, 2B, and 2C show an example in which the extension portion 12 of the die pad 11 is formed along a direction connecting the top portions at the diagonal positions of the semiconductor package (referred to as a diagonal direction). Correspondingly, the shape of the die pad of the mounting base 20 and the land 22 corresponding to the extended portion has a region extending diagonally. When the semiconductor package 10 is connected to the mounting substrate 20, the solder layer 17 protrudes and the protruding portion 32 is formed on the diagonal edge of the semiconductor package 10 corresponding to the extension portion 12.

ダイパッド11の外側に延長部12を接続することにより、接着面積は増大する。接着面積の増大は、接着強度の増加と放熱性の向上ももたらす。   By connecting the extension 12 to the outside of the die pad 11, the bonding area increases. An increase in the bonding area also results in an increase in adhesive strength and an improvement in heat dissipation.

ダイパッドから4方向に延長部が延在するパターンを説明したが、延長部の延在する方向の数は増減することもできる。   Although the pattern in which the extension portion extends in four directions from the die pad has been described, the number of directions in which the extension portion extends can be increased or decreased.

図3Aは、ダイパッド11から上下、左右方向に加え対角方向にも延長部12を形成した配置を示す。8方向に延長部を形成することで、接着面積も増大し、接着強度、放熱性も更に向上する。   FIG. 3A shows an arrangement in which extensions 12 are formed in the diagonal direction in addition to the vertical and horizontal directions from the die pad 11. By forming the extension in eight directions, the bonding area is increased, and the bonding strength and heat dissipation are further improved.

図3Bは、2方向にのみ延長部を延在させるパターンを示す。延長部の面積が減少すると、その分接着強度、放熱性の向上は妨げられるが、半田層が樹脂封止体底面端部に達し、はみ出す限り、半田の濡れ性確認は目視で行える。   FIG. 3B shows a pattern in which the extension is extended only in two directions. If the area of the extension portion is reduced, the improvement of the adhesive strength and heat dissipation is prevented accordingly, but the solder wettability can be confirmed visually as long as the solder layer reaches the bottom end portion of the resin sealing body and protrudes.

次に、実装半導体装置の製造方法を、図2A〜2Cに示す第2の実施例の構成を例にとって説明する。   Next, a method for manufacturing a mounted semiconductor device will be described by taking the configuration of the second embodiment shown in FIGS.

図4Aに示すように、リードフレーム8のダイパッド11の上にAgペーストで形成された導電性接着剤3を塗布する。ダイパッド11と同一平面上で延長部12がダイパッド11から外側に延在する。   As shown in FIG. 4A, the conductive adhesive 3 formed of Ag paste is applied on the die pad 11 of the lead frame 8. An extension 12 extends outward from the die pad 11 on the same plane as the die pad 11.

図5A、5Bは、本例で用いるリードフレームの形状例を示す。リードフレーム8は、複数個の半導体チップに対応する形状を有する。1つの半導体チップ搭載部の周辺部分のみを示す。図5Aは平面図、図5Bは図5A中のVB−VB線に沿う断面図である。図4A〜4Iは、図5B同様半導体パッケージの対角方向に沿う断面である。   5A and 5B show examples of the shape of the lead frame used in this example. The lead frame 8 has a shape corresponding to a plurality of semiconductor chips. Only the peripheral portion of one semiconductor chip mounting portion is shown. 5A is a plan view, and FIG. 5B is a cross-sectional view taken along line VB-VB in FIG. 5A. 4A to 4I are cross-sectional views along the diagonal direction of the semiconductor package as in FIG. 5B.

図5Aにおいて、中央にダイパッド11が配置され、その4辺の外側に所定数のリード13が配置される。リードの数を5×4で示したが、リードの数、ピン数は任意であり、実際のピン数はより多い。リード13はタイバー14で互いに接続され、枠体に支持される。ダイパッド11は、同一平面上に配置され、対角方向に伸びる延長部12を備え、延長部の外端部が吊りリード15によって引き上げられ、枠体に接続されている。ダイパッド11は、延長部12と吊りリード15により枠体に支持されるので、延長部12は吊りリードの機能も兼用している。図5Bに示すように、リード13の存在する面に対してダイパッド11は沈められた高さに配置される。この高さ差を吊りリード15が接続する。ダイパッド11上に半導体チップを配置したとき、チップ上面がリード13上面とほぼ同じ高さ(レベル)になる。延長部12は、ダイパッド11と略同一平面に配置される。ダイパッド11は複数のリード13の内側端部から離隔され、より内側に配置される。延長部12は、複数のリード13の内側端部を結ぶ線より外側(リード側)に入り込んで配置される。   In FIG. 5A, the die pad 11 is arranged at the center, and a predetermined number of leads 13 are arranged outside the four sides. Although the number of leads is shown as 5 × 4, the number of leads and the number of pins are arbitrary, and the actual number of pins is larger. The leads 13 are connected to each other by a tie bar 14 and supported by a frame. The die pad 11 is disposed on the same plane and includes an extension portion 12 extending in a diagonal direction. The outer end portion of the extension portion is pulled up by a suspension lead 15 and connected to the frame body. Since the die pad 11 is supported on the frame body by the extension portion 12 and the suspension lead 15, the extension portion 12 also functions as a suspension lead. As shown in FIG. 5B, the die pad 11 is disposed at a submerged height with respect to the surface on which the lead 13 exists. The suspension lead 15 connects this height difference. When a semiconductor chip is disposed on the die pad 11, the upper surface of the chip becomes almost the same height (level) as the upper surface of the leads 13. The extension portion 12 is disposed on substantially the same plane as the die pad 11. The die pad 11 is spaced apart from the inner ends of the plurality of leads 13 and is disposed further inside. The extension portion 12 is arranged so as to enter the outside (lead side) from the line connecting the inner end portions of the plurality of leads 13.

図4Bに示すように、ダイシングした半導体チップ1を導電性接着剤3の上に配置し、加熱して導電性接着剤3をフローさせた後、冷却し、半導体チップ1をダイパッド11上に固定する。   As shown in FIG. 4B, the diced semiconductor chip 1 is placed on the conductive adhesive 3, heated to flow the conductive adhesive 3, cooled, and the semiconductor chip 1 is fixed on the die pad 11. To do.

図4Cに示すように、半導体チップ1上の電極(ボンディングパッド)とリード13の間を金線などのワイヤ5でボンディングする。必要に応じて、半導体チップ1のグランド電極をダイパッド11にワイヤボンディングする。ダイパッド11を共通グランド端子とすると、グランド用リードの数を減少することができる場合がある。   As shown in FIG. 4C, the electrodes (bonding pads) on the semiconductor chip 1 and the leads 13 are bonded with wires 5 such as gold wires. If necessary, the ground electrode of the semiconductor chip 1 is wire bonded to the die pad 11. If the die pad 11 is a common ground terminal, the number of ground leads may be reduced.

図4Dに示すように、リードフレーム8のダイパッド11上に接続した半導体チップ1、半導体チップとリードを接続するワイヤ5を包み込むように、フィラー入りエポキシ樹脂等の樹脂をモールドし、樹脂封止体7を形成する。リード13の外側部分は樹脂封止体7の外側に延在する。タイバー14などをパンチング除去する。   As shown in FIG. 4D, a resin such as an epoxy resin containing a filler is molded so as to wrap the semiconductor chip 1 connected on the die pad 11 of the lead frame 8 and the wire 5 connecting the semiconductor chip and the lead. 7 is formed. The outer portion of the lead 13 extends outside the resin sealing body 7. The tie bar 14 and the like are removed by punching.

図4Eに示すように、樹脂封止体7外側に突出するリード13表面をメッキ後、リード13を曲げ加工する。曲げ加工したリード13の底面(接続領域)と、パッケージ10底面に露出するダイパッド11、延長部12は、略同一平面上に配置される。なお、物理的に厳密な同一平面でなくとも、実装上同一平面と見なせる場合、略同一平面と呼ぶ。リードの接続領域はダイパッドの露出面と略同一平面にある。   As shown in FIG. 4E, after plating the surface of the lead 13 protruding to the outside of the resin sealing body 7, the lead 13 is bent. The bottom surface (connection region) of the bent lead 13, the die pad 11 exposed on the bottom surface of the package 10, and the extension portion 12 are arranged on substantially the same plane. Note that even if they are not physically strict planes, they are referred to as substantially the same plane when they can be regarded as the same plane in mounting. The lead connection area is substantially flush with the exposed surface of the die pad.

図4Fに示すように、実装基盤2010年9月20日のダイパッド対応ランド22上に半田ペースト17pを塗布する。ランド22はダイパッド11と延長部12とに対応した形状を有し、延長部12に対向する部分は延長部12より長い。なお、4層配線を有する実装基板を概略的に例示するが、配線は図1Aに示すように、回路に応じて分離、接続される。   As shown in FIG. 4F, a solder paste 17p is applied on the die pad-compatible land 22 on September 20, 2010 on the mounting substrate. The land 22 has a shape corresponding to the die pad 11 and the extension portion 12, and a portion facing the extension portion 12 is longer than the extension portion 12. In addition, although the mounting board | substrate which has 4 layer wiring is illustrated schematically, as shown to FIG. 1A, wiring is isolate | separated and connected according to a circuit.

図4Gに示すように、半田ペースト17pの上に図4Eの工程で得た半導体パッケージ10を配置する。   As shown in FIG. 4G, the semiconductor package 10 obtained in the step of FIG. 4E is disposed on the solder paste 17p.

図4Hに示すように、この構成に対して加熱工程を行い、半田ペースト17pからフラックスを蒸発させ、半田を溶融させる。その後降温して、半田を固化させ、実装基板20上に半導体パッケージ10を固定する。半田層17は、ランド22とダイパッド11、延長部12を接続し、端部は半導体パッケージ10外に達する。   As shown in FIG. 4H, a heating process is performed on this configuration, the flux is evaporated from the solder paste 17p, and the solder is melted. Thereafter, the temperature is lowered to solidify the solder, and the semiconductor package 10 is fixed on the mounting substrate 20. The solder layer 17 connects the land 22, the die pad 11, and the extension 12, and the end reaches the outside of the semiconductor package 10.

図4Iに示すように、半田層17の端部は半導体パッケージ10の端部に達し、外側にはみ出すので、観察者35が目視で半田濡れ性を確認できる。   As shown in FIG. 4I, the end portion of the solder layer 17 reaches the end portion of the semiconductor package 10 and protrudes to the outside, so that the observer 35 can visually confirm the solder wettability.

以上の工程においては、吊りリードをダイパッドの延長部としても利用した。勿論、吊りリードとダイパッドの延長部を別に作成することもできる。   In the above process, the suspension lead was also used as an extension part of the die pad. Of course, the extension part of the suspension lead and the die pad can be created separately.

図5Cはダイパッド11の対角方向に吊りリード15が形成され、4辺の中央部からタイバー14近傍まで延長部12が配置された形状を示す。図1A〜1Eに示した実施例に用いることができる。図5Aのリードフレーム同様、延長部12は、ダイパッド11と略同一平面に配置される。ダイパッド11は複数のリード13の内側端部から離隔され、より内側に配置される。延長部12は、複数のリード13の内側端部を結ぶ線より外側(リード側)に入り込んで配置される。   FIG. 5C shows a shape in which the suspension leads 15 are formed in the diagonal direction of the die pad 11 and the extension portions 12 are arranged from the central portion of the four sides to the vicinity of the tie bar 14. It can be used in the embodiment shown in FIGS. Similar to the lead frame of FIG. 5A, the extension portion 12 is disposed in substantially the same plane as the die pad 11. The die pad 11 is spaced apart from the inner ends of the plurality of leads 13 and is disposed further inside. The extension portion 12 is arranged so as to enter the outside (lead side) from the line connecting the inner end portions of the plurality of leads 13.

なお、図5Cの構成において、延長部12の先端にタイバー14と接続する吊りリードを設けてもよい。この場合、半導体パッケージの対角方向に設けた吊りリード15をリードに交換することもできる。   In the configuration of FIG. 5C, a suspension lead connected to the tie bar 14 may be provided at the tip of the extension portion 12. In this case, the suspension leads 15 provided in the diagonal direction of the semiconductor package can be replaced with leads.

以上、実施例に沿って本発明を説明したが、本発明はこれらに限られるものではない。種々の変更、置換、改良、組み合わせ等が可能なことは、当業者に自明であろう。   As mentioned above, although this invention was demonstrated along the Example, this invention is not limited to these. It will be apparent to those skilled in the art that various modifications, substitutions, improvements, combinations, and the like can be made.

1 半導体チップ、
3 導電性接着層、
5 ワイヤ、
7 樹脂封止体、
8 リードフレーム、
10 半導体パッケージ、
11 ダイパッド、
12 延長部、
13 リード、
14 タイバー、
15 吊りリード、
17 半田層、
20 実装基盤、
22 ランド、
30 実装半導体装置、
32 はみ出し部。
1 Semiconductor chip,
3 conductive adhesive layer,
5 wires,
7 Resin encapsulant,
8 Lead frame,
10 Semiconductor package,
11 Die pad,
12 Extension,
13 leads,
14 Tie bar,
15 hanging leads,
17 Solder layer,
20 mounting base,
22 rand
30 Mounting semiconductor device,
32 Extruding part.

Claims (5)

表面にダイパッド接着用ランド、リード接続用ランドを有する実装基板と、
ダイパッドがリードの内側部分の存在する平面より沈んだ構成のリードフレームと、前記ダイパッド上にダイボンディングされた半導体チップと、前記半導体チップと前記リードの内側部分との間を接続するワイヤと、樹脂封止体とを含み、前記樹脂封止体底面に前記ダイパッドが露出し、前記リードの外側部分が前記樹脂封止体外側で折り曲げられ、前記ダイパッドと略同一平面の接続領域を形成する半導体パッケージと、
前記リードの接続領域を前記リード接続用ランドに接続し、前記ダイパッドを前記ダイパッド接続用ランドに接着する半田層と、
を含み、
前記半導体パッケージが、前記ダイパッドに連続して前記樹脂封止体底面端部近くまで延在する延長部を含み、
前記ダイパッド接続用ランドが、前記ダイパッドに対応する部分と、前記延長部に対応する部分とを有し、前記延長部に対応する部分は前記樹脂封止体底面端部外側に達し、前記ダイパッド接続用ランドの、延長部に対応する部分と前記延長部との間の前記半田層は、前記樹脂封止体底面端部に達し、はみ出す部分を形成する、
実装半導体装置。
A mounting substrate having a die pad bonding land and a lead connection land on the surface;
A lead frame having a die pad sinking from a plane on which an inner portion of the lead exists, a semiconductor chip die-bonded on the die pad, a wire connecting the semiconductor chip and the inner portion of the lead, and a resin A semiconductor package including a sealing body, wherein the die pad is exposed on a bottom surface of the resin sealing body, and an outer portion of the lead is bent outside the resin sealing body to form a connection region substantially flush with the die pad. When,
A solder layer for connecting the lead connection region to the lead connection land, and bonding the die pad to the die pad connection land;
Including
The semiconductor package includes an extension that extends to the bottom of the bottom of the resin sealing body continuously to the die pad,
The die pad connection land has a portion corresponding to the die pad and a portion corresponding to the extension portion, and the portion corresponding to the extension portion reaches the outside of the bottom end portion of the resin sealing body, and the die pad connection The solder layer between the portion corresponding to the extension portion and the extension portion of the land for use reaches the bottom end portion of the resin sealing body and forms a protruding portion.
Mounting semiconductor device.
前記延長部は、前記ダイパッドと略同一平面上に配置される請求項1記載の実装半導体装置。   The mounting semiconductor device according to claim 1, wherein the extension portion is disposed on substantially the same plane as the die pad. 前記延長部は、前記半導体パッケージの2辺に沿う方向か、対角方向に沿う方向に配置される請求項1または2記載の実装半導体装置。   The mounting semiconductor device according to claim 1, wherein the extension portion is disposed in a direction along two sides of the semiconductor package or in a direction along a diagonal direction. 前記延長部が、前記ダイパッドを支持する吊りリードの機能を兼用する請求項1〜3のいずれか1項記載の実装半導体装置。   The mounting semiconductor device according to claim 1, wherein the extension portion also functions as a suspension lead that supports the die pad. ダイパッドがリードの内側部分が存在する平面より沈んだ構成のリードフレームを用い、前記ダイパッド上に半導体チップをダイボンディングし、
前記半導体チップと前記リードとの間をワイヤで接続し、
前記半導体チップと前記ワイヤを覆う樹脂封止体を形成し、前記樹脂封止体底面に前記ダイパッドを露出させ、
前記樹脂封止体外に突出するリードを曲げ加工して、前記ダイパッド底面と略同一平面に接着領域を配置して半導体パッケージを形成し、
表面に、リード接続用ランドとダイパッド接着用ランドとを有する実装基板の各ランド上に半田ペースト層を形成し、
前記半田ペースト層上に前記半導体パッケージを配置し、
前記半田ペースト層を加熱、溶融後、冷却固化して半田層とし、前記リードを前記リード接続用ランドに接続すると共に、前記ダイパッドを前記ダイパッド接着用ランドに接着する、
実装半導体装置の製造方法において、
前記半導体パッケージが、前記ダイパッドに連続して前記樹脂封止体底面端部近くまで略同一平面に延在する延長部を有し、前記樹脂封止体底面に前記延長部を露出し、
前記ダイパッド接着用ランドが、前記ダイパッドに対応する部分と、前記延長部に対応する部分とを有し、前記延長部に対応する部分は前記樹脂封止体底面端部外に達し、前記加熱溶融後、固化した半田層が前記樹脂封止体底面端部に達し、はみ出し部を形成する、
実装半導体装置の製造方法。
Using a lead frame having a structure in which the die pad is sunk from the plane where the inner portion of the lead exists, a semiconductor chip is die-bonded on the die pad,
A wire is connected between the semiconductor chip and the lead,
Forming a resin sealing body covering the semiconductor chip and the wire, exposing the die pad on the bottom surface of the resin sealing body;
Bending a lead projecting out of the resin sealing body, and forming a semiconductor package by arranging an adhesive region in substantially the same plane as the bottom surface of the die pad;
On the surface, a solder paste layer is formed on each land of the mounting substrate having a land for lead connection and a land for bonding a die pad,
Placing the semiconductor package on the solder paste layer;
The solder paste layer is heated, melted, cooled and solidified to form a solder layer, the lead is connected to the lead connection land, and the die pad is bonded to the die pad bonding land.
In a method for manufacturing a mounted semiconductor device,
The semiconductor package has an extension portion extending substantially in the same plane to the resin pad bottom end portion continuously to the die pad, exposing the extension portion on the resin seal bottom surface,
The die pad bonding land has a portion corresponding to the die pad and a portion corresponding to the extension portion, and the portion corresponding to the extension portion reaches the outside of the bottom end portion of the resin sealing body, and is heated and melted. After that, the solidified solder layer reaches the bottom end of the resin sealing body to form a protruding portion.
A method of manufacturing a mounted semiconductor device.
JP2010231736A 2010-10-14 2010-10-14 Mounting semiconductor device and manufacturing method thereof Withdrawn JP2012084806A (en)

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