JP2012069583A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable high integration of a circuit constituting a semiconductor memory.SOLUTION: A semiconductor memory comprises a semiconductor substrate and a plurality of memory cell transistors. The plurality of memory cell transistors are connected in series by trench gates embedded in deep tranches provided on the semiconductor substrate. Inversion layers of the opposite conductive type to that of the semiconductor substrate are formed in regions of the semiconductor substrate around and between the trench gates during write operations and read operations of the memory cells.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  An electrically writable and erasable nonvolatile semiconductor memory device such as a flash memory is widely adopted as a large-capacity data storage medium such as a digital camera, a mobile terminal, a portable audio device, or a personal computer (PC).

  With the progress of miniaturization and low power consumption of consumer devices and industrial devices, the higher integration of memory cells and memory cell peripheral circuits (for example, decoders) constituting a semiconductor memory device has been achieved. It has been demanded.

JP 2006-319202 A

  An object of the present invention is to provide a semiconductor memory device in which a circuit can be highly integrated.

  According to one embodiment, a semiconductor memory device has a plurality of memory cells including a semiconductor substrate and a plurality of memory cell transistors. The plurality of memory cell transistors have trench gates embedded in a plurality of deep grooves provided in the semiconductor substrate, and are connected in series. During the write operation and read operation of the memory cell, an inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed in the region of the semiconductor substrate around and between the trench gates.

FIG. 1A is a diagram illustrating a semiconductor memory device according to a first embodiment, FIG. 1A is a circuit diagram illustrating the semiconductor memory device, and FIG. 1B is a plan view illustrating the semiconductor memory device. 1 is an enlarged plan view showing a semiconductor memory device according to a first embodiment. It is sectional drawing of the semiconductor memory device which follows the AA line of FIG.1 (b). FIG. 4A is a band diagram, and FIG. 4B is a diagram illustrating the gate voltage and the thickness of the inversion layer, illustrating generation of the inversion layer according to the first embodiment.

It is a figure which shows the relationship of the fringe electric field with respect to a trench gate space | interval.
It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor memory device which concerns on 1st embodiment. FIG. 12A is a plan view showing a trench gate in a cylindrical shape, and FIG. 12B is a plan view in which a cylindrical dummy is arranged between the trench gates. is there. It is sectional drawing which shows the laminated gate type semiconductor memory device of a modification. FIG. 14A is a circuit diagram illustrating a semiconductor memory device, and FIG. 14B is a plan view illustrating the semiconductor memory device. It is sectional drawing of the semiconductor memory device which follows the BB line of FIG.14 (b). It is sectional drawing which shows the four-layer semiconductor memory device of a modification. FIG. 17A is a circuit diagram illustrating a semiconductor memory device, and FIG. 17B is a plan view illustrating the semiconductor memory device. It is an enlarged plan view showing a semiconductor memory device according to a third embodiment. It is a figure explaining the write-in operation | movement of the semiconductor memory device concerning 3rd embodiment. It is a figure explaining the read-out operation | movement of the semiconductor memory device concerning 3rd embodiment. It is a figure explaining the batch erase operation | movement of the semiconductor memory device concerning 3rd embodiment. FIG. 22A is a circuit diagram showing a column decoder, FIG. 22B is an enlarged plan view showing the decoder, and FIG. 22A is a diagram showing a column decoder according to the fourth embodiment. It is a figure explaining erase operation of the column decoder concerning a 4th embodiment. It is a figure explaining the write-in operation | movement of the column decoder which concerns on 4th embodiment. It is a figure explaining operation | movement of the column decoder which concerns on 4th embodiment. FIG. 10 is a circuit diagram showing a column decoder according to a fifth embodiment. It is a figure explaining the multi-value column control transistor which concerns on 5th embodiment. It is a figure explaining operation | movement of the column decoder which concerns on 5th embodiment. FIG. 10 is a circuit diagram showing a semiconductor memory device according to a sixth embodiment. It is sectional drawing which shows the semiconductor memory device which concerns on 6th embodiment. FIG. 10 is a circuit diagram showing a semiconductor memory device according to a seventh embodiment. It is a top view which shows the semiconductor memory device which concerns on 7th embodiment. It is sectional drawing which follows the CC line of FIG. It is sectional drawing which follows the DD line | wire of FIG.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
First, a semiconductor memory device according to a first embodiment of the present invention will be described with reference to the drawings. 1 is a diagram illustrating a semiconductor memory device, FIG. 1A is a circuit diagram illustrating the semiconductor memory device, and FIG. 1B is a plan view illustrating the semiconductor memory device. FIG. 2 is an enlarged plan view showing the semiconductor memory device. FIG. 3 is a cross-sectional view of the semiconductor memory device taken along line AA in FIG. In the present embodiment, the selection transistor constituting the memory cell and the gate of the memory cell transistor are trench gates embedded in the deep groove, and the stored information flows using the side surfaces of the trench gate.

  As shown in FIG. 1A, the semiconductor memory device 90 is provided with a plurality of memory cells including the memory cell MC1. The plurality of memory cells constitute a memory cell block. The semiconductor memory device 90 is a NAND flash memory having a charge trap flash (CTF) structure. The charge trap flash (CTF) may be called MONOS (Metal Oxide Nitride Oxide Silicon), SONOS (Silicon Oxide Nitride Oxide Silicon), or TANOS (TaN AlO Nitride Oxide Silicon).

  In the memory cell MC1, a selection transistor SGDT1 is provided on the bit line BL2 side, a selection transistor SGST1 is provided on the source line SL side, and a plurality of memory cell transistors (MCT1 to MCT1 to MCT4) connected in series are provided therebetween. The bit lines BL1, BL2, BL3, and BL4 and the selection line SGD, the word line WL4, the word line WL3, the word line WL2, the word line WL1, the selection line SGS, and the source line SL cross each other. The plate line PL as the substrate potential is spaced from the plurality of memory cells.

  Here, the memory cell transistor has a threshold value of 1 bit (two), but may have a threshold value of 2 bits or more.

  The selection line SGD is connected to the gates of the selection transistors on the bit lines BL1 to BL4 side. The word line WL4 is connected to the gate of the fourth memory cell transistor connected to the bit lines BL1 to BL4. The word line WL3 is connected to the gate of the third memory cell transistor connected to the bit lines BL1 to BL4. The word line WL2 is connected to the gate of the second memory cell transistor connected to the bit lines BL1 to BL4. The word line WL1 is connected to the gate of the first memory cell transistor connected to the bit lines BL1 to BL4. The selection line SGS is connected to the gate of the selection transistor on the bit lines BL1 to BL4 side connected to the source line SL.

  As shown in FIG. 1B, in the semiconductor memory device 90, the plate line PL, the source line SL, the selection line SGS, the word line WL1, the word line WL2, the word line WL3, the word line WL4, and the selection line SGD are in the vertical direction. (In the figure) spaced apart from each other and arranged in parallel. Bit lines BL1 to BL4 are spaced apart from each other in the horizontal direction (in the drawing) and arranged in parallel.

The plate line PL is connected to a P ⁺ layer plate line contact PLC provided on the P-type semiconductor substrate 1. The source line SL is provided on the P-type semiconductor substrate 1 and is connected to an N ⁺ layer source line contact SLC in contact with the selection transistor SGST. Bit lines BL1 to BL4 are spaced apart from each other and are connected to N ⁺ layer bit line contacts BLC in contact with a select transistor SGDT provided on a P-type semiconductor substrate 1, respectively.

The interval between the word lines adjacent to the word lines (the horizontal pitch in the figure) is set to 1F, which is the minimum design dimension. The pitch of the transistors arranged in the vertical direction in the figure is set to 1F which is the minimum design dimension. Cell size of the memory cell is set to 2F ^2.

  As shown in FIG. 2, in the memory cell MC1, a selection transistor SGST1, a memory cell transistor MCT1, a memory cell transistor MCT2, a memory cell transistor MCT3, a memory cell transistor MCT4, and a selection transistor SGDT1 having a quadrangular prism shape are separated from each other. Arranged in series.

Select transistor SGST1 is in contact with N ⁺ layer source line contact SLC at the side surface opposite to memory cell transistor MCT1. In the select transistor SGST1, a trench gate 3 is embedded in a deep groove 2 having a quadrangular prism shape. The trench gate 3 includes a gate insulating film 11 and a gate electrode film 12.

The selection transistor SGDT1 is in contact with the N ⁺ layer bit line contact BLC at the side surface facing the memory cell transistor MCT4. In the select transistor SGDT1, the trench gate 3 is embedded in the deep groove 2. The trench gate 3 of the selection transistor SGDT1 includes a gate insulating film 11 and a gate electrode film 12.

  In the memory cell transistors MCT1 to MCT4, a trench gate 4 is embedded in the deep groove 2. The trench gate 4 includes a gate insulating film 21, a charge storage film 22, a high dielectric constant insulating film 23, and a gate electrode film 12.

  Memory cell transistors MCT1 to MCT4 are arranged at a pitch of word line interval Wwl1. The memory cell transistors MCT1 to MCT4 are spaced apart from each other by a trench gate interval Wgp1, and an inversion layer 31 having a reverse conductivity type (N type) with respect to the semiconductor substrate 1 is formed in the trench gate 4 during the write operation and read operation of the memory cell. Formed around and between.

  Select transistor SGST1 and memory cell transistor MCT1 are spaced apart by a trench gate interval Wgp2. In the select transistor SGST1, an inversion layer 31 having a conductivity type (N-type) opposite to that of the semiconductor substrate 1 is formed around the trench gate 3 during a write operation and a read operation of the memory cell. Between the select transistor SGST1 and the memory cell transistor MCT1, an inversion layer 31 having a conductivity type opposite to that of the semiconductor substrate 1 (N-type) is formed during a memory cell write operation and read operation.

  Select transistor SGDT1 and memory cell transistor MCT4 are spaced apart by a trench gate interval Wgp3. In the select transistor SGDT1, an inversion layer 31 having a conductivity type opposite to that of the semiconductor substrate 1 (N-type) is formed around the trench gate 3 during a memory cell write operation and read operation. Between the select transistor SGDT1 and the memory cell transistor MCT4, an inversion layer 31 having a conductivity type opposite to that of the semiconductor substrate 1 (N-type) is formed in the memory cell write operation and read operation. Details of the formation of the inversion layer will be described later.

  During the write operation and read operation of the memory cell, the inversion layer 31 is formed around the select transistor SGST1, the memory cell transistors MCT1 to MCT4, the select transistor SGDT1, and between the transistors. During the memory cell read operation, the memory information of the memory cell transistor flows from the source line SL in the direction of the bit line BL (information is read from the bit line BL).

As shown in FIG. 3, the semiconductor memory device 90 includes a P ⁺ layer 34 as a plate line contact connected to the plate line PL on the P-type semiconductor substrate 1 and a source line contact connected to the source line SL. An N ⁺ layer 5 is provided as a bit line contact connected to the N ⁺ layer 5 and the bit line BL. Between the N ⁺ layer 5 which is connected to the N ⁺ layer 5 and the bit lines BL connected to the source line SL, and shallow deep groove 2 depths are plurality than the P ⁺ layer 34 and the N ⁺ layer 5.

A trench gate 3 is buried in the deep groove 2 in contact with the N ⁺ layer 5 connected to the source line SL. A trench gate 3 is buried in the deep groove 2 in contact with the N ⁺ layer 5 connected to the bit line BL. A plurality of deep grooves 2 in which the trench gates 4 are embedded are provided between the deep grooves 2 in which the trench gates 3 are embedded.

Here, the memory cell transistors MCT1 to MCT4 are not provided with an N ⁺ layer serving as a source or a drain. The select transistor SGST1 is not provided with an N ⁺ layer serving as a source or a drain in a region where the inversion layer 31 is formed. The selection transistor SGDT1 is not provided with an N ⁺ layer serving as a source or a drain in a region where the inversion layer 31 is formed.

The inversion layer 31 is N ⁺ layers serve charge transfer, the source or drain of the source or the drain layer of the selection transistor SGDT1 connected to the selected transistor SGST1 and select line SGD is connected to select line SGS At least the write and read operations of the memory cell transistor are performed.

  Next, generation of the inversion layer 31 will be described with reference to FIG. FIG. 4 is a diagram for explaining the generation of the inversion layer, FIG. 4 (a) is a band diagram, and FIG. 4 (b) is a diagram for explaining the gate voltage and the thickness of the inversion layer. Here, the operation of MOSFETs such as selection transistors and memory cell transistors will be described. This MOSFET is an E-type N-channel MOSFET, the semiconductor substrate is P-type, and the source and drain are 0V.

  As shown in FIG. 4A, when a gate voltage Vg is applied to the gate, a depletion layer is formed on the surface of the P-type semiconductor substrate. When the gate voltage Vg is increased and the surface potential Φs (conduction band drop) becomes equal to or higher than Φp (acceptor potential), an inversion layer is generated on the surface of the P-type semiconductor substrate. When the gate voltage Vg is raised and the surface potential Φs becomes 2 × Φp, the threshold voltage Vth is obtained. A region of Φp <Φs <2 × Φp that is equal to or lower than the threshold voltage Vth is a weak inversion region. When the gate voltage Vg is increased and the surface potential Φs becomes 2 × Φp or more, an inversion layer is generated up to the inner side of the P-type semiconductor substrate. A region of Φs> 2 × Φp is a strong inversion region.

  As shown in FIG. 4B, the gate voltage Vg is applied to the gate, and no inversion layer is generated in the region where Φs <Φp. When the gate voltage Vg is raised and Φs becomes Φp or more, an inversion layer is generated. When the gate voltage Vg is further increased, the thickness of the inversion layer increases. When the voltage exceeds a predetermined gate voltage, the depletion width becomes the maximum value, and the thickness of the inversion layer becomes a constant value and becomes saturated. Note that the maximum value of the thickness of the inversion layer depends on the concentration of the P-type semiconductor substrate, and becomes lower at a lower concentration.

  As a result shown in FIG. 4, the trench gate interval Wgp1 is set in consideration of the threshold voltage of the adjacent memory cell transistor MCT, the voltage applied to the adjacent memory cell transistor MCT, the concentration of the semiconductor substrate 1, and the like.

  In addition, as a result shown in FIG. 4, the trench gate interval Wgp2 is set in consideration of the threshold voltage of the selection transistor SGST1 and the memory cell transistor MCT1, the voltage applied to the selection transistor SGST1 and the memory cell transistor MCT1, the concentration of the semiconductor substrate 1, and the like. Is set.

  In addition, as a result shown in FIG. 4, the trench gate interval Wgp3 is set in consideration of the threshold voltage of the selection transistor SGDT1 and the memory cell transistor MCT4, the voltage applied to the selection transistor SGDT1 and the memory cell transistor MCT4, the concentration of the semiconductor substrate 1, and the like. Is set.

In the erase operation of the memory cell, since the N ⁺ layer is not introduced, a hole accumulation layer is formed in the semiconductor substrate 1 immediately below and on the side surface of the trench gate, and this hole is injected into the charge accumulation layer. The stored information in the memory cell is erased.

  Next, a method for manufacturing a semiconductor memory device will be described with reference to FIGS. 5 to 11 are cross-sectional views showing the manufacturing process of the semiconductor memory device.

As shown in FIG. 5, first, a P ⁺ layer 34 and an N ⁺ layer 5 are formed on a semiconductor substrate 1 made of P-type silicon. The P ⁺ layer 34 and the N ⁺ layer 5 are formed using, for example, a relatively high acceleration ion implantation method and high-temperature heat treatment.

After forming the P ⁺ layer 34 and the N ⁺ layer 5, a mask material 6 is deposited on the semiconductor substrate 1. A resist film (not shown) is formed using a known lithography method. Using this resist film as a mask, the mask material 6 is removed by etching to form a mask material 6 in a predetermined region. Here, the width of the mask material 6 in the region where the memory cell transistor is formed (the width in the direction from the source line SL to the bit line BL) is, for example, 1F. The pitch of the mask material 6 is 2F, for example.

  Next, as shown in FIG. 6, the upper surface and side surfaces of the mask material 6 are etched to reduce the width of the mask material 6.

  Subsequently, as shown in FIG. 7, a mask material 7 is deposited on the mask material 6 and the semiconductor substrate 1. After the mask material 7 is deposited, the mask material 7 is etched until the surface of the semiconductor substrate 1 is exposed, and the mask material 7 is formed on the upper surface and side surfaces of the mask material 6.

  Then, as shown in FIG. 8, the mask material 7 is flatly polished until the surface of the mask material 6 is exposed. The flat polishing is performed using, for example, a CMP (chemical mechanical polishing) method.

  Next, as shown in FIG. 9, the mask material 6 is selectively etched to leave only the mask material 7. As a result, the pitch of the mask material 6 is 1F.

  Subsequently, as shown in FIG. 10, a mask material 8 is formed on the mask material 7 at both ends and the semiconductor substrate 1 at both ends. After the mask material 8 is formed, the deep groove 2 is formed by vertically etching the semiconductor substrate 1 using, for example, the RIE (reactive ion etching) method using the mask materials 7 and 8 as a mask. After the deep groove 2 is formed, a post-RIE treatment is performed to remove the surface damage layer.

  Then, as shown in FIG. 11, the width and depth of the deep groove 2 are expanded by isotropic etching. As a result, a region of the semiconductor substrate 1 having plate-like trench gate intervals Wgp 1 to 3 in the vertical direction is formed between the deep grooves 2.

After the mask materials 7 and 8 are removed by etching, the gate insulating film 11 is formed in the deep groove 2 adjacent to the N ⁺ layer 5, the gate insulating film 21, the charge storage film 22, and the high dielectric are formed in the deep groove 2 where the memory cell transistor is to be formed. A rate insulating film 23 is stacked. Thereafter, the gate electrode film 12 is formed in the deep groove 2, and the trench gates 3 and 4 are embedded in the deep groove.

  Here, for example, silicon oxide films are used for the mask materials 6 and 8. For the mask material 7, for example, a SiN film (silicon nitride film) is used.

As the gate insulating film 11, a SiO ₂ film (silicon oxide film) is used. The gate insulating film 21 uses a SiO ₂ film (silicon oxide film) having a thickness in the range of 0.5 to 10 nm as a tunnel oxide film. Instead, SiN having the same thickness in terms of EOT (Equivalent Oxide Thickness) is used. Film / SiO ₂ film laminate film (SiO ₂ is the semiconductor substrate 1 side), SiO ₂ film / SiN film / SiO ₂ laminate film, SiO ₂ film / high dielectric constant insulating film / SiO ₂ film laminate film, or high A laminated film of a dielectric constant insulating film / SiO ₂ film may be used.

As the charge storage film 22, a SiN film (silicon nitride film) having a thickness in the range of 3 to 50 nm is used, but an HfAlO film may be used instead. Further, Al ₂ O ₃ film, MgO film, SrO film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, dielectric constant higher than silicon oxide film, A stacked film including a high dielectric constant insulating film such as a Y ₂ O ₃ film, a ZrSiO film, an HSiO film, or a LaAlO film may be used. In this case, the laminated film is SiN film / insulating film with high dielectric constant / SiN film, HfAlO film / insulating film with high dielectric constant / SiN film (SiN film on the gate insulating film 2 side), SiN film / insulating with high dielectric constant. Film / HfAlO film or HfAlO film / high dielectric constant insulating film / HfAlO film.

The Al ₂ O ₃ film (alumina film) having a thickness in the range of 5 to 30 nm is used for the high dielectric constant insulating film 23 as the block film, but instead, an MgO film having a dielectric constant higher than that of the silicon oxide film, SrO film, SiN film, BaO film, TiO film, Ta ₂ O ₅ film, BaTiO ₃ film, BaZrO film, ZrO ₂ film, HfO ₂ film, Y ₂ O ₃ film, ZrSiO film, HfSiO film, LaAlO film, etc. A high dielectric constant insulating film or a laminated film thereof (including a laminated film of an Al ₂ O ₃ film (alumina film)) may be used. In that case, the laminated film is SiO ₂ film / high dielectric constant insulating film / SiO ₂ film, SiO ₂ film / high dielectric constant insulating film, high dielectric constant insulating film / SiO ₂ film, or high dielectric constant insulating film / SiO _2. Film / high dielectric constant insulating film.

The gate electrode film 12 is a stacked film of a P ⁺ polycrystalline silicon film doped with a high concentration of P-type impurities and a metal silicide. Instead, a P ⁺ polycrystalline silicon film or an N-type impurity is highly concentrated. Alternatively, an N ⁺ polycrystalline silicon film doped may be used. Alternatively, a metal film / polycrystalline silicon laminated film or a metal film / metal nitride laminated film may be used. In this case, the metal silicide is CoSi, NiSi, WSi, MoSi, TiSi or the like, the metal is W or the like, the metal nitride is WN, TaN, TiN or the like, and the carbide metal is TaC or the like.

  After forming the trench gates 3 and 4, an interlayer insulating film and a wiring layer are formed using a known technique, and a semiconductor memory device 90 as a NAND flash memory having a charge trap flash (CTF) memory structure is formed. Complete.

  In this embodiment, the shape of the trench gate which is a single-layer gate is a quadrangular shape, but it is not necessarily limited to this. For example, a structure as shown in FIGS. 12A, 12B, and 13 may be used. FIG. 12A is a plan view of a trench gate having a cylindrical shape. FIG. 12B is a plan view in which a cylindrical dummy is arranged between the trench gates.

  As shown in FIG. 12A, in the semiconductor memory device 90a, the cylindrical selection transistor SGST1 is in contact with the source contact SLC, and the cylindrical selection transistor SGDT1 is in contact with the bit contact BLC. The cylindrical memory cell transistors MCT1 to MCT4 are arranged in series between the selection transistor SGST1 and the selection transistor SGDT1. An inversion layer (not shown) is formed around and between the selection transistor SGST1, the memory cell transistors MCT1 to MCT4, and the selection transistor SGDT1.

  As shown in FIG. 12B, in the semiconductor memory device 90b, the cylindrical selection transistor SGST1 is in contact with the source contact SLC, and the cylindrical selection transistor SGDT1 is in contact with the bit contact BLC. A dummy DM1, a memory cell transistor MCT1, a dummy DM2, a memory cell transistor MCT2, and a dummy DM3 are arranged in series between the selection transistor SGST1 and the selection transistor SGDT1.

  The selection transistor SGST1, the dummy DM1, the memory cell transistor MCT1, the dummy DM2, the memory cell transistor MCT2, the dummy DM3, and the periphery of and between the selection transistor SGDT1 are connected by an inversion layer (not shown). The reason why the dummy is provided between the transistors is to increase the mechanical strength.

  As shown in FIG. 13, in the semiconductor memory device 90c, the memory cell transistors MCT1 to MCT4 have a stacked gate structure. Specifically, a trench stacked gate 9 is embedded in the deep groove 2. The trench stacked gate 9 includes a floating gate (FG) composed of a floating gate insulating film and a first gate electrode film 42, and a control gate (CG) composed of a control gate insulating film 43 and a second gate electrode film 44. Consists of. Others are the same as the semiconductor memory device 90 of this embodiment.

  As described above, in the semiconductor memory device of this embodiment, the selection transistor SGST1, the memory cell transistor MCT1, the memory cell transistor MCT2, the memory cell transistor MCT3, the memory cell transistor MCT4, and the selection transistor SGDT1 having a quadrangular prism shape are separated from each other. The memory cells MC1 are arranged in series. In the selection transistor SGST1 and the selection transistor SGDT1, the trench gate 3 is embedded in the deep groove 2. In the memory cell transistors MCT 1 to MCT 4, the trench gate 4 is embedded in the deep groove 2. The word line interval Wwl1 is set to 1F which is the minimum design dimension.

For this reason, the memory cell comprised of the memory cell transistor and the selection transistor can be highly integrated. In addition, the cell size of the memory cell can be 2F ² . Therefore, the cost per bit can be reduced, and the semiconductor memory device 90 with a low manufacturing unit price can be provided.

  In the present embodiment, four memory cell transistors are connected in series, but the present invention is not necessarily limited to this. The number of memory cell transistors may be changed as appropriate.

(Second embodiment)
Next, a semiconductor memory device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 14 is a diagram illustrating a semiconductor memory device, FIG. 14A is a circuit diagram illustrating the semiconductor memory device, and FIG. 14B is a plan view illustrating the semiconductor memory device. FIG. 15 is a cross-sectional view of the semiconductor memory device taken along line BB in FIG. In the present embodiment, a substrate in which a P layer and a buried insulating film are repeatedly formed is used, and the gate of the selection transistor and the memory cell transistor constituting the memory cell is a trench gate buried in a deep groove in which the substrate is formed. On the other hand, a plurality of transistors are formed in the vertical direction.

  Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

  As shown in FIG. 14A, the semiconductor memory device 91 is provided with a plurality of memory cells including the memory cells MC1a and MC1b. The plurality of memory cells constitute a memory cell block. The semiconductor memory device 91 is a NAND flash memory having a charge trap flash (CTF) structure.

  The memory cell MC1a is provided with a selection transistor SGDT1a on the bit line BL3 side, a selection transistor SGST1a on the source line SL side, and a plurality of memory cell transistors (MCT1a to 4a) connected in series therebetween.

  In the memory cell MC1b, a selection transistor SGDT1b is provided on the bit line BL4 side, a selection transistor SGST1b is provided on the source line SL side, and a plurality of memory cell transistors (MCT1b to 4b) connected in series are provided therebetween.

  As shown in FIG. 14B, in the semiconductor memory device 91, for example, the memory cells MC1a and the memory cells MC1b are stacked in a direction perpendicular to the substrate 201, so that they overlap when viewed from the surface of the substrate 210. Illustrated. The memory cell transistors MCT1a to 4a, the memory cell transistors MCT1b to 4b, the selection transistor SGST1a, the selection transistor SGST1b, the selection transistor SGDT1a, and the selection transistor SGDT1b have a rectangular column shape as in the first embodiment, and are separated from each other. Arranged in series.

The word line interval (lateral pitch in the figure) is set to 1F which is the minimum design dimension. The pitch of the transistors arranged in the vertical direction in the figure is set to 2F. Cell size of the memory cell is set to 2F ^2.

As shown in FIG. 15, in the semiconductor memory device 91, a P ⁺ layer 34 and an N ⁺ layer are formed on a substrate 201 composed of a P layer 202a, a buried insulating film BOX1, a P layer 202b, a buried insulating film BOX2, and a P layer 202c. 5 is provided. The P ⁺ layer 34 is connected to the plate line PL, and is formed so as to penetrate the P layer 202c, the buried insulating film BOX2, the P layer 202b, and the buried insulating film BOX1 to reach the P layer 202a. The N ⁺ layer 5 is connected to the source line SL, and is formed so as to penetrate the P layer 202c, the buried insulating film BOX2, the P layer 202b, and the buried insulating film BOX1 to reach the P layer 202a.

The N ⁺ layer 5b is provided in a region of the P layer 202b between the buried insulating film BOX1 and the buried insulating film BOX2, and a region penetrating the P layer 202c and the buried insulating film BOX2, and is connected to the bit line BL4. The N ⁺ layer 5a is provided in the region of the P layer 202c and connected to the bit line BL3.

The deep groove 2 is formed so as to penetrate the P layer 202c, the buried insulating film BOX2, the P layer 202b, and the buried insulating film BOX1 and reach the P layer 202a. The deep groove 2 is formed shallower than the P ⁺ layer 34 and the N ⁺ layer 5.

A trench gate 3 is buried in the deep groove 2 in contact with the N ⁺ layer 5 connected to the source line SL. A trench gate 3 is buried in the deep groove 2 in contact with the N ⁺ layers 5a and 5b. A plurality of deep grooves 2 in which the trench gates 4 are embedded are provided between the deep grooves 2 in which the trench gates 3 are embedded. An inversion layer 31 having a conductivity type opposite to that of the P layers 202a to 202c is formed in the region of the substrate 1 between the deep groove 2 and the deep groove 2 and in the bottom of the deep groove 2 in the memory cell write operation and read operation.

  Here, the region where the P layer 202c and the trench gate 3 are in contact with each other becomes the selection transistor SGST1a and the selection transistor SGDT1a. Regions where the P layer 202c and the trench gate 4 are in contact are the memory cell transistors MCT1a to 4a. The region where the P layer 202b and the trench gate 3 are in contact with each other becomes the selection transistor SGST1b and the selection transistor SGDT1b. Regions where the P layer 202b and the trench gate 4 are in contact are the memory cell transistors MCT1b to 4b.

  Since the semiconductor memory device 91 has two transistors in the direction perpendicular to the substrate 201, the degree of integration can be doubled compared to the semiconductor memory device 90 of the first embodiment.

  In this embodiment mode, the transistor is two-stage offensive in a direction perpendicular to the substrate 201, but the present invention is not limited to this. For example, as shown in FIG. 16, a four-stage transistor may be configured in a direction perpendicular to the substrate. FIG. 16 is a cross-sectional view showing a semiconductor memory device.

As shown in FIG. 16, in the semiconductor memory device 91a, a P layer 202a, a buried insulating film BOX1, a P layer 202b, a buried insulating film BOX2, a P layer 202c, a buried insulating film BOX3, a P layer 202d, a buried insulating film BOX4, and The P ⁺ layer 34 and the N ⁺ layer 5 are provided on the substrate 201a formed of the P layer 202e.

The P ⁺ layer 34 is connected to the plate line PL and penetrates the P layer 202e, the buried insulating film BOX4, the P layer 202d, the buried insulating film BOX3, the P layer 202c, the buried insulating film BOX2, the P layer 202b, and the buried insulating film BOX1. Thus, the P layer 202a is formed.

The N ⁺ layer 5 is connected to the source line SL and penetrates the P layer 202e, the buried insulating film BOX4, the P layer 202d, the buried insulating film BOX3, the P layer 202c, the buried insulating film BOX2, the P layer 202b, and the buried insulating film BOX1. Thus, the P layer 202a is formed.

The N ⁺ layer 5d includes a region of the P layer 202b between the buried insulating film BOX1 and the buried insulating film BOX2, a P layer 202e, a buried insulating film BOX4, a P layer 202d, a buried insulating film BOX3, a P layer 202c, and a buried insulating film. It is provided in a region penetrating the film BOX2 and connected to the bit line BL4.

The N ⁺ layer 5c is provided in a region of the P layer 202c between the buried insulating film BOX2 and the buried insulating film BOX3, and a region penetrating the P layer 202e, the buried insulating film BOX4, the P layer 202d, and the buried insulating film BOX3. Are connected to the bit line BL3.

The N ⁺ layer 5b is provided in a region of the P layer 202d between the buried insulating film BOX3 and the buried insulating film BOX4, and a region penetrating the P layer 202e and the buried insulating film BOX4, and is connected to the bit line BL2. The N ⁺ layer 5a is provided in the region of the P layer 202e and is connected to the bit line BL1.

The deep groove 2 penetrates the P layer 202e, the buried insulating film BOX4, the P layer 202d, the buried insulating film BOX3, the P layer 202c, the buried insulating film BOX2, the P layer 202b, and the buried insulating film BOX1, and reaches the P layer 202a. It is formed. The deep groove 2 is formed shallower than the P ⁺ layer 34 and the N ⁺ layer 5.

A trench gate 3 is buried in the deep groove 2 in contact with the N ⁺ layer 5 connected to the source line SL. A trench gate 3 is buried in the deep groove 2 in contact with the N ⁺ layers 5a to 5d. A plurality of deep grooves 2 in which the trench gates 4 are embedded are provided between the deep grooves 2 in which the trench gates 3 are embedded. In the region of the substrate 1 between the deep groove 2 and the deep groove 2, an inversion layer 31 in which the P layer 202 e, the P layer 202 d, the P layer 202 c, and the P layer 202 b are inverted to a reverse conductivity type during a memory cell write operation and read operation. Is formed.

  Since the semiconductor memory device 91a has four transistors in the direction perpendicular to the substrate 201a, the degree of integration can be quadrupled compared to the semiconductor memory device 90 of the first embodiment.

  As described above, in the semiconductor memory device of this embodiment, the memory cells MC1a and the memory cells MC1b are stacked in the direction perpendicular to the substrate 201. The word line interval is set to 1F which is the minimum design dimension.

Therefore, the memory cell composed of the memory cell transistor and the selection transistor can be twice as highly integrated as in the first embodiment. In addition, the cell size of the memory cell can be 2F ² . Therefore, the cost per bit can be reduced and the semiconductor memory device 91 with a low manufacturing unit price can be provided.

  In this embodiment, the deep groove 2 is formed in a direction perpendicular to the substrate 201, but the deep groove and the substrate may be formed by rotating in an oblique direction. In this case, the bit line BL can be easily taken out. In addition, it is preferable to use an oblique anisotropic etching technique for the oblique deep grooves.

(Third embodiment)
Next, a semiconductor memory device according to a third embodiment of the present invention will be described with reference to the drawings.

  17 is a diagram illustrating a semiconductor memory device, FIG. 17A is a circuit diagram illustrating the semiconductor memory device, and FIG. 17B is a plan view illustrating the semiconductor memory device. FIG. 18 is an enlarged plan view showing the semiconductor memory device. In this embodiment, an insulating film embedded in the isolation trench is provided on the semiconductor substrate, and the selection transistor and the gate of the memory cell transistor constituting the memory cell are trench gates embedded in the deep trench formed across the isolation trench. Two transistors are formed at both ends of the trench gate separated by the isolation trench.

  Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, description thereof will be omitted, and only different portions will be described.

  As shown in FIG. 17A, the semiconductor memory device 92 is provided with a plurality of memory cells including the memory cells MC11 and MC12. The plurality of memory cells constitute a memory cell block. The semiconductor memory device 92 is a NAND flash memory having a charge trap flash (CTF) structure.

  The memory cell MC11 is provided with a selection transistor SGDT1a on the bit line BL3 side, a selection transistor SGST1a on the source line SL side, and a plurality of memory cell transistors (MCT1a to 4a) connected in series therebetween.

  The memory cell MC12 is provided with a selection transistor SGDT1b on the bit line BL4 side, a selection transistor SGST1b on the source line SL side, and a plurality of memory cell transistors (MCT1b to 4b) connected in series therebetween.

  As shown in FIG. 17B, in the semiconductor memory device 92, the memory cells are connected in series in the horizontal direction in the figure, and for example, the transistors constituting the memory cell MC11 and the memory cell MC12 share the gate.

  Specifically, the selection transistor SGST1a and the selection transistor SGST1b share the same trench gate 3a, and the selection transistor SGDT1a and the selection transistor SGDT1b share the same trench gate 3a. Memory cell transistor MCT1a and memory cell transistor MCT1b, memory cell transistor MCT2a and memory cell transistor MCT2b, memory cell transistor MCT3a and memory cell transistor MCT3b, and memory cell transistor MCT4a and memory cell transistor MCT4b share the same trench gate 4a. Yes. The trench gate 3a and the trench gate 4a have a quadrangular prism shape.

  As shown in FIG. 18, the deep groove 2a has a quadrangular prism shape, and the semiconductor substrate is disposed so as to straddle the insulating film 52 (isolating groove insulating film) embedded in the isolating groove 51 having a long horizontal direction in the figure and having the quadrangular prism shape. 1 is provided. The deep groove 2a is formed shallower than the insulating film 52 (isolation groove insulating film).

  A trench gate 3a is buried in the deep groove 2a in contact with the source line contact SLC. A trench gate 3a is buried in the deep groove 2a in contact with the bit line contact BLC. The trench gate 3a has the same structure as the trench gate 3 of the first embodiment. Trench gates 4a are embedded in the plurality of deep grooves 2a between the deep groove 2a in contact with the source line contact SLC and the deep groove 2a in contact with the bit line contact BLC. The trench gate 4a has the same structure as the trench gate 4 of the first embodiment.

  The selection transistor SGST1a and the selection transistor SGST1b are separated by an insulating film 52 (isolation groove insulating film). A region where the semiconductor substrate 1 is in contact with one end (upper end in the drawing) of the trench gate 3a divided by the insulating film 52 (isolation groove insulating film) is the select transistor SGST1a. A region where the semiconductor substrate 1 is in contact with the other end (lower end in the figure) of the trench gate 3a divided by the insulating film 52 (isolation trench insulating film) is the select transistor SGST1b.

  The selection transistor SGDT1a and the selection transistor SGDT1b are separated by an insulating film 52 (isolation groove insulating film). A region where the semiconductor substrate 1 is in contact with one end (upper end in the figure) of the trench gate 3a divided by the insulating film 52 (isolation groove insulating film) is the selection transistor SGDT1a. A region where the semiconductor substrate 1 is in contact with the other end (lower end in the figure) of the trench gate 3a divided by the insulating film 52 (isolation groove insulating film) is the select transistor SGDT1b.

  The memory cell transistor MCT1a and the memory cell transistor MCT1b, the memory cell transistor MCT2a and the memory cell transistor MCT2b, the memory cell transistor MCT3a and the memory cell transistor MCT3b, the memory cell transistor MCT4a and the memory cell transistor MCT4b, respectively, have an insulating film 52 (isolation groove insulating film). ).

  A region where the semiconductor substrate 1 is in contact with one end (upper end in the figure) of the trench gate 4a divided by the insulating film 52 (isolation groove insulating film) is the memory cell transistor MCT1a, the memory cell transistor MCT2a, the memory cell transistor MCT3a, and the memory cell transistor. It becomes MCT4a. A region where the semiconductor substrate 1 is in contact with the other end (lower end in the figure) of the trench gate 4a divided by the insulating film 52 (isolation groove insulating film) is a memory cell transistor MCT1b, a memory cell transistor MCT2b, a memory cell transistor MCT3b, a memory cell transistor. It becomes MCT4b.

  Memory cell transistors MCT1a to 4a and memory cell transistors MCT1b to 4b are arranged at a pitch of word line interval Wwl1. The memory cell transistors MCT1a to 4a and the memory cell transistors MCT1b to 4b are spaced apart from each other by a trench gate interval Wgp1, and are inverted in a conductivity type (N type) opposite to that of the semiconductor substrate 1 during the write operation and read operation of the memory cell. Layer 31 is formed.

  The selection transistor SGST1a and the memory cell transistor MCT1a, the selection transistor SGST1b and the memory cell transistor MCT1b are spaced apart by a trench gate interval Wgp2, and have a conductivity type opposite to that of the semiconductor substrate 1 (N-type) during a write operation and a read operation of the memory cell. ) Inversion layer 31 is formed.

  The selection transistor SGDT1a and the memory cell transistor MCT4a, and the selection transistor SGDT1b and the memory cell transistor MCT4b are spaced apart by a trench gate interval Wgp3, and have a conductivity type opposite to that of the semiconductor substrate 1 (N-type) during a write operation and a read operation of the memory cell. ) Inversion layer 31 is formed.

  During the write operation and read operation of the memory cell, the inversion layer 31 is formed in each of the selection transistor SGST1a, the memory cell transistors MCT1a to 4a, and the selection transistor SGDT1a. In the memory cell read operation, the memory information of the memory cell transistor flows from the source line SL in the bit line BL direction (information is read from the bit line BL3).

  During the write operation and the read operation of the memory cell, the inversion layer 31 is formed in each of the selection transistor SGST1b, the memory cell transistors MCT1b to 4b, and the selection transistor SGDT1b. In the memory cell read operation, the memory information of the memory cell transistor flows from the source line SL in the direction of the bit line BL (information is read from the bit line BL4).

  Next, the operation of the semiconductor memory device will be described with reference to FIGS. FIG. 19 illustrates a write operation of the semiconductor memory device.

  As shown in FIG. 19, when a write operation is performed on the selected memory cell transistor (MCT2a) selected by the word line WL2 and the bit line BL3 of the memory cell block, “0 (zero)” is applied to the selected memory cell transistor (MCT2a). Is written, the corresponding bit line BL is set to “0V”, and when “1” is written to the selection transistor, the corresponding bit line BL is set to the boosted high potential side power supply voltage Vdd. The source line SL is set to 0V. The plate line PL is set to 0V. The selection line SGD is set to the control voltage Vsg1 that is the (+) voltage, and the control voltage Vsg2 that is the (+) voltage is applied to the selection line SGS to turn on the selection transistors (SGST1a, SGDT1a). The selected word line WL2 is set to the write voltage Vpgm, and the non-selected word line WL is set to the intermediate voltage Vm.

Here, the write voltage Vpgm is set to 20 V, for example, and the intermediate voltage Vm is set to 6 V, for example. Therefore, an inversion layer is formed on the semiconductor substrate 1 around and between the memory cell transistors and around and between the memory cell transistors and the selection transistor, and the memory cell transistor can perform a write operation without an N ⁺ layer serving as a source or drain. It becomes possible.

  FIG. 20 is a diagram for explaining the read operation of the semiconductor memory device. As shown in FIG. 20, when the read operation of the selected memory cell transistor (MCT2a) selected by the word line WL2 and the bit line BL3 of the memory cell block is performed, the corresponding bit line BL is set to the (+) voltage precharge voltage. Vbl and the source line SL are set to 0V. The plate line PL is set to 0V. The selection line SGD is set to the control voltage Vsg1 that is the (+) voltage, and the control voltage Vsg2 that is the (+) voltage is applied to the selection line SGS to turn on the selection transistors (SGST1a, SGDT1a). The selected word line WL2 is set to 0V, and the non-selected word line WL is set to the pass voltage Vread.

Here, the pass voltage Vread is set to 5.5 V, for example. Therefore, an inversion layer is formed in the semiconductor substrate 1 around and between the trench gates of the memory cell transistor and around and between the memory cell transistor and the selection transistor, and the memory cell transistor can be formed without an N ⁺ layer serving as a source or a drain. A read operation is possible.

  FIG. 21 is a diagram for explaining the batch erase operation of the semiconductor memory device. As shown in FIG. 21, when performing the batch erase operation of the memory cell block, for example, the corresponding bit line BL, selection line SGD, source line SL, and selection line SGS are floated, and the plate line PL (semiconductor substrate 1) is set. The erase voltage is set to Vera, and the word line WL is set to 0V. When the plate line PL is formed in the P well layer, the erase voltage Vera is applied to the P well layer.

  Here, the erase voltage Vera is set to 20 V, for example. For this reason, the information stored in the memory cell transistors of the memory cell block is erased collectively. Although the selection line SGD and the selection line SGS are in a floating state, they may be set to the erase voltage Vera.

  As described above, in the semiconductor memory device of this embodiment, the deep groove 2 a is formed in the semiconductor substrate 1 so as to straddle the insulating film 52 embedded in the isolation groove 51. Transistors constituting the memory cell MC11 and the memory cell MC12 share a trench gate embedded in the deep groove 2a.

  For this reason, the memory cell composed of the memory cell transistor and the selection transistor can be more highly integrated than in the first embodiment. Therefore, the cost per bit can be reduced, and the semiconductor memory device 92 with a low manufacturing unit price can be provided.

  In the present embodiment, the deep groove 2a is formed in the semiconductor substrate 1 so as to straddle the insulating film 52 embedded in the isolation groove 51. However, instead of the semiconductor substrate 1, the semiconductor substrate 1 includes a semiconductor layer and a buried insulating film. A substrate may be used.

(Fourth embodiment)
Next, a decoder of the semiconductor memory device according to the fourth embodiment of the present invention will be described with reference to the drawings. 22 is a diagram showing the column decoder, FIG. 22A is a circuit diagram showing the column decoder, and FIG. 22B is an enlarged plan view showing the column decoder. In this embodiment, a trench gate embedded in a deep groove is formed in a P layer separated by an N well around the periphery, and a column decoder including a column control transistor and a column selection transistor is formed. Provided.

  As shown in FIG. 22A, the column decoder 100 functions as a select circuit that receives, for example, bit line information of a memory cell of a semiconductor memory device and selects a necessary bit line during a write operation or a read operation. To do.

  In the column decoder 100, m decoder units 110 are arranged in parallel in the horizontal direction in the figure between the bit line and the decode line DCL. The decoder unit 110 includes a column selection transistor SCDDT connected in series, n column control transistors (CST1, CST2, CST3,..., CSTn), and a column selection transistor SCDST. The decoder unit 110 is provided with a column plate line CPL.

  The column selection transistor SCDDT has a gate connected to the column selection line SCDD. Column select transistor SCDST has a gate connected to column select line SCDS. The column control transistor CST1 has a gate connected to the column control line CS1. The column control transistor CST2 has a gate connected to the column control line CS2. The column control transistor CST3 has a gate connected to the column control line CS3. The column control transistor CSTn has a gate connected to the column control line CSn.

  The column decoder 100 can be more highly integrated than the column decoders used so far in semiconductor memory devices. Details will be described later.

As shown in FIG. 22 (b), the decoder unit 110 is provided with a P layer 61, the periphery of which is separated by an N well layer 60. The P layer 61 has a P ⁺ layer connected to the column plate line CPLm. Provided. The column selection transistor SCDDT, the n column control transistors (CST1, CST2, CST3,..., CSTn) and the column selection transistor SCDST that are connected in series are connected to the P layer 61 separated by the N-well layer 60. Provided. The column selection transistor SCDDT, the n column control transistors (CST1, CST2, CST3,..., CSTn), and the column selection transistor SCDST have the same arrangement and structure as the memory cell of the first embodiment.

The column selection transistor SCDDT is connected to a bit line and is in contact with an N ⁺ layer to which bit line information is input. The column selection transistor SCDDT has a quadrangular prism-shaped trench gate and has the same structure as the selection transistor SGDT1 of the first embodiment.

Column select transistor SCDST is connected to decode line DCLm and is in contact with the N ⁺ layer. The column selection transistor SCDST has a quadrangular prism-shaped trench gate and has the same structure as the selection transistor SGST1 of the first embodiment.

  The n column control transistors (CST1, CST2, CST3,..., CSTn) provided in the column selection transistor SCDDT and the column selection transistor SCDST each have a quadrangular prism-shaped trench gate. It has the same structure as the memory cell transistor. Here, the n column control transistors (CST1, CST2, CST3,..., CSTn) have a threshold of 1 bit (two), but may have a threshold of 2 bits or more.

  Next, the operation of the column decoder will be described with reference to FIGS. FIG. 23 is a diagram for explaining the erase operation of the column decoder.

  As shown in FIG. 23, in the erase operation of the column decoder 100, the column select line SCDD, the decode line DCL, and the column plate line CPL on the bit line side are set to 0V, the column control line CS is set to the erase voltage Vbac, and the column select line SCDS is set to the control voltage Vsc1. For example, the erase voltage Vbac is set to 20V, the control voltage Vsc1 is set to 11V, and a threshold value between 4V and 5V is written to n column control transistors (CST1, CST2, CST3,..., CSTn). As a result, back batch erasure is performed.

  FIG. 24 is a diagram for explaining the write operation of the column decoder. As shown in FIG. 24, when a write operation is performed on the column control transistor CST1b selected by the column control line CS1, the decode line DCL2, and the column plate line CPL2, the column select lines SCDD and SCDS are set to the control voltage Vsc1, and the decode line DCL is set. To float. The selected column control line CS1 is set to 0V, the non-selected column control line CS is set to the write voltage Vreadcs, and the selected column plate line CPL2 is set to the write voltage Vwr. For example, the write voltage Vwr is set to 20V, the write voltage Vreadcs is set to 9V, and the control voltage Vsc1 is set to 11V, and a threshold value lower than 0V is written to the selected column control transistor CST1b. As a result, back writing is performed.

  FIG. 25 is a diagram for explaining the operation of the column decoder. FIG. 25 shows the column decoding operation in a state where the write operation is performed as shown in FIG.

  As shown in FIG. 25, when the selected decode line DCL2 is activated, the column select lines SCDD and SCDS are set to the control voltage Vsc2, and the column plate line CPL is set to 0V. The selected column control line CS1 is set to 0V, and the non-selected column control line CS is set to the control voltage Vac. For example, the control voltage Vsc2 and the control voltage Vac are set to 5V. With this setting, the column control transistor CST1b connected to the column control line CS1 is turned on and the other column control transistors CST1 are turned off, so that the selected decode line DCL2 becomes active and the unselected decode line DCL becomes non-active. It becomes.

  As described above, the decoder of this embodiment includes the column selection transistor SCDDT, n column control transistors (CST1, CST2, CST3,..., CSTn) connected in series, and the column selection transistor SCDST. A decoder unit 110 is provided. The decoder unit 110 is provided with a column plate line CPL. The column selection transistor SCDDT, the n column control transistors (CST1, CST2, CST3,..., CSTn), and the column selection transistor SCDST have the same arrangement and shape as the memory cell of the first embodiment.

  For this reason, since it can respond by one time data writing at the shipping stage, the degree of freedom in design can be improved. Further, the degree of integration can be increased as compared with the conventional case. Therefore, it is possible to provide the column decoder 100 with a low manufacturing unit price.

  In this embodiment, the column decoder 100 is applied to a semiconductor memory device, but is not necessarily limited to this. The present invention can also be applied to a decoder used for a semiconductor integrated circuit, a semiconductor total circuit module, or the like.

(Fifth embodiment)
Next, a decoder of the semiconductor memory device according to the fifth embodiment of the present invention will be described with reference to the drawings. FIG. 26 shows a column decoder. In this embodiment, a trench gate embedded in a deep groove is formed as in the third embodiment, and a column decoder including a column control transistor and a column selection transistor is provided.

  As shown in FIG. 26, the column decoder 101 receives, for example, bit line information of a memory cell of a semiconductor memory device, and functions as a select circuit that selects a necessary bit line during a write operation or a read operation.

  The column decoder 101 includes a decoder unit 110a between the bit line and the decode line DCL, and a decoder unit 110b that shares the column plate line CPL with the decoder unit 110a and is arranged adjacent to the decoder unit 110a in the horizontal direction in the figure. m are arranged in parallel.

  The decoder unit 110a includes a column select transistor SCDDTa connected in series, n column control transistors (CST1a, CST2a, CST3a,..., CSTna), and a column select transistor SCDSTa. The column selection transistor SCDDTa has a gate connected to the column selection line SCDD1. Column select transistor SCDSTa has a gate connected to column select line SCDS1.

  The decoder unit 110b includes a column selection transistor SCDDTb connected in series, n column control transistors (CST1b, CST2b, CST3b,..., CSTnb), and a column selection transistor SCDSTb. The column selection transistor SCDDTb has a gate connected to the column selection line SCDD2. Column select transistor SCDSTb has a gate connected to column select line SCDS2.

  Next, a column decoder in which the number of transistors is minimized with respect to the number of decode lines will be described with reference to FIGS. Here, there are four decode lines DCL, and two column control transistors are provided for each decode line DCL.

  FIG. 27 is a diagram illustrating a multi-value column control transistor. FIG. 28 is a diagram for explaining the operation of the column decoder.

  As shown in FIG. 27, the column control transistor has a threshold of 2 bits (4). Specifically, the threshold Vth “11” lower than 0V, the threshold Vth “10” higher than 0V, the threshold Vth “01” higher than the threshold Vth “10”, and the threshold Vth “higher than the threshold Vth“ 01 ”. 00 ”. The threshold Vth “11”, the threshold Vth “10”, the threshold Vth “01”, and the threshold Vth “00” are distributed apart from each other and do not overlap.

  As shown in FIG. 28, data is written to the multi-value column control transistor by the same method as the column decoder write (FIG. 24) in the fourth embodiment.

  For example, the column control transistor CST11a has a threshold value Vth “10”, the column control transistor CST21a has a threshold value Vth “01”, the column control transistor CST11b has a threshold value Vth “10”, the column control transistor CST21b has a threshold value Vth “01”, and the column control transistor CST12a , Threshold value Vth “00” is written in the column control transistor CST22a, threshold value Vth “00” is written in the column control transistor CST12b, and threshold value Vth “11” is written in the column control transistor CST22b.

  In the operation of the column decoder (decoding line DCL selection operation), when selecting the decoding line DCL1, the column selection lines SCDD1 and SCDS1 are set to the control voltage Vsc2, and the column selection lines SCDD2 and SCDS2 are set to 0V. The column control lines CS1 and CS2 are set to the control voltage Vcs01.

  With this setting, the column selection transistor SCDDT1a, the column control transistor CST11a, the column control transistor CST21a, and the column selection transistor SCDST1a are turned on and the decode line DCL1 is activated.

  When selecting the decode line DCL2, the column selection lines SCDD1 and SCDS1 are set to 0V, and the column selection lines SCDD2 and SCDS2 are set to the control voltage Vsc2. The column control lines CS1 and CS2 are set to the control voltage Vcs01.

  With this setting, the column selection transistor SCDDT1b, the column control transistor CST11b, the column control transistor CST21b, and the column selection transistor SCDST1b are turned on and the decode line DCL2 is activated.

  When selecting the decode line DCL3, the column selection lines SCDD1 and SCDS1 are set to 0V, and the column selection lines SCDD2 and SCDS2 are set to the control voltage Vsc2. The column control line CS1 is set to the control voltage Vcs00, and the column control line CS2 is set to the control voltage Vcs11.

  With this setting, the column selection transistor SCDDT2a, the column control transistor CST12a, the column control transistor CST22a, and the column selection transistor SCDST2a are turned on and the decode line DCL3 is activated.

  When selecting the decode line DCL4, the column selection lines SCDD1 and SCDS1 are set to the control voltage Vsc2, and the column selection lines SCDD2 and SCDS2 are set to 0V. The column control line CS1 is set to the control voltage Vcs00, and the column control line CS2 is set to the control voltage Vcs11.

  With this setting, the column selection transistor SCDDT2b, the column control transistor CST12b, the column control transistor CST22b, and the column selection transistor SCDST2b are turned on and the decode line DCL4 is activated.

The column control transistor having a threshold of 2 bits (4), for example, four the number of column control lines CS, i.e. connected in series as a column control number four to the sixteen transistors of (2 ⁴⁾ Any one of the decode lines DCL can be activated.

  As described above, in the decoder of this embodiment, the decoder unit 110a and the decoder unit 110b are arranged adjacent to each other and share the column plate line CPL. The transistors constituting the decoder unit 110a and the decoder unit 110b have the same arrangement and shape as the memory cell of the first embodiment.

  For this reason, since it can respond by one time data writing at the shipping stage, the degree of freedom in design can be improved. Further, the degree of integration can be increased as compared with the fourth embodiment. Therefore, it is possible to provide the column decoder 101 with a low manufacturing unit price.

  In this embodiment, the column decoder 101 is applied to a semiconductor memory device, but is not necessarily limited to this. The present invention can also be applied to a decoder used for a semiconductor integrated circuit, a semiconductor total circuit module, or the like.

(Sixth embodiment)
Next, a semiconductor memory device according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 29 is a circuit diagram showing a semiconductor memory device. FIG. 30 is a cross-sectional view showing a semiconductor memory device. In the present embodiment, a trench gate embedded in a deep groove is formed, a memory cell block composed of a select transistor and a memory cell transistor, and a trench gate embedded in a deep groove in a P layer separated by an N well around the periphery. And a column decoder composed of a column control transistor and a column selection transistor is formed on the same substrate.

  As shown in FIG. 29, the semiconductor memory device 93 is provided with a memory cell block MCB1 and a column decoder 100. The semiconductor memory device 93 is a NAND flash memory having a charge trap flash (CTF) structure.

  In the memory cell block MCB1, a plurality of memory cells provided between the source line SL and the bit line BL are arranged in parallel. This memory cell has n memory cell transistors connected in series, and has the same arrangement and structure as the first embodiment. The memory cell block MCB1 is provided with n word lines.

  The column decoder 100 is arranged adjacent to the memory cell block MCB1, and is provided with k column control lines CS smaller than the number of word lines WL of the memory cell block MCB1. Bit line information of the bit line BL1 is transmitted to the decode line DCL1. Bit line information of the bit line BL2 is transmitted to the decode line DCL2. Bit line information of the bit line BL3 is transmitted to the decode line DCL3. Bit line information of the bit line BLm is transmitted to the decode line DCLm.

  As shown in FIG. 30, in the semiconductor memory device 93, the memory cell block MCB <b> 1 is provided on the P-type semiconductor substrate 1. An N well 200 is provided in a P-type semiconductor substrate 1. A P well 203 is provided in the N well 200. The decoder block 110 constituting the column decoder 100 is provided in a P well 203 separated from the P type semiconductor substrate 1 by an N well 200.

  As described above, in the semiconductor memory device of this embodiment, the memory cell block MCB1 and the column decoder 100 disposed adjacent to the memory cell block MCB1 are provided. Transistors constituting the memory cell and the column decoder 100 have trench gates and have the same arrangement and structure. The decoder block 110 is separated from the semiconductor substrate 1 by an N well 200.

  For this reason, the memory cell comprised of the memory cell transistor and the selection transistor can be highly integrated. In addition, since the data can be handled once in the shipment stage, the degree of freedom in designing the column decoder 100 can be improved. Further, the degree of integration of the column decoder 100 can be increased as compared with the conventional case. Therefore, the cost per bit can be reduced, the cost of the peripheral circuit of the memory cell can be reduced, and the semiconductor memory device 93 with a low manufacturing unit price can be provided.

(Seventh embodiment)
Next, a semiconductor memory device according to a seventh embodiment of the present invention will be described with reference to the drawings. FIG. 31 is a circuit diagram showing a semiconductor memory device. FIG. 32 is an enlarged plan view showing the semiconductor memory device. 33 is a cross-sectional view taken along the line CC of FIG. 34 is a cross-sectional view taken along the line DD of FIG. In the present embodiment, a trench gate embedded in a deep groove straddling the insulating film embedded in the isolation trench is formed, and a memory cell block including a selection transistor and a memory cell transistor and an insulating film embedded in the isolation trench are provided. A trench gate embedded in a straddling deep groove is formed, and a column decoder including a column control transistor and a column selection transistor is formed on the same substrate.

  As shown in FIG. 31, the semiconductor memory device 94 is provided with a memory cell block MCB2 and a column decoder 101. The semiconductor memory device 94 is a NAND flash memory having a charge trap flash (CTF) structure.

  The memory cell block MCB2 is provided between the source line SL and the bit line BL, and includes the first memory cell connected to the selection line SGS1, the word lines WL1 to WLn, and the selection line SGD1, the source line SL, and the bit line BL. A plurality of selection memory lines SGS2, word lines WL1 to WLn, and second memory cells connected to the selection line SGD2 are alternately arranged in parallel.

  The column decoder 101 is disposed adjacent to the memory cell block MCB2, and is provided with k column control lines CS smaller than the number of word lines WL of the memory cell block MCB2.

  Bit line information of the bit line BL1 is transmitted to the decode line DCL1. Bit line information of the bit line BL2 is transmitted to the decode line DCL2. Bit line information of the bit line BL3 is transmitted to the decode line DCL3. Bit line information of the bit line BL4 is transmitted to the decode line DCL4. Bit line information of the bit line BLm-1 is transmitted to the decode line DCLm-1. Bit line information of the bit line BLm is transmitted to the decode line DCLm.

  As shown in FIG. 32, the memory cells constituting the memory cell block MCB2 are provided on the semiconductor substrate 1, and the select transistor SGST, the memory cell transistor MCT, and the trench gates of the select transistor SGDT are provided as in the third embodiment. It is divided by an insulating film 52 (separation groove insulating film) embedded in the separation groove 51. Memory cells are respectively provided at one end (upper side in the figure) and the other end (lower side in the figure) of the trench gate divided by the insulating film 52 (isolation groove insulating film). As shown in FIG. 34, the insulating film 52 (isolation groove insulating film) is deeper than the trench gate.

  The selection line SGS1 and the selection line SGD1 are connected to the upper selection transistor in the drawing, and the selection line SGS2 and the selection line SGD2 are connected to the upper selection transistor in the drawing.

  A decoder unit constituting the column decoder 101 is provided in a P well 203 separated from the semiconductor substrate 1 by an N well 200. Similar to the third embodiment, the column selection transistor SCDDT, the column control transistor, and the column selection transistor SCDST have their trench gates separated by an insulating film 52 (isolation groove insulating film) embedded in the isolation groove 51. Decoder units are respectively provided at one end (upper side in the figure) and the other end (lower side in the figure) of the trench gate divided by the insulating film 52 (isolation groove insulating film). 33, the N well 200 is deeper than the P well 203 and the insulating film 52 (isolation groove insulating film), and the P well 203 is deeper than the insulating film 52 (isolation groove insulating film).

  As described above, in the semiconductor memory device of this embodiment, the memory cell block MCB2 and the column decoder 101 arranged adjacent to the memory cell block MCB2 are provided. Transistors constituting the memory cell and the column decoder 101 have trench gates and have a similar arrangement and structure. The decoder block is separated from the semiconductor substrate 1 by an N well 200.

  For this reason, the memory cell comprised of the memory cell transistor and the selection transistor can be highly integrated. In addition, since data can be written once in the shipping stage, the degree of freedom in designing the column decoder 101 can be improved. Further, the degree of integration of the column decoder 101 can be increased as compared with the conventional case. Therefore, the cost per bit can be reduced, the cost of the peripheral circuit of the memory cell can be reduced, and the semiconductor memory device 94 with a low manufacturing unit price can be provided.

  The present invention is not limited to the above embodiment, and various modifications may be made without departing from the spirit of the invention.

  In the embodiment, the present invention is applied to a NAND flash memory having a CTF structure, but can also be applied to an AND flash memory having a CTF structure or a stacked gate structure, a NOR flash memory having a CTF structure or a stacked gate structure, and the like.

  Although several embodiments have been described above, these embodiments are merely shown as examples and are not intended to limit the scope of the present invention. In fact, the novel semiconductor memory device and decoder described herein may be embodied in various other forms, and further, without departing from the spirit or spirit of the present invention. Various omissions, substitutions and changes in the form of the decoder may be made. The appended claims and their equivalents are intended to include such forms or modifications as would fall within the scope and spirit or spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2, 2a Deep groove 3, 3a, 4, 4a Trench gate 5, 5a-dN ⁺ layer 6-8 Mask material 9 Trench laminated gates 11, 21 Gate insulating film 12 Gate electrode film 22 Charge storage film 23 High dielectric Rate insulating film 34 P ⁺ layer 41 Floating gate insulating film 42 First gate electrode film 43 Control gate insulating film 44 Second gate electrode film 51 Separation groove 52 Insulating film 60, 200 N well 61, 202a to e P layer 203 P well 90, 90a-c, 91, 91a, 92, 93, 94 Semiconductor memory device 100, 101 Column decoder 110, 110a, 110b Decoder unit 201 Substrate BL1-4 Bit line BLC Bit line contact BOX1-4 Buried insulating film CPL1 , CPL2, CPL3, CPLm Column plate lines CS1, CS2, S3, CSn Column control lines CST1, CST2, CST3, CSTn, CST1a, CST2a, CST3a, CSTna, CST1b, CST2b, CST3b, CSTnb, CST11a, CST11b, CST12a, CST12b, CST21a, CST21c, CST21b, CST21b, CST21b 4, DCLm-1, DCLm decode line DM1-3 dummy MC1, MC1a, MC1b, MC11, MC12 memory cell MCB1, MCB2 memory cell block MCT1-5, MCT1a-4a, MCT1b-4b memory cell transistor PL plate line PLC plate line Contacts SCDD, SCDS, SCDD1, SCDS1, SCDD2, SCDS2 Column selection lines SCDDT, SCDST, CDDTa, SCDSTa, SCDDTb, SCDSTb, SCDDT1a, SCDDT1b, SCDDT2a, SCDDT2b, SCDST1a, SCDST1b, SCDST2a, SCDST2b Column selection transistor SGD, SGS Selection line SGDT1, SGST1 SGST1, SGDT1SGST Contact Vbl Precharge voltage Vdd High side power supply voltage Vbac, Vera Erase voltage Vm Intermediate voltage Vprgm, Vreadcs, Vwr Write voltage Vread Pass voltage Vac, Vcs00, Vcs01, Vcs10, Vcs11, Vsc1, Vsc2, Vsg1, Vsg2 Control voltage Wgg1 3 Trench gate interval WL1-4 Word line Wwl1 Word line spacing

Claims (7)

A semiconductor substrate;
A plurality of memory cells having a plurality of memory cell transistors arranged in series with trench gates embedded in a plurality of deep grooves provided in the semiconductor substrate;
And an inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed around the trench gate during the write operation and the read operation of the memory cell, and the plurality of memory cell transistors are connected in series by the inversion layer. A semiconductor memory device. A semiconductor substrate;
A first select transistor in which a first trench gate is embedded in a first deep groove provided in the semiconductor substrate;
A second select transistor embedded in a second trench formed in the semiconductor substrate and spaced apart from the first select transistor;
A plurality of memory cell transistors provided between the first and second select transistors, a third trench gate embedded in a plurality of third deep grooves provided in the semiconductor substrate, and a plurality of memory cell transistors arranged in series;
A plurality of memory cells including the first selection transistor, the second selection transistor, and the plurality of memory cell transistors;
And an inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed around the first to third trench gates during the write operation and the read operation of the memory cell. A semiconductor memory device, wherein a selection transistor, the plurality of memory cell transistors, and the second selection transistor are connected in series. First conductive type first semiconductor layer, first buried insulating film, first conductive type second semiconductor layer, second buried insulating film, and first conductive type third semiconductor layer are stacked. A substrate to be
A first trench gate embedded in a first deep groove provided in the substrate so as to reach at least a first buried insulating film and connected to a first selection line;
A second trench gate embedded in a second deep groove provided in the substrate so as to reach at least the first buried insulating film, connected to a second selection line, and spaced apart from the first trench gate When,
Provided between the first trench gate and the second trench gate, embedded in a plurality of third deep grooves provided in the substrate so as to reach at least the first buried insulating film, and connected to a word line A plurality of third trench gates arranged in series;
A first select transistor provided in a region where the third semiconductor layer and the first trench gate intersect;
A second select transistor provided in a region where the third semiconductor layer and the second trench gate intersect;
A plurality of first memory cell transistors provided in a region where the third semiconductor layer and the third trench gate intersect;
A third select transistor provided in a region where the second semiconductor layer and the first trench gate intersect;
A fourth select transistor provided in a region where the second semiconductor layer and the second trench gate intersect;
A plurality of second memory cell transistors provided in a region where the second semiconductor layer and the third trench gate intersect;
A first memory cell comprising the first selection transistor, the second selection transistor, and the plurality of first memory cell transistors;
A second memory cell comprising the third selection transistor, the fourth selection transistor, and the plurality of second memory cell transistors;
And an inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed around the first to third trench gates during the write operation and the read operation of the memory cell. A selection transistor, the plurality of first memory cell transistors, and the second selection transistor are connected in series, and the third selection transistor, the plurality of second memory cell transistors, and the fourth are connected by the inversion layer. The select transistors are connected in series. A semiconductor substrate;
An isolation trench insulating film embedded in the isolation trench provided in the semiconductor substrate;
A first trench gate that is buried in a first deep groove shallower than the isolation trench insulating film across the isolation trench insulating film and connected to a first control line;
A second trench gate embedded in a second deep groove shallower than the isolation trench insulating film across the isolation trench insulating film, connected to a second control line, and spaced apart from the first trench gate; ,
Provided between the first trench gate and the second trench gate, embedded in a plurality of third deep grooves shallower than the isolation trench insulating film across the isolation trench insulating film, and connected to a word line; A plurality of third trench gates arranged in series;
A first selection transistor formed in one end side region of the first trench gate divided by the isolation trench insulating film, and formed in one end side region of the second trench gate divided by the isolation trench insulating film A first memory cell including a second select transistor and a plurality of first memory cell transistors formed in one end side region of the third trench gate divided by the isolation trench insulating film;
A third select transistor formed in the other end region of the first trench gate divided by the isolation trench insulating film, and formed in the other end region of the second trench gate divided by the isolation trench insulating film And a second memory cell comprising a plurality of second memory cell transistors formed in the other end side region of the third trench gate divided by the isolation trench insulating film. ,
And an inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed around the first to third trench gates in contact with the semiconductor substrate during a write operation and a read operation of the memory cell. The first selection transistor, the plurality of first memory cell transistors, and the second selection transistor are connected in series by the inversion layer, and the third selection transistor, the plurality of second memory cell transistors And a fourth select transistor connected in series.   5. The semiconductor memory device according to claim 1, wherein the memory cell transistor has a charge trap structure or a stacked gate structure including a floating gate and a control gate. 6. A side surface of the first trench gate opposite to the third trench gate is provided with a first semiconductor layer having a conductivity type opposite to that of the semiconductor substrate connected to a source line,
2. A second semiconductor layer having a conductivity type opposite to that of the semiconductor substrate connected to a bit line is provided on a side surface of the second trench gate opposite to the third trench gate. Item 3. The semiconductor memory device according to Item 2. A semiconductor memory device having a memory cell provided between a source line and a bit line, and a decoder provided between the bit line and the decode line,
The memory cell is
A semiconductor substrate;
A first select gate embedded in a first deep groove provided in the semiconductor substrate and connected to the source line;
A second trench gate embedded in a second deep groove provided in the semiconductor substrate, spaced apart from the first select transistor, and connected to the bit line;
A plurality of memory cell transistors provided between the first and second select transistors, a third trench gate embedded in a plurality of third deep grooves provided in the semiconductor substrate, and a plurality of memory cell transistors arranged in series;
And a first inversion layer having a conductivity type opposite to that of the semiconductor substrate is formed around the first to third trench gates during the write operation and the read operation of the memory cell. The first selection transistor, the plurality of memory cell transistors, and the second selection transistor are connected in series by a layer,
The decoder
A semiconductor layer provided on the semiconductor substrate via an isolation region;
A third select transistor provided in the semiconductor layer, a fourth trench gate embedded in a fourth deep groove provided in the semiconductor layer, and connected to the bit line;
A fourth selection is provided in the semiconductor layer, a fifth trench gate is embedded in a fifth deep groove provided in the semiconductor layer, spaced apart from the third selection transistor, and connected to the decode line. A transistor,
A sixth trench gate is embedded in the plurality of sixth deep grooves provided between the third and fourth selection transistors and provided in the semiconductor layer, and has a threshold voltage of 1 bit or more, and is connected in series. A plurality of control transistors disposed;
And a second inversion layer having a conductivity type opposite to that of the semiconductor layer is formed around the fourth to sixth trench gates during the write operation and the decoder operation of the decoder. The semiconductor memory device, wherein the third selection transistor, the plurality of control transistors, and the fourth selection transistor are connected in series.

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