JP2012054701A - Communication system, transceiver, and node - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable identifying an initiation frame to a self-node in a communication system capable of independently waking up a node in a sleep mode without increasing power consumption of the node in the sleep mode.SOLUTION: An initiation frame detector 17 monitors a communication path LN via a comparator CP2 of a receiver 16, recognizes, as an initiation frame, a frame in which the number of count edges in an initiation pattern region coincides with the number of initiation times, and changes an indiscriminate wake-up signal WA to an active level. Further, when a designation code represented by a decode data Ddc that is given by regarding, as a duty signal, a designation pattern set in a designation pattern region of the wakeup frame and decoding the designation pattern set, coincides with an allocation pattern allocated beforehand to a self ECU 10, the initiation frame detector 17 initiates (wakes up) an ECU 10 by changing an individual wake-up signal WU to the active level .

Description

    The present invention relates to a communication network configured by nodes having a sleep / wake-up function, and more particularly to a technique for individually starting a sleeping node.

  Conventionally, CAN (Controller Area Network) has been standardized as an in-vehicle LAN protocol for realizing communication between a plurality of nodes mounted on a vehicle (ISO 11898-1).

  In CAN, dominant and recessive are defined as signal levels on a communication path, and when any one node outputs a dominant signal, the signal level on the communication path is set to be dominant. .

  In addition, in order to enable clock error correction from a signal received via a communication path, it is also defined that a stuff bit having an inverted signal level is inserted when the same signal level continues for 5 bits.

  Furthermore, in CAN, a physical layer having a sleep / wake-up function is also defined (ISO11898-5). Specifically, a node in the sleep mode, which is an operation mode for stopping the communication function for power saving, wakes up when detecting a dominant on the communication path, and is a normal mode in which the communication function can be used. It is specified to transition to.

  By the way, in such a communication system having a wake-up / sleep function, when there is a node in a sleep mode (hereinafter referred to as a dormant node), the normal operation mode is a normal operation mode while the dormant node is kept in a sleep state. There has been a problem that it is not possible to communicate with only nodes in the mode (hereinafter referred to as startup nodes) or to selectively wake up only necessary nodes.

That is, performing communication means that a dominant appears on the communication path, and therefore, if the activation nodes communicate with each other, all the dormant nodes are activated.
In contrast, if the transceiver of the dormant node monitors the bus and the transceiver detects that the bus is not idle, the protocol controller that analyzes the received frame is activated in a limited manner (power supply is resumed), and the protocol is A technique is described in which the controller starts (wakes up) the entire ECU when the protocol controller determines that the received frame is a frame for wakeup of the own node (see, for example, Patent Document 1). .

JP 2005-529393 A

  By the way, in the protocol controller, since each bit constituting the frame must be individually identified, it is usually necessary for the operation to be supplied with a clock from a highly accurate clock source. That is, in order to start the protocol controller, a high-accuracy clock source must be started at the same time.

  In a situation where the start node and the dormant node coexist, if the communication between the start nodes (that is, the non-idle state of the bus) continues, during that time, the dormant node has a protocol controller and a high-accuracy clock source. There has been a problem that power that cannot be ignored continues to be consumed despite being a dormant node (not functioning as an ECU).

  In order to solve the above problems, the present invention provides a communication system capable of individually waking up a node in the sleep mode, and starting up the own node without increasing the power consumption of the node in the sleep mode. It is intended to make it possible to identify a frame for use.

  In the communication system of the present invention made to achieve the above object, an NRZ (Non Return to Zero) code is used for communication between nodes connected to a communication path. Note that the signal level of the communication channel is inferior in the communication channel over a period corresponding to the allowable number of consecutive bits that is the maximum number of consecutive bits of the same signal level permitted by the generation rule of the frame transmitted to the communication channel. A state in which the signal level continues to be recessive is defined as a standby state.

  When the node changes to a dominant signal level in the communication channel after the communication channel is in a standby state, the node recognizes this as the head of the frame and stops communication via the communication channel. Configured to switch to normal mode, which is an operation mode that can execute communication via the communication path, when a predetermined start frame is sent to the communication path in the sleep mode, which is an operation mode for setting a low power consumption state. Has been.

  Further, in the communication system of the present invention, a frame used for communication has a boundary area that is defined so that the same signal level is continuous for 2 bits or more. The area located on the head side of the frame from the area is used as an activation pattern area that is an area for setting a bit pattern for indicating that the frame is an activation frame. At least a part of the area located on the end side is used as a designated pattern area that is an area for setting a bit pattern for designating a node to be activated, and the activated pattern area includes a dominant and recessive area. A bit pattern in which and are arranged alternately is set.

  The node detects at least one of the edge changing from recessive to dominant, or the edge changing from dominant to recessive, as the count edge, and detects it in the start pattern area of the frame sent to the communication path when the operation mode is in the sleep mode. The number of counted edges matches the number of activations determined by the bit pattern in the activation pattern area, and the bit pattern detected in the specified pattern area of the frame is assigned in advance to specify the own node. Transitions to the normal mode.

  According to the communication system of the present invention configured as described above, it is determined whether or not the frame on the communication path has a unique pattern (here, the number of count edges in the activation pattern area is unique). Thus, it is identified whether or not it is a start frame without interpreting (decoding) individual bits constituting the frame.

  Therefore, according to the communication system of the present invention, it is not necessary to operate a protocol controller or a high-accuracy clock source when determining whether or not a node in the sleep mode has received a startup frame. The power consumption of a certain node can be greatly reduced.

  Also, instead of unconditionally starting all the nodes that have received the start frame, only the node specified by the bit pattern detected in the specified pattern area is started. As a result, power consumption of the entire communication system can be reduced.

  By the way, in the communication system of the present invention, it is desirable that the designated pattern area is encoded for each unit block composed of a plurality of bits. In this case, since it is sufficient to perform processing in units of blocks, if a plurality of bits are M bits, even if decoding is performed using a clock, if the accuracy is 1 / M of the clock required for a normal protocol controller. Processing is possible.

  In this case, for example, the unit block may be composed of 3 bits or more, and 1-bit information may be represented by two types of code patterns having different duty ratios. Specifically, “001”, “011” when the unit block is 3 bits, “0001”, “1110”, etc. when the unit block is 4 bits can be considered.

  Further, in the communication system of the present invention, when CAN (Controller Area Network) is used as a communication protocol in the communication path, the SOF and arbitration field of the data frame in CAN are used as the start pattern area, and the data field of the CAN data frame is used. May be used as the designated pattern area.

  Next, the transceiver according to the present invention described in claim 4 is connected to a communication path that performs communication using an NRZ code (Non Return to Zero), and stops communication via the communication path to suppress power consumption. A node configured to transition to a normal mode, which is an operation mode capable of executing communication via a communication path, when a predetermined activation frame is sent to the communication path in the sleep mode, which is an operation mode for Is used for transmitting and receiving signals via the communication path.

  In the transceiver of the present invention, the start timing detection means exceeds a period corresponding to the allowable number of consecutive bits that is the maximum number of consecutive bits of the same signal level permitted by the generation rule of the frame transmitted to the communication path. The state where the signal level of the communication path continues in a recessive state where the signal level is inferior in the communication path is set as a standby state, and after the communication path enters the standby state, the dominant signal level in the communication path is The changed timing is detected as the start timing. Further, the end timing detection means detects the timing at which a bit pattern in which the dominant continues for 2 bits or more appears as the end timing.

  Then, the edge count determining means sets at least one of an edge where the signal level of the communication path changes from recessive to dominant or an edge where the signal level changes from dominant to recessive as a count edge, and ends after the start timing is detected by the start timing detecting means. The number of count edges generated until the first end timing is detected by the timing detection means is counted, and it is determined whether or not the count value matches a preset activation number.

  Further, when the edge count determination means determines that the count value matches the activation number, the code pattern determination means compares the code pattern indicated in the designated pattern area of the frame with a preset allocation pattern. When the two match, a wakeup signal indicating that the activation frame has been received is output.

The transceiver of the present invention configured as described above can be suitably used when configuring a node in the communication system of the present invention described above.
By the way, the start timing detection means can be configured as follows, for example.

  That is, the first charge / discharge circuit resets the charging voltage of the first capacitive element to the initial voltage when the signal level of the communication path is dominant, and the first capacitance when the signal level of the communication path is recessive. The active element is charged with a constant charge current.

  Then, the start timing detection means has a standby determination threshold value set to a magnitude corresponding to the charging voltage of the first capacitive element when charging by the first charging circuit has continued for a period corresponding to the allowable number of consecutive bits. Is compared with the charging voltage of the first capacitive element to determine whether or not it is in a standby state. Specifically, when the charging voltage of the first capacitive element is larger than the standby determination threshold, it is determined that the standby state is set.

With the start timing detecting means configured as described above, the determination as to whether or not the apparatus is in the standby state can be realized by an analog circuit without using a clock.
Further, the end timing detection means can be configured as follows, for example.

  That is, the second charging circuit charges the second capacitive element with a constant charge current when the signal level of the communication path is dominant, and when the signal level of the communication path is recessive, The charging voltage of the capacitive element is reset to the initial voltage.

  The end timing detection means includes an end determination threshold set to a magnitude corresponding to the charge voltage of the second capacitive element when charging by the second charge / discharge circuit continues for a period corresponding to 2 bits or more. The end timing is detected by comparing the received voltage of the second capacitive element. Specifically, the timing at which the charging voltage of the second capacitive element increases beyond the termination determination threshold is detected as the termination timing.

With the end timing detection means configured as described above, the end timing can be detected by an analog circuit without using a clock.
By the way, the code pattern to be determined by the code pattern determination means of the transceiver of the present invention is divided by the edge of interest with either the edge changing from recessive to dominant or the edge changing from dominant to recessive as the edge of attention. The code pattern determination means can be configured as follows, for example, when it is composed of two types of patterns having different duty ratios.

  That is, the third charging circuit alternately switches the positive charge current having a constant magnitude or the negative charge current having a constant magnitude every time the signal level of the communication path changes to change the third capacity. By supplying to the capacitive element, the third capacitive element is charged and discharged, and the charging voltage of the third capacitive element is reset to the initial voltage every time an edge of interest is detected.

  The code pattern determination unit determines whether or not the charging voltage of the third capacitive element before the third charging circuit is reset is greater than a preset threshold every time an edge of interest is detected. It is determined whether the code pattern corresponds to 0 or 1.

  That is, when the positive charge current and the negative charge current are the same, the period ends if the duty ratio of the code pattern in the period (unit block) divided by the edge of interest is 50%. Since the charging voltage of the third capacitive element at the time coincides with the initial voltage, if the duty ratio is set to a value other than 50%, the code pattern determining means determines either 0 or 1; The duty signal can be decoded.

In the transceiver of the present invention, the decoding means may be configured as follows.
That is, the clock generation circuit generates a clock synchronized with the received frame based on the signal on the communication path, and the decoder circuit decodes the code pattern using the clock generated by the clock generation circuit.

  In other words, since the code pattern is composed of a plurality of bits, the decoder circuit can be operated with a clock with a lower accuracy than the clock for operating a normal protocol controller. Can be used.

  Next, a node according to the present invention described in claim 9 includes the transceiver according to any one of claims 4 to 8. The communication control means transmits and receives signals via the transceiver, and the operation mode transition means transitions the operation mode to the sleep mode when a preset sleep condition is satisfied when the operation mode is the normal mode. When the wakeup signal is output from the transceiver when the operation mode is the sleep mode, the operation mode is returned to the normal mode.

  The node of the present invention configured as described above can be suitably used when configuring the above-described communication system.

1 is a block diagram showing a configuration of a communication system to which the present invention is applied. Explanatory drawing which shows the structure of the data frame in a communication system. The block diagram containing the partial circuit diagram which shows schematic structure of a transceiver. The circuit diagram which shows the structure of a standby state detection circuit, and the timing diagram which shows the operation | movement. The circuit diagram which shows the structure of a starting pattern determination circuit. The timing diagram which shows operation | movement of the starting pattern determination circuit at the time of starting frame reception. The timing diagram which shows operation | movement of the starting pattern determination circuit at the time of non-starting frame reception. The circuit diagram which shows the structure of a designated pattern determination circuit. The timing diagram which shows operation | movement of an edge detection circuit and a duty ratio decoder. The timing diagram which shows operation | movement of the designated pattern determination circuit when it corresponds with an allocation pattern. The timing diagram which shows operation | movement of the designation | designated pattern determination circuit when it is inconsistent with an allocation pattern. The block diagram which shows the other structural example of a designated pattern determination circuit.

Embodiments of the present invention will be described below with reference to the drawings.
[overall structure]
FIG. 1 is a block diagram illustrating a configuration of an in-vehicle communication system 1 in which a CAN (Controller Area Network) is used as a communication protocol.

  As shown in FIG. 1, the communication system 1 connects a plurality of electronic control units 10a, 10b, 10c,... Mounted on a vehicle so that they can communicate with each other via a common communication path LN. Each of these electronic control units 10a, 10b, 10c,... Functions as a node. In the following, the electronic control unit is referred to as an ECU, and the ECUs 10a, 10b, 10c, 10d,.

  Among these, the communication path LN is composed of a pair of buses CANH and CANL, and both ends thereof are terminated by termination resistors (not shown). In the communication path LN, a dominant (for example, 0) that is a dominant signal level in the communication path LN or a recessive (for example, 1) that is an inferior signal level in the communication path LN is expressed by the potential difference between the two buses CANH and CANL. The NRZ code is transmitted by the differential signal.

  Specifically, as the ECUs 10a, 10b, 10c, 10d, etc., the engine ECU that controls the engine, the brake ECU that controls the brake control, the steering ECU that controls the steering control, the suspension ECU that controls the suspension control, and the light on / off Various electronic control devices, such as ECU to control, can be mentioned. In FIG. 1, only four ECUs 10 are illustrated, but it goes without saying that the number of ECUs 10 constituting the communication system 1 is not limited to this.

  Further, one of the ECUs 10 (in this case, the ECU 10b) is configured such that an external event serving as a trigger for starting the entire communication system 1 is input from an in-vehicle device (not shown).

  The external event may be generated, for example, when a door of the vehicle is opened or closed, or may be generated when a switch provided for starting up the communication system 1 is operated.

  Furthermore, the ECU 10 is configured to transition between a normal mode that is a normal operation mode when controlling the controlled object and a sleep mode that is an operation mode for stopping communication and suppressing power consumption.

[Frame format]
Here, FIG. 2 is an explanatory diagram showing a configuration of a data frame used for data transmission / reception in the communication system 1.

  As shown in FIG. 2, the data frame is composed of a 1-bit start-of-frame (SOF), an 11-bit identifier (ID) and an 1-bit RTR bit, an arbitration field, 1-bit IDE bit, From a control field consisting of reserved bits (rO) and a 4-bit data length code (DLC), a data field consisting of 0 to 64 bits (ie 0 to 8 bytes) of data, a 15-bit CRC sequence and a 1-bit CRC delimiter CRC field, ACK field consisting of 1-bit ACK slot and ACK delimiter, and 7-bit end-of-frame (EOF).

  In the standard format data frame, as shown by the bold lines in the figure, the SOF, RTR bit, IDE bit, and r0 are always dominant, and the CRC delimiter, ACK delimiter, and EOF are always recessive. That is, an area (RTR, IDE, r0) which is always dominant for 3 bits continuously exists in the data frame, and this area is hereinafter referred to as a boundary area. Further, the area (SOF, ID) on the head side from the boundary area is also referred to as a start pattern area, and the data field is also referred to as a designated pattern area.

  When a frame is transmitted, it is defined that transmission is started from the bit next to an intermission (not shown) composed of a recessive 3-bit inserted after the EOF of the preceding frame. . In the frame, when the same signal level continues for N (N = 5 in this case) bits, it is defined that a stuff bit having an inverted signal level is inserted.

[Startup frame]
Further, in the communication system 1, a data frame having an ID set to 0x555 is used as an activation frame used when activating (wakes up) the ECU 10 whose operation mode is the sleep mode. That is, this ID is prohibited from being used for communication between the ECUs 10 whose operation mode is the normal mode.

  When the activation pattern area (SOF, ID) of the activation frame is represented by a bit pattern, <0> 10101010101 is obtained. However, <0> represents SOF. In this way, when ID = 0x555, the edge pattern (hereinafter referred to as “count edge”) that changes from dominant to recessive is the only bit pattern that has the largest number (six times) in the activation pattern area.

  In addition, a designation pattern for individually designating the ECU 10 to be activated is set in the designation pattern area (data field) of the activation frame. This designated pattern represents a 1-bit value using a predetermined code pattern for each unit block, with 4 bits as a unit block.

  The code pattern is set so that an edge that changes from recessive to dominant (hereinafter referred to as “target edge”) is always detected at the boundary of the unit block. Specifically, the code pattern represents data “0”. It is assumed that “0111” is used as “0001” and “0001” is used as a code pattern representing data “1”. That is, one bit is set by two types of code patterns having different duty ratios. Hereinafter, data obtained by decoding the code pattern in the designated pattern area is also referred to as a designated code.

  Furthermore, since the end of the last unit block is a boundary with the CRC sequence, and the edge of interest is not always detected, the last unit block has a code pattern corresponding to the above-described data “0” and “1”. Instead, the end pattern “0010” or “0100” is set. That is, the end pattern may be set so that a total of two noticed edges can be reliably detected at locations other than the boundary on the head side and the boundary on the tail side of the unit block.

  Note that the data length code (DLC) of the start frame is always recessive at the end of the DLC area, and always changes from recessive to dominant at the boundary between the control field and the data field (that is, the beginning of the first unit block). Is set to an odd number or 8 bytes with the end of the DLC area being recessive.

  That is, the code length (number of unit blocks) of the specified code is p (bytes) × 8 (bit number of 1 byte) / 4 (bit number of unit block) −1 (end pattern), where p is the data length. Therefore, specifically, it is selected from 1 (when p = 1), 5 (when p = 3), 9 (when p = 5), 13 (when p = 7), and the like. .

[ECU]
Returning to FIG. 1, the ECU 10 is connected to a communication path LN and a microcomputer (hereinafter referred to as “microcomputer”) 11 that executes a control process for controlling each part of the vehicle and a process for communicating with other ECUs. In addition, the data (transmission frame) TxD given from the microcomputer 11 is output to the communication path LN, and the transceiver 12 that receives the data (reception frame) RxD on the communication path LN and inputs the data to the microcomputer 11; 12 is provided with a power supply circuit 13 for supplying power. Further, the microcomputer 11 supplies a standby signal STB for switching the operation of the transceiver 12 to the transceiver 12, and the transceiver 12 receives a wake-up signal WU or WA indicating that the activation frame has been received via the communication path LN. It is configured to supply.

  Of the two wake-up signals WU and WA, the wake-up signal WA is required to be activated whenever a frame is sent to the communication path LN (for example, an ECU having a function of monitoring an in-vehicle LAN, In the following, it is also referred to as an indiscriminate wakeup signal. The wake-up signal WU is used by the ECU 10 that only needs to wake up when it receives a start frame in which a designated pattern for designating its own ECU is set. Hereinafter, it is also referred to as an individual wake-up signal.

  The configuration of the ECU 10 shown in FIG. 1 is common to any ECU 10, and each ECU 10 has a configuration for realizing functions individually assigned to each ECU 10, in addition to the above configuration. .

[Microcomputer]
In addition to the well-known configuration of a microcomputer comprising a CPU, ROM, RAM, IO port, etc., the microcomputer 11 transmits and receives frames according to the CAN protocol, arbitration control for determining which frames are preferentially processed, and communication errors. A CAN controller 14 that executes processing and the like is provided.

  In addition, the microcomputer 11 includes a clock circuit (not shown) that generates an operation clock for operating the CPU and the CAN controller 14, and the operation of the clock circuit ( As a result, the operation of the CPU itself can be stopped. The operation mode when the clock circuit is operating is the normal mode, and the operation mode when the clock circuit is not operating is the sleep mode.

  Further, the microcomputer 11 sets the standby signal STB to inactive if the operation mode is the normal mode, and sets the standby signal STB to active if the operation mode is the sleep mode.

  The microcomputer 11 executes various controls assigned to it when the operation mode is the normal mode, and executes a sleep process when a predetermined sleep condition is satisfied during the execution.

  In this sleep process, the standby signal STB is switched to active to stop the communication function of the transceiver 12, operate the start frame monitoring function of the transceiver 12, cut off the power supply to the clock circuit, and By stopping itself, the operation mode is changed to the sleep mode.

  Further, the microcomputer 11 is configured such that the clock circuit is activated when the wakeup signal WU (or WA) from the transceiver 12 becomes active (high level in the present embodiment) in the sleep mode. When the clock circuit is activated, the CPU starts its operation and executes a wake-up process.

  In this wake-up process, the standby signal STB is switched to inactive to stop the activation frame monitoring function of the transceiver 12 and operate the communication function of the transceiver 12. Thereby, the operation mode of ECU10 changes to normal mode.

  In addition, the ECU 10 having a function of waking up another ECU transmits an activation frame in which a designated pattern of the ECU to be activated is set when a predetermined activation condition is satisfied when the operation mode is the normal mode. Then, the ECU to be activated is activated (waked up). When the ECU 10b whose operation mode is the sleep mode receives an external event (one of the activation conditions), the microcomputer 11 has the clock circuit in the same manner as when the wakeup signal WU (or WA) is activated. After activation and execution of the above wake-up process, an activation frame is transmitted.

[Transceiver]
FIG. 3 is a block diagram including a partial circuit diagram showing a schematic configuration of the transceiver.
As shown in FIG. 3, the transceiver 12 includes a bus driving transistor TR1 that conducts / cuts off a path that connects one bus CANH that configures the communication path LN and the power supply VCC, and the other bus that configures the communication path LN. A bus driving transistor TR2 for conducting / cutting off a path connecting CANL and ground GND, and a driver 15 for simultaneously turning on / off the transistors TR1 and TR2 according to the signal level of transmission data TxD input from the CAN controller. I have. Note that diodes D1 and D2 for protecting the transistors TR1 and TR2 are connected to the connection ends of the transistors TR1 and TR2 with the buses CANH and CANL, respectively.

  The transceiver 12 compares the signal levels of the buses CANH and CANL (that is, the signal level of the differential signal), and outputs a comparison result as received data RxD supplied to the CAN controller 14. And a receiver 16 including a second comparator CP2 that compares the signal levels of the buses CANH and CANL and outputs the comparison result as a reception signal Rsl. By the way, these comparators (CP1, CP2) compare whether the signal level difference (potential difference) between CANH and CANL is equal to or greater than the value defined in the specification (0.5 V in this embodiment). Output.

  Further, the transceiver 12 detects a pre-designated start frame based on the received signal Rsl from the second comparator CP2, and outputs a wake-up signal WU, WA to the microcomputer 11 and a start frame detector 17 from the microcomputer 11 A wakeup control unit 18 that controls the operation of each unit by permitting or prohibiting power supply to the driver 15, the receiver 16, and the activation frame detection unit 17 in accordance with the standby signal STB is provided.

  Note that the signal lines of the transmission data TxD and the standby signal STB are pulled up to the power supply voltage VCC via the resistors R1 and R2, respectively. That is, when the ECU 10 enters the sleep mode and the operation of the microcomputer 11 stops, the transmission data TxD input to the transceiver 12 is set to “1” and the standby signal STB is fixed to the active level.

  Further, the buses CANH and CANL are set in a recessive state in which no signal level difference is generated by a known termination resistor (not shown) when the transistors TR1 and TR2 are off.

  The driver 15 turns off the transistors TR1 and TR2 when the transmission data TxD is “1”, and turns on the transistors TR1 and TR2 when the transmission data TxD is “0”. That is, the signal level of the differential signal on the communication path LN is set to 0 V (recessive) when the transmission data TxD is “1”, and to 2 V (dominant) when the transmission data TxD is “0”. .

  The first comparator CP1 and the second comparator CP2 constituting the receiver 16 are configured such that either one operates according to an instruction from the wakeup control unit 18. In addition, the first comparator CP1 is configured using an element having a high operating speed (relatively large power consumption) so that the signal waveform of the differential signal can be accurately reproduced, while the second comparator CP2 is configured to consume power. It is configured using elements with low power.

  When the standby signal STB is in an inactive level (the operation mode is the normal mode), the wakeup control unit 18 permits power supply to the first comparator CP1 of the driver 15 and the receiver 16 via the communication path LN. The communication function for communicating with the other ECU 10 is operated, and the activation frame monitoring function for detecting the activation frame is stopped by prohibiting the power supply to the second comparator CP2 and the activation frame detection unit 17 of the receiver 16.

  On the other hand, when the standby signal STB is at the active level (the operation mode is the sleep mode), the wake-up control unit 18 conversely inhibits the power supply to the first comparator CP1 of the driver 15 and the receiver 16, thereby enabling the communication function. And the power supply to the second comparator CP2 and the start frame detector 17 of the receiver 16 is permitted to operate the start frame monitoring function.

[Startup frame detector]
As shown in FIG. 3B, the activation frame detection unit 17 generates a standby state detection signal DTw that becomes high level when the communication path LN is in the standby state based on the reception signal Rsl from the second comparator CP2. When the standby state detection circuit 21 to be generated and the standby state detection signal DTw change from the high level to the low level, that is, the pattern set in the startup pattern area of the frame sent to the communication path LN sets the startup ID. The activation pattern determination circuit 22 that generates the indiscriminate wakeup signal WA whose signal level becomes the active level when the signal is expressed, and set in the designated pattern area of the frame when the indiscriminate wakeup signal WA becomes active If the designated pattern represents the assignment code assigned to the ECU, the signal level is the active level. And a specified pattern decision circuit 23 for generating an individual wake-up signal WU to be Le.

Hereinafter, the circuit configuration and operation of each unit constituting the activation frame detection unit 17 will be described in detail.
[Standby detection circuit]
4A is a circuit diagram showing a detailed configuration of the standby state detection circuit 21, and FIG. 4B is a timing diagram showing the operation of each part of the standby state detection circuit 21.

  As shown in FIG. 4A, the standby state detection circuit 21 has a capacitor 31 that is grounded at one end and is capable of charging and discharging charges, and a non-grounded end of the capacitor 31 according to the signal level of the reception signal Rsl. A switch 33 connected to one of the constant current sources 32, a voltage dividing circuit 34 including a pair of resistors for dividing the power supply voltage VCC and generating a reference voltage (standby determination threshold value) Vref1, and a reference voltage Vref1 at an inverting input terminal. And a comparator 35 to which a non-grounded terminal voltage (hereinafter referred to as “charging voltage”) Vc of the capacitor 31 is applied to the non-inverting input terminal, and the output of the comparator 35 is output as the standby state detection signal DTw. It is configured.

The switch 33 is set to be connected to the ground side when the received signal Rsl is dominant, and to the constant current source 32 side when it is recessive.
The magnitude of the current supplied from the constant current source 32, the capacity of the capacitor 31, and the magnitude of the reference voltage Vref1 are such that the period during which the capacitor 31 is continuously charged corresponds to 5 bits of the transmission code on the communication path LN. In the following length, the charging voltage Vc does not reach the reference voltage Vref1, and is set so that the charging voltage Vc exceeds the reference voltage Vref1 when the length exceeds a period corresponding to 6 bits. ing.

  In the standby state detection circuit 21 configured as described above, as shown in FIG. 4B, the charging voltage Vc is reset to 0 V when the reception signal Rsl is dominant, and is constant while the reception signal Rsl is recessive. Increase in proportion.

  When the recessive continuous number is less than 6 bits and the charging voltage Vc is equal to or lower than the reference voltage Vref1, the standby state detection signal DTw becomes an inactive level indicating that the standby state is not set. On the other hand, when the recessive continuous number becomes 6 bits or more and the charging voltage Vc exceeds the reference voltage Vref1, the standby state detection signal DTw indicates that the standby state detection signal DTw is in the standby state until the reception signal Rsl changes to dominant. It becomes the active level shown.

  Note that the 6 bits, which are the criteria for determining whether or not to be in the standby state, are based on a stuff bit insertion rule (inserting a stuff bit having an inverted signal level when the same signal level continues for 5 bits), which is one of the frame generation rules. Based on 5 bits, which is the maximum continuous number (allowable continuous bit number) of the same signal level allowed in the frame, a value larger than this is set.

[Startup pattern determination circuit]
FIG. 5 is a circuit diagram showing a detailed configuration of the activation pattern determination circuit 22. 6 and 7 are timing charts showing the operation of each part of the activation pattern determination circuit 22.

  As shown in FIG. 5, the activation pattern determination circuit 22 is provided in the supply path of the reception signal Rsl, becomes conductive at the timing of the falling edge of the standby state detection signal DTw, and the timing of the rising edge of the end signal DTs described later. When an area in which the dominant continues for a period corresponding to 2 bits is detected from the switch 24 that is opened in FIG. 4 and the received signal Rsl supplied via the switch 24, the end timing for generating the end signal DTs that becomes the active level The detection circuit 25, the low-pass filter 26 provided for removing distortion of the reception signal Rsl supplied via the switch 24, and the number of count edges in the reception signal Rsl supplied via the low-pass filter 26 are calculated. The edge signal DTs changes from the inactive level to the active level. A counter circuit 27 that counts until imming, and a determination circuit 28 that generates an indiscriminate wakeup signal WA that becomes an active level when the count value of the counter circuit 27 is a preset activation number (here, 6). I have.

<End timing detection circuit>
The end timing detection circuit 25 connects the non-grounded end of the capacitor 41 to either the ground level or the constant current source 42 according to the signal level of the reception signal Rsl and the capacitor 41 that can charge and discharge the charge whose one end is grounded. Switch 43, a pair of resistors for dividing the power supply voltage VCC, a voltage dividing circuit 44 for generating a reference voltage (end determination threshold value) Vref2, a reference voltage Vref2 is applied to the inverting input terminal, and a capacitor is connected to the non-inverting input terminal Comparator 45 to which a non-grounded terminal voltage 41 (hereinafter referred to as “charge voltage”) Vd is applied is configured to output the output of comparator 45 as end signal DTs.

The switch 43 is set to be connected to the ground side when the received signal Rsl is recessive and to the constant current source 42 side when the received signal Rsl is dominant.
Further, the magnitude of the current supplied by the constant current source 42, the capacity of the capacitor 41, and the magnitude of the reference voltage Vref2 are such that the period during which the capacitor 41 is continuously charged corresponds to one bit of the transmission code on the communication path LN. In the following length, the charging voltage Vd does not reach the reference voltage Vref2, and is set so that the charging voltage Vd exceeds the reference voltage Vref2 when the length is longer than a period corresponding to 2 bits. ing.

<Counter circuit>
The counter circuit 27 is formed of a known synchronous counter mainly composed of three D-type flip-flop circuits FF0 to FF2. Then, the counter circuit 27 is released from the reset only while the end signal DTs is at the inactive level, and at the timing of the count edge (the edge that changes from dominant to recessive) of the reception signal Rsl supplied through the low-pass filter 26. Connected to count up.

<Determination circuit>
The determination circuit 28 receives the high-order bits of the count result of the counter circuit 27 (the non-inverted outputs Q1 and Q2 of the flip-flop circuits FF1 and FF2), and indiscriminately wakes up when both are at a high level. It consists of a logical product (AND gate) that generates the signal WA.

<Operation of startup pattern determination circuit>
In the startup pattern determination circuit 22 configured in this way, as shown in FIGS. 6 and 7, via the switch 24 at the timing when the falling edge of the standby state detection signal DTw, that is, the beginning of the frame is detected. When the supply of the reception signal Rsl is started, the count operation of the counter circuit 27 is started. This counting operation is continued until the end signal DTs changes to the active level.

  When an activation ID is set in the activation pattern area (SOF, ID) of the frame transmitted to the communication path LN, the same signal level is continuously 2 bits in the activation pattern area as shown in FIG. Therefore, the end signal DTs remains in an inactive level, and the count value of the counter circuit 27 represents the number of activations 6 (Q0, Q) at the count edge that is the start timing of the last bit in the activation pattern area. Q1, Q2) = (0, 1, 1), and at this timing, the indiscriminate wakeup signal WA changes to the active level. Thereafter, when the end signal DTs changes to the active level in the boundary region (RTR, IDE, r0) where the dominant continues for 3 bits, the counter circuit 27 is reset so that the indiscriminate wakeup signal WA is also deactivated. Return. At the same time, since the switch 24 is opened and the supply of the reception signal Rsl is stopped, the count value of the counter circuit 27 is held as it is at the time of reset.

  On the other hand, when an activation ID other than the activation ID is set in the activation pattern area of the frame transmitted to the communication path LN, as shown in FIG. 7, the same signal level is continuously 2 bits or more in the activation pattern area. Is necessarily present (in FIG. 7, a case where a 2-bit continuous dominant exists) is shown.

  Then, if there is a place where the dominant is continuous for 2 bits or more in the activation pattern area, the end signal DTs becomes active at that point, and the count operation of the counter circuit 27 is stopped, so that the count value does not reach the activation number. Since it is reset, the indiscriminate wakeup signal WA is maintained at an inactive level.

  If there is no portion where the dominant continues in the start pattern region and there is a portion where recessive continues for 2 bits or more, the counter circuit 27 operates until the end signal DTs changes to the active level in the boundary region. As described above, the count edge appears in the activation pattern area by the number of activations only when the activation ID is set. In this case, the count value of the counter circuit 27 reaches the activation number. Indiscriminately, the indiscriminate wakeup signal WA is held at an inactive level.

[Designated pattern judgment circuit]
FIG. 8 is a circuit diagram showing a detailed configuration of the designated pattern determination circuit 23. 9 and 10 are timing charts showing the operation of each part of the designated pattern determination circuit 23. FIG.

  As shown in FIG. 8, the designated pattern determination circuit 23 is provided in the supply path of the reception signal Rsl, and the edge timing at which the indiscriminate wakeup signal WA changes from the inactive level (low level) to the active level (high level). And the switch 51 which is opened at the timing of an edge at which an enable signal EN described later changes from an active level (low level) to an inactive level (high level), and a reception signal Rsl supplied via the switch 51. The edge detection circuit 52 that generates the edge detection signal ED representing the timing of the target edge (the edge that changes from recessive to dominant) and the reception signal Rsl supplied via the switch 51 are decoded by decoding as a duty signal. A duty ratio decoder 53 for generating data Ddc; Based on the edge detection signal ED and the decoded data Ddc, a data comparison circuit 54 that generates an individual wakeup signal WU that becomes an active level when the decoded data Ddc matches the activation code assigned to the ECU. .

Hereinafter, the circuit configuration and operation of each part constituting the designated pattern determination circuit 23 will be described in detail.
<Edge detection circuit>
The edge detection circuit 52 receives an inversion circuit (NOT gate) 65 that inverts the signal level of the reception signal Rsl and outputs of the reception signal Rsl and the NOT gate 65, that is, an inversion signal of the reception signal Rsl, both of which are low level. At this time, it is composed of a negative OR circuit (NOR gate) 66 whose output becomes a high level, and the output of the NOR gate 37 is output as the edge detection signal ED.

  As shown in FIG. 9A, the edge detection circuit 52 configured as described above has a width corresponding to the delay time of the NOT gate 65 as the edge detection signal ED, for each received signal Rsl at the timing of the edge of interest. Outputs a pulse signal.

<Duty ratio decoder>
Returning to FIG. 8, in the duty ratio decoder 53, a capacitor 61a capable of charging and discharging charges is connected between the inverting input terminal and the output terminal, and a reference voltage (sign determination threshold) Vref3 is applied to the non-inverting input terminal. When the edge detection signal ED is at a high level, the well-known integration circuit 61 composed of an operational amplifier connected to the inverting input terminal so that the reception signal Rsl is applied via a resistor is short-circuited when the edge detection signal ED is at a high level. The switch 62 includes a comparator 63 to which the output Vy of the integrating circuit 61 is applied to the inverting input terminal and the reference voltage Vref3 is applied to the non-inverting input terminal, and a D-type flip-flop. The output CPy of the comparator 63 is used as an edge detection signal. And a latch circuit 64 that latches at the timing of ED, and is configured to output the output of the latch circuit 64 as decoded data Ddc.

  The reference voltage Vref3 is set so that the high level (recessive) of the received signal Rsl is VH and the low level (dominant) is VL, and an intermediate value between them, that is, Vref3 = (VH + VL) / 2.

  In the duty ratio decoder 53 configured in this way, as shown in FIG. 9B, every time a noticed edge is detected, the charging voltage of the capacitor 61a, which is the output of the integrating circuit 61 (on the output terminal side of the operational amplifier). The voltage Vy is initialized to the reference voltage Vref3. While the reception signal Rsl is at a low level, the charging voltage Vy increases at a constant rate, and when the reception signal Rsl changes to a high level, the charging voltage Vy decreases at the same constant rate as when increasing.

  In other words, if the signal level of the received signal Rsl is longer than the low level period during successive edges of interest, the charging voltage Vy becomes smaller than the reference voltage Vref3 at the end of that period. On the contrary, if the low level period is longer than the high level period, the charging voltage Vy becomes higher than the reference voltage Vref3 at the end of the period. In other words, the interval between successive edges of interest is regarded as one duty code, and the duty code is decoded into binary digital data depending on whether the duty ratio of the duty code is 50% or more.

  In the designated pattern area (that is, the data field) of the start frame, since the edge of interest is always detected for each 4-bit unit block, the bit pattern in the designated pattern area is the duty ratio decoder 53. Thus, each unit block is decoded.

<Data comparison circuit>
Returning to FIG. 8, the data comparison circuit 54 includes a decode data holding circuit 71 including a multistage shift register that receives the decode data Ddc and operates using the edge detection signal ED as a shift clock, a plurality of switches, and the like. The assigned pattern setting circuit 73 in which a signal level corresponding to the assigned pattern assigned to the input pattern is set, and the decoded data held in the decoded data holding circuit 71 and the setting content of the assigned pattern setting circuit 73 match each other. And a comparator 72 that generates comparison data cp.

  In addition, the data comparison circuit 54 receives the permission signal EN and the comparison data Dcp indicating the timing at which the comparison data Dcp indicating the desired comparison result is output from the comparator 72 based on the edge detection signal ED and the standby state detection signal DTw. The timing generation circuit 74 generates a latch clock LCK representing the latch timing, and a D-type flip-flop circuit. The enable signal EN is applied to the reset terminal, and the comparison data Dcp from the comparator 72 is used as the timing of the latch clock LCK. The latch circuit 75 is configured to output the signal latched by the latch circuit 75 as the individual wake-up signal WU.

  The enable signal EN changes to an active level (low level) that permits the operation of the latch circuit 75 at the timing between the last unit block and the end pattern, and the standby state detection signal DTw changes from the inactive level to the active level. It is generated so as to change to an inactive level (high level) that prohibits the operation of the latch circuit 75 at the changing timing. Further, the latch clock LCK changes from the low level to the high level from the time when the enable signal EN becomes the low level to the timing of the target edge of the end pattern, and the standby state detection signal DTw changes from the inactive level to the active level. It is generated so as to return to the low level at the changing timing.

  Such a timing generation circuit 74 determines the number of edges of interest that occur after the indiscriminate wakeup signal WA changes to the active level (high level) during the period in which the received signal Rsl is supplied via the switch 51. In consideration, the counter, the shift register, the latch circuit, the delay circuit, and the like can be easily created by appropriately combining them. Therefore, detailed description thereof is omitted here.

  In the data comparison circuit 54 configured as described above, the decoded data Ddc, which is the result of decoding by the duty ratio decoder 53, is sequentially held in the decoded data holding circuit 71, and the held contents and allocation pattern setting are set by the comparator 72. It is compared whether the setting contents of the circuit 73 match.

  As shown in FIG. 10, all of the decoded data Ddc is decoded data from the timing of the target edge between the last unit block and the end pattern until the timing of the next target edge, as shown in FIG. Comparison data Dcp held in the holding circuit 71 and indicating an effective comparison result with the assigned pattern is obtained. The comparison data Dcp is latched in the latch circuit 75 by the latch clock LCK that rises at the timing when this effective comparison result is obtained.

  FIG. 10 shows a case where the designation code obtained by decoding the designation pattern set in the designation pattern area matches the assigned pattern, and the comparison data Dcp matches at the timing when the latch clock LCK rises. Since the signal level is expressed (high level), the individual wakeup signal WU, which is the output of the latch circuit 75, changes to the active level at this timing. Thereafter, the individual wakeup signal WU returns to the inactive level at the timing when the standby state detection signal DTw changes to the active level.

  FIG. 11 shows a case where the designated code does not match the assigned pattern. Since the comparison data Dcp is at a signal level (low level) indicating a mismatch at the timing when the latch clock LCK rises, the individual codes are individually displayed. The wake-up signal WU is held at an inactive level.

[effect]
As described above, in the communication system 1, the ECU 10 in the sleep mode monitors the communication path LN and recognizes a frame in which the number of count edges in the activation pattern area matches the activation number as an activation frame (promiscuous wakeup The signal WA is changed to an active level), and a designation code represented by the decoded data Ddc decoded by regarding the designation pattern set in the designation pattern area of the start frame as a duty signal is assigned to the ECU 10 in advance. When the assigned pattern matches, the normal mode is changed (the individual wake-up signal WU is changed to the active level).

  Therefore, according to the communication system 1, it is not necessary to operate the CAN controller 14 or the clock circuit in order to determine whether or not the activation frame has been received, so that the power consumption of the ECU 10 in the sleep mode is greatly reduced. be able to.

  Further, according to the communication system 1, not all nodes that have received the activation frame are activated unconditionally, but only the node specified in the activation frame is activated, so that a node that does not need to be activated is activated wastefully. In other words, the power consumption of the entire communication system 1 can be reduced.

[Correspondence with Invention]
In this embodiment, the standby state detection circuit 21 is a start timing detection means, the end timing detection circuit 25 is an end timing detection means, the counter circuit 27 and the determination circuit 28 are edge count determination means, and the designated pattern determination circuit 23 is a code pattern determination means. It corresponds to.

  The capacitor 31 in the standby state detection circuit 21 is the first capacitive element, the constant current source 32 and the switch 33 are the first charging circuit, and the capacitor 41 in the end timing detection circuit 25 is the second capacitive element, the constant current. The source 42 and the switch 43 correspond to the second charging circuit, the capacitor 61a in the duty ratio decoder 53 corresponds to the third capacitive element, and the integrating circuit 61 corresponds to the third charging circuit.

  Furthermore, the configuration for the CAN controller 14 to start and stop the communication control means, the wake-up process executed by the microcomputer 11, the sleep process, and the clock circuit that is a part of the microcomputer 11 corresponds to the operation mode transition means.

[Other Embodiments]
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to the said embodiment, In the range which does not deviate from the summary of this invention, it is possible to implement in various aspects.

  For example, in the above embodiment, the receiver 16 is configured with two comparators CP1 and CP2, and the comparator to be used is switched depending on the operation mode. However, the receiver is configured with one comparator CP1 and the output of the comparator CP1. Depending on the operation mode.

  In the designated pattern determination circuit 23 of the above embodiment, the duty ratio decoder 53 regards the bit pattern for each unit block set in the designated pattern area as a duty signal, and the length of the period of two signal levels in the unit block. , The start frame is recognized as in the designated pattern determination circuit 23a shown in FIG. 12 (the indiscriminate wakeup signal WA becomes active). ), The PLL circuit 55 for reproducing the clock signal from the received signal Rsl may be operated, and the decoder 56 may be configured to decode the bit pattern of the data field according to the clock generated by the PLL circuit 55. In this case, the data comparison circuit 57 may generate the enable signal EN and the latch clock LCK based on the clock generated by the PLL circuit 55 instead of the edge detection signal ED. In this case, the bit pattern set in the designated pattern area of the start frame is set for each unit block composed of a plurality of bits, and can be decoded with a clock having a lower accuracy than the clock used by the CAN controller 14. Any pattern is possible. Here, the PLL circuit 55 corresponds to the clock generation circuit according to the present invention (claim 8), and the decoder 56 corresponds to the decoder circuit.

  In the above embodiment, the edge that changes from dominant to recessive is used as the count edge counted by the activation pattern determination circuit 22, but conversely, an edge that changes from recessive to dominant is used, or both are used. Also good.

  In the above-described embodiment, it is determined that the dominant state is in the standby state when the dominant continues for 6 bits or more. However, the present invention is not limited to this. As long as it is N + 1 bits or more and 11 bits or less. Note that 11 bits is the total number of bits of the ACK delimiter (1 bit), EOF (7 bits), and intermission (3 bits) inserted between frames.

  In the above-described embodiment, the standby state detection circuit 21 and the end timing detection circuit 25 having the same circuit configuration are provided separately, but they may be configured as a single circuit. In this case, however, circuit constants (reference voltage, constant current magnitude, relationship between signal level and switch connection destination, etc.) depend on whether the standby state detection circuit 21 or the end timing detection circuit 25 is used. Must be configured to switch.

DESCRIPTION OF SYMBOLS 1 ... Communication system 10 (10a-10d) ... Electronic control unit 11 ... Microcomputer (microcomputer) 12 ... Transceiver 13 ... Power supply circuit 14 ... CAN controller 15 ... Driver 16 ... Receiver 17 ... Startup frame detection part 18 ... Wake-up control part DESCRIPTION OF SYMBOLS 21 ... Standby state detection circuit 22 ... Startup pattern determination circuit 23, 23a ... Designated pattern determination circuit 24, 33, 43, 51, 62 ... Switch 25 ... End timing detection circuit 26 ... Low-pass filter 27 ... Counter circuit 28 ... Determination circuit 31 , 41, 61a ... Capacitors 32, 42 ... Constant current source 34, 44 ... Voltage dividing circuit 35, 45, 63 ... Comparator 52 ... Edge detection circuit 53 ... Duty ratio decoder 54 ... Data comparison circuit 55 ... PLL circuit 56 ... Decoder 57 ... de Data comparison circuit 61 ... integrating circuit 64 ... latch circuit 71 ... decoding data holding circuit 72 ... comparator 73 ... allocation pattern setting circuit 74 ... timing generator 75 ... latch circuit

Claims (9)

An NRZ (Non Return to Zero) code is used for communication between nodes connected to the communication path, and the node has the maximum number of consecutive bits of the same signal level permitted by a generation rule of a frame sent to the communication path. The state in which the signal level of the communication path continues in a recessive state, which is an inferior signal level in the communication path, exceeds the period corresponding to the allowable continuous bit number, and the communication path is in the standby state. After this, when the dominant signal level changes in the communication path, it is recognized as the beginning of the frame, and the communication via the communication path is stopped and the power consumption state is set. When a predetermined activation frame is sent to the communication path in the sleep mode, the mode is changed to the normal mode, which is an operation mode capable of executing communication via the communication path. A a communications system configured to,
The frame used for the communication has a boundary area that is an area defined so that the same signal level is continuous for 2 bits or more,
The activation frame is used as an activation pattern area in which an area located on the head side of the frame from the boundary area is an area for setting a bit pattern for indicating that the frame is an activation frame. In addition, at least a part of the region located at the end of the frame from the boundary region is used as a designated pattern region that is a region for setting a bit pattern for designating a node to be activated, and In the activation pattern area, a bit pattern in which dominant and recessive are arranged alternately is set.
The node has a start pattern area of a frame transmitted to the communication path when the operation mode is the sleep mode, with at least one of an edge changing from recessive to dominant or an edge changing from dominant to recessive as a count edge. The number of detected count edges matches the number of activations determined by the bit pattern of the activation pattern area, and the bit pattern detected in the designated pattern area of the frame is assigned in advance to designate the own node. A communication system characterized by transitioning to a normal mode when the assigned pattern matches.   The communication system according to claim 1, wherein the designated pattern area is encoded for each unit block composed of a plurality of bits.   A CAN (Controller Area Network) is used as a communication protocol in the communication path, the area sandwiched between the ID and DLC of the data frame in CAN is the boundary area, the SOF and ID are the activation pattern area, and the data field is the designation. The communication system according to claim 1, wherein the communication system is used as a pattern area. Connected to a communication path that performs communication using NRZ code (Non Return to Zero), predetermined activation in the sleep mode, which is an operation mode for stopping communication through the communication path and suppressing power consumption When a frame is transmitted to the communication path, a node configured to shift to a normal mode, which is an operation mode capable of performing communication via the communication path, transmits and receives signals via the communication path. Transceiver used in
The signal level of the communication path exceeds the period corresponding to the allowable number of consecutive bits that is the maximum number of consecutive bits of the same signal level allowed by the generation rule of the frame transmitted to the communication path. A state in which the recessive signal level continues in a recessive state is set as a standby state, and after the communication path is in a standby state, a timing at which the dominant signal level in the communication path changes to a dominant is detected as a start timing. Timing detection means;
End timing detection means for detecting a timing at which a bit pattern in which a dominant continues for 2 bits or more appears as an end timing;
At least one of the edge where the signal level of the communication path changes from recessive to dominant or the edge where the signal level changes from dominant to recessive is used as a count edge, and after the start timing is detected by the start timing detection means, the end timing detection means first Edge count determination means for counting the number of count edges generated until the end timing is detected, and determining whether the count value matches a preset activation number;
If it is determined by the edge count determination means that the count value matches the number of activations, the code pattern shown in the specified pattern area of the frame is compared with a preset allocation pattern, and the two match. Code pattern determination means for outputting a wake-up signal indicating that the activation frame has been received,
A transceiver comprising: The start timing detecting means includes
A first capacitive element capable of charging and discharging electric charge;
When the signal level of the communication path is dominant, the charging voltage of the first capacitive element is reset to an initial voltage, and when the signal level of the communication path is recessive, the first capacitive element is set to a certain level. A first charging circuit for charging with a charging current of
With
A standby determination threshold set to a magnitude corresponding to a charging voltage of the first capacitive element when charging by the first charging circuit has continued for a period corresponding to the allowable number of consecutive bits; 5. The transceiver according to claim 4, wherein it is determined whether or not it is in a standby state by comparing with a charging voltage of the capacitive element. The end timing detection means includes
A second capacitive element capable of charging and discharging electric charge;
When the signal level of the communication path is dominant, the second capacitive element is charged with a constant charging current, and when the signal level of the communication path is recessive, the second capacitive element is charged. A second charging circuit for resetting the voltage to an initial voltage;
With
An end determination threshold set to a magnitude corresponding to a charging voltage of the second capacitive element when charging by the second charging circuit continues for a period corresponding to 2 bits, and the second capacitive 6. The transceiver according to claim 4, wherein the end timing is detected by comparing with a charging voltage of an element. The code pattern is composed of a plurality of bits divided by the target edge, with either one of the edge changing from recessive to dominant or the edge changing from dominant to recessive as the target edge, and having two different duty ratios. Consists of patterns,
The code pattern determination means includes
A third capacitive element capable of charging and discharging electric charge;
By switching a positive charge current having a certain magnitude or a negative charge current having a certain magnitude every time the signal level of the communication path is changed, the charge current is supplied to the third capacitive element. A third charging circuit that charges and discharges the third capacitive element and resets a charging voltage of the third capacitive element to an initial voltage each time the edge of interest is detected;
With
Every time the edge of interest is detected, the code pattern depends on whether the charging voltage of the third capacitive element before the third charging circuit is reset is larger than a preset code determination threshold. The transceiver according to claim 4, wherein it is determined whether 0 corresponds to 0 or 1. The code pattern determination means includes
A clock generation circuit that generates a clock synchronized with the received frame based on the signal on the communication path;
A decoder circuit for decoding the code pattern using the clock generated by the clock generation circuit;
The transceiver according to any one of claims 4 to 6, characterized by comprising: A transceiver according to any one of claims 4 to 8,
Communication control means for transmitting and receiving signals via the transceiver;
When a preset sleep condition is satisfied when the operation mode is the normal mode, the operation mode transitions to the sleep mode, and when the operation mode is the sleep mode, a wakeup signal is output from the transceiver. An operation mode transition means for returning the operation mode to the normal mode;
A node characterized by comprising:

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