CN110321304A - Bus communication system under vehicle environment between FPGA and STM32 - Google Patents
Bus communication system under vehicle environment between FPGA and STM32 Download PDFInfo
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- CN110321304A CN110321304A CN201910602841.2A CN201910602841A CN110321304A CN 110321304 A CN110321304 A CN 110321304A CN 201910602841 A CN201910602841 A CN 201910602841A CN 110321304 A CN110321304 A CN 110321304A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
- G06F13/124—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
- G06F13/126—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine and has means for transferring I/O instructions and statuses between control unit and main processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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Abstract
The invention discloses the bus communication systems under a kind of vehicle environment between FPGA and STM32, belong to vehicle bus field of wireless communications, and technical problems to be solved are the hetero-com-munication how realized based on CAN bus under vehicle environment between FPGA and STM32；Its structure includes the first CAN controller, STM32 chip is built in, for carrying out data transmit-receive；First CAN transceiver is connect with the first CAN controller, for STM chip to be accessed CAN bus；Second CAN controller, is built in fpga chip, for carrying out data transmit-receive；Second CAN transceiver is connect with the second CAN controller, for FGPA chip to be accessed CAN bus；Communication control module is built in fpga chip, and connect with the second CAN controller, for controlling the second CAN controller.
Description
Technical field
The present invention relates to vehicle bus field of wireless communications, under specifically a kind of vehicle environment FPGA and STM32 it
Between bus communication system.
Background technique
FPGA calculation process fast speed, it is powerful, but interface control logic realization is more complex, and STM32 single-chip microcontroller is arrogated to oneself
Length controls but speed is relatively slow, and the two has complementary functions in embedded systems, and carrying out coordinated design can be achieved almost institute
There are digital circuitry functions.
The technology that FPGA and STM32 carries out collaborative design focuses on communication between the two.FPGA and STM32 is logical at present
The commonly used mode of letter is communicated using UART serial ports or spi bus.Serial ports speed is reliable compared with slow and communication robust
Property it is poor, be only suitable for requiring lower debugging occasion to use；Spi bus fast speed, it is easy to use, it is suitble under general scene
Interchip communication.
CAN bus is one of most widely used fieldbus in the world, it is widely used in industrial automation monitoring
Differential signal transmission is used in network.CAN bus has very strong error detection capability, and communication distance is remote, therefore is used
Special occasion, such as automobile, factories and miness etc. interfere stronger place.
In conclusion CAN bus has stronger compared to serial ports, spi bus etc. under vehicle environment or other industrial environments
Error detection capability and fault-tolerance, reliability is higher, using the bus network mode of more main, non-principals and subordinates, can preferably play
The features such as FPGA is parallel, flexible, free.In addition, it is farther compared to spi bus transmission range using CAN bus, there is highly resistance electromagnetism
Interference, error probability is lower, and only needs both threads, saves line, is very suitable under the actual industrials environment such as vehicle-mounted
Hetero-com-munication between FPGA and STM32 piece.
It to sum up, is to need to solve how based on the hetero-com-munication under CAN bus realization vehicle environment between FPGA and STM32
Certainly the technical issues of.
Summary of the invention
Technical assignment of the invention is against the above deficiency, to provide total between FPGA and STM32 under a kind of vehicle environment
Line communication system, to solve how based on CAN bus to realize asking for hetero-com-munication between FPGA and STM32 under vehicle environment
Topic.
The present invention provides the bus communication system under a kind of vehicle environment between FPGA and STM32, the bus communication system
For realizing the hetero-com-munication between fpga chip and STM32 chip by CAN bus, the bus communication system includes: system
First CAN controller, first CAN controller is built in STM32 chip, for carrying out data transmit-receive；
First CAN transceiver, first CAN transceiver are connect with the first CAN controller, for accessing STM chip
CAN bus；
Second CAN controller, second CAN controller is built in fpga chip, for carrying out data transmit-receive；
Second CAN transceiver, second CAN transceiver are connect with the second CAN controller, for accessing FGPA chip
CAN bus；
Communication control module, the communication control module is built in fpga chip, and connect with the second CAN controller, uses
In controlling the second CAN controller.
Preferably, the first CAN controller carries out data receiver using interrupt mode.
Preferably, between the first CAN transceiver and the first CAN controller and the second CAN transceiver and the 2nd CAN control
It is attached by CAN_RX data line and CAN_TX data line between device processed.
Preferably, the first CAN transceiver is the chip of model TJA1050, for received data frame to be switched to object
Layer differential signal is managed, and fpga chip is transmitted to by CAN bus.
Preferably, the second CAN controller is controlled using hardware logic and state machine mode, without soft core and stone CPU, and
Using AVALON bus general-purpose interface form, with AVALON bus IP Core Universal joint.
Preferably, the second CAN controller includes:
Register module, the register module includes control register, writes RAM and read RAM, for passing through control deposit
Device is communicated with logic modules other in fpga chip, and for data to be sent according to ID+ length+data frame lattice
Formula writes RAM, and received data message is stored in and reads RAM；
Fifo module is sent, the fifo module is connect with register module, buffered data when for sending data；
Data flow processing module, the data flow processing module are used for according to CAN bus agreement data group to be sent
It is bundled into CAN message data flow, and for unpacking received message data stream, obtaining receiving message；
Time-sequence control module, the time-sequence control module are connect with data flow processing module, and pass through CAN_RX data line
It is connect with CAN_TX data line with the second CAN transceiver, for monitoring CAN bus timing and synchronous with bus timing holding, and
For sending or receiving CAN bus data flow according to bus timing；
Data filter is received, the reception data filter is connect with data flow processing module, for docking receiving text
It is filtered, obtains filtering and be followed by receiving text；
Fifo module is received, the reception fifo module is connect with data filter is received, and is followed by receiving for caching filtering
Message, and filtering is followed by the text write-in reading RAM that receives telegraph；
Error detection module, the error detection module is for each bit-errors of detection data stream and carries out error count；
State machine module, other are each for control except transmission fifo module and in addition to receiving fifo module for the state machine module
The working condition of module is converted, and for monitoring control register, reading RAM and write RAM.
Preferably, control register includes:
Command register, the command register are used to receive the order that other logic modules are sent in fpga chip, and
Control the first CAN controller；
Status register, the status register are used to read the information of the first CAN controller, including current state information
And error message.
Preferably, data flow processing module includes CAN protocol group packet module and CRC check module；
Data flow processing module is bundled into CAN message data flow for the data group to be sent as follows:
Calculate data frame CRC16 check bit；
Data bit, including frame start bit, ACK, End of Frame are added according to CAN bus agreement；
It packages processing to ID and data frame, group is bundled into CAN message data flow.
Bus communication system under vehicle environment of the invention between FPGA and STM32 has the advantage that
1, the communication of FPGA and STM32 is realized by CAN bus, bus error, long transmission distance, transmission can be detected by having
Rate height, high reliability；
2, CAN bus use multiple host pattern, online any node can at any time initiatively on network other
Node sends information, is very suitable to the construction characteristic of FPGA and STM32, without CPU, freely receive and dispatch to send out FPGA to large extent
Wave the flexible feature of FPGA；
3, second CAN controller at the end FPGA is realized using hardware logic Programming with Pascal Language, no CPU, and no software sequence executes
Caused by postpone, the first CAN master controller built in STM32 is operated by software, and software delay is smaller, and whole system can be most
The feature that CAN bus speed is fast, high-efficient is played to limits, system communication fast speed is delayed smaller, and reliability is higher；
4, using CAN bus, other mobile units such as vehicle-mounted OBD, various sensors can be easily accessed, are supplied
FPGA and STM32 freely obtains data and is handled, and has biggish device extension；
5, FPGA is expansible is connect using internal AVALON bus with CAN bus, realizes that other modules are linked into CAN by FPGA
Bus is directly communicated with STM32, has biggish bus scalability.
Detailed description of the invention
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to required in being described in embodiment
The attached drawing used is briefly introduced, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those skilled in the art, without creative efforts, it can also be obtained according to these attached drawings
His attached drawing.
The following further describes the present invention with reference to the drawings.
Attached drawing 1 is the structural schematic diagram of the bus communication system under embodiment vehicle environment between FPGA and STM32；
Attached drawing 2 is the second CAN controller in the bus communication system under embodiment vehicle environment between FPGA and STM32
Structural block diagram.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings and specific examples, so that those skilled in the art can be with
It more fully understands the present invention and can be practiced, but illustrated embodiment is not as a limitation of the invention, the case where not conflicting
Under, the technical characteristic in the embodiment of the present invention and embodiment can be combined with each other.
It is to be appreciated that in the description of the embodiment of the present invention, the vocabulary such as " first ", " second " are only used for distinguishing and retouch
The purpose stated, is not understood to indicate or imply relative importance, can not be interpreted as indication or suggestion sequence.
The embodiment of the present invention provides the bus communication system under vehicle environment between FPGA and STM32, how is used for solution
The technical issues of realizing the hetero-com-munication under vehicle environment between FPGA and STM32 based on CAN bus.
Embodiment:
As shown in Figure 1 and Figure 2, the bus communication system under vehicle environment of the invention between FPGA and STM32 is used
By the hetero-com-munication of CAN bus between realization fpga chip and STM32 chip, which includes the first CAN
Controller, the first CAN transceiver, the first CAN transceiver, the second CAN transceiver and communication control module.First CAN controller
It is built in STM32 chip, for carrying out data transmit-receive；First CAN transceiver is connect with the first CAN controller, is used for STM core
Piece accesses CAN bus；Second CAN controller is built in fpga chip, for carrying out data transmit-receive；Second CAN transceiver with
Second CAN controller connection, for FGPA chip to be accessed CAN bus；Communication control module is built in fpga chip, and with
Two CAN controllers connection, for controlling the second CAN controller.
Wherein, the first CAN transceiver and the second CAN transceiver are all made of the chip of model TJA1050.
The end STM32 embedded software, the first CAN controller peripheral hardware built in STM32, realizes the transmitting-receiving of data frame, and pass through
The data frame of receiving is switched to physical layer differential signal by the first CAN transceiver, and is transmitted to fpga chip by CAN bus.
The second CAN controller is designed using Verilog hardware description language at the end FPGA, using hardware logic and state machine
Mode controls, and without soft core and stone CPU, and uses AVALON bus general-purpose interface form, logical with AVALON bus IP Core interface
With to facilitate subsequent expansion AVALON bus.
Second CAN controller include register module, send fifo module, data flow processing module, time-sequence control module,
It receives data filter, receive fifo module, error detection module state machine module.
Register module include control register, write RAM and read RAM, control register be used for by control register with
Other logic modules are communicated in fpga chip, and are write for data to be sent according to ID+ length+data frame format
Enter to write RAM, received data message is stored in and reads RAM；Specifically, control register includes command register and Status register
Device, command register is used to receive the order that other logic modules are sent in fpga chip, and controls the first CAN controller；Shape
State register is used to read the information of the first CAN controller, including current state information and error message.
Fifo module is connect with register module, buffered data when for sending data.
Data flow processing module includes CAN protocol group packet module and CRC check module, and being used for will according to CAN bus agreement
The data group to be sent is bundled into CAN message data flow, and for unpacking received message data stream, obtaining receiving message.Number
CAN message data flow is bundled into according to the data group that stream process module to be sent as follows:
(1) data frame CRC16 check bit is calculated；
(2) data bit, including frame start bit, ACK, End of Frame are added according to CAN bus agreement；
(3) it packages processing to ID and data frame, group is bundled into CAN message data flow.
Time-sequence control module is connect with data flow processing module, and passes through CAN_RX data line and CAN_TX data line and the
The connection of two CAN transceivers for monitoring CAN bus timing and synchronous with bus timing holdings, and is used to be sent out according to bus timing
Send or receive CAN bus data flow.When wherein sending CAN bus data flow, when by CAN message synchronization of data streams at CAN bus
Sequence, and CAN message data flow is sent to the second CAN transceiver by CAN_TX data line, object is changed by the second CAN transceiver
STM32 or other nodes are sent to by CAN bus after reason layer differential signal；When receiving CAN bus data flow, pass through CAN_RX
After data line receives the message data stream of the second CAN transceiver transmission, time-sequence control module is received according to bus timing,
And received message data stream is sent to data flow processing module and is unpacked.
It receives data filter to connect with data flow processing module, be filtered for docking receiving text, after obtaining filtering
Receive message.
It receives fifo module and is connect with data filter is received, be followed by receiving text for caching filtering, and filtering is followed by
RAM is read in receiving text write-in.
Error detection module is for each bit-errors of detection data stream and carries out error count.
State machine module is used to control the working condition of other each modules in addition to sending fifo module and receiving fifo module
Conversion, and for monitoring control register, reading RAM and write RAM.
When FPGA sends data, communication is using extension frame, data frame, 29 ID, traffic rate 500Kbps, process are as follows:
After data to be sent write RAM according to ID+ length+data frame format；
The data to be sent are buffered by sending fifo module, and are sent according to fifo mode data to be sent
Enter data flow processing module；
By data flow processing module calculate data frame CRC16 check bit, according to CAN bus agreement add frame start bit,
The data bit such as ACK, End of Frame package processing to ID and data frame, and group is bundled into CAN message data flow, and by CAN message number
According to streaming into timing Logic control module；
Time series stereodata module plays bat according to clock count, by CAN message synchronization of data streams at CAN bus timing, and
Data flow is sent to the second CAN transceiver by CAN_TX data line, after the second CAN transceiver changes into physical layer differential signal
It is sent to STM32 or other nodes by CAN bus, time-sequence control module is responsible for monitoring CAN bus timing, and and bus simultaneously
Timing keeps synchronizing.
When FPGA receives data, process are as follows:
After CAN_RX signal wire receives the message data stream of the second CAN transceiver, received message data stream is passed to
Time-sequence control module；
Time-sequence control module is received according to bus timing, and is sent to data flow processing module；
Data flow processing module unpacks received message data stream, then calculates CRC16 check bit and is compared
Compared with appearance mistake is then sent into error detection module and is counted and notified state machine module, while giving up present frame, when mistake goes out
Now after certain number, state machine jumps into error condition, terminates to receive, and reception data filter is then sent into after verification is correct and is reported
Text filtering, the message for choosing needs is sent into after receiving FIFO buffering reads RAM, reads for other modules of FPGA.
In the present embodiment, chip of the fpga chip using the model EP4CE115F29C7 of altera corp, STM32 core
Piece uses the chip of the model STM32F407ZGT6 of ST company.
The communication control at the end FPGA and the end STM32 realizes that the end STM32 is logical at the end FPGA by hardware logic and state machine
Cross software programming realization.Specific implementation process is that FPGA passes through CAN controller to STM32 transmission data packet, and STM32 passes through interruption
Mode is received.
STM32 sends data to FPGA by the first CAN controller peripheral hardware and CAN bus, and FPGA is in a parallel fashion to shape
State register and reading RAM are polled detection, after the completion of detecting data receiver, are read out, complete to data in RAM are read
It receives.
Embodiment described above is only to absolutely prove preferred embodiment that is of the invention and being lifted, protection model of the invention
It encloses without being limited thereto.Those skilled in the art's made equivalent substitute or transformation on the basis of the present invention, in the present invention
Protection scope within.Protection scope of the present invention is subject to claims.
Claims (8)
1. the bus communication system under vehicle environment between FPGA and STM32, it is characterised in that for realizing fpga chip with
By the hetero-com-munication of CAN bus between STM32 chip, the bus communication system includes:
First CAN controller, first CAN controller is built in STM32 chip, for carrying out data transmit-receive；
First CAN transceiver, first CAN transceiver are connect with the first CAN controller, for STM chip access CAN is total
Line；
Second CAN controller, second CAN controller is built in fpga chip, for carrying out data transmit-receive；
Second CAN transceiver, second CAN transceiver are connect with the second CAN controller, for FGPA chip to be accessed CAN
Bus；
Communication control module, the communication control module is built in fpga chip, and connect with the second CAN controller, for controlling
Make the second CAN controller.
2. the bus communication system under vehicle environment according to claim 1 between FPGA and STM32, it is characterised in that the
One CAN controller carries out data receiver using interrupt mode.
3. the bus communication system under vehicle environment according to claim 1 or 2 between FPGA and STM32, feature exist
Pass through between the first CAN transceiver and the first CAN controller and between the second CAN transceiver and the second CAN controller
CAN_RX data line and CAN_TX data line are attached.
4. the bus communication system under vehicle environment according to claim 1 between FPGA and STM32, it is characterised in that the
One CAN transceiver is the chip of model TJA1050, for received data frame to be switched to physical layer differential signal, and is passed through
CAN bus is transmitted to fpga chip.
5. the bus communication system under vehicle environment according to claim 3 between FPGA and STM32, it is characterised in that the
Two CAN controllers are controlled using hardware logic and state machine mode, without soft core and stone CPU, and it is general using AVALON bus
Interface form, with AVALON bus IP Core Universal joint.
6. the bus communication system under vehicle environment according to claim 5 between FPGA and STM32, it is characterised in that the
Two CAN controllers include:
Register module, the register module include control register, write RAM and read RAM, for by control register with
Other logic modules are communicated in fpga chip, and are write for data to be sent according to ID+ length+data frame format
Enter to write RAM, received data message is stored in and reads RAM；
Fifo module is sent, the fifo module is connect with register module, buffered data when for sending data；
Data flow processing module, the data flow processing module according to CAN bus agreement data group to be sent for being bundled into
CAN message data flow, and for being unpacked received message data stream, obtaining receiving message；
Time-sequence control module, the time-sequence control module are connect with data flow processing module, and by CAN_RX data line and
CAN_TX data line is connect with the second CAN transceiver, for monitoring CAN bus timing and synchronous with bus timing holding, is used in combination
In sending or receiving CAN bus data flow according to bus timing；
Data filter is received, the reception data filter is connect with data flow processing module, is carried out for docking receiving text
Filtering obtains filtering and is followed by receiving text；
Fifo module is received, the reception fifo module is connect with data filter is received, it is followed by receiving text for caching filtering,
And filtering is followed by the text write-in reading RAM that receives telegraph；
Error detection module, the error detection module is for each bit-errors of detection data stream and carries out error count；
State machine module, the state machine module is for controlling other each modules in addition to sending fifo module and receiving fifo module
Working condition conversion, and for monitor control register, read RAM and write RAM.
7. the bus communication system under vehicle environment according to claim 6 between FPGA and STM32, it is characterised in that control
Register processed includes:
Command register, the command register is used to receive the order that other logic modules are sent in fpga chip, and controls
First CAN controller；
Status register, the status register are used to read the information of the first CAN controller, including current state information and mistake
False information.
8. the bus communication system under vehicle environment according to claim 6 between FPGA and STM32, it is characterised in that number
It include CAN protocol group packet module and CRC check module according to stream process module；
Data flow processing module is bundled into CAN message data flow for the data group to be sent as follows:
Calculate data frame CRC16 check bit；
Data bit, including frame start bit, ACK, End of Frame are added according to CAN bus agreement；
It packages processing to ID and data frame, group is bundled into CAN message data flow.
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| CN111628920A (en) * | 2020-05-28 | 2020-09-04 | 上海辰瞻医疗科技有限公司 | Intercommunication method between multiple serial interface devices |
| CN115327999A (en) * | 2022-09-07 | 2022-11-11 | 大连理工大学 | AGV control circuit based on STM32 chip and FPGA |
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Application publication date: 20191011 |