CN213399265U

CN213399265U - FPGA-based field bus control circuit device

Info

Publication number: CN213399265U
Application number: CN202022692080.5U
Authority: CN
Inventors: 曹鹏飞
Original assignee: Tianjin Sino German University of Applied Sciences
Current assignee: Tianjin Sino German University of Applied Sciences
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2021-06-08
Anticipated expiration: 2030-11-19

Abstract

The utility model relates to a field bus control circuit device based on FPGA realizes mainly is applied to industrial automation control field. The device comprises an FPGA chip, a CAN bus controller, a CAN bus transceiver, a level conversion chip, an RS485 interface chip, an optical module and an industrial personal computer, wherein the industrial personal computer is connected with the FPGA chip through the optical module, the FPGA chip is connected with the CAN bus controller through the level conversion chip, the CAN bus controller is connected with the CAN bus transceiver, and the FPGA chip is connected with the RS485 interface chip. The utility model discloses can be used to industrial automation control field bus information acquisition and control system, reduce product design and maintenance cost, save storage resource, stability is good.

Description

FPGA-based field bus control circuit device

Technical Field

The utility model belongs to the industrial automation control field, in particular to field bus control circuit device based on FPGA realizes.

Background

The Field bus (Field bus) is an industrial data bus that has developed rapidly in recent years. The intelligent management system is mainly used for processing digital communication among field devices such as controllers, actuating mechanisms, intelligent instruments and meters and the like in an industrial field and data transmission between the management control system and the field control devices. The field bus has the advantages of simple use, stability, reliability, economy, practicality and the like, thereby being widely applied to the field of industrial automation.

A controller Area network (can), which belongs to the field of field bus, is a serial communication network that effectively supports a distributed control system, and is widely applied in the fields of automobile industry, aviation industry, industrial control, safety protection, etc. The CAN bus is a serial communication bus developed by bosch company, germany, specifically for the automotive industry in the 80 s of the 20 th century. When the signal transmission distance reaches 10km, CAN still provide a data transmission rate of up to 50kbit/s and CAN detect bit errors in the data stream. Compared with a common communication bus, the CAN bus has good data communication reliability, real-time performance and flexibility, very high real-time performance and application range, CAN be randomly collocated from a high-speed network with the bit rate up to 1Mbps to a low-cost multi-line 50Kbps network, and is widely applied to various fields.

Although the existing field bus control circuit device CAN realize the control of the CAN bus and the 485 bus, a plurality of special chips are needed, and the device has a complex structure and high cost.

Disclosure of Invention

The utility model discloses to the technical problem who exists among the prior art, provide a field bus control circuit device based on FPGA realizes, CAN realize conversion and remote transmission that 1 way CAN bus data and 2 way 485 bus data arrive the ethernet data, utilize FPGA to simplify the structure, save the cost.

The utility model adopts the technical proposal that: the utility model provides a field bus control circuit device based on FPGA realizes, includes FPGA chip, CAN bus controller, CAN bus transceiver, level conversion chip, RS485 interface chip, optical module and industrial computer, the industrial computer passes through the optical module and is connected with the FPGA chip, the FPGA chip passes through the level conversion chip and is connected with CAN bus controller, CAN bus controller is connected with CAN bus transceiver, the FPGA chip is connected with RS485 interface chip.

The CAN bus transceiver is connected to the control equipment through a CAN bus, and the RS485 interface chip is connected to the control equipment through an RS485 bus.

The FPGA chip is connected with the crystal oscillator.

The FPGA chip comprises a clock processing circuit, a data scheduling and forwarding circuit, a CAN bus interface processing circuit, an RS485 interface processing circuit, an Ethernet data frame processing circuit, an Ethernet optical port processing circuit and a BLOCK RAM control circuit, wherein the data scheduling and forwarding circuit is connected with the CAN bus interface processing circuit, the RS485 interface processing circuit, the Ethernet data frame processing circuit and the BLOCK RAM control circuit, the Ethernet data frame processing circuit is connected with the Ethernet optical port processing circuit, and the clock processing circuit is used for providing a clock.

The FPGA chip adopts XC7VX485T-FFG1157 from XILINX company.

The CAN bus controller adopts SJA1000 of PHILIPS company.

The number of the RS485 interface chips is two.

The working principle is as follows: the industrial personal computer mainly completes the control of field bus signals, the state monitoring function and the human-computer interaction function; the FPGA chip mainly receives, processes and forwards CAN bus signals, RS485 bus signals and Ethernet data signals; the level conversion chip mainly completes the level conversion matching function; the CAN bus controller mainly completes the control function of CAN bus signals; the CAN bus transceiver mainly completes the transceiving function of CAN bus physical layer data signals.

The data scheduling and forwarding circuit of the FPGA chip is connected with other circuits in the FPGA chip and is responsible for scheduling and forwarding data of each unit circuit. The CAN bus interface processing circuit is connected with the data scheduling and forwarding circuit and is connected to the CAN bus controller through an address data bus. The two RS485 interface processing circuits are connected with the data scheduling and forwarding circuit and are respectively accessed to the RS485 bus through the RS485 interface chips. The data receiving and transmitting signals of the Ethernet data frame processing circuit are connected with the data scheduling and forwarding circuit, and the Ethernet framing signals are connected with the Ethernet optical port processing circuit. The Ethernet optical interface processing circuit is connected with the Ethernet data frame processing circuit, and the Ethernet physical layer signal is connected to the optical module. The BLOCK RAM control circuit is connected with the data scheduling and forwarding circuit. The clock processing circuit is externally connected with a crystal oscillator and outputs a clock of 1MMHz, 125MHz and a clock of 24 MHz.

Compared with the prior art, the utility model discloses the beneficial effect who has is: the utility model discloses a accomplish the function that utilizes special chip could realize in the FPGA chip, CAN realize conversion and remote transmission of CAN bus, RS485 bus data to ethernet data, the operation is stable, reliable, easy operation, maintenance convenience, has reached the designing requirement. The utility model discloses can be used to industrial automation control field bus information acquisition and control system, reduce product design and maintenance cost, save storage resource, stability is good.

Drawings

Fig. 1 is a schematic structural diagram of an embodiment of the present invention;

fig. 2 is the schematic diagram of the internal structure of the FPGA chip according to the embodiment of the present invention.

Detailed Description

In order to make the technical solution of the present invention better understood by those skilled in the art, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.

The embodiment of the utility model provides a field bus control circuit device based on FPGA realizes, as shown in FIG. 1, it includes FPGA chip, CAN bus controller, CAN bus transceiver, level conversion chip, two way RS485 interface chips, optical module and industrial computer, the industrial computer passes through the optical module and is connected with the FPGA chip, the FPGA chip adopts XC7VX485T-FFG1157 of XILINX company. The FPGA chip is connected with a CAN bus controller through a level conversion chip, and the CAN bus controller adopts SJA1000 of PHILIPS company. The CAN bus controller is connected with the CAN bus transceiver, the CAN bus transceiver is connected to the control equipment through a CAN bus, the FPGA chip is connected with the RS485 interface chip, and the RS485 interface chip is connected to the control equipment through an RS485 bus. The FPGA chip is connected with the crystal oscillator. The industrial personal computer mainly completes the control of field bus signals, the state monitoring function and the human-computer interaction function; the optical module mainly completes the conversion function between Ethernet photoelectric signals; the FPGA chip mainly receives, processes and forwards CAN bus signals, RS485 bus signals and Ethernet data signals; the crystal oscillator provides a 125MHz high-precision low-jitter clock signal for the FPGA chip; the level conversion chip mainly completes the level conversion matching function; the CAN bus controller mainly completes the control function of CAN bus signals; the CAN bus transceiver mainly completes the transceiving function of CAN bus physical layer data signals; the RS485 interface chip mainly completes the level conversion function of the RS485 interface.

As shown in fig. 2, the FPGA chip includes a clock processing circuit, a data scheduling forwarding circuit, a CAN bus interface processing circuit, an RS485 interface processing circuit, an ethernet data frame processing circuit, an ethernet optical port processing circuit, and a BLOCK RAM control circuit inside, the data scheduling forwarding circuit is connected to the CAN bus interface processing circuit, the RS485 interface processing circuit, the ethernet data frame processing circuit, and the BLOCK RAM control circuit, the ethernet data frame processing circuit is connected to the ethernet optical port processing circuit, and the clock processing circuit is used to provide a clock.

After the device is powered on, the system firstly initializes each unit. The FPGA chip is accessed into the CAN bus through the CAN bus controller and the CAN bus transceiver, and is accessed into the RS485 bus through the RS485 interface chip. The CAN bus controller realizes the receiving, sending and storing of data by realizing a CAN bus protocol. The CAN bus transceiver realizes the transmission of CAN bus physical layer data. The FPGA chip internally realizes the storage, processing and conversion among the 1-path CAN bus, the 2-path RS485 bus and the 1-path Ethernet data. The industrial personal computer and the FPGA chip are communicated through the Ethernet interface, the optical module converts an electric signal into an optical signal and sends the optical signal to the industrial personal computer through optical fibers, CAN bus and RS485 bus data CAN be received and sent remotely, and data display and interface state monitoring are achieved on the industrial personal computer.

The clock processing circuit is realized by calling an FPGA IP core, inputs a 125MHz clock, outputs the 125MHz clock as a main working clock of a system and serves as a reference clock of an FPGA GTP high-speed transceiver; outputting a 1MMHz clock as a working reference clock of an RS485 bus; and outputting the 24MMHz clock as the working reference clock of the CAN bus controller.

The data scheduling and forwarding circuit is connected with each circuit and is responsible for scheduling and forwarding data of each unit circuit. FIFO buffer is realized by controlling a BLOCK RAM control circuit, and buffer processing of data in different time domains is completed.

The CAN bus interface processing circuit completes analysis and processing of a CAN bus protocol. The interface is connected with the CAN bus controller through an address data bus, and the address bus and the data bus are multiplexed in a time-sharing mode. And the CAN bus state machine is controlled to realize the receiving and sending of data. The state machine includes an initialization state, a query state, a transmit state, and a receive state. The initialization state sets a receiving verification code register, a receiving shielding register and a bus timing register, and the control register is set to be in a working mode. Setting 0AH and 0BH address registers in the sending state, writing sending data in the registers from 0CH to 13H, and writing a sending request in the register 01H. The data information is received in the reception status pair 14H-1 DH. In the inquiry state, the bus state is judged by inquiring the state register 02H or the interrupt register 03H.

The RS485 interface processing circuit completes the analysis and processing of an RS485 protocol, and the RS485 bus is accessed through the RS485 interface chip, so that the control of RS485 bus equipment is realized.

The Ethernet data frame processing circuit realizes an Ethernet UDP protocol, additional communication data cannot be added by adopting a UDP communication mode, the communication speed is higher than that of a TCP mode, and the real-time requirement of an industrial field is favorably ensured. And finishing the framing and unframing processing of the Ethernet data frame according to the UDP protocol format requirement.

The Ethernet optical interface processing circuit utilizes a GTP high-speed transceiver IP core in the FPGA to complete the parallel-to-serial conversion and the serial-to-parallel conversion of 8-bit parallel data, and the line speed is 1 GHz. The line transmission code pattern adopts 8B/10B coding.

The BLOCK RAM control circuit realizes the storage of data, and the read-write operation of the data is realized by controlling the BLOCK RAM storage module in the FPGA.

The present invention has been described in detail with reference to the embodiments, but the description is only exemplary of the present invention and should not be construed as limiting the scope of the present invention. The protection scope of the present invention is defined by the claims. Technical scheme, or technical personnel in the field are in the utility model technical scheme's inspiration the utility model discloses an essence and protection within range, design similar technical scheme and reach above-mentioned technological effect, perhaps to the impartial change that application scope was made and improve etc. all should still belong to within the protection scope is covered to the patent of the utility model.

Claims

1. The utility model provides a field bus control circuit device based on FPGA realizes which characterized in that: including FPGA chip, CAN bus controller, CAN bus transceiver, level conversion chip, RS485 interface chip, optical module and industrial computer, the industrial computer passes through the optical module and is connected with the FPGA chip, the FPGA chip passes through the level conversion chip and is connected with CAN bus controller, CAN bus controller is connected with CAN bus transceiver, the FPGA chip is connected with RS485 interface chip.

2. The FPGA-based fieldbus control circuit apparatus of claim 1, wherein: the CAN bus transceiver is connected to the control equipment through a CAN bus, and the RS485 interface chip is connected to the control equipment through an RS485 bus.

3. The FPGA-based fieldbus control circuit apparatus of claim 1, wherein: the FPGA chip is connected with the crystal oscillator.

4. The FPGA-based fieldbus control circuit apparatus of claim 1 or 2, wherein: the FPGA chip comprises a clock processing circuit, a data scheduling and forwarding circuit, a CAN bus interface processing circuit, an RS485 interface processing circuit, an Ethernet data frame processing circuit, an Ethernet optical port processing circuit and a BLOCK RAM control circuit, wherein the data scheduling and forwarding circuit is connected with the CAN bus interface processing circuit, the RS485 interface processing circuit, the Ethernet data frame processing circuit and the BLOCK RAM control circuit, the Ethernet data frame processing circuit is connected with the Ethernet optical port processing circuit, and the clock processing circuit is used for providing a clock.

5. The FPGA-based fieldbus control circuit apparatus of claim 1, wherein: the FPGA chip adopts XC7VX485T-FFG1157 from XILINX company.

6. The FPGA-based fieldbus control circuit apparatus of claim 1, wherein: the CAN bus controller adopts SJA1000 of PHILIPS company.

7. The FPGA-based fieldbus control circuit apparatus of claim 1, wherein: the number of the RS485 interface chips is two.