JP2012044087A - Laser driving circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve low power consumption when a laser is quenched without lowering reliability of a laser driving circuit.SOLUTION: A modulation circuit 1 has a gate circuit 10 which controls supply and interruption of a modulation current in response to a burst circuit control signal CTL1, current source circuits 14-17, and a circuit current control circuit 18 which controls supply and interruption of a current by the circuits 14-17 in response to a current source circuit control signal CTL2. A bias circuit 3a has a bias current control circuit 30 which controls supply and interruption of a bias current in response to the signal CTL1, a current source circuit 31, and a circuit current control circuit 32 which controls supply and interruption of a current by the circuit 31 in response to the signal CTL2. A control signal generating circuit 5 delays the signal CTL2 behind the signal CTL1 when switching is made from emission to quenching, and delays the signal CTL1 behind the signal CTL2 when switching is made from quenching to emission.

Description

  The present invention relates to a laser driving circuit constituted by a semiconductor integrated circuit, and more particularly, to a circuit current in a direct modulation type laser driving circuit corresponding to a burst mode operation in which a laser is driven according to a data signal inputted in bursts. It relates to the technology to control.

In the burst laser driver, it is a major premise that the laser can be turned on / off according to the burst control signal.
FIG. 8 is a block diagram showing a configuration example of a burst laser driving circuit (BLDD) capable of operating at an ultra high speed. Here, a configuration using a general differential circuit with high-speed operation is illustrated. The present invention also assumes a differential circuit, but the principle is the same for a single phase.

  The BLDD is a modulation circuit 1 that applies a modulation current corresponding to a data signal Data to a laser diode (LD) 4 and a modulation / bias current automatic control (APC) that controls the modulation current and bias current to be applied to the LD 4 to be optimal. Automatic Power Control) circuit 2 and bias circuit 3 for applying a bias current to LD 4. In FIG. 8, L1 is supplied with a laser power supply voltage VCCLD at one end and the other end is connected to the anode of the LD4. It is a connected coil.

The modulation circuit 1 includes a gate circuit 10 serving as a modulation control unit whose on / off is controlled by a transmission permission signal TX_EN input from the outside, predrive circuits 11 and 12, an output buffer circuit 13, a gate A current source circuit 14 for supplying a constant current to the circuit 10, a current source circuit 15 for supplying a constant current to the pre-drive circuit 11, a current source circuit 16 for supplying a constant current to the pre-drive circuit 12, and an output buffer circuit 13 And a current source circuit 17 for supplying a constant current.
The bias circuit 3 includes a bias current control circuit 30 and a current source circuit 31 that supplies a constant current to the bias current control circuit 30.

  In the modulation circuit 1, the output buffer circuit 13 is usually driven by a plurality of predrive circuits 11 and 12. The gate circuit 10 is often arranged at the input portion of the BLDD, but is inserted between the BLDD-IC and the IC that outputs the data signal Data as an external IC separately from the BLDD chip (BLDD-IC). There are many cases. The gate circuit 10 is logically an AND circuit.

  That is, the gate circuit 10 outputs a low signal when the transmission permission signal TX_EN is low, and the same logic as the high or low data signal Data when the transmission permission signal TX_EN is high. The signal is output. Normally, the gate circuit 10 also has a differential circuit configuration in order to realize high-speed control. When the gate circuit 10 has a differential circuit configuration and transmission is permitted when the transmission permission signal TX_EN is high, that is, when data transmission is prohibited when the transmission permission signal TX_EN is low, the positive phase side of the gate circuit 10 is AND logic and reverse-phase side are OR logic (see Non-Patent Document 1).

  In general, the bias current and modulation current of the LD 4 are optimized by the bias current control voltage VCSB and the modulation current control voltage VCSM output from the APC circuit 2. That is, the bias circuit 3 performs control so that a bias current corresponding to the bias current control voltage VCSB flows through the LD 4. The current source circuit 15, the current source circuit 16, and the current source circuit 17 modulate the current by supplying a current corresponding to the modulation current control voltage VCSM to the predrive circuit 11, the predrive circuit 12, and the output buffer circuit 13, respectively. A modulation current corresponding to the current control voltage VCSM is caused to flow through the LD 4. When receiving the transmission permission signal TX_EN for instructing the data transmission inhibition, the APC circuit 2 stores and holds the values of the modulation current control voltage VCSM and the bias current control voltage VCSB immediately before that.

  9A and 9B are diagrams for explaining how the quenching of the LD 4 can be realized by the operation of the transmission permission signal TX_EN and the gate circuit 10, and FIG. FIG. 9B is a circuit diagram showing a configuration example of the bias circuit 3, and FIG. 9B is a circuit diagram showing a configuration example of the buffer circuit 13 and the current source circuit 17.

  The output buffer circuit 13 includes a transistor Q1 whose base is connected to the differential input terminal ISPB on the positive phase side, a transistor Q2 whose base is connected to the differential input terminal ISNB on the negative phase side, and a power supply voltage VCC at one end. A resistor R1 having the other end connected to the collector of the transistor Q1, a power supply voltage VCC applied to one end, a resistor R2 having the other end connected to the collector of the transistor Q2, and one end connected to the emitter of the transistor Q1. The other end of the resistor R3 is connected to the current source circuit 17, and the other end is connected to the emitter of the transistor Q2, and the other end is connected to the current source circuit 17. The current source circuit 17 is provided with a modulation current control voltage VCSM at its base, a current source transistor Q3 whose collector is connected to the other ends of the resistors R3 and R4, and one end connected to the emitter of the current source transistor Q3. Is composed of a grounded resistor R5. Note that the current source circuits 14, 15, 16 also have the same configuration as the current source circuit 17.

  The anode of LD4 is connected to the positive phase output terminal LDP which is a connection point between the collector of the transistor Q2 and the resistor R2, and the cathode of LD4 is connected to the negative phase output terminal LDN which is a connection point between the collector of the transistor Q1 and the resistor R1. Is done. When the transmission enable signal TX_EN changes from high (transmission enabled) to low (data transmission prohibited), the differential input terminal ISNB on the LDP side becomes high and the differential input terminal ISPB on the LDN side becomes low by the operation of the gate circuit 10. Thus, the positive phase output terminal LDP is fixed at a low impedance, the negative phase output terminal LDN is fixed at a high impedance, and the modulation data signal output stops.

  On the other hand, the bias circuit 3 also has a differential circuit configuration. As described above, the bias circuit 3 includes the bias current control circuit 30 and the current source circuit 31. The bias current control circuit 30 is provided with a burst circuit control signal TX_EN_P at its base, a transistor Q4 whose collector is connected to the other end of the coil L2, a transistor Q5 whose base is supplied with a burst circuit control signal TX_EN_N, and a power supply at one end. The voltage VCC2 is applied, the other end of the resistor R6 is connected to the collector of the transistor Q5, the other end is connected to the emitter of the transistor Q4, the other end is connected to the current source circuit 31, and the other end is the transistor Q5. And a resistor R8 having the other end connected to the current source circuit 31. The current source circuit 31 is supplied with a bias current control voltage VCSB at its base, the collector is connected to the other ends of the resistors R7 and R8, one end is connected to the emitter of the current source transistor Q6, and the other end Is composed of a grounded resistor R9.

  The collector of the transistor Q4 is connected to the cathode LDK of the LD4 via the coil L2. When the LD 4 emits light, a current flows through the transistor Q4 to which the LD 4 is connected, and when the light is extinguished, a current flows through the transistor Q5 to which the power supply is connected. For example, when the transmission permission signal TX_EN is a CMOS level signal, this signal is differentiated by a level conversion circuit (not shown) and converted into level-adjusted burst circuit control signals TX_EN_P and TX_EN_N. Burst circuit control signal TX_EN_P is input to the differential input terminal (base of transistor Q4) to which LD4 is connected, and burst circuit control signal TX_EN_N is the differential input terminal (base of transistor Q5) to which power is connected. Is input.

  When the transmission permission signal TX_EN changes from high (transmission permission) to low (data transmission prohibition), the burst circuit control signal TX_EN_P becomes low, the burst circuit control signal TX_EN_N becomes high, and the current flowing through the LD 4 is cut off. Thus, the quenching operation of both the modulation circuit 1 and the bias circuit 3 realizes the quenching of the LD 4.

SY88216L, 3.3V 2.5 Gbps Burst Mode Laser Driver data sheet, Microl INC. , <Http: // www. micrel. jp / doc / products / digital / OPT_laser-driver. html>

  In the conventional differential switching method, the circuit current consumption basically does not change when the laser is turned on / off. The reason is that the amount of current consumed by the circuit is determined by the amount of current flowing by the current source transistor of each current source circuit, and this amount of current is determined by the modulation current control voltage VCSM and the bias current control voltage VCSB output from the APC circuit 2. It is because it has been.

  In order to reduce the current consumption of the laser driving circuit, the current source current is cut off by turning off the current source transistors of the current source circuits 15 to 17 and 31 by the modulation current control voltage VCSM and the bias current control voltage VCSB when the laser is extinguished. This can be realized, but it involves a sudden increase or decrease in current in the process of recovering from the interrupted state to the energized state, or in the process of shifting from the energized state to the interrupted state. In particular, it is not uncommon for the current flowing through the laser to be 100 mA or more, and such sudden energization and interruption of a large current can be a heavy burden on the circuit. There is a risk that it is difficult to maintain the breakdown voltage and ensure reliability.

  An object of the present invention is to provide a laser driving circuit capable of realizing low power consumption during laser extinction without lowering the reliability of the laser driving circuit in order to solve such a problem of the conventional configuration. And

The present invention provides a laser driving circuit that supports burst mode operation, comprising: a bias circuit that applies a bias current to the laser; and a modulation circuit that applies a modulation current corresponding to an input data signal to the laser; A gate circuit for controlling the supply and cutoff of the modulation current in accordance with a burst circuit control signal, a first current source circuit for supplying current to a component circuit in the modulation circuit including the gate circuit, and the first current source A first circuit current control circuit that controls supply and interruption of current by the circuit according to a current source circuit control signal, and the bias circuit supplies and interrupts the bias current according to the burst circuit control signal. A bias current control circuit that controls the current, a second current source circuit that supplies current to the bias current control circuit, and supply of current by the second current source circuit And a second circuit current control circuit that controls the interruption according to the current source circuit control signal, and the timings of the burst circuit control signal and the current source circuit control signal are different from each other. is there.
Further, in one configuration example of the laser driving circuit of the present invention, the burst circuit control signal having a binary logic level from the transmission permission signal having a binary logic level for controlling the emission and extinction of the laser and the current source are further provided. A control signal generation circuit that generates at least one of the circuit control signals is provided.

In one configuration example of the laser drive circuit of the present invention, the control signal generation circuit includes a delay circuit, outputs the transmission permission signal as the burst circuit control signal, and outputs a signal obtained by delaying the transmission permission signal. It outputs as the said current source circuit control signal, It is characterized by the above-mentioned.
In one configuration example of the laser driving circuit according to the present invention, the control signal generation circuit includes a delay circuit, outputs the transmission permission signal as the current source circuit control signal, and delays the transmission permission signal. Is output as the burst circuit control signal.
Further, in one configuration example of the laser driving circuit of the present invention, the control signal generation circuit delays the current source circuit control signal by delaying from turning off the burst circuit control signal when the laser is switched from light emission to quenching. When the laser is switched from extinction to light emission, the burst circuit control signal is turned on with a delay from the turning on of the current source circuit control signal.
In one configuration example of the laser drive circuit of the present invention, the control signal generation circuit includes the delay circuit, an AND circuit, and an OR circuit, and the transmission permission signal and the transmission permission signal are transmitted to the transmission circuit. The signal delayed by the delay circuit is input to the AND circuit and the OR circuit, the output of the AND circuit is output as the burst circuit control signal, and the output of the OR circuit is controlled by the current source circuit It outputs as a signal.

In the configuration example of the laser driving circuit of the present invention, the modulation circuit further includes an output buffer circuit, and an output of the gate circuit is connected to an input of the output buffer circuit, and an output of the output buffer circuit Is connected to the laser, and the bias current control circuit is configured by a differential circuit, and a light emission mode in which the bias current is supplied to the laser by a differential operation according to the burst circuit control signal and the bias current does not flow It is characterized by switching to the extinction mode.
Further, in one configuration example of the laser driving circuit of the present invention, the modulation circuit and the bias current control circuit are configured by a differential circuit, and the gate circuit has an AND logic on the positive phase side and an OR logic on the negative phase side. And the bias current control circuit sends the bias current to the laser when the positive phase side receives the burst circuit control signal having a high level, and the first and second circuit current control circuits are unipolar and bi-polar. The switch includes a throw switch, and the first and second current source circuits cut off or reduce the current in a state where the first and second current source circuits supply a predetermined current according to the current source circuit control signal. It is characterized by switching to either one of the states.

  According to the present invention, the first current source that supplies current to the modulation circuit including the gate circuit that controls the supply and interruption of the modulation current according to the burst circuit control signal, and the circuit in the modulation circuit including the gate circuit. And a first circuit current control circuit for controlling supply and cutoff of current by the first current source circuit in accordance with a current source circuit control signal, and supplying and blocking bias current to the bias circuit in a burst circuit A bias current control circuit controlled according to the control signal, a second current source circuit for supplying current to the bias current control circuit, and current supply and interruption by the second current source circuit according to the current source circuit control signal A second circuit current control circuit that controls the current flowing through the laser during the transition from light emission to extinction by shifting the timing of the burst circuit control signal and the current source circuit control signal. Can suppress variations, it is possible to reduce the burden of the laser device or circuit, without lowering the reliability of the laser driver, it is possible to achieve low power consumption during the extinction of the laser. In the present invention, the power consumption of the laser drive circuit can be increased / decreased at a high speed only by the transmission permission signal. However, such a technique can save power of an ONU (Optical Network Unit) in a PON (Passive Optical Network) system, for example. Demonstrates enormous effect on crystallization. Because, if power control synchronized with light emission and extinction is possible only with a transmission permission signal, a new sleep control signal depending on the protocol of the PON system is unnecessary, and what is necessary if the system satisfies the international standard. This is because power saving means can be added to such a system without changing the pin arrangement of the transceiver. Since no additional signal is required, not only is it advantageous in terms of cost, but an ideal power saving mode can be realized by always reducing the power consumption during the time the laser is off. By using the present invention, it is possible to provide a basic technology that can safely realize such power saving for each burst communication. As a result, in the present invention, circuit design is facilitated, and highly effective power saving can be realized with high reliability.

It is a block diagram which shows the structural example of the laser drive circuit which concerns on the 1st Embodiment of this invention. FIG. 3 is a circuit diagram illustrating a configuration example of an output buffer circuit, a current source circuit, and a circuit current control circuit according to the first embodiment of the present invention. FIG. 3 is a circuit diagram showing a configuration example of a bias circuit in the first embodiment of the present invention. It is a figure which shows one example of the result of the transient characteristic simulation of the output voltage in the laser drive circuit which concerns on the 1st Embodiment of this invention. It is a figure which shows an example of the result of the transient characteristic simulation of the laser current in the 2nd Embodiment of this invention. It is a circuit diagram which shows the structural example of the control signal generation circuit which concerns on the 3rd Embodiment of this invention. It is a timing chart which shows the signal of each part of the control signal generation circuit which concerns on the 3rd Embodiment of this invention. It is a block diagram which shows the structural example of the conventional burst laser drive circuit. It is a circuit diagram which shows the structural example of an output buffer circuit and a bias circuit.

[Principle of the Invention]
A basic feature of the present invention is that a current source circuit current of a component circuit is provided in a laser driving circuit including laser quenching means (a gate circuit for controlling blocking and transmission of a data signal and a bias circuit for turning on / off a laser bias current). A signal for controlling on / off of the laser (burst circuit control signal) and a signal for controlling on / off of the current source circuit current (current source circuit control signal). It acts on the laser drive circuit at different timings.

  For example, the on / off of the laser and the on / off of the current source current are considered with reference to the relationship between ignition / extinguishing of the gas stove and opening / closing of the gas main plug. When the gas main plug is closed, there is no gas supply, so it does not ignite even if the stove is operated. Similarly, if the current source current is cut off, the laser does not emit light even when the laser on / off control is operated. In general, it is a normal procedure to open a gas main plug, operate the stove to ignite, and operate the stove to extinguish the fire before closing the main plug.

Also in the laser driving circuit, the procedure of turning on the laser after applying the current source current and flowing the circuit current to form the extinction state similar to the prior art is a proven and safe method. Also, after turning off the laser in the same procedure as before, that is, cutting off the current of the laser element and then cutting off the current source current cuts off the circuit current when no current flows through the laser element. It is considered that there is little risk of damaging the laser element.
As described above, in the present invention, by separately controlling laser emission / extinction and circuit current supply / cutoff, it is possible to realize low power consumption during extinction without damaging the laser element or the drive circuit itself. .

[First Embodiment]
Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration example of a laser drive circuit according to the first embodiment of the present invention. The same reference numerals are given to the same configurations as those in FIG.
The laser drive circuit of the present embodiment includes a modulation circuit 1a, an APC circuit 2, a bias circuit 3a, and a control signal generation circuit 5.

The modulation circuit 1a includes a gate circuit 10 serving as modulation control means, predrive circuits 11 and 12, an output buffer circuit 13, current source circuits 14 to 17, and a circuit current control circuit 18.
The bias circuit 3a includes a bias current control circuit 30, a current source circuit 31, and a circuit current control circuit 32.

  In the present embodiment, a gate circuit 10 is provided in the subsequent stage of the n-th (n = 2 in the example of FIG. 1) pre-drive circuit 12, and an output buffer circuit 13 is connected to the output of the gate circuit 10. LD4 is DC (direct current) connected to the output. Of course, the LD 4 may be connected by AC (alternating current) connection, but from the viewpoint of the response of the light emission / extinction of the LD 4, a DC connection is advantageous between the modulation circuit 1 a and the LD 4. The cathode of the LD 4 is connected to the bias circuit 3a.

  The transmission permission signal TX_EN is input to the control signal generation circuit 5. The control signal generation circuit 5 generates and outputs a burst circuit control signal CTL1 and a current source circuit control signal CTL2 from the transmission permission signal TX_EN. The control signal generation circuit 5 is a delay circuit, for example, and uses the transmission permission signal TX_EN as the burst circuit control signal CTL1 without delaying, and uses the signal obtained by delaying the transmission permission signal TX_EN as the current source circuit control signal CTL2. Conversely, a signal obtained by delaying the transmission permission signal TX_EN is used as the burst circuit control signal CTL1.

  That is, the control signal generation circuit 5 outputs the burst circuit control signal CTL1 and the current source circuit control signal CTL2 while shifting the timing. Note that the levels of the signals such as the transmission permission signal TX_EN, the burst circuit control signal CTL1, and the current source circuit control signal CTL2 may be levels suitable for the circuit, and these signals may be differential signals.

The gate circuit 10, the pre-drive circuits 11, 12, the output buffer circuit 13, and the bias circuit 3a include independent current source circuits 14, 15, 16, 17, 31, respectively.
The APC circuit 2 generates a modulation current control voltage VCSM and a bias current control voltage VCSB as control voltages for optimizing the modulation current and the bias current flowing through the LD 4 according to the desired output optical power of the LD 4. The modulation current control voltage VCSM is input to a circuit current control circuit 18 provided in each of the current source circuits 14, 15, 16, and 17, and the bias current control voltage VCSB is provided in a circuit current control circuit provided in the current source circuit 31. 32.

  FIG. 2 shows a configuration example of the output buffer circuit 13, the current source circuit 17, and the circuit current control circuit 18. As described with reference to FIG. 9A, the output buffer circuit 13 includes transistors Q1 and Q2 and resistors R1, R2, R3, and R4. The anode of LD4 is connected to the positive phase output terminal LDP which is a connection point between the collector of the transistor Q2 and the resistor R2, and the cathode of LD4 is connected to the negative phase output terminal LDN which is a connection point between the collector of the transistor Q1 and the resistor R1. Is done. The differential input terminal ISPB on the positive phase side of the output buffer circuit 13 is connected to the positive phase output terminal of the gate circuit 10, and the differential input terminal ISNB on the negative phase side is connected to the negative phase output terminal of the gate circuit 10. The

  As in the prior art, the current source circuit 17 includes a current source transistor Q3 and a resistor R5. The difference from the prior art is that the output of the circuit current control circuit 18 is input to the base of the current source transistor Q3.

  In the circuit current control circuit 18, the modulation current control voltage VCSM is input to one input terminal, the voltage VSL (VCSM> VSL) is input to the other input terminal, and the output terminal is connected to the base of the current source transistor Q3. It consists of a single pole double throw switch SW1. The switch SW1 is controlled by a current source circuit control signal CTL2. That is, the switch SW1 selects and outputs the modulation current control voltage VCSM when the current source circuit control signal CTL2 is high (transmission permitted), and when the current source circuit control signal CTL2 is low (data transmission prohibited). Selects and outputs the voltage VSL. Thus, the base potential of the current source transistor Q3 of the current source circuit 17 is switched to either VCSM or VSL.

  The voltage VSL input to the current source transistor Q3 when the LD 4 is extinguished is preferably equal to or lower than the base-emitter voltage Vbe of the current source transistor Q3. Thereby, the circuit current control circuit 18 can turn off the current source transistor Q3 and cut off the current source circuit current flowing through the transistors Q1 and Q2 and the current source transistor Q3. However, in the present embodiment, the mechanism for extinguishing / light-emitting LD 4 by the gate circuit 10 and the mechanism for conducting / cutting off the current source circuit current by the current source circuit 17 and the circuit current control circuit 18 are independent. A value of VSL that does not completely cut off the current source circuit current may be used.

  The configuration of the current source circuits 14, 15 and 16 is the same as that of the current source circuit 17. The configuration of the circuit current control circuit 18 provided in each of the current source circuits 14, 15 and 16 is the same as that in FIG. 2, and the output of the switch SW1 is the base of the current source transistors of the current source circuits 14, 15 and 16. Should be input to

  FIG. 3 shows a configuration example of the bias circuit 3a. As described with reference to FIG. 9B, the bias current control circuit 30 constituting the bias circuit 3a includes transistors Q4 and Q5 and resistors R6, R7, and R8. In the present embodiment, the bias current control circuit 30 has a differential circuit configuration, and the burst circuit control signal CTL1 is also differentiated by the control signal generation circuit 5. The burst circuit control signal CTL1_P on the positive phase side is input to the differential input terminal (base of the transistor Q4) to which LD4 is connected, and the burst circuit control signal CTL1_N on the negative phase side is differential on the side to which the power supply is connected. Input to the input terminal (base of transistor Q5).

  As described above, the gate circuit 10 has AND logic on the positive phase side and OR logic on the negative phase side. That is, when the burst circuit control signal CTL1_P is high (transmission permitted) and the burst circuit control signal CTL1_N is low, the gate circuit 10 outputs a signal having the same logic as the output of the pre-drive circuit 12 in the previous stage to the reverse-phase output terminal. Output from the phase output terminal. As a result, a modulation current corresponding to the data signal Data is given to the LD 4. Further, when the burst circuit control signal CTL1_P is low (transmission prohibited) and the burst circuit control signal CTL1_N is high, the gate circuit 10 outputs a low signal from the positive phase output terminal and a high signal from the negative phase output terminal. Is output. Thereby, the modulation current is cut off.

  As in the prior art, the current source circuit 31 includes a current source transistor Q6 and a resistor R9. The difference from the prior art is that the output of the circuit current control circuit 32 is input to the base of the current source transistor Q6.

  In the circuit current control circuit 32, the bias current control voltage VCSB is input to one input terminal, the voltage VSL (VCSB> VSL) is input to the other input terminal, and the output terminal is connected to the base of the current source transistor Q6. It consists of a single pole double throw switch SW2. The switch SW2 selects and outputs the bias current control voltage VCSB when the current source circuit control signal CTL2 is high (transmission permitted), and the voltage when the current source circuit control signal CTL2 is low (data transmission prohibited). Select VSL and output. As in the case of the current source circuit 17, the voltage VSL is desirably equal to or lower than the base-emitter voltage Vbe of the current source transistor Q6. Thereby, the circuit current control circuit 32 can turn off the current source transistor Q6 and cut off the current source circuit current flowing through the transistors Q4 and Q5 and the current source transistor Q6.

  FIG. 4 is a diagram showing an example of the result of the transient characteristic simulation of the output voltage in the laser drive circuit of the present embodiment. The positive phase output terminal LDP (the anode of LD4) and the negative phase output terminal LDN of the output buffer circuit 13 are shown. The voltage of (LD4 cathode) is shown. Here, the results of simulating the voltage change of the output terminals LDP and LDN when the current source circuit control signal CTL2 is delayed by 10 ns from the burst circuit control signal CTL1 and when not delayed are shown.

  In FIG. 4, 40 indicates the voltage of the output terminal LDP when the current source circuit control signal CTL2 is delayed, and 41 indicates the voltage of the output terminal LDP when the current source circuit control signal CTL2 is not delayed. Reference numeral 42 indicates the voltage at the output terminal LDN when the current source circuit control signal CTL2 is delayed, and reference numeral 43 indicates the voltage at the output terminal LDN when the current source circuit control signal CTL2 is not delayed. The voltage VSL was 0V.

  When there is no delay of the current source circuit control signal CTL2 with respect to the burst circuit control signal CTL1, the burst circuit control signal CTL1 and the current source circuit control signal CTL2 are simultaneously turned off (low) after 50 ns from the start of the simulation, and simultaneously turned on after 150 ns ( High). In this case, as is apparent from the waveforms 41 and 43 in FIG. 4, a large voltage change occurs at the output terminals LDP and LDN at the moment when the current source circuit current is turned off.

  On the other hand, when the current source circuit control signal CTL2 is delayed by 10 ns from the burst circuit control signal CTL1, as is apparent from the waveforms 40 and 42 in FIG. It can be seen that the degree of voltage change is small. In this way, by operating the extinction control of the LD 4 to extinguish the LD 4 and then interrupting the current source circuit current, it is possible to suppress voltage fluctuations of the output terminals LDP and LDN when switching to the power saving mode. . As a result, in the present embodiment, fluctuations in the current flowing through the LD 4 can be suppressed, and the burden on the transistors of the LD 4 and the bias circuit 3a can be reduced, so that the reliability of the laser drive circuit is not reduced. Low power consumption can be realized when the LD 4 is extinguished.

[Second Embodiment]
In the present embodiment, a case will be described in which the burst circuit control signal CTL1 is controlled with a delay of 10 ns from the current source circuit control signal CTL2, contrary to the first embodiment. FIG. 5 is a diagram showing an example of the result of the transient simulation of the laser current in the present embodiment. The configuration of the laser driving circuit and the value of the voltage VSL are the same as those in the simulation example shown in the first embodiment. FIG. 5 shows a case where the energized state is restored from the interrupted state, that is, the case where the burst circuit control signal CTL1 and the current source circuit control signal CTL2 are turned on. In FIG. 5, 60 indicates a laser current when there is no delay of the burst circuit control signal CTL1 with respect to the current source circuit control signal CTL2, and 61 indicates a laser current when the burst circuit control signal CTL1 is delayed.

  Although not shown, in the present embodiment, the voltage change of the output terminals LDP and LDN is almost unchanged with no delay. However, it can be seen that the current flowing through the LD 4 varies greatly without the delay of the burst circuit control signal CTL 1.

  When the burst circuit control signal CTL1 is delayed from the current source circuit control signal CTL2 as in the present embodiment, the modulation by the gate circuit 10 is performed after the currents of the current source circuits 14 to 17, 31 are recovered. Since the operation is started, it can be seen that the time from the start of modulation to the stabilization of the amplitude of the laser current is shorter than when there is no delay of the burst circuit control signal CTL1.

  For example, when there is no delay of the burst circuit control signal CTL1, the burst circuit control signal CTL1 is turned on at 150 ns and the modulation operation is started. However, the amplitude of the laser current is stabilized around 165 ns, It takes about 15 ns for the amplitude of the laser current to stabilize. On the other hand, when the burst circuit control signal CTL1 is delayed, the burst circuit control signal CTL1 is turned on at 160 ns, but the laser current amplitude is stable in the vicinity of 167 ns, and the laser current amplitude is stable. The time to do is about 7 ns. Thus, in this embodiment, it can be seen that good bit data can be transmitted immediately after laser emission.

[Third Embodiment]
In the first embodiment, there is an advantage that the overshoot of the voltages of the output terminals LDP and LDN can be suppressed when the current source circuit current is cut off, but the second embodiment is used when the current source circuit current is recovered. Such benefits are not enjoyed. On the other hand, in the second embodiment, the advantage at the time of cutting off the current source circuit current as in the first embodiment cannot be obtained.

  In order to obtain the effect of the present invention to the maximum, when the laser is switched from light emission to quenching, the current source circuit control signal CTL2 is delayed from the burst circuit control signal CTL1, and conversely, when the laser is switched from quenching to light emission. It is desirable that the burst circuit control signal CTL1 be delayed from the current source circuit control signal CTL2. In this case, the control signal generation circuit 5 cannot be realized by a simple delay circuit.

FIG. 6 is a circuit diagram illustrating a configuration example of the control signal generation circuit 5 according to the present embodiment, and FIG. 7 is a timing chart illustrating signals of respective units of the control signal generation circuit 5.
The control signal generation circuit 5 includes a delay circuit 50 that delays the transmission permission signal TX_EN by, for example, 10 ns, an AND circuit 51 that performs a logical product of the transmission permission signal TX_EN and the signal Dly_TX_EN that is delayed from the transmission permission signal TX_EN, and a transmission permission signal. An OR circuit 52 that takes the logical sum of TX_EN and the signal Dly_TX_EN.

  In the circuit shown in FIG. 6, a signal obtained by the logical product of the transmission permission signal TX_EN and the signal Dly_TX_EN obtained by delaying the transmission permission signal TX_EN is A, and a signal obtained by the logical sum is B. As shown in FIG. 7, when the transmission permission signal TX_EN changes from high (transmission permission) to low (data transmission prohibition), the signal A changes from high to low, and the signal B is also delayed by the delay time by the delay circuit 50. From low to low. When the transmission permission signal TX_EN changes from low to high, the signal B changes from low to high, and the signal A also changes from low to high after a delay time by the delay circuit 50. Therefore, if the signal A is used as the burst circuit control signal CTL1 and the signal B is used as the current source circuit control signal CTL2, the object of the present embodiment can be achieved. When the signal A is used as the burst circuit control signal CTL1 and the signal B is used as the current source circuit control signal CTL2, the signal A high (on) means transmission permission, and the signal A low (off) means transmission prohibition. The high (on) of the signal B means that the current source circuit is on, and the low (off) of the signal B means that the current source circuit is off.

  In the example shown in FIG. 3, the burst circuit control signal CTL1 is differentiated. However, in order to differentiate the burst circuit control signal CTL1, for example, a differential output type AND circuit is used as the AND circuit 51. Needless to say, it can be used.

In the first to third embodiments, the delay time set in the delay circuit of the control signal generation circuit 5 is 10 ns, for example, but the delay time may be set as follows.
In the first to third embodiments, an effect can be obtained if the timings of the burst circuit control signal CTL1 and the current source circuit control signal CTL2 are slightly shifted, but ideally, a rise or fall is required first. The delay time may be set to a value longer than the time required for the circuit to become stable.

If the delay time is long, there is no problem in terms of stable operation of the circuit. However, if the delay time is too long, the time from when the transmission permission signal TX_EN changes until the laser emits / extinguishes becomes longer. Therefore, there is no need to unnecessarily increase the delay time.
The delay time of 10 ns is a value considering the case where a laser drive circuit is used in a subscriber side device (ONU: Optical Network Unit) of a PON (Passive Optical Network) system, for example.

  The present invention can be applied to a technique for controlling circuit current in a laser driving circuit that supports burst mode operation.

  DESCRIPTION OF SYMBOLS 1a ... Modulation circuit, 2 ... APC circuit, 3a ... Bias circuit, 4 ... Laser diode, 5 ... Control signal generation circuit, 10 ... Gate circuit, 11, 12 ... Predrive circuit, 13 ... Output buffer circuit, 14-17, DESCRIPTION OF SYMBOLS 31 ... Current source circuit 18, 32 ... Circuit current control circuit, 30 ... Bias current control circuit, 50 ... Delay circuit, 51 ... AND circuit, 52 ... OR circuit, Q1, Q2, Q3, Q4, Q5, Q6 ... Transistor , R1, R2, R3, R4, R5, R6, R7, R8, R9... Resistors, SW1, SW2.

Claims (8)

In the laser drive circuit that supports burst mode operation,
A bias circuit for applying a bias current to the laser;
A modulation circuit for applying a modulation current corresponding to an input data signal to the laser;
The modulation circuit includes a gate circuit that controls supply and cutoff of the modulation current according to a burst circuit control signal, a first current source circuit that supplies current to a component circuit in the modulation circuit including the gate circuit, A first circuit current control circuit that controls supply and interruption of current by the first current source circuit according to a current source circuit control signal;
The bias circuit includes a bias current control circuit that controls supply and cutoff of the bias current according to the burst circuit control signal, a second current source circuit that supplies current to the bias current control circuit, A second circuit current control circuit that controls supply and interruption of current by the current source circuit according to the current source circuit control signal,
The laser driving circuit, wherein the burst circuit control signal and the current source circuit control signal have different timings. The laser drive circuit according to claim 1, wherein
Further, a control signal generation circuit for generating at least one of the burst circuit control signal having a binary logic level and the current source circuit control signal from a transmission permission signal having a binary logic level for controlling light emission and extinction of the laser A laser driving circuit comprising: The laser drive circuit according to claim 2, wherein
The control signal generation circuit includes a delay circuit, outputs the transmission permission signal as the burst circuit control signal, and outputs a signal obtained by delaying the transmission permission signal as the current source circuit control signal. Laser drive circuit. The laser drive circuit according to claim 2, wherein
The control signal generation circuit includes a delay circuit, outputs the transmission permission signal as the current source circuit control signal, and outputs a signal obtained by delaying the transmission permission signal as the burst circuit control signal. Laser drive circuit. The laser driving circuit according to claim 3 or 4,
The control signal generation circuit turns off the current source circuit control signal with a delay from turning off the burst circuit control signal when the laser switches from light emission to quenching, and turns off the current source circuit control signal when the laser switches from quenching to light emission. A laser driving circuit characterized in that the burst circuit control signal is turned on with a delay from the turning on of the current source circuit control signal. The laser drive circuit according to claim 5, wherein
The control signal generation circuit includes the delay circuit, a logical product circuit, and a logical sum circuit, and the logical product circuit includes the transmission permission signal and a signal obtained by delaying the transmission permission signal by the delay circuit. A laser drive circuit, wherein the laser drive circuit inputs to the OR circuit, outputs the output of the AND circuit as the burst circuit control signal, and outputs the output of the OR circuit as the current source circuit control signal. In the laser drive circuit according to any one of claims 1 to 6,
The modulation circuit further includes an output buffer circuit, an output of the gate circuit is connected to an input of the output buffer circuit, an output of the output buffer circuit is connected to the laser,
The bias current control circuit includes a differential circuit, and switches between a light emission mode in which the bias current flows to the laser and an extinction mode in which the bias current does not flow by a differential operation according to the burst circuit control signal. A featured laser drive circuit. In the laser drive circuit according to any one of claims 1 to 7,
The modulation circuit and the bias current control circuit are configured by a differential circuit,
In the gate circuit, the positive phase side is AND logic and the negative phase side is OR logic.
The bias current control circuit flows the bias current to the laser when the positive phase side receives the burst circuit control signal having a high level,
The first and second circuit current control circuits are configured by single-pole double-throw switches, and the first and second current source circuits supply a predetermined current according to the current source circuit control signal; A laser driving circuit, wherein the first and second current source circuits are switched to one of a state where current is cut off or reduced.

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