JPH1065274A - Driver for light-emitting element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a general purpose interface circuit by providing a high impedance threshold voltage generation circuit, where an interface circuit inputting a data signal is connected with each of a plurality of input terminals, and a circuit for comparing the data signal at respective input terminals. SOLUTION: An input interface circuit has two input terminals (a), (b), wherein one input terminal (a) is connected with a high impedance threshold voltage generation circuit A and the non-inverted input (+) of a comparison circuit CMP. The other input terminal (b) is connected with a high-impedance threshold voltage generation circuit B and the inverted input (-) of the comparison circuit CMP. Consequently, the input terminals (a), (b) are applied with predetermined threshold voltages Vth1 , Vth2 , respectively, and terminated with high impedances. An interface circuit having such a structure can interface with any type of input signal (unbalanced, balanced), thus realizing a general-purpose interface circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device driving device, and more particularly, to a light emitting device (laser diode LD).
Etc.), a driving circuit thereof, and a control circuit for performing constant light output control of the light emitting element.
In recent years, with the spread of optical communication, this type of light emitting element driving device has been widely used as an electric-optical signal conversion device for optical subscribers. In particular, CMOS integrated circuits are being promoted for the LD driver for optical subscribers for the purpose of lowering costs and lowering power consumption.

[0002]

2. Description of the Related Art FIG. 26 is a diagram showing a schematic configuration of a conventional LD driving device. This LD driving device includes an LD driving LSI 200 for performing main control of the LD driving, a load resistor RL corresponding to the LD, a laser diode LD, a photodiode PD for monitoring the back light of the LD, and an LD current control signal V
_{It includes} an external capacitor C1 for holding _PCNT and a resistor R1.

The LD driving LSI 200 includes a main signal unit 50 for processing a data signal and an APC unit 60 for controlling the optical output of the LD to a constant value. In the main signal section 50, 51
Is an input interface circuit for terminating (interface) an input data signal, and 52 is a flip-flop circuit (F) for retiming (pulse width shaping) the input data signal.
F) and 54 are signal detection circuits for extracting a data signal and a clock signal, and 55 is to deactivate (cut off the LD current) the LD drive circuit when data is not transmitted in time division multiplexing (TCM) communication or the like to save power. A power saving control circuit 56 is a pulse width compensating circuit for compensating for (decreasing) a light pulse width due to an LD light emission delay, and 57 is a LD driving pre-stage for performing voltage compression / level shifting of a data signal and matching with an LD driving circuit. The circuit 58 is an LD drive circuit for driving the LD.

In the APC section 60, a reference signal generating circuit 61 generates a predetermined reference signal based on a data signal;
62, an I / V conversion circuit for converting the photocurrent of the PD into a voltage signal; 63, an automatic optical output control (APC) circuit for performing constant control of the optical output of the LD; and 66, the optical output level of the LD being lower than a predetermined level. An optical output alarm circuit 67 for detecting the state of occurrence and generating an alarm signal SALM, and 67 is a current limiting circuit for setting an upper limit of the LD drive current in order to protect the LD and the drive circuit from damage due to overcurrent.

[0005] However, there are some problems to be improved in the above-mentioned conventional LD driving device and each circuit constituting the same. The details will be described below. FIG. 27 is a diagram illustrating a conventional input interface circuit. by the way,
There are various types of data signals (such as balanced type (differential type), unbalanced type (single signal), etc.) and termination characteristics in data signals received from the outside of this type of LD drive LSI. Conventionally, dedicated input interface circuits have been configured for each type of input signal and termination characteristics. Hereinafter, a specific description will be given.

FIG. 27A shows a case where the input signal is a single signal (positive logic input). In this case, one input terminal, a threshold voltage generation circuit, and a comparison circuit CMP are provided, and the input signal IN1 is input to the + input terminal of the CMP,
The threshold voltage (threshold voltage) _Vth generated by the threshold voltage generation circuit is input to the input terminal. The output signal OUT is IN
When 1> _Vth , logic 1 (HIGH) level, IN1 ≦ V
_At the time of _th , it becomes a logic 0 (LOW) level.

FIG. 27B shows a case where the input signal is a single signal (negative logic input). In this case, one input terminal, a threshold voltage generation circuit, and a comparison circuit CMP are provided, and the threshold voltage _Vth is input to the + input terminal of the CMP, and the input signal IN2 is input to the-input terminal of the CMP. Output signal OUT
Is a logic 1 level when IN2 ≦ V _{th and} a logic 0 level when IN2> V _th .

FIG. 27 (C) shows a case where the input signal is of a balanced type (differential input). In this case, two input terminals and one comparison circuit CMP are provided. A balanced input signal IN1 is input to a + input terminal of the CMP, and a balanced input signal IN2 is input to a-input terminal of the CMP. I do. Output signal O
UT is at logic 1 level when IN1> IN2, IN1 ≦
At the time of IN2, it is at the logic 0 level.

Further, the types of input signals (TTL, CML)
And the like). For example, if there is a request to terminate the line at 51Ω,
At the end. However, if the configuration is such that a dedicated input interface circuit is provided corresponding to each case as described above,
The same input interface circuit cannot be used for other types of input signals having different signal forms and termination conditions. Conventionally, measures have been taken by adding components to the outside, but this leads to a deterioration in space factor, an increase in power consumption, and an increase in cost. Furthermore, when such a dedicated input interface circuit is built in an LSI, it is necessary to manufacture an LSI corresponding to the input signal, and it is desired to improve this problem.

FIG. 28 is a diagram for explaining a conventional pulse width compensation circuit. Conventionally, a pulse width compensation circuit using a comparison circuit CMP is provided at a stage preceding the LD drive circuit DRV, and the pulse width of the input signal is increased (compensated). Hereinafter, a specific description will be given. FIG. 28A is a circuit diagram of a pulse width compensation circuit, and FIG. 28B is an operation timing chart thereof. In the figure, full Rupp flop FF is a data signal DATA input retiming to the clock signal CLK, and outputs the data signal v _i with a predetermined pulse width of the clock cycles is. Of the comparator circuit CMP - to the input terminal has entered the threshold voltage V _th, the threshold voltage V _th is set slightly lower than half of the amplitude of the data signal v _i. The output signal v _o of the CMP, v _i> V logic 1 level when the _th, when v _i ≦ V _th is a logic 0 level. Therefore, the pulse width of the output signal v _o is wider than when V _th is v _i / 2, and the reduction of the light emission pulse width is improved.

However, when the ordinary comparison circuit CMP is used for the pulse width compensation circuit as described above, the consumption current increases,
Problems such as occurrence of jitter due to the inability of the MP to operate at high speed occur. Therefore, improvement of such a pulse width compensation circuit is desired. FIG. 29 illustrates a conventional LD drive circuit with a current limiting function. Conventionally, LD drive current I2 of 1
By extracting a current I1 corresponding to / n by a pseudo current mirror and comparing the extracted current with a predetermined current I _CONST ,
This prevents an excessive current from flowing through the LD. Hereinafter, a specific description will be given.

In the LD driving circuit, the NMOSFET T11,
T12 forms a current switch circuit, and balanced input signals DATA and XDATA are input to each gate. D
When ATA = 0 and XDATA = 1, drive current I _{LD is} supplied to _LD.
Does not flow, and the LD is turned off. Conversely, DATA = 1, XDA
When TA = 0, the drive current I _LD flows through the LD, and the LD emits light. This LD drive current I2 (= I _LD ) is supplied from an NMOSFET T13 forming a constant current source circuit, and its magnitude is L
D current control signal V _PCNT (ie, v _{GS of} NMOSFET T13)
Is determined by If V _PCNT is high, I2 is large and V
_{If PCNT} is low, I2 is small.

In the APC output stage circuit, a comparison circuit CM
P compares the LD monitor signal V _MON with a predetermined reference signal V _REF . When the power is turned on, the external capacitor C1 is discharged and V _PCNT ≒ GND, which is low, so that the light output of the LD is small. Therefore, V _MON ≦ V _REF , and the output of the CMP becomes the LOW level. This allows the PMOSFET T1 to have A
The PC charging current _IAPC flows, the capacitor C1 is charged, and V
_{The PCNT} rises and the light output of the LD rises. Eventually, V
_{When MON} > _VREF , the output of CMP becomes HIGH level, PMOSFET T1 is turned off, and _VPCNT does not rise any further. The capacitance C1 (≒ 10000 pF) and the resistance R1 (≒ 10 MΩ) determine the time constant (gain) of such an APC loop, and thus the light output constant control of the LD is performed.

In the current limiting circuit, NMOSFETs T3 and L
It has the same electrical characteristics as the NMOSFET T13 of the D drive circuit, has the same channel length L, has a channel width of W ₁ ,
W ₂ (W ₁ / W ₂ = 1/100).
The same V _PCNT is added to the _NMOSFETs T3 and T13, and the currents I1 and I2 flowing through these _NMOSFETs have the same V _GS due to the same V _GS (however, the pseudo current mirror is not necessarily V _S1 = V _S2). ). For example, if I2 = 100 mA (normal), I1 = 1 mA
Becomes If I2 = 150 mA (upper limit), I1
= 1.5 mA.

On the other hand, the constant current source CCS supplies a constant current I _CONST to the drain of the NMOSFET T3. In such a configuration, the current comparison between the monitor current I1 and the constant current I _CONST is performed, and the current limit signal V
_LIMIT is set to HIGH level when I1 <I _CONST ,
In the case of I1> I _CONST , it becomes a LOW level. Thereby, in the case of I1 <I _CONST , that is, I2 <150 m
In the case of A, the PMOSFET T2 is turned off, so that the next-stage PMOSFET T1 can perform APC control of _VPCNT . Conversely I
When 1 ≧ I _CONST , that is, when I2 ≧ 150 mA, the PMOSFET T2 is turned on, and the next-stage PMOSFET T1 is forcibly turned off. Therefore, it is possible to prevent an excessive current from flowing through the LD.

However, in general, the drive current I2 of the LD greatly fluctuates due to variations in characteristics of the used optical element (LD / PD). Also, the current mirror current I1 is made as small as possible from the viewpoint of power saving.
A drain voltage V _S1 of T3, variation between the drain voltage V _S2 of the NMOSFET T13 occurs. As a result, NM
An error occurs in the current mirror between OSFET T3 and T13,
There has been a problem that variation in V _LIMIT under power supply fluctuation and temperature fluctuation becomes large. Furthermore, recently, the LSI voltage is reduced for the purpose of economy. However, according to the above-mentioned conventional method, the variation between V _S1 and V _S2 becomes relatively large with respect to the power supply voltage. There was also a problem that it could not cope with the change.

FIG. 30 is a diagram for explaining a driving method of a conventional LD driving circuit. The pulse width of the input data signal DATA varies depending on various external conditions. conventionally,
The input data signal DATA is retimed by the FF at the preceding stage to eliminate the fluctuation of the pulse width. Incidentally, this type of LSI test includes a DC operation test of the LD drive circuit DRV. In this DC operation test, it is desired to perform a DC operation test of the DRV or the LD by adding an arbitrary DC level (such as 1/0) to the input of the DRV.

However, conventionally, in order to change the input level of the DRV, the data signal DATA and the clock signal C
LK had to be entered. For this reason, a clock generator (including a jig) is required even when testing a DC operation. In addition, since the measurement is started by inputting the clock signal CLK, the test time is increased, and as a result, the cost reduction of the LSI is prevented.

FIG. 31 is a diagram for explaining a conventional power saving control circuit. FIG. 31 (A) is a circuit diagram thereof, and FIG. 31 (B) is an operation timing chart. Conventionally, data signals V _D , V
NMOSFET T between each line of _XD and ground GND
1, T2, and at the time of data transmission, the power saving signal S
By setting AVE = 0 and SAVE = 1 when data is not transmitted, current is prevented from flowing to the LD drive circuit except during data transmission.

However, the NMOSFETs T11 and T for driving the LD
12 has a gate width W,
That is, the gate capacitance _CG is large. Therefore, NMOSFET T1
1, the addition of fast signals to the gates of T12, thus the hazard current flows to the LD through the gate capacitance C _G. This causes a problem because the extinction ratio is degraded and adversely affects received data in other communication nodes.

FIGS. 32 and 33 are diagrams (1) and (2) for explaining a conventional bottom detection circuit. In this type of LSI intended to be mounted on a telecommunication or optical communication system, a bottom detection circuit that instantaneously detects the amplitude (for example, bottom value) of an input signal and holds the amplitude for a predetermined time includes a transmitting unit, a receiving unit, Used by both departments. FIG. 32 is a circuit diagram of a conventional bottom detection circuit. FIG. 32A shows a case of a negative logic input, and FIG. 32B shows a case of a positive logic input.

In FIG. 32A, the input signal IN = H
When I (> output signal OUT), the output of the differential AMP = L
O, whereby the NMOSFET T1 is turned off and the capacitance C
Is charged (initialized) at a low speed via a relatively large resistor R1 until OUT = IN. Next, the input signal IN =
When it becomes LO (<output signal OUT), the output of the differential AMP becomes HI, whereby the NMOSFET T1 is turned on, and the capacitance C is rapidly discharged (bottom detection) until OUT = IN through the NMOSFET T1. You.

FIG. 33A shows an operation timing chart in this case. Since the bottom-level detection time t is proportional to the capacitance C and inversely proportional to the discharge current I1 of the NMOSFET T1, the detection time t must be small, and the capacitance C must be small in order to perform a high-speed bottom value detection operation. It is conceivable to increase the discharge current I1. However, when the capacitance C is reduced, the charging time by the resistor R1 is also reduced, and it becomes difficult to hold the bottom detection value. Further, when the discharge current I is increased, as shown in FIG. 33B, excessive detection (overshoot) occurs when the bottom value is detected. As described above, conventionally, there is a trade-off relationship between the capacitance C and the discharge current I1, and it has been difficult to achieve both high-speed bottom detection and maintenance. The same applies to the bottom circuit in FIG.

FIGS. 34 and 35 are diagrams (1) and (2) for explaining a conventional APC output stage circuit, and FIG. 34 (A) shows a system configuration of an example optical subscriber transmission system. The optical line coupler is branched and connected between the optical line terminal OSU and the plurality of subscriber units ONU # 1 to #n. Here, the signal transmitted at the time of transmission (particularly from the subscriber side to the station side) is a burst signal generated periodically, and except for the first (at power-on etc.) first burst, the second burst starts. Since an optical output of a predetermined power is requested from the beginning, the LD current control signal _VPCNT formed last time needs to be held during this burst (data non-transmission section). However, since the APC circuit requires a high-speed operation of _VPCNT (starts up within the first burst), the capacity C1 cannot be increased so much. Further, since the burst cycle is long (up to 1 msec), there is a restriction that the resistance R1 needs to be increased.

FIG. 34B shows a burst hold function included in a conventional APC output stage circuit. Conventionally, an external capacitor C1 (≒ 10000 pF) and an external resistor R
1 (≒ 10 MΩ) and a time constant τ = C1 × R1
Is used to hold the _VPCNT between bursts. However, even if an external resistor having a large value is protected by a resin or the like, the resistance value fluctuates under the influence of temperature, humidity, and the like, and the amount of the fluctuation is not guaranteed. was there.

Conventionally, the capacitance C1 is set to the ground GND.
Because it is connected between_PCNTThe initial voltage of
And the start of APC in the first burst is delayed
There was a problem. FIG. 35 shows the APC of the first burst.
4 shows an operation timing chart of startup. Figure smell
When the transmission data is generated after the power is turned on, the APC function
Is activated and V _PCNTFlows from the earth potential to this section
APC charging current I_APCCharged sequentially by the desired light
Increases to the output potential. In this case, LD
First burst because light is emitted after the threshold current is exceeded
Is significantly delayed as shown in the figure.

FIG. 36 is a diagram for explaining a conventional optical output interruption alarm circuit. FIG. 36 (A) is a circuit diagram thereof, and FIG. 36 (A).
Is an operation timing chart thereof. The photocurrent signal of the monitor PD is converted into a corresponding monitor voltage signal by the I / V conversion circuit IVMON. A signal MONH is generated by detecting the peak of the monitor voltage signal, and a signal MONL is generated by detecting the bottom of the monitor voltage signal.

On the other hand, a reference signal (reference data signal) REF
DAT is input to the IVREF circuit, where its LOW
The level is converted to a REF voltage signal having a potential lower than that of MONL and its HIGH level being the same potential as signal MONH. The signal REFH is generated by detecting the peak of the REF-side voltage signal. And MONL and REFH
Is divided by a resistor to form a threshold voltage _Vth for detecting a light output interruption alarm. The comparison circuit CMP outputs an alarm signal SALM when MONH < _Vth .

However, if the circuit configuration is complicated as shown in the figure, offsets and the like of each circuit (IVM0N, IVREF, peak detection, bottom detection, and converter) are synthesized.
As a result, the relationship between MONH and _Vth deviates from a desired set value. Further, for example, when the LD deterioration progresses and MONH is near _Vth , the alarm signal SALM flaps due to the influence of the noise component of MONH.
Furthermore, since noise is included in the monitor voltage signal, there is a disadvantage that an incorrect peak value or bottom value is detected in a subsequent stage. As a result, a large number of LD drive devices having an optical output interruption alarm failure have occurred.

[0030]

As described above, the conventional light emitting device driving device has many problems to be improved. An object of the present invention is to provide a light emitting element driving device which can achieve further reduction in cost and power consumption and has high operation reliability.

[0031]

The above-mentioned problems can be solved, for example, by the structure shown in FIGS. That is, a light emitting element driving device according to the present invention (1) is a light emitting device driving device including a light emitting element, a driving circuit for the light emitting element, and a control circuit for performing constant light output control of the light emitting element. An input interface circuit comprising: a plurality of input terminals a and b; high impedance threshold voltage generation circuits A and B connected to the input terminals;
And a comparison circuit CMP for comparing the data signal of each input terminal.

When the input signal is a single signal, a single signal is input to one input terminal a / b and the other input terminal b
/ A is not connected, and the internal threshold voltage V _th2 / V _th1 is used to determine the input signal. When the input signal is a differential signal, the differential signal is input to two input terminals a and b.
Accordingly, an LSI having a general-purpose interface circuit can be provided, which leads to a reduction in the cost of the device.

Preferably, in the present invention (2), in the present invention (1), the threshold voltage generating circuit comprises a voltage dividing circuit of a resistance element. Also preferably, the present invention (3)
In the present invention (1), the threshold voltage generating circuit comprises a voltage dividing circuit in which the FET is self-biased.
Preferably, in the present invention (4), in the present invention (1), the threshold voltage generating circuit comprises a voltage dividing circuit in which a bipolar transistor is self-biased.

The above-mentioned problem is solved, for example, by referring to FIGS.
Is solved. That is, the light emitting element driving device of the present invention (5) is provided with a pulse width compensating circuit for shaping the pulse width of a data signal in the light emitting element driving device based on the above premise, and the pulse width compensating circuit has a different mutual conductance. It is composed of an inverter circuit in which FETs are complementarily connected.

[0035] Different transconductance g _m of the FET with complementary connections, the threshold V _th of inversion of the output signal v _o is shifted to a higher / lower side than the half of the amplitude v _i of the input signal. Therefore, it is possible to increase the pulse width of the output signal _vo using this. In addition, this type of inverter circuit can be configured at low cost, operates at high speed, and has low power consumption.

The above-described problem is solved, for example, by referring to FIGS.
Is solved. That is, the light emitting element driving device of the present invention (6) is the light emitting element driving device based on the above premise, and includes a pulse width compensation circuit for shaping the pulse width of the data signal, and the pulse width compensation circuit has different transconductance. The FET comprises an inverter circuit in which one of the FETs is a resistive load and the other is an inverting amplifier circuit.

[0037] Different transconductance g _m of the resistive load FET inverting amplifier FET, it is possible to fatten the pulse width of the output signal v _o by accelerating the transition of the inverted output signal v _o. In addition, this type of inverter circuit can be configured at low cost, operates at high speed, and has low power consumption. Further, the light emitting element driving device of the present invention (7) includes:
In the light emitting element driving device presupposed above, a pulse width compensation circuit for shaping the pulse width of the data signal is provided, and the pulse width compensation circuit comprises an inverter circuit in which bipolar transistors having different current amplification factors are complementarily connected. . Therefore, the same operation and effect as those of the invention (5) can be obtained.

Further, the light emitting element driving device of the present invention (8)
The light-emitting element driving device based on the above premise includes a pulse width compensation circuit for shaping a pulse width of a data signal. The pulse width compensation circuit forms one of bipolar transistors having different current amplification factors as a resistance load and inverts the other. It consists of an inverter circuit as an amplifier circuit. Therefore, the same operations and effects as those of the invention (6) can be obtained.

The above-mentioned problem can be solved, for example, by the structures shown in FIGS. That is, in the light emitting element driving device according to the present invention (9), the driving circuit includes a constant current source circuit T13 for driving the light emitting element and a differential pair T11 and T12 for switching the current in the light emitting element driving device based on the above premise. A pre-stage circuit that performs amplitude adjustment and / or level conversion of a data signal input to the differential pair; and monitors the light-emitting element driving current I2 of the driving circuit and monitors the constant current so that the driving current does not exceed a predetermined value. A current limiting circuit for limiting the driving signal V _PCNT applied to the source circuit T13, wherein the current limiting circuit is a circuit which duplicates at least one of the pre-stage circuit and the driving circuit related to the flow of the data signal. (Tn ', etc.), and the operating currents required for the pre-stage circuit and the driving circuit are current mirrored at a predetermined ratio to operate them under the same conditions. , For monitoring the light emitting element drive current I2 of the drive circuit.

As a result, the drain voltage V _S1 of T13 ′, which becomes a current mirror of T13, is changed according to the power supply, temperature, LD current I2, LD current control voltage V _PCNT , and input signals V _DATA and V _{XDATA of the} LD drive circuit. Irrespective of this, a highly accurate current mirror can be performed with the same state as the drain voltage V _{S2 of} T13. Therefore, it is possible to accurately monitor and determine the upper limit of the LD current I2, and to provide a device with high operation reliability.

The above-mentioned problem can be solved, for example, by the structures shown in FIGS. That is, the light emitting device driving device of the present invention (10) is a light emitting device driving device based on the above premise,
A flip-flop circuit for retiming an input data signal by a predetermined clock signal; and a selection circuit for selecting and outputting one of the input data signal and the output signal of the flip-flop circuit by an external control MODE. The driving circuit is configured to be driven by an output signal.

Therefore, for example, when a DC test of an LSI device is performed, the driving circuit DRV is driven by an input data signal.
Can be directly driven, and the reduction in the number of test steps can reduce the manufacturing cost. In addition, the above-described problems are described in, for example, FIGS.
Is solved. That is, the light emitting element driving device of the present invention (11) is a light emitting device driving device based on the premise described above, wherein the driving circuit includes a constant current source circuit for driving the light emitting element and a differential pair T11 and T12 for switching the current. ,
A power saving control circuit for clamping each data signal V _D , V _XD to be applied to the differential pair to a cutoff region of the differential pair by a predetermined control signal SAVE, wherein the power saving control circuit Is provided.

[0043] Thus, for example, via the gate capacitance C _G of the LD driving element T12 it can effectively prevent the hazard current flows to the light-emitting element LD. Preferably, the present invention (12)
In the present invention (11), for example, FIG.
As shown in FIG. 1, the low-pass filter circuit includes a capacitor C and a first signal from the capacitor in accordance with one level of the control signal SAVE.
And a second constant current source circuit T4 for supplying a second current I2 to the capacitor according to the other level of the control signal SAVE.

Accordingly, the capacitance C, that is, the rising and falling speeds of the clamp signal can be respectively set optimally.
Preferably, in the present invention (13), in the present invention (12), the first and second constant current source circuits do not include a resistance element. Therefore, accurate control can be performed without being affected by variations in resistance.

The above-mentioned problem can be solved, for example, by the structures shown in FIGS. That is, in the light emitting element driving device according to the present invention (14), the peak of the input signal is obtained by charging / discharging the capacitance C based on the comparison between the input signal IN and the output signal OUT ′ in the light emitting element driving device based on the above premise. A peak detection circuit for detecting and holding a value (bottom value in the figure), the input signal IN and the output signal OUT ′ of the peak detection circuit
And an auxiliary current generating circuit for generating an auxiliary current I2 for assisting charging / discharging of the capacitor C based on a comparison with a signal obtained via the resistor R2.

As a result, the electric charge of the capacitor C is discharged instantaneously (about several ns compared to the conventional tens of nsec) by the main current I1 of the peak detection circuit and the auxiliary current I2 of the auxiliary current generation circuit. In addition, the detected bottom value is held for a long time by the resistor R1 having a relatively large value. Preferably, in the present invention (15), the present invention (14)
Wherein the auxiliary current generation circuit corresponds to a differential amplification or comparison circuit that compares an input signal and an output signal of the peak detection circuit via a resistor, based on an output of the differential amplification or comparison circuit. And an FET element T2 for supplying an auxiliary current to the ground or the power supply side.

Preferably, in the present invention (16), in the present invention (14), for example, FIG.
As shown in (A), the auxiliary current generation circuit includes a differential amplifier or a comparison circuit that compares an input signal with an output signal of the peak detection circuit via a resistor, and the differential amplifier or the comparison circuit. And a diode element D1 for passing a corresponding auxiliary current to the differential amplification or comparison circuit based on the output of the diode D1.

Preferably, in the present invention (17), in the present invention (16), for example, as shown in FIG.
-As shown in (b) and (d), the diode element is a MOSFET having a gate, a drain, and an element substrate in common.
It consists of a T element. Therefore, integration is easy. More preferably, in the present invention (18), the present invention (1)
In (6), for example, as shown in FIGS. 16 (B)-(c) and (e), the diode element comprises a MOSFET element having a common gate and drain. Therefore, integration is easy.

Preferably, in the present invention (19), in the above-mentioned present invention (14), for example, as shown in FIG. 17, the auxiliary current generating circuit connects the input signal and the output signal of the peak detecting circuit via a resistor. A differential amplification or comparison circuit for comparing the obtained signal with a signal obtained, and a bipolar transistor element T2 for flowing a corresponding auxiliary current to the ground or the power supply side based on the output of the differential amplification or comparison circuit.

The above-mentioned problem is solved, for example, by referring to FIGS.
The problem is solved by the configuration of (A). That is, the present invention (20)
The light-emitting element driving device according to the above-mentioned premise is a driving circuit having a constant current source circuit T13 for driving the light-emitting device and differential pairs T11 and T12 for switching the current, and a light output of the light-emitting device. And a control circuit for generating a control voltage _VPCNT to be applied to the constant current source circuit T13 for constant light output control to the capacitor C1, and a burst for holding the generated control voltage _VPCNT until the next burst transmission. And an inter-burst holding circuit. The inter-burst holding circuit includes an FET element T5 which is turned on / off by a data transmission / reception control signal T / R, and a resistor R2 connected in series to the FET element. Things.

In the section of the control signal T / R = 1 (burst transmission), since the FET element T5 is turned on, the voltage of the capacitor C1
_{The PCNT} is controlled according to the constant optical output control of the loop gain including the resistor R2. On the other hand, in the section where the control signal T / R = 0 (non-transmission), since the FET element T5 is turned off, the _VPCNT generated this time is effectively held until the next burst transmission. Therefore, from the second burst, data transmission can be performed at a predetermined optical power from the beginning. Further, since the resistance value R2 in this case can be made relatively small (about 500 KΩ), this resistance 2 can be formed inside the LSI together with T5.
Therefore, a highly reliable operation that is not affected by temperature, humidity, or the like can be obtained.

The above-mentioned problem is solved, for example, by referring to FIGS.
The problem is solved by the configuration of (A). That is, the present invention (21)
The light-emitting element driving device according to the above-mentioned premise is a driving circuit having a constant current source circuit T13 for driving the light-emitting device and a differential pair for switching the current, and a light output of the light-emitting device. The control voltage V _PCNT applied to the constant current source circuit T13 for constant light output control is
1, a control circuit for generating a predetermined initialization voltage VTH, and a switch interposed between the capacitor and the initial voltage generation circuit, the switch being turned on when the power of the apparatus is turned on. And a circuit T7.

When the power of the device is turned on, the switch circuit T7 is turned on.
When N, the capacitor CI is quickly charged to a predetermined initialization voltage VTH (for example, a voltage for supplying a slightly smaller current than the threshold current to the LD element). Therefore, it is possible to increase the optical power of the first burst to a predetermined power earlier than before. Preferably, in the present invention (22), in the present invention (21), for example, FIG.
As shown in (A), a FET element T5 connected in parallel with a capacitor C1 and driven ON / OFF by a data transmission / reception control signal T / R, and a resistor R2 connected in series to the FET element And an inter-burst holding circuit having the following.

Therefore, this configuration has the functions and effects of the present invention (20) and the present invention (21). Preferably, in the present invention (23), the present invention (21)
23, for example, as shown in FIG. 23A, an FE connected between the capacitor C1 and the initial voltage generation circuit and driven ON / OFF by a data transmission / reception control signal T / R.
A T element T5 and a resistor R connected in series with the FET element.
2 is provided.

In this case, since one end of the resistor R2 is connected to the VTH side instead of the ground side, the voltage between the terminals of the resistor R2 is reduced, and the value of the resistor R2 can be reduced. The above-mentioned problem is solved by, for example, the configuration shown in FIGS. That is, the light emitting element driving device of the present invention (24)
In the light emitting element driving device presupposed above, a light output alarm circuit that detects a state where the light output of the light emitting element is equal to or less than a predetermined value, the light output alarm circuit generates a predetermined threshold value _Vtn , an amplifier circuit IVMON for amplifying the monitoring signal of the light output variations or amplitude of the signals in consideration of the variation of the threshold V _tn, a peak detection circuit for detecting and holding a peak value of the monitor signal after the amplification, and the threshold value A comparison circuit CMP for comparing the peak value of the monitor signal with the peak value to generate an alarm signal.

By providing a simple and single threshold value generation circuit, the adverse effect of offset synthesis by a plurality of circuits can be effectively eliminated. On the other hand, the monitor signal of the optical output is amplified to a signal having an amplitude in consideration of the variation or fluctuation of the threshold value V _tn . For example, it is amplified a little. As a result, the ratio of the variation or change of the threshold value V _tn to the amplified monitor signal becomes relatively small. Therefore, highly reliable alarm detection can be performed with a simple configuration.

Preferably, in the present invention (25),
In the present invention (24), the comparison circuit has a hysteresis characteristic. Therefore, fluttering of the alarm detection signal SALM can be prevented. Also preferably, the present invention (2)
6) In the present invention (24), a low-pass filter circuit for filtering a monitor signal of an optical output is provided. Accordingly, noise components included in the optical output monitor signal to be compared can be effectively suppressed, and highly reliable alarm detection can be performed.

[0058]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a schematic configuration of an LD driving device according to an embodiment. This LD driving device is an LD driving LS that performs main control of the LD driving.
I100, a load resistor RL corresponding to the LD, a laser diode LD, a photodiode PD for monitoring the back light of the LD, and an external capacitor C1 for holding the LD current control signal _VPCNT .

The LD driving LSI 100 is roughly divided into
It comprises a main signal section 10 for processing data signals, and an APC section 20 for controlling constant light output of the LD. Main signal section 1
At 0, 11 is an input interface circuit for terminating (interface) an input data signal, 12 is a flip-flop circuit (FF) for retiming (pulse width shaping) the input data signal, and 13 is a DC test of the LD drive LSI 100. A selector (SEL) for bypassing an input data signal when the input is performed, a signal detection circuit 14 for extracting a data signal or a clock signal, and a time division multiplexing (TC) 15.
M) A power saving control circuit that deactivates the LD drive circuit when data is not transmitted in communication or the like (cuts off the LD current) to save power.
6 is a pulse width compensating circuit for compensating for (decreasing) the light pulse width due to LD emission delay, 17 is an LD driving pre-stage circuit for performing voltage compression / level shifting of the data signal and matching the input to the LD driving circuit, Reference numeral 18 denotes an LD drive circuit.

In the APC section 20, reference numeral 21 denotes a reference signal generation circuit for generating a predetermined reference signal V _REF based on a data signal, reference numeral 22 denotes an I / V conversion circuit for converting a photocurrent of a PD into a corresponding voltage signal V _MON , _{Reference numeral} 23 denotes an automatic optical output control (APC) circuit that performs constant optical output control of the LD, etc., 24 denotes a VTH generation circuit that generates an initial voltage value VTH applied to the LD current control signal V _PCNT , and 25 denotes the current control. V _PCNT
Is a burst holding circuit for holding until the next transmission burst, 26 is an optical output alarm circuit that detects a state where the optical output level of the LD is below a predetermined level and generates an alarm signal SALM, 27 is an LD or This is a current limiting circuit that determines the upper limit of the LD drive current in order to protect the drive circuit from damage due to overcurrent. Hereinafter, details of each circuit will be described.

FIGS. 2 to 4 show input interfaces according to the embodiment.
(1) to (3) for describing a face circuit. FIG.
(A) shows a conceptual configuration of the input interface circuit.
This input interface circuit has two input terminals a and b.
And one input terminal a has a high impedance.
Non-inverting input of threshold voltage generation circuit A and comparison circuit CMP
And the other input terminal b is also high.
Threshold voltage generation circuit B having impedance and comparison circuit
Connected to the inverted input (-) of CMP. This
A predetermined threshold (threshold) voltage is applied to each of the input terminals a and b.
V_th1, V _th2Are applied and these are high impedance
Terminated with a Each threshold voltage generating circuit A, B
Threshold voltage V_th1, V_th2(V_th1= V_th2But it's fine)
And generate a relatively high impedance with respect to the input signal.
The circuit configuration does not matter as long as it has a dance.

The interface circuit having such a structure can be used as a general-purpose interface circuit, and any type (unbalanced type, balanced type) of input signal can be interfaced as it is. For example, unbalanced input (single signal)
To convert the positive pulse signal IN1 into a positive output pulse signal OUT, connect the input signal IN1 to the terminal a,
Terminal b is left open. As a result, the voltage of the terminal a becomes the input signal IN1 driven with low output impedance.
, The voltage at the terminal b is held at the internally generated threshold voltage V _th2 . Therefore, the output signal OUT is logic 1 when IN1> _Vth2.
(HIGH) level, a logic 0 when IN1 ≦ V _th2 (L
OW) level.

When the input unbalanced (single signal) negative pulse signal IN2 is to be converted into a positive output pulse signal OUT, the terminal a is left open and the input signal IN2 is connected to the terminal b. . As a result, the voltage at the terminal b is driven to the logic 1/0 level by the input signal IN2 driven at a low output impedance, but the voltage at the terminal a is held at the internally generated threshold voltage V _th1 . Therefore, the output signal OUT has a logic 1 level when IN2 ≦ V _th1 ,
When IN2> V _th1 , it is at logic 0 level.

The input balanced (differential input) positive and negative pulse signals IN1 and IN2 are converted to a positive output pulse signal OU.
To convert to T, the input signal IN1 is connected to the terminal a and the input signal IN2 is connected to the terminal b. As a result, the voltages at the terminals a and b are changed to logic 1/0,
Driven to 0/1 level. Therefore, the output signal OUT
Is a logical 1 level when IN1> IN2, and IN1 ≦ IN
At the time of 2, it is at the logic 0 level.

FIG. 2B shows a case where the threshold voltage generating circuit is composed of a resistance voltage dividing circuit. The two input terminals a and b are connected to, for example, a resistor voltage dividing circuit including resistors R1 and R2 of 50 kΩ and resistors R3 and R4, respectively, to generate respective threshold voltages _Vth . For example, if the input signal is LVCMOS level or CMOS
In the case of a single signal by level and no input termination condition,
A signal is input to one input terminal a / b, and the other input terminal b / a is left open for use. When the input signal is a CML level differential signal as shown in the figure and the input termination condition is 51Ω, each signal is input to the two input terminals a and b, and between the power supply and each of the input terminals a and b. Is connected (externally connected) to a terminal resistor of 51Ω. Such usage is the same for each of the following configurations.

FIG. 3A shows that the threshold voltage generating circuit is a PMOSFET.
Is shown. 2 input terminals, each PMOS
Each of the voltage dividing circuits including the FETs T1, T2 and T3, T4 is connected to provide an intermediate threshold voltage _Vth . Each of the PMOSFETs T1 to T4 having a gate connected to the drain is self-biased in a saturation region (pinch-off or higher), and their channel impedance is as high as about 100 KΩ.

FIG. 3B shows that the threshold voltage generating circuit is an NMOSFET.
Is shown. 2 input terminals, each NMOS
Each of the voltage dividing circuits including the FETs T1, T2 and T3, T4 is connected to provide an intermediate threshold voltage _Vth . Each of the NMOSFETs T1 to T4 whose gates are connected to the drain is self-biased in a saturation region (pinch-off or higher), and their channel impedance is as high as about 100 KΩ.

FIG. 4A shows a case where the threshold voltage generating circuit is composed of a voltage dividing circuit of a pnp transistor. Two input terminals are connected to respective voltage dividing circuits composed of pnp transistors T1, T2 and T3, T4, respectively, and each intermediate threshold voltage V _th
I will provide a. Each of the pnp transistors T1 to T4 whose base is connected to the collector is self-biased in the saturation region, and their collector impedance is sufficiently high.

FIG. 4B shows a case where the threshold voltage generating circuit is composed of an npn transistor voltage dividing circuit. Two input terminals are connected to respective voltage dividing circuits each including npn transistors T1, T2 and T3, T4, and each intermediate threshold voltage V _th
I will provide a. Each of the npn transistors T1 to T4 whose base is connected to the collector is self-biased in the saturation region, and their collector impedance is sufficiently high.

It is to be noted that, in addition to the above, various modifications can be considered in consideration of the positive / negative power supply voltage supplied to the threshold voltage generating circuit. Further, the configuration of the present invention can be applied to an application having three or more input terminals and performing various comparisons of three or more input signals using a plurality of comparison circuits CMP. 5 to 7 are diagrams (1) to (3) for explaining the pulse width compensation circuit according to the embodiment.

FIG. 5A is a circuit diagram of a pulse width compensation circuit according to the embodiment. In this embodiment, the pulse width compensation of the output signal _vo is realized by adopting a CMOS inverter circuit instead of using the conventional comparator circuit CMP. FIG. 5B shows the operation characteristics. The section of the input signal v _i <A, a V _GS <V _T of NMOSFET T1 (threshold voltage), the T1 is turn OFF. Meanwhile, PM
OSFET T2 is ON in the linear region due to its V _DS = small. Next, A <v _i <becomes the D, first NMOSFET at point A
T1 turns ON in the saturation region (V _DS = large) and PMOSFE
T T2 reaches the point B in the linear region. Further, at the point B, the PMOSFET T2 shifts to the saturation region (V _DS = large), and reaches the point C together with the NMOSFET T1 in the saturation region. Further, at this point C, the NMOS FET1 changes to a linear region (V _DS = small),
Further, the PMOSFET T2 reaches the point D while maintaining the saturation region. Then, the input signal v _i> In section D, V _GS of PMOSFET T2
< _VT (threshold voltage), and T2 is turned off. On the other hand, the NMOSFET T1 is ON in the linear region.

Under the symmetry of the switching operation,
In a general CMOS inverter circuit, NMOSFETs T1 and PM
By making the mutual conductances g _m1 and g _m2 of the OSFET T2 the same, the inversion threshold value V _th of the output signal _vo is selected to be about の of the power supply voltage V _SS . By the way, the mutual conductance g _m, in the case of V _DS constant, g _m = (d
I _D / dV _GS ), which is proportional to the channel widths W ₁ , W ₂ of T1 and T2 (provided that the channel length L = constant) and the channel lengths L ₁ , L ₂ (where Width W = constant).

In this embodiment, the NMOSFET T1 and the PMOSFE
By making the mutual conductances g _m1 and g _m2 of T T2 different, the threshold value V _th for inversion of the output signal v _o is offset left / right from the center. Specifically, FIG.
In the sections A to D of (B), for example, if g _m1 > g _m2 is selected, the relationship of I1> I2 is established, and the inversion threshold value V _th of the output signal _vo is substantially shifted in the direction of arrow a. That is, the output signal v _o at small values of the input signal v _i is inverted. If g _m1 <g _m2 is selected, the relationship of I1 <I2 holds, and the threshold value V _th for inversion of the output signal _vo is substantially shifted in the direction of the arrow b. That is, the output signal v _{o is} set to a large value of the input signal v _i.
Is inverted. Therefore, a positive logic or negative logic input signal v _i
By selecting g _m1 > g _m2 or g _m1 <g _m2 in accordance with, the pulse width of the output signal v _o can be increased.

FIG. 6 shows the operation of the pulse width compensation circuit shown in FIG.
FIG. 6A shows an input signal v._iIs negative
It shows input / output operations in the case of logic. g_m1<G_m2Selected
Output signal v_oInversion threshold V_thIs the middle V_SS/ 2
Higher, so that the output signal v_oNo pa
Loose width increases. FIG. 6B shows the input signal v_iIs positive logic input
4 shows the input / output operation in the case of. g _m1> G_m2Choose
And the output signal v_oInversion threshold V_thIs the middle V_SS/ 2
Lower, which results in the output signal v_oPal
The width becomes thicker.

It is needless to say that such a pulse width compensating circuit can be used as a general pulse shaping circuit including not only increasing the pulse width as described above but also reducing the pulse width. . FIG. 7A is a circuit diagram of a pulse width compensation circuit according to another embodiment. In this embodiment, the pulse width compensation of the output signal _vo is realized by employing a MOS inverter circuit instead of using the conventional comparator circuit CMP.

Although an inverter circuit using NMOSFETs T1 and T2 is shown here, it can also be configured using PMOSFETs T1 and T2. The gate of NMOSFET T2 is connected to its drain terminal D or to a predetermined voltage source _VGG , which acts as a resistive load. In this case, the NMOSFET T2 has a pinch-off or more depending on the gate bias method.
Although there are various operation modes such as a pinch-off mode and a depletion mode, the transition tendency of the input / output characteristics is similar.

FIG. 7B shows the input / output characteristics of an example of this MOS inverter circuit. It is assumed that the NMOSFET T2 operates at a pinch-off or higher. In this MOS inverter circuit, if λ = g _m1 / g _m2 , λ∝ (W ₁
/ W ₂₎ · (have a relationship of L ₂ / L _1), when choosing λ to large, the threshold V _th of inversion of the output signal v _o is shifted in the direction of arrow a, the pulse width of the output signal v _o Get fat.

The pulse width compensation circuit according to each of the above embodiments may be realized by an inverter circuit combining bipolar transistors having different current amplification factors or a complementary inverter circuit. FIG. 8 is a diagram illustrating a current limiting circuit according to the embodiment. By the way, the drive current I2 of the LD is affected by variations in the optical elements LD and PD, and the like.
In order to obtain the same light output, the drive current I2 may be large or small. On the other hand, the differential pair T11, T1 of the LD drive circuit
In the case of _{No. 2} , it is necessary to add data signals V _DATA and V _XDATA having an amplitude corresponding to the drive current I2 at that time in order to suppress the occurrence of ringing or the like on the switching current. LD driving stage circuit, the optimum data signal V _DATA which is added to the differential pair T11, T12, and generates a V _XDATA.
The details are described below.

The input non-inverted data signal DATA and inverted data signal XDATA are supplied to a differential pair of PMOSFETs T4 and T4.
Input to each gate of T5. A constant current I3 is supplied to the differential pair T4 and T5, and the constant current I3 is
The drive current I2 of the drive circuit is changed to the same LD current control signal V
It is current mirrored by _{PCNT at} a predetermined ratio through NMOSFET T1 and PMOSFET T2. Therefore, the differential pair T
4, the current I3 flowing through T5 is linked to the LD drive current I2.

The loads on the differential pair T4 and T5 are resistors R1 and R2 (where R1 = R2).
4, T5 outputs a constant current I3 and a resistor R1,
This is a signal (voltage-compressed signal) having an amplitude between GND and a voltage determined by the product of R2. However, since the DC level of the signal is low, further, the source follower circuit T9, T10 for the respective signals each subsequent level up by a predetermined amount, the data signal V _{DA TA,} generates a V _XDATA.

On the other hand, in the current limiting circuit, the LD drive
The drain voltage V of the NMOSFET T13 in the circuit_S2And current limit times
Drain voltage V of NMOSFET T13 '_S1And the LD drive
Dynamic current I2, LD current control voltage V_PCNTAnd data signal V
_DATANo matter how _S2= V_S1I made it
No. In this way, the NMOS MOSFET T13 with the same characteristics
T T13 'has V_PCNT= Common, and V_S2= V_S1Condition
As a result, the current I1 (for example,
This is because (I1 = I2 / 100) flows.

Therefore, in order to realize the condition of V _S2 = V _S1 , necessary circuit configurations in the LD drive pre-stage circuit and the LD drive circuit are copied in the current limiting circuit. Specifically, an NMOS is provided between the NMOSFET T13 'and the PMOSFET T15.
An NMOSFET T12 'corresponding to the FET T12 is inserted. Furthermore,
In order to make the operation state of the NMOSFET T12 'the same as that of the NMOSFET T12, T3, T5, R
T3'T5 'and R2 are provided in the current limiting circuit corresponding to the circuit No. 2, and the current I3 is current-mirrored thereto. Also, LD
T7'T9 'is provided in the current limiting circuit corresponding to T7 and T9 in the pre-driving circuit, and the constant current of T6 is current-mirrored thereto. Incidentally, PMOSFET t5 'is always set to ON, H of the generated by resistors R2 data signal V _DATA
A DC voltage corresponding to the IGH level is input to the gate of the NMOSFET T12 '.

As described above, V_S2= V_S1NM
The LD drive current I2 is always positive in the current I1 of the OSFET13 '.
Surely reflected. This current I1 is transmitted through the NMOS FET 15
The current I4 obtained by current mirroring the PMOSFET T14
And constant current I of constant current source CCS _CONSTCompare with Soshi
The current limit signal V according to the magnitude comparison._LIMITTo
Generate. Therefore, there is a current mirror error as described above.
LD drive current control due to power supply and temperature fluctuations
Limit value V_LIMITCan be effectively suppressed.

FIG. 9 is a diagram for explaining a bypass circuit according to the embodiment. The flip-flop circuit FF re-times the input data signal DATA with the clock signal CLK, and shapes the data signal FDATA so as to have a clock cycle as a unit. That is, fluctuations in pulse width and jitter are suppressed. The selector SEL switches between the input data signal DATA and the shaped data signal FDATA according to the external mode selection signal MODE. Normally, the mode selection signal MODE = 1 is set, and the LD driving circuit DRV is driven by the FF output data signal FDATA.
At the time of the operation test (at the time of DC test) of the LD drive circuit,
The mode selection signal MODE = 0, and the LD drive circuit DRV is directly driven by the input data signal DATA. The DC test data signal DATA is obtained by simply applying an appropriate DC level (logic 1/0, etc.) to the data input terminal, and there is no need to input the clock signal CLK to the clock input terminal as in the conventional case. . Therefore, the time and man-hour for this type of operation test can be greatly reduced.

FIGS. 10 and 11 show power saving control according to the embodiment.
It is a figure (1) explaining a control circuit, (2). FIG.
1A is a circuit diagram of a power saving control circuit according to an embodiment, and FIG.
0 (B) is an operation timing chart thereof. Input
Data signal V_D, V_XD(Voltage compression signal) is LD drive circuit
To the respective gates of the differential pair T11, T12. on the other hand,
In the power saving control circuit, the input power saving control signal SAVE is
"1" (high level) when the LD drive circuit is not transmitting
It is in. As a result, the capacitor C is charged and the NMOSFET
T1 and T2 are both ON (V_D, V _XDTo GND)
ing. Thereby, the differential pair T11, T1 of the LD drive circuit
2 are both turned off, thus saving the LD drive current.
It is.

Next, at the time of data transmission, the input power saving control signal SAVE changes from "1" to "0" (LOW level). In the present embodiment, a waveform shaping circuit (for example, RC) for blunting the rising and falling portions of the power saving control signal SAVE before the NMOSFETs T1 and T2.
Low-pass filter). As a result, the capacitor C discharges relatively slowly through the resistor R,
NMOSFETs T1 and T2 are soft-off. NM in this case
Each drain voltage of OSFET T1, T2 is gradually rises (is opened), effectively prevented from flowing hazard current to the load resistor RL and LD through each gate capacitance C _G of the differential pair T11,12 it can. Input power saving control signal SAV
The same applies when E changes from “0” to “1”.

FIG. 11A is a circuit diagram of a power saving control circuit according to another embodiment, and FIG. 11B is an operation timing chart thereof. In FIG. 11A, this power saving control circuit includes an integral capacitor C for smoothing the waveform of an input power saving control signal SAVE before the NMOSFETs T1 and T2.
And a current source NM for discharging the first constant current I1
OSFET T3 and this current source NMOSFET T3 ON / OFF
And a current source PMOSFET T4 for charging the integration capacitor C with a second constant current I2.
And a switch circuit S2 for controlling ON / OFF of the current source PMOSFET T4.

The power saving control signal SAVE changes from "1" to "0".
, The switch circuit S1 becomes V _GG1 (> GND)
And the constant current I1 flows through the NMOSFET T3. On the other hand, the switch circuit S2 is connected to the side of the power supply V _SS, PMOSFE
T T4 is turned off. As a result, the capacitor C is gradually discharged by the constant current I1, and the outputs of the NMOSFETs T1 and T2 rise gradually.

Next, when the power saving control signal SAVE changes from "0" to "1", the switch circuit S1 is connected to the GND side, and the NMOSFET T3 is turned off. On the other hand, the switch circuit S2 is connected to the side of the _{V GG2 (<V SS),} PMOSFET T4
, A constant current I2 flows. As a result, the capacitance C becomes constant current I2
And the outputs of the NMOSFETs T1 and T2 gradually decrease.

Preferably, by selecting I1 ≠ I2, each transition time of the rising portion and the falling portion of the power saving control signal SAVE can be adjusted independently. In addition, the output of the NMOSFETs T1 and T2 is changed in each minimum time width in consideration of the characteristics (gate capacitance C _G ) of the LD drive circuit, and the generation of the hazard is effectively suppressed. Further, since the power saving control circuit (filter circuit) does not use a resistor, there is no variation in the transition time, and a highly accurate rise time and fall time can be obtained.

FIGS. 12 to 17 are diagrams (1) to (6) for explaining the bottom detection circuit according to the embodiment. FIG. 12 is a circuit diagram of the bottom detection circuit according to the embodiment. The basic part of this bottom detection circuit may be the same as the conventional one shown in FIG. In the present embodiment, an auxiliary charging current generating circuit is added to this.

The auxiliary charging current generating circuit includes a differential AMP2
(Or a comparison circuit CMP), and an NMOSFET T2 whose output is connected to the gate. The source of the NMOSFET T2 is connected to the ground GND, and the drain is connected to the drain (point A) of the NMOSFET T1 via the resistor R2. Further, the input signal IN is input to the inverting input side (−) of the differential AMP2, and the non-inverting input side (+) is connected to the NMOSFET T
2 drain. Then, the output signal OUT is extracted from the drain of the NMOSFET T2.

FIG. 13 is an operation timing chart of the bottom detection circuit. In FIG. 13A, the input signal IN
Becomes LOW level, the NMOSFET T1 cannot instantaneously detect the bottom of the input signal IN as in the related art, so that a potential difference occurs between the input signal IN and the voltage OUT 'at the point A. In FIG. 13B, the output of the differential AMP2 becomes HIGH due to this potential difference, and the NMOSFET T2
Turns on, and an auxiliary current is drawn from the capacitor C via the resistor R2. By appropriately selecting the value of the resistor R2, it is possible to set so that the charge of the capacitor C is discharged to the bottom value in the shortest time without overshooting.

In FIG. 13C, the NMOSFET T1
The output signal OUT quickly decreases due to the discharge current I1 of the NMOSFET T2 and the auxiliary discharge current I2 of the NMOSFET T2.
Instantaneous bottom detection of N can be performed. And the output signal O
When the UT (voltage OUT 'at point A) becomes equal to the bottom value of the input signal IN, the outputs of the differential AMPs 1 and 2 decrease respectively, and the outputs become the threshold voltages V of the NMOSFETs T1 and T2.
_By setting it to be _T or less, NMOSFETs T1, T
2 turns off. Therefore, the output signal OUT (the voltage OUT ′ at the point A) is held at the bottom value of the input signal IN. Then, even if the input signal IN becomes HIGH level, the differential A
Both the output of MP1 and 2 becomes LOW level and NMOSFET
T and T2 are kept OFF.

As described above, the charging current (discharge current in this example) is increased at the time of bottom detection. However, since the auxiliary charging current generating circuit operates as a voltage comparator, the discharge time, which has been a problem in the prior art, is reduced. A good bottom detection operation can be performed without reducing the size or excessively moving the bottom detection. Note that a resistor R1 for charging the capacitor C
May be constituted by a MOSFET. Further, one end of the capacitor C may be connected to the power supply _VDD side instead of the ground GND.
This is the same in other embodiments described below.

FIG. 14A is a circuit diagram of a bottom detection circuit according to another embodiment. Here, the bottom detection circuit side includes a differential AMP1 and a PMOSFET T1 whose output is connected to the gate, and the non-inverting input side (+) of the differential AMP1 is connected to the input signal IN. And its inverting input side (-) is connected to the source of the PMOSFET T1. The auxiliary charging current generating circuit is the same as that of FIG. Even in this combination, instantaneous bottom detection can be performed in the same manner as described above.

FIG. 14B is a circuit diagram of a bottom detection circuit according to still another embodiment. Here, the side of the auxiliary charging current generating circuit is composed of a differential AMP2 and a PMOSFET T2 whose gate is connected to its output, and the non-inverting input side (+) of the differential AMP2 is connected to the input signal IN. And its inverting input (-) is connected to the source of PMOSFET T2. The bottom detection circuit side is the same as FIG. Even in this combination, instantaneous bottom detection can be performed in the same manner as described above.

FIG. 15A is a circuit diagram of a bottom detection circuit according to still another embodiment. Here, FIG.
The configuration is such that the bottom detection circuit of FIG. 14A is combined with the auxiliary charging current generation circuit of FIG. Even in this combination, instantaneous bottom detection can be performed in the same manner as described above. FIG. 15B is a circuit diagram of a bottom detection circuit according to still another embodiment.

Here, the side of the auxiliary charging current generating circuit is
In this configuration, a diode D1 is connected as shown in the figure instead of the conventional MOSFET T2. In the auxiliary charging current generating circuit, when IN <OUT, the output of the differential AMP2 becomes LOW level, and the auxiliary current I
2 flows to assist discharge of the capacity C. Also, IN ≧ OUT
, The output of the differential AMP2 becomes HIGH level, and the diode D1 is turned off. This diode D1
Any of those shown in FIG. 16B described later may be used. Even with this configuration, instantaneous bottom detection can be performed in the same manner as described above.

FIG. 16A is a circuit diagram of a bottom detection circuit according to still another embodiment. Here, FIG.
The configuration is such that the bottom detection circuit of FIG. 15A is combined with the auxiliary charging current generation circuit using the diode D1 of FIG. Even in this combination, instantaneous bottom detection can be performed in the same manner as described above. FIG. 16B shows various types of the diode D1.

In FIG. 16B, (a) shows a normal p
It is an n-junction type diode. (B) is a pn junction type diode using an NMOSFET. In an NMOSFET, an n-type source and a drain are formed in a p-type substrate, and an n-channel is formed between the source and the drain by applying a positive potential to a gate via an insulating film. However, when the gate and the drain are short-circuited (commonly) and the p-type substrate is short-circuited (commonly) as shown in the figure, the function as the NMOSFET is lost, and the n-type source and the p-type substrate (ie, A normal pn junction is formed between the pn junction and the drain terminal. This part is used as a pn junction type diode.

(C) shows a channel formation type using an NMOSFET.
Diode. As shown, the gate of the NMOSFET and
When the drains are short-circuited (common), v_S<V _G(=
v_DIn the case of ()), an n-channel is formed in the p-type substrate and
Although the drain current of the power characteristic flows,_S> V_G(=
v_D), No n-channel is formed, and the NMOSFET becomes O
FF. Operating characteristics similar to these diodes
We use as iod.

Similarly, (d) shows a P-type MOSFET using a PMOSFET.
An N-junction diode, (e) is a channel-forming diode in which the gate and drain of the PMOSFET are common. FIG. 17A is a circuit diagram of a bottom detection circuit according to still another embodiment. Here, the auxiliary charging current generating circuit has a configuration in which an npn transistor T2 is connected as shown in the figure instead of the MOSFET T2.

In the auxiliary charging current generating circuit, IN <O
In the case of the UT, the output of the differential AMP2 becomes HIGH level, the auxiliary current I2 flows through the npn transistor T2, and assists the discharge of the capacitor C. When IN ≧ OUT, the output of the differential AMP2 becomes LOW level, and the npn transistor T2 is turned off. FIG. 17B is a circuit diagram of a bottom detection circuit according to still another embodiment.

Here, the side of the auxiliary charging current generating circuit is
The configuration is such that a pnp transistor T2 is connected as shown in the figure instead of the npn transistor T2. In the auxiliary charging current generating circuit, when IN <OUT, the output of the differential AMP2 becomes LOW level, the auxiliary current I2 flows through the pnp transistor T2, and assists the discharge of the capacitor C. When IN ≧ OUT, the output of the differential AMP2 becomes HIGH level, and the pnp transistor T2 becomes O
FF.

FIG. 18 is a diagram for explaining an inter-burst holding circuit according to the embodiment. FIG. 18A is a circuit diagram of an inter-burst holding circuit according to the embodiment. This APC output stage circuit includes a conventional external resistor R1 for holding between bursts.
(About 10MΩ) instead of NMOSFET T5 and resistor R2
(Approximately 500 KΩ) are connected in series to form an inter-burst holding circuit inside the LSI. Note that the capacitance C1 is externally provided.

When the transmission / reception switching signal T / R = 1 (burst transmission), the NMOSFET T5 is turned on, and the electric charge of the capacitor C1 can be discharged via the resistor R2. That is, constant light output (APC) control of the LD is performed with a loop gain determined by the capacitance C1 and the resistance R2. On the other hand, the transmission / reception switching signal T /
In the section of R = 0 (reception), since the NMOSFET T5 is turned off, the electric charge charged in the capacitor C1 by the previous APC control is not discharged, and the LD current control signal _VPCNT is held as it is. In this case, the NMOSFET T5 OF
Since the channel impedance at the time of F is very large, L
The D current control signal _VPCNT is held at each voltage regardless of the burst transmission cycle.

FIG. 18B is a circuit diagram of an inter-burst holding circuit according to another embodiment. Here, FIG.
(A) Instead of the NMOSFET T5 of the inter-burst holding circuit,
A PMOSFET T5 is used, and an inverter circuit I is inserted in its gate circuit. The operation is shown in FIG.
It can be considered in the same way as (A). 19 and 20 are diagrams (1) and (2) illustrating an APC initial voltage generation circuit (VTH generation circuit) according to the embodiment.

FIG. 19A is a circuit diagram of a VTH generation circuit according to the embodiment. The VTH generation circuit has a constant current I
_Consisting of a constant current source circuit CCS for supplying _CONST and a series circuit of a diode-connected NMOSFET T6,
By flowing a predetermined constant current I _CONST through the NMOSFET T6, an initial voltage VTH for APC is generated at the gate (drain) of the NMOSFET T6. Further, between the gate terminal and the NMOSFET T6 of the LD driving current control signal V _{PCON T} connected by NMOSFET T7 for switching, the NMOSFET T7
Is controlled by an inverted signal of the shutdown signal SD. It is to be noted that the resistor R1 in this example shows an external case as in the prior art.

FIG. 20 shows an operation timing chart of the VTH generation circuit. The shutdown signal SD is at the LOW level from the time when the power is turned on until the transmission data is generated, and the inverted output of the shutdown signal SD turns on the NMOSFET T7. In this interval, the V _PCONT of the capacitor C1 is initialized to VTH. The initialization voltage VTH is previously supplied to the LD with its threshold current I _T
It is a voltage at which a slightly smaller current flows.

Next, when the transmission data is input, the shutdown signal SD goes to a high level.
The NMOSFET T7 is turned off, and the capacitance C1 is the APC charging current I
Under _APC control. At this time, _VPCNT already has VTH
, The APC can be started up at a high speed. FIG. 19B shows VTH according to another embodiment.
It is a circuit diagram of a generation circuit.

Here, the switching NMOSFET T7 in FIG. 19A is replaced with a switching PMOSFET T7, and the inverter circuit I is omitted. The operation is shown in Fig. 1.
It can be considered in the same manner as in the case of 9 (A). FIGS. 21 to 24 are diagrams for explaining an APC output circuit according to the embodiment (1) to FIG.
(4).

FIG. 21A is a circuit diagram of an APC output circuit according to the embodiment. This APC output circuit is shown in FIG.
(A) Inter-burst hold circuit (NMOSFET T5 and resistor R
2) and the VTH generation circuit of FIG. 19A. As a result, the inter-burst holding function shown in FIG. 18A and the high-speed APC start-up function shown in FIG.

FIG. 21B shows an AP according to another embodiment.
It is a circuit diagram of a C output circuit. This APC output circuit has a configuration in which the inter-burst holding circuit (PMOSFET T5 and resistor R2) in FIG. 18B and the VTH generating circuit in FIG. 19A are combined. As a result, the inter-burst holding function shown in FIG. 18B and the high-speed APC start-up function shown in FIG.

FIG. 22A is a circuit diagram of an APC output circuit according to still another embodiment. This APC output circuit corresponds to the burst hold circuit (NMOSFET T5) shown in FIG.
And the resistor R2) and the VTH generation circuit of FIG. 19B. As a result, FIG.
The function of holding the inter-burst shown in FIG. 19A and the function of starting up the high-speed APC shown in FIG.

FIG. 22B is a circuit diagram of an APC output circuit according to still another embodiment. This APC output circuit corresponds to the inter-burst holding circuit (PMOSFET T5 in FIG. 18B).
And the resistor R2) and the VTH generation circuit of FIG. 19B. As a result, FIG.
The inter-burst holding function shown in FIG. 19B and the high-speed APC start-up function shown in FIG.

FIG. 23A is a circuit diagram of an APC output circuit according to still another embodiment. This APC output circuit is an NMOSFET which is a burst hold circuit shown in FIG.
A discharge circuit composed of T5 and a resistor R2 is connected to V
_{It has} a configuration connected between the terminal of _PCONT and the gate of NMOSFET T6. As a result, the capacity C1 at the time of burst transmission is discharged toward the initialization voltage VTH of the APC in place of the ground GND, but the potential difference between both ends of the resistor R2 is reduced. Therefore, there is an advantage that a small value resistor R2 can be used even when the loop gain has the same time constant.

FIG. 23B is a circuit diagram of an APC output circuit according to still another embodiment. This APC output circuit is a PMOSFET which is a burst hold circuit shown in FIG.
A discharge circuit composed of T5 and a resistor R2 is connected to V
_{It has} a configuration connected between the terminal of _PCONT and the gate of NMOSFET T6. The operation can be considered as in the case of FIG.

FIG. 24A is a circuit diagram of an APC output circuit according to still another embodiment. This APC output circuit connects the switching NMOSFET T7 of FIG.
A configuration is provided in which the inverter circuit I is omitted instead of the OSFET T7. FIG. 24B is a circuit diagram of an APC output circuit according to still another embodiment. This APC output circuit connects the switching NMOSFET T7 of FIG.
A configuration is provided in which the inverter circuit I is omitted instead of the OSFET T7.

FIG. 25 is a diagram for explaining an optical output disconnection alarm circuit according to the embodiment, and FIG. 25 (A) is a circuit diagram thereof. This optical output interruption alarm circuit is basically a monitor photoelectric conversion circuit I which converts a monitor signal of a PD into a voltage signal.
VMON, a peak detection circuit for detecting the peak value MONH thereof, a V _th generation circuit for generating a predetermined threshold voltage V _th , and a comparison circuit CMP for comparing MONH with V _th . The comparison circuit CMP outputs the alarm signal SALM = 0 when MONH ≧ _Vth , and outputs the signal MONH <V
_When it becomes _th , SALM = 1 (alarm) is output.

In this case, the current-to-voltage conversion gain of IVMON is increased, and the amplitude of the monitor signal is increased. This increases the amplitude (sensitivity) of the optical output peak detection signal MONH. On the other hand, the Vth generation circuit has a simple circuit configuration that generates a predetermined threshold value _Vth . For example, a predetermined threshold voltage _Vth is generated by applying a constant current to a resistance load.
According to the above relationship, even if the threshold voltage _Vth slightly shifts due to, for example, an offset generated in the _Vth generation circuit, the ratio of the shift of _{Vth to} MONH is reduced because the signal amplitude of the monitor signal is increased. Therefore, the deviation of the alarm issuance level is also reduced.

Although the basic configuration according to the present embodiment may be the above-described one, preferably, the comparison circuit CMP has a hysteresis characteristic. Generally, the noise component of the signal MONH is about 50 mV, and thus, in this case, the threshold voltage V _th ′ is H = {5 kΩ / (200 kΩ + 5 kΩ)} × 3.3.
A hysteresis characteristic of about V ≒ 80 mV is provided.

FIG. 25B is an operation timing chart for detecting a light output cutoff having a hysteresis characteristic. As shown in the drawing, the potential of the signal MONH gradually decreases due to the deterioration of the LD and the like, and once MONH <V _th ', SALM = 1.
(HIGH level). In this case, the potential of V _th ′ increases by 80 mV due to the hysteresis characteristic, so that the potential of MONH due to noise does not become higher than V _th ′ again. Therefore, it is possible to prevent the optical output interruption alarm signal SALM from flapping.

Preferably, the monitor photoelectric conversion circuit IV
A low-pass filter for removing noise is inserted after the MON. As a result, the noise of the signal MONH is attenuated,
Is small. In each of the above embodiments, the circuit configuration using MOSFETs has been mainly described in accordance with the recent trend of the integration of this type of LSI into CMOS, but the idea of the present invention is to use other junction FETs or bipolar transistors. Needless to say, this can be achieved. Further, each circuit is not limited to the LSI, and each circuit may be configured as a discrete circuit.

In each of the above embodiments, an example of application to an LD driving device has been described.
It can be applied to driving of other light emitting elements. In addition, the input interface circuit, pulse width compensation circuit, bypass circuit, power saving control circuit, bottom detection circuit (peak detection circuit), inter-burst holding circuit, initial voltage generation circuit, optical output disconnection alarm circuit, etc. It goes without saying that each of the included inventive ideas can be applied to not only the light emitting element driving device but also various other communication devices and electronic devices.

Although the preferred embodiments of the present invention have been described, it is needless to say that various changes in the configuration, control, and combinations thereof can be made without departing from the spirit of the present invention. There is no.

[0127]

As described above, according to the present invention, the cost and power consumption can be further reduced, and a light emitting element driving device with high operation reliability can be provided, which contributes to the spread of optical communication. large.

[Brief description of the drawings]

FIG. 1 is a diagram showing a schematic configuration of an LD driving device according to an embodiment.

FIG. 2 is a diagram illustrating an input interface circuit according to an embodiment;

FIG. 3 is a diagram (2) illustrating the input interface circuit according to the embodiment;

FIG. 4 is a diagram (3) illustrating the input interface circuit according to the embodiment;

FIG. 5 is a diagram (1) illustrating a pulse width compensation circuit according to the embodiment;

FIG. 6 is a diagram (2) illustrating a pulse width compensation circuit according to the embodiment;

FIG. 7 is a diagram (3) illustrating a pulse width compensation circuit according to the embodiment;

FIG. 8 is a diagram illustrating a current limiting circuit according to the embodiment.

FIG. 9 is a diagram illustrating a bypass circuit according to the embodiment;

FIG. 10 is a diagram (1) illustrating a power saving control circuit according to the embodiment;

FIG. 11 is a diagram (2) illustrating the power saving control circuit according to the embodiment;

FIG. 12 is a diagram (1) illustrating a bottom detection circuit according to the embodiment;

FIG. 13 is a diagram (2) illustrating the bottom detection circuit according to the embodiment;

FIG. 14 is a diagram (3) illustrating a bottom detection circuit according to the embodiment;

FIG. 15 is a diagram (4) illustrating the bottom detection circuit according to the embodiment;

FIG. 16 is a diagram (5) illustrating the bottom detection circuit according to the embodiment;

FIG. 17 is a diagram (6) illustrating the bottom detection circuit according to the embodiment;

FIG. 18 is a diagram illustrating an inter-burst holding circuit according to the embodiment;

FIG. 19 is a diagram (1) illustrating an APC initial voltage generation circuit (VTH generation circuit) according to the embodiment;

FIG. 20 is a diagram (2) illustrating an APC initial voltage generation circuit (VTH generation circuit) according to the embodiment;

FIG. 21 is a diagram (1) illustrating an APC output circuit according to the embodiment;

FIG. 22 is a diagram (2) illustrating an APC output circuit according to the embodiment;

FIG. 23 is a diagram (3) illustrating an APC output circuit according to the embodiment;

FIG. 24 is a diagram (4) illustrating an APC output circuit according to the embodiment;

FIG. 25 is a diagram illustrating an optical output disconnection alarm circuit according to an embodiment.

FIG. 26 is a diagram showing a schematic configuration of a conventional LD driving device.

FIG. 27 is a diagram illustrating a conventional input interface circuit.

FIG. 28 is a diagram illustrating a conventional pulse width compensation circuit.

FIG. 29 is a diagram illustrating a conventional LD drive circuit with a current limiting function.

FIG. 30 is a diagram illustrating a driving method of a conventional LD driving circuit.

FIG. 31 is a diagram illustrating a conventional power saving control circuit.

FIG. 32 is a diagram (1) illustrating a conventional bottom detection circuit.

FIG. 33 is a diagram (2) illustrating a conventional bottom detection circuit;

FIG. 34 is a diagram (1) illustrating a conventional APC output stage circuit;

FIG. 35 is a diagram (2) illustrating a conventional APC output stage circuit;

FIG. 36 is a diagram illustrating a conventional light output interruption alarm circuit.

[Explanation of symbols]

Reference Signs List 10 main signal section 11 input interface circuit 12 flip-flop circuit 13 selector 14 signal detection circuit 15 power saving control circuit 16 pulse width compensation circuit 17 LD drive pre-stage circuit 18 LD drive circuit 20 APC section 21 reference signal generation circuit 22 I / V conversion circuit 23 Automatic light output control (APC) circuit 24 VTH generation circuit 25 Burst hold circuit 26 Optical output alarm circuit 27 Current limiting circuit 100 LD drive LSI LD Laser diode PD Photodiode V _PCNT LD current control signal

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Makoto Miki 2-1-1 Kitaichijo Nishi, Chuo-ku, Sapporo City, Hokkaido Inside Fujitsu Hokkaido Digital Technology Co., Ltd. (72) Inventor Shuichi Yasuda Kitaichijo-Nishi, Chuo-ku, Sapporo, Hokkaido 2-1-1 Fujitsu Hokkaido Digital Technology Co., Ltd. (72) Inventor Satoshi Matsuyama 2-1-1 Kita-Ichijo Nishi, Chuo-ku, Sapporo-city, Hokkaido Fujitsu Hokkaido Digital Technology Co., Ltd. (72) Inventor Norio Murakami Hokkaido Sapporo, Hokkaido Fujitsu Hokkaido Digital Technology Co., Ltd. (2-1) Kita-Ichijo-Nishi 2-chome, Chuo-ku, Tokyo (72) Inventor Hiroki Kanasaka 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Fujitsu Limited (72) Yukio Akazawa 3-19-2 Nishishinjuku, Shinjuku-ku, Tokyo Sun Within Telegraph and Telephone Co., Ltd. (72) Noboru Ishihara, Inventor 3-19-2 Nishi-Shinjuku, Shinjuku-ku, Tokyo Japan Within Telegraph and Telephone Co., Ltd. Telegraph and Telephone Corporation

Claims (26)

[Claims] 1. A light-emitting element driving device comprising a light-emitting element, a driving circuit for the light-emitting element, and a control circuit for controlling the light output of the light-emitting element to be constant, comprising: an input interface circuit for inputting a data signal; Comprises a plurality of input terminals, a high-impedance threshold voltage generation circuit connected to each input terminal, and a comparison circuit for comparing a data signal of each input terminal. 2. The light emitting element driving device according to claim 1, wherein the threshold voltage generating circuit comprises a voltage dividing circuit of a resistance element. 3. The light emitting device driving device according to claim 1, wherein the threshold voltage generating circuit comprises a voltage dividing circuit in which the FET is self-biased. 4. The light emitting device driving device according to claim 1, wherein the threshold voltage generating circuit comprises a voltage dividing circuit in which a bipolar transistor is self-biased. 5. A light-emitting element driving device comprising a light-emitting element, a driving circuit for the light-emitting element, and a control circuit for performing constant light output control of the light-emitting element, comprising: a pulse width compensation circuit for shaping a pulse width of a data signal; The pulse width compensating circuit has different transconductances of F.
A light-emitting element driving device comprising an inverter circuit in which ETs are complementarily connected. 6. A light-emitting element driving device including a light-emitting element, a driving circuit for the light-emitting element, and a control circuit for controlling constant light output of the light-emitting element, comprising: a pulse width compensation circuit for shaping a pulse width of a data signal; The pulse width compensating circuit has different transconductances of F.
A light emitting element driving device comprising an inverter circuit in which one of the ETs is a resistive load and the other is an inverting amplifier circuit. 7. A light emitting element driving device including a light emitting element, a driving circuit for the light emitting element, and a control circuit for performing constant light output control of the light emitting element, comprising: a pulse width compensation circuit for shaping a pulse width of a data signal; The pulse width compensation circuit comprises an inverter circuit in which bipolar transistors having different current amplification factors are connected in a complementary manner. 8. A light-emitting element driving device including a light-emitting element, a drive circuit for the light-emitting element, and a control circuit for performing constant light output control of the light-emitting element, comprising: a pulse width compensation circuit for shaping a pulse width of a data signal; The pulse width compensation circuit comprises an inverter circuit in which one of the bipolar transistors having different current amplification factors is used as a resistance load and the other is an inverting amplifier circuit. 9. A light-emitting element driving device comprising a light-emitting element, a driving circuit for the light-emitting element, and a control circuit for performing constant light output control of the light-emitting element, wherein a constant current source circuit for driving the light-emitting element and the current are switched. A driving circuit having a differential pair; a pre-stage circuit that performs amplitude adjustment and / or level conversion of a data signal input to the differential pair; and monitors a light emitting element driving current of the driving circuit so that the driving current is equal to or more than a predetermined value. A current limiting circuit that limits a drive signal applied to the constant current source circuit so as not to cause the constant current source circuit to lose a portion related to a data signal flow of at least one of the pre-stage circuit and the drive circuit. In addition to having a circuit configuration that is replicated, each of the necessary operating currents of the pre-stage circuit and the driving circuit is current mirrored at a predetermined ratio, and these are operated under the same conditions. Light emitting element driving apparatus characterized by monitoring light emitting element driving current of the circuit. 10. A light-emitting element driving device comprising a light-emitting element, a driving circuit for the light-emitting element, and a control circuit for controlling the light output of the light-emitting element to be constant. A flip-flop for retiming an input data signal by a predetermined clock signal And a selection circuit for selecting and outputting one of an input data signal and an output signal of the flip-flop circuit by external control, wherein the driving circuit is driven by the output signal of the selection circuit. Device driving device. 11. A light-emitting element driving device comprising a light-emitting element, a driving circuit for the light-emitting element, and a control circuit for performing constant light output control of the light-emitting element, wherein a constant current source circuit for driving the light-emitting element and the current are switched. A driving circuit having a differential pair; and a power saving control circuit for clamping each data signal to be applied to the differential pair to a cutoff region of the differential pair by a predetermined control signal. A light-emitting element driving device comprising a low-pass filter circuit for smoothing. 12. A low-pass filter circuit comprising: a capacitor; a first constant current source circuit for extracting a first current from the capacitor according to one level of a control signal; 12. The light emitting element driving device according to claim 11, further comprising: a second constant current source circuit that supplies the current. 13. The light emitting element driving device according to claim 12, wherein the first and second constant current source circuits do not include a resistance element. 14. A light emitting element driving device comprising a light emitting element, a driving circuit for the light emitting element, and a control circuit for controlling constant light output of the light emitting element, wherein a charge / recharge capacity based on a comparison between an input signal and an output signal. A peak detection circuit for detecting and holding a peak value of the input signal by discharging; and assisting charging / discharging of the capacitance based on a comparison between the input signal and an output signal of the peak detection circuit via a resistor. A light emitting element driving device, comprising: 15. An auxiliary current generating circuit, comprising: a differential amplifying or comparing circuit for comparing an input signal with an output signal of a peak detecting circuit via a resistor; and an output of the differential amplifying or comparing circuit. And an FET element for supplying a corresponding auxiliary current to the ground or the power supply side based on the following.
4. The light-emitting element driving device of 4. 16. A differential amplification or comparison circuit for comparing an input signal and a signal obtained from an output signal of a peak detection circuit via a resistor, and an output of the differential amplification or comparison circuit. 15. The light emitting element driving device according to claim 14, further comprising: a diode element that supplies a corresponding auxiliary current to the differential amplification or comparison circuit based on the following. 17. The light emitting device driving device according to claim 16, wherein the diode device is a MOSFET device having a common gate, drain, and device substrate. 18. The light-emitting element driving device according to claim 16, wherein the diode element comprises a MOSFET element having a common gate and drain. 19. A differential amplifier or comparison circuit for comparing an input signal with a signal obtained from an output signal of a peak detection circuit via a resistor, and an output of the differential amplification or comparison circuit. 15. The light-emitting element driving device according to claim 14, further comprising a bipolar transistor element that supplies a corresponding auxiliary current to the ground or the power supply side based on the following. 20. A light emitting element driving device comprising a light emitting element, a driving circuit for the light emitting element, and a control circuit for controlling the light output of the light emitting element constant. A constant current source circuit for driving the light emitting element and switching the current. A drive circuit having a differential pair, a control circuit for monitoring a light output of the light emitting element and generating a control voltage applied to the constant current source circuit for constant light output control to a capacitor, and the generated control voltage An inter-burst holding circuit for holding until a next burst transmission, wherein the inter-burst holding circuit includes an FET element which is driven ON / OFF by a control signal for data transmission / reception, and a resistor connected in series to the FET element A light-emitting element driving device comprising: 21. A light emitting element driving device comprising a light emitting element, a driving circuit for the light emitting element, and a control circuit for controlling the light output of the light emitting element constant. A constant current source circuit for driving the light emitting element and switching the current. A drive circuit having a differential pair, a control circuit for monitoring a light output of the light emitting element and generating a control voltage applied to the constant current source circuit for constant light output control to a capacitor, and generating a predetermined initialization voltage And a switch circuit interposed between the capacitor and the initial voltage generation circuit, the switch circuit being turned on when the power of the device is turned on. 22. An FET connected in parallel with a capacitor and driven ON / OFF by a control signal for data transmission / reception.
22. The light emitting element driving device according to claim 21, further comprising an inter-burst holding circuit having an element and a resistor connected in series to the FET element. 23. An on / off switch connected between a capacitor and an initial voltage generation circuit and controlled by a data transmission / reception control signal.
22. The light-emitting element driving device according to claim 21, further comprising: an inter-burst holding circuit having an F-driven FET element and a resistor connected in series to the FET element. 24. A light emitting element driving device comprising a light emitting element, a driving circuit for the light emitting element, and a control circuit for controlling the light output of the light emitting element to be constant. An alarm circuit, wherein the optical output alarm circuit comprises: a threshold generation circuit for generating a predetermined threshold; an amplifier circuit for amplifying a monitor signal of the optical output to a signal having an amplitude in consideration of the variation or fluctuation of the threshold; A light emitting element drive device comprising: a peak detection circuit that detects and holds a peak value of a subsequent monitor signal; and a comparison circuit that compares the threshold value with the peak value of the monitor signal to generate an alarm signal. . 25. The light emitting device driving device according to claim 24, wherein the comparison circuit has a hysteresis characteristic. 26. The light-emitting element driving device according to claim 24, further comprising a low-pass filter circuit for filtering a monitor signal of an optical output.