JP2012028497A - Circuit module - Google Patents

Circuit module Download PDF

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JP2012028497A
JP2012028497A JP2010164795A JP2010164795A JP2012028497A JP 2012028497 A JP2012028497 A JP 2012028497A JP 2010164795 A JP2010164795 A JP 2010164795A JP 2010164795 A JP2010164795 A JP 2010164795A JP 2012028497 A JP2012028497 A JP 2012028497A
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resin
thermal expansion
expansion coefficient
wiring board
bare chip
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JP5625578B2 (en
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Fumihiro Sano
文洋 佐野
Masato Nomiya
正人 野宮
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29075—Plural core members
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    • H01L2224/29082—Two-layer arrangements
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29499—Shape or distribution of the fillers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/325—Material
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PROBLEM TO BE SOLVED: To provide a circuit module having high connection reliability between a bare chip IC and a wiring board by making a thermal expansion coefficient of a filling resin between the bare chip IC and the wiring board in the vicinity of a bare chip IC protection film different from that in the vicinity of the wiring board.SOLUTION: A circuit module reduces a peeling failure of a filling resin by making a thermal expansion coefficient of a filling resin in the vicinity of a wiring board similar to a thermal expansion coefficient of the wiring board and making a thermal expansion coefficient of filling resin in the vicinity of a bare chip IC protection film similar to a thermal expansion coefficient of the bare chip IC protection film.

Description

本発明は、回路モジュールに関し、特に配線基板とベアチップＩＣとの間に樹脂が充填された回路モジュールに関する。   The present invention relates to a circuit module, and more particularly to a circuit module in which a resin is filled between a wiring board and a bare chip IC.

従来の回路モジュールは、例えば特許文献１に記載の構造が知られている。以下に、図５を参照しながら、特許文献１に記載の回路モジュールについて説明する。図５は回路モジュールを示す断面図である。   As a conventional circuit module, for example, a structure described in Patent Document 1 is known. The circuit module described in Patent Document 1 will be described below with reference to FIG. FIG. 5 is a cross-sectional view showing the circuit module.

ベアチップＩＣ１０１は機能面に端子電極１０２を備えるとともに、機能面が保護膜１０８で覆われている。端子電極１０２は半田バンプ１０３によって、基板１０４の上に形成された配線パターン１０５と接続している。配線パターン１０５には半田の流出を防止するソルダーレジスト１０６が形成されている。前記ベアチップＩＣ１０１と基板１０４の間には、アンダーフィル樹脂１０７が充填されている。   The bare chip IC 101 includes a terminal electrode 102 on a functional surface, and the functional surface is covered with a protective film 108. The terminal electrode 102 is connected to a wiring pattern 105 formed on the substrate 104 by solder bumps 103. A solder resist 106 for preventing the solder from flowing out is formed on the wiring pattern 105. An underfill resin 107 is filled between the bare chip IC 101 and the substrate 104.

特開２００１−６８５８４号公報JP 2001-65884 A

このようなベアチップＩＣの機能面には保護膜層が形成されている。この保護膜層と配線基板との熱膨張係数が大きく異なっている場合、間に配置される充填樹脂との熱膨張係数差により、保護膜と充填樹脂間、充填樹脂と配線基板間で剥離が生じることがあった。充填樹脂の熱膨張係数を調整することは可能だが、保護膜と配線基板との熱膨張係数が大きく異なっている場合は不十分な調整となっていた。   A protective film layer is formed on the functional surface of such a bare chip IC. When the thermal expansion coefficients of the protective film layer and the wiring board are greatly different, peeling is caused between the protective film and the filling resin and between the filling resin and the wiring board due to the difference in the thermal expansion coefficient with the filling resin arranged therebetween. It sometimes occurred. Although it is possible to adjust the thermal expansion coefficient of the filling resin, the adjustment is insufficient when the thermal expansion coefficients of the protective film and the wiring board are greatly different.

本発明は、これらの状況を鑑み、ベアチップＩＣと配線基板の間の充填樹脂の熱膨張係数をベアチップＩＣ保護膜近傍と配線基板近傍とで異なる状態とすることで充填樹脂の剥離不良を削減し、その結果、ベアチップＩＣと配線基板の接続信頼性の高い回路モジュールを提供しようとするものである。   In view of these situations, the present invention reduces the filling resin peeling failure by making the thermal expansion coefficient of the filling resin between the bare chip IC and the wiring board different between the bare chip IC protective film and the wiring board. As a result, an object of the present invention is to provide a circuit module having high connection reliability between a bare chip IC and a wiring board.

本発明に係る回路モジュールは、配線基板と、機能面を保護する保護膜を備え、配線基板の上に配置されたベアチップＩＣと、前記配線基板と前記ベアチップＩＣとを接続するバンプと、前記配線基板と前記ベアチップＩＣの間に充填された樹脂とを有する回路モジュールにおいて、前記樹脂の熱膨張係数は、前記配線基板近傍では配線基板の熱膨張係数に近い状態となっており、前記ベアチップＩＣ保護膜近傍では前記配線基板近傍の樹脂の熱膨張係数と異なり、かつベアチップＩＣ保護膜の熱膨張係数に近い状態となっていることを特徴としている。   The circuit module according to the present invention includes a wiring board, a protective film that protects the functional surface, a bare chip IC disposed on the wiring board, a bump that connects the wiring board and the bare chip IC, and the wiring In a circuit module having a substrate and a resin filled between the bare chip IC, the thermal expansion coefficient of the resin is close to the thermal expansion coefficient of the wiring substrate in the vicinity of the wiring substrate, and the bare chip IC protection In the vicinity of the film, the thermal expansion coefficient is different from that of the resin in the vicinity of the wiring board and is close to the thermal expansion coefficient of the bare chip IC protective film.

樹脂の熱膨張係数を変化させることで、剥離が生じやすい異種接合間である、保護膜と樹脂間、樹脂と配線基板間の熱膨張係数差による熱応力を緩和でき、剥離不良を削減することができる。その結果、ベアチップＩＣと配線基板の接続信頼性の向上が実現できる。   By changing the thermal expansion coefficient of the resin, it is possible to alleviate thermal stress due to the difference in thermal expansion coefficient between the protective film and the resin, between the resin and the wiring board, between different types of joints where peeling easily occurs, and to reduce peeling defects Can do. As a result, the connection reliability between the bare chip IC and the wiring board can be improved.

また、本発明に係る回路モジュールは、前記樹脂の前記配線基板近傍の熱膨張係数と、前記樹脂の前記ベアチップＩＣ保護膜近傍の熱膨張係数の差は、樹脂内のフィラー分布の変化によるものであることを特徴としている。   In the circuit module according to the present invention, the difference between the thermal expansion coefficient of the resin in the vicinity of the wiring board and the thermal expansion coefficient of the resin in the vicinity of the bare chip IC protective film is due to a change in filler distribution in the resin. It is characterized by being.

この場合には、フィラーの分布状態が変化することで、保護膜と樹脂間、樹脂と配線基板間の熱膨張係数差による熱応力を緩和でき、剥離不良を削減することができる。その結果、ベアチップＩＣと配線基板の接続信頼性の向上が実現できる。   In this case, by changing the filler distribution state, the thermal stress due to the difference in thermal expansion coefficient between the protective film and the resin, and between the resin and the wiring board can be relieved, and the separation failure can be reduced. As a result, the connection reliability between the bare chip IC and the wiring board can be improved.

また、本発明に係る回路モジュールは、前記樹脂内のフィラー分布は、前記配線基板近傍のフィラー密度がベアチップＩＣ保護膜近傍のフィラーの密度より高くなっていることを特徴としている。   The circuit module according to the present invention is characterized in that the filler distribution in the resin is such that the filler density in the vicinity of the wiring board is higher than the density of the filler in the vicinity of the bare chip IC protective film.

この場合には、フィラーの分布状態が変化することで、保護膜と樹脂間、樹脂と配線基板間の熱膨張係数差による熱応力を緩和でき、剥離不良を削減することができる。その結果、ベアチップＩＣと配線基板の接続信頼性の向上が実現できる。   In this case, by changing the filler distribution state, the thermal stress due to the difference in thermal expansion coefficient between the protective film and the resin, and between the resin and the wiring board can be relieved, and the separation failure can be reduced. As a result, the connection reliability between the bare chip IC and the wiring board can be improved.

また、本発明に係る回路モジュールは、前記樹脂は、熱膨張係数の異なる第１の樹脂層と第２の樹脂層を含むことを特徴としている。   The circuit module according to the present invention is characterized in that the resin includes a first resin layer and a second resin layer having different thermal expansion coefficients.

この場合には、保護膜と樹脂間、樹脂と配線基板間の熱膨張係数差による熱応力を緩和でき、剥離不良を削減することができる。その結果、ベアチップＩＣと配線基板の接続信頼性の向上が実現できる。   In this case, the thermal stress due to the difference in thermal expansion coefficient between the protective film and the resin and between the resin and the wiring board can be alleviated, and defective peeling can be reduced. As a result, the connection reliability between the bare chip IC and the wiring board can be improved.

本発明によれば、樹脂の熱膨張係数を変化させることで、剥離が生じやすい異種接合間である、保護膜と樹脂間、樹脂と配線基板間の熱膨張係数差による熱応力を緩和でき、剥離不良を削減することができる。その結果、ベアチップＩＣと配線基板の接続信頼性の向上が実現できる。   According to the present invention, by changing the thermal expansion coefficient of the resin, it is possible to relieve the thermal stress due to the difference in thermal expansion coefficient between the protective film and the resin, between the protective film and the resin, between the heterogeneous joints that are likely to peel off, Peeling defects can be reduced. As a result, the connection reliability between the bare chip IC and the wiring board can be improved.

本発明の回路モジュールの第１の実施形態を示す断面図である。It is sectional drawing which shows 1st Embodiment of the circuit module of this invention. 本発明の回路モジュールの第２の実施形態を示す断面図である。It is sectional drawing which shows 2nd Embodiment of the circuit module of this invention. 本発明の回路モジュールの第２の実施形態の変形例を示す断面図である。It is sectional drawing which shows the modification of 2nd Embodiment of the circuit module of this invention. 本発明の回路モジュールの第３の実施形態を示す断面図である。It is sectional drawing which shows 3rd Embodiment of the circuit module of this invention. 従来のフリップチップ実装構造を示す断面図である。It is sectional drawing which shows the conventional flip chip mounting structure.

以下に、本発明の第１〜第３の実施形態に係る回路モジュールについて、図１〜図４を参照して説明する。
（第１の実施形態）
本発明の第１の実施形態の回路モジュールは、図１に示すように、電極２を備えた配線基板１と、バンプ４を備えるとともに機能面を保護膜８で覆われ、配線基板１の上に配置されたベアチップＩＣ３と、配線基板１とベアチップＩＣ３の間に充填された樹脂５を備えている。 Below, the circuit module which concerns on the 1st-3rd embodiment of this invention is demonstrated with reference to FIGS. 1-4.
(First embodiment)
As shown in FIG. 1, the circuit module of the first embodiment of the present invention includes a wiring board 1 having electrodes 2 and bumps 4 and a functional surface covered with a protective film 8. And a resin 5 filled between the wiring substrate 1 and the bare chip IC3.

次に、第１の実施形態の回路モジュールの製造方法について説明する。まず、配線基板１を用意する。この配線基板１は低温焼成セラミック等からなるセラミック基板（熱膨張係数＝７〜１５ｐｐｍ／℃）やガラス・エポキシ等からなるプリント基板（熱膨張係数＝１５〜５０ｐｐｍ／℃）で構成される。この配線基板１の上に金属箔を用いてまたは印刷等でＣｕやＡｇ等からなる膜状電極２を形成する。   Next, a method for manufacturing the circuit module according to the first embodiment will be described. First, the wiring board 1 is prepared. The wiring substrate 1 is composed of a ceramic substrate (thermal expansion coefficient = 7 to 15 ppm / ° C.) made of low-temperature fired ceramic or the like, and a printed circuit board (thermal expansion coefficient = 15 to 50 ppm / ° C.) made of glass or epoxy. A film electrode 2 made of Cu, Ag, or the like is formed on the wiring substrate 1 using a metal foil or printing.

次に、バンプ４を備えたＷＬＣＳＰ等のベアチップＩＣ３を用意する。このベアチップＩＣ３の機能面は保護膜８で覆われている。この保護膜８はポリイミド樹脂膜等の有機膜やＳｉＮ等の無機膜で構成されている。この保護膜８の熱膨張係数は１０〜６４ｐｐｍ／℃である。   Next, a bare chip IC 3 such as WLCSP provided with bumps 4 is prepared. The functional surface of the bare chip IC 3 is covered with a protective film 8. The protective film 8 is composed of an organic film such as a polyimide resin film or an inorganic film such as SiN. The thermal expansion coefficient of the protective film 8 is 10 to 64 ppm / ° C.

なお、配線基板１と保護膜８は、一般的に選定される材料については、熱膨張係数は基板の方が小さくなっている。本実施形態はこの前提に基づき、以下説明する。   Note that the wiring substrate 1 and the protective film 8 have a smaller coefficient of thermal expansion for the generally selected material. This embodiment will be described below based on this premise.

次に、ベアチップＩＣ３を前記配線基板１の上に形成された電極２の上に配置し、加熱圧着等で接合する。   Next, the bare chip IC 3 is placed on the electrode 2 formed on the wiring substrate 1 and bonded by thermocompression bonding or the like.

次に、フラックス残渣を除去するため、ベアチップＩＣ３を実装した配線基板１を準水系洗浄剤で洗浄する。その後、洗浄剤を除去するため、ベーキング処理を行う。   Next, in order to remove the flux residue, the wiring board 1 on which the bare chip IC 3 is mounted is cleaned with a semi-aqueous cleaning agent. Thereafter, a baking process is performed to remove the cleaning agent.

次に、前記配線基板１とベアチップＩＣ３の間に、エポキシ樹脂等の熱硬化性樹脂からなる樹脂５を充填する。樹脂５を構成するエポキシ樹脂の樹脂成分単体での熱膨張係数は６０ｐｐｍ／℃である。この樹脂５にはＳｉＯ２からなるフィラーが、フィラーを含む樹脂５の重量に対して６５重量％含有されている。このフィラーの熱膨張係数は０．５ｐｐｍ／℃である。その後、ベアチップＩＣ３が実装され樹脂５が充填された配線基板１を熱処理炉に投入し、樹脂５を熱硬化する。硬化条件は、温度が７０℃〜１５０℃、時間が２時間〜８時間である。   Next, a resin 5 made of a thermosetting resin such as an epoxy resin is filled between the wiring board 1 and the bare chip IC 3. The thermal expansion coefficient of the resin component alone of the epoxy resin constituting the resin 5 is 60 ppm / ° C. This resin 5 contains 65% by weight of a filler made of SiO 2 with respect to the weight of the resin 5 containing the filler. The thermal expansion coefficient of this filler is 0.5 ppm / ° C. Thereafter, the wiring substrate 1 on which the bare chip IC 3 is mounted and filled with the resin 5 is put into a heat treatment furnace, and the resin 5 is thermoset. The curing conditions are a temperature of 70 ° C. to 150 ° C. and a time of 2 hours to 8 hours.

このような硬化条件で硬化すると、樹脂５に含有されているフィラーの移動により、前記配線基板１近傍の樹脂５は、前記ベアチップＩＣ３の保護膜８近傍の樹脂５に比べてフィラーの密度が高くなる。フィラーの熱膨張係数は配線基板１の熱膨張係数と近いため、配線基板１近傍の樹脂５の熱膨張係数は、熱硬化する前に比べて配線基板１の熱膨張係数に近くなる。   When cured under such curing conditions, due to the movement of the filler contained in the resin 5, the resin 5 in the vicinity of the wiring board 1 has a higher filler density than the resin 5 in the vicinity of the protective film 8 of the bare chip IC3. Become. Since the thermal expansion coefficient of the filler is close to the thermal expansion coefficient of the wiring board 1, the thermal expansion coefficient of the resin 5 in the vicinity of the wiring board 1 is closer to the thermal expansion coefficient of the wiring board 1 than before thermal curing.

一方、ベアチップＩＣ３の保護膜８近傍の樹脂５は、配線基板１近傍の樹脂５に比べてフィラーの密度が低くなる。つまり、樹脂成分であるエポキシ樹脂の割合が配線基板１近傍の樹脂５に比べて高くなる。樹脂５の主成分であるエポキシ樹脂の熱膨張係数はベアチップＩＣ３の保護膜８の熱膨張係数と近いため、ベアチップＩＣ３の保護膜８近傍の樹脂５の熱膨張係数は、熱硬化前に比べてベアチップＩＣ３の保護膜８の熱膨張係数に近くなる。   On the other hand, the resin 5 near the protective film 8 of the bare chip IC 3 has a lower filler density than the resin 5 near the wiring substrate 1. That is, the ratio of the epoxy resin that is a resin component is higher than that of the resin 5 in the vicinity of the wiring board 1. Since the thermal expansion coefficient of the epoxy resin, which is the main component of the resin 5, is close to the thermal expansion coefficient of the protective film 8 of the bare chip IC3, the thermal expansion coefficient of the resin 5 in the vicinity of the protective film 8 of the bare chip IC3 is larger than that before thermosetting. It becomes close to the thermal expansion coefficient of the protective film 8 of the bare chip IC3.

なお、材料、硬化温度、硬化時間等を制御することにより、バンプ４の周囲で樹脂５に含有されるフィラーの密度を高めることが可能になる。この場合、樹脂５の熱膨張係数とバンプ４の熱膨張係数が近づくことになるため、樹脂５とバンプ４の剥離が抑制できる。その結果、バンプ４近傍の配線基板１と樹脂５のより確実な密着が可能となる。
（第２の実施形態）
本発明の第２の実施形態の回路モジュールは、図２に示すように、電極１２を備えた配線基板１１と、バンプ１４を備えるとともに機能面を保護膜１８で覆われ、配線基板１１の上に配置されたベアチップＩＣ１３と、配線基板１１とベアチップＩＣ１３の間に第１の樹脂層１５と第２の樹脂層１６を備えている。 Note that the density of the filler contained in the resin 5 around the bump 4 can be increased by controlling the material, the curing temperature, the curing time, and the like. In this case, since the thermal expansion coefficient of the resin 5 and the thermal expansion coefficient of the bump 4 are close to each other, peeling of the resin 5 and the bump 4 can be suppressed. As a result, the wiring substrate 1 in the vicinity of the bump 4 and the resin 5 can be more securely adhered.
(Second Embodiment)
As shown in FIG. 2, the circuit module according to the second embodiment of the present invention includes a wiring board 11 provided with electrodes 12, bumps 14 and a functional surface covered with a protective film 18. And a first resin layer 15 and a second resin layer 16 between the wiring substrate 11 and the bare chip IC 13.

次に、第２の実施形態の回路モジュールの製造方法について説明する。まず、配線基板１１を用意する。この配線基板１１は低温焼成セラミック等からなるセラミック基板（熱膨張係数＝７〜１５ｐｐｍ／℃）やガラス・エポキシ等からなるプリント基板（熱膨張係数＝１５〜５０ｐｐｍ／℃）で構成される。この配線基板１１の上に金属箔を用いてまたは印刷等でＣｕやＡｇ等からなる膜状電極１２を形成する。   Next, a method for manufacturing the circuit module according to the second embodiment will be described. First, the wiring board 11 is prepared. The wiring board 11 is composed of a ceramic substrate (thermal expansion coefficient = 7 to 15 ppm / ° C.) made of low-temperature fired ceramic or the like, or a printed board (thermal expansion coefficient = 15 to 50 ppm / ° C.) made of glass or epoxy. A film electrode 12 made of Cu, Ag, or the like is formed on the wiring substrate 11 by using a metal foil or printing.

次に、電極１２が形成された配線基板１１の上に、エポキシ樹脂からなる厚さ２５〜７５μｍの非導電性フィルム１５ａを貼り付ける。この非導電性フィルム１５ａの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。次に、この非導電性フィルム１５ａの上に、エポキシ樹脂からなる厚さ２５〜７５μｍの非導電性フィルム１６ａを貼り付ける。この非導電性フィルム１６ａの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。非導電性フィルム１６ａは、非導電性フィルム１５ａの熱膨張係数に比べて、ベアチップＩＣ１３の保護膜１８の熱膨張係数に近い値となるようなエポキシ樹脂が選定されている。一方、非導電性フィルム１５ａは、非導電性フィルム１６ａの熱膨張係数に比べて、配線基板１１の熱膨張係数の熱膨張係数に近い値となるようなエポキシ樹脂が選定されている。なお、非導電性フィルムは３枚以上配置することも可能である。   Next, a non-conductive film 15a made of an epoxy resin and having a thickness of 25 to 75 μm is pasted on the wiring substrate 11 on which the electrodes 12 are formed. The thermal expansion coefficient of the nonconductive film 15a is generally 10 to 40 ppm / ° C. because an epoxy resin is used. Next, a non-conductive film 16a made of an epoxy resin and having a thickness of 25 to 75 μm is pasted on the non-conductive film 15a. The non-conductive film 16a generally has a thermal expansion coefficient of 10 to 40 ppm / ° C. because an epoxy resin is used. The non-conductive film 16a is selected from an epoxy resin that has a value closer to the thermal expansion coefficient of the protective film 18 of the bare chip IC 13 than the thermal expansion coefficient of the non-conductive film 15a. On the other hand, the non-conductive film 15a is selected from an epoxy resin that has a value closer to the thermal expansion coefficient of the wiring substrate 11 than the thermal expansion coefficient of the non-conductive film 16a. Note that three or more non-conductive films can be arranged.

次に、バンプ１４を備えたＷＬＣＳＰ等のベアチップＩＣ１３を用意する。このベアチップＩＣ１３の機能面は、保護膜１８で覆われている。この保護膜１８はポリイミド樹脂膜等の有機膜やＳｉＮ等の無機膜で構成されている。この保護膜１８の熱膨張係数は１０〜６４ｐｐｍ／℃である。このベアチップＩＣ１３を前記配線基板１１の上に貼りつけられた非導電性フィルム１５ａ及び非導電性フィルム１６ａの上に配置する。配置する位置は、配線基板１１の上に形成された電極１２の位置である。その後、加熱圧着にてバンプ１４を電極１２と接合させるとともに、非導電性フィルム１５ａおよび非導電性フィルム１６ａを硬化させることで、第１の樹脂層１５と第２の樹脂層１６を形成する。なお、バンプ１４と電極１２の間の非導電性フィルム１５ａおよび非導電性フィルム１６ａは、加熱圧着することで溶融するため、バンプ１４と電極１２の接続が可能となる。
（第２の実施形態の変形例１）
第２の実施形態の回路モジュールの変形例１について、第２の実施形態との相違点についてのみ説明する。配線基板１１の上に貼り付けられたエポキシ樹脂からなる非導電性フィルム１５ａの上に、バンプ１４を備えたＷＬＣＳＰ等のベアチップＩＣ１３を配置し、加熱圧着する。加熱することで非導電性フィルム１５ａが硬化し、第１の樹脂層１５となる。この第１の樹脂層１５と前記ベアチップＩＣ１３との間に、前記非導電性フィルム１６ａの代わりにエポキシ樹脂からなる液状樹脂１６ｂを充填する。この液状樹脂１６ｂの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。液状樹脂１６ｂおよび非導電性フィムル１５ａは、第２の実施形態と同様に、それぞれ所望の熱膨張係数となるようなエポキシ樹脂が選定されている。 Next, a bare chip IC 13 such as WLCSP provided with bumps 14 is prepared. The functional surface of the bare chip IC 13 is covered with a protective film 18. The protective film 18 is composed of an organic film such as a polyimide resin film or an inorganic film such as SiN. The thermal expansion coefficient of the protective film 18 is 10 to 64 ppm / ° C. The bare chip IC 13 is disposed on a non-conductive film 15a and a non-conductive film 16a attached on the wiring substrate 11. The position to be arranged is the position of the electrode 12 formed on the wiring board 11. Thereafter, the bumps 14 are joined to the electrodes 12 by thermocompression bonding, and the first and second resin layers 15 and 16 are formed by curing the nonconductive film 15a and the nonconductive film 16a. Since the nonconductive film 15a and the nonconductive film 16a between the bump 14 and the electrode 12 are melted by thermocompression bonding, the bump 14 and the electrode 12 can be connected.
(Modification 1 of 2nd Embodiment)
Only a difference from the second embodiment will be described in the first modification of the circuit module of the second embodiment. A bare chip IC 13 such as a WLCSP provided with bumps 14 is placed on a non-conductive film 15a made of an epoxy resin attached on the wiring board 11, and is thermocompression bonded. By heating, the non-conductive film 15 a is cured and becomes the first resin layer 15. A liquid resin 16b made of an epoxy resin is filled between the first resin layer 15 and the bare chip IC 13 instead of the non-conductive film 16a. The thermal expansion coefficient of the liquid resin 16b is generally 10 to 40 ppm / ° C. because an epoxy resin is used. As for the liquid resin 16b and the non-conductive film 15a, as in the second embodiment, an epoxy resin having a desired thermal expansion coefficient is selected.

その後、加熱して液状樹脂１６ｂを硬化させることで、第２の樹脂層１６を形成する。
（第２の実施形態の変形例２）
第２の実施形態の回路モジュールの変形例２の製造方法について図３を用いて説明する。まず、配線基板１１を用意する。この配線基板１１は低温焼成セラミック等からなるセラミック基板（熱膨張係数＝７〜１５ｐｐｍ／℃）やガラス・エポキシ等からなるプリント基板（熱膨張係数＝１５〜５０ｐｐｍ／℃）で構成される。この配線基板１１の上に金属箔を用いてまたは印刷等でＣｕやＡｇ等からなる膜状電極１２を形成する。この電極１２の上にハンダペーストを印刷、またはＡｕメッキする等で、柱状電極１７を形成する。 Thereafter, the second resin layer 16 is formed by heating to cure the liquid resin 16b.
(Modification 2 of the second embodiment)
The manufacturing method of the modification 2 of the circuit module of 2nd Embodiment is demonstrated using FIG. First, the wiring board 11 is prepared. The wiring board 11 is composed of a ceramic substrate (thermal expansion coefficient = 7 to 15 ppm / ° C.) made of low-temperature fired ceramic or the like, or a printed board (thermal expansion coefficient = 15 to 50 ppm / ° C.) made of glass or epoxy. A film electrode 12 made of Cu, Ag, or the like is formed on the wiring substrate 11 by using a metal foil or printing. The columnar electrode 17 is formed on the electrode 12 by printing solder paste or Au plating.

次に、電極（図示せず）を備えたＩＣウエハを用意する。ＩＣウエハの保護膜１８の上に、エポキシ樹脂からなる厚さ２５〜７５μｍの非導電性フィルム１６ａを貼り付ける。この非導電性フィルム１６ａの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。次に、この非導電性フィルム１６ａの上に、エポキシ樹脂からなる厚さ２５〜７５μｍの非導電性フィルム１５ａを貼り付ける。この非導電性フィルム１５ａの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍである。非導電性フィルム１５ａおよび非導電性フィムル１６ａは、第２の実施形態と同様に、それぞれ所望の熱膨張係数となるようなエポキシ樹脂が選定されている。その後、ＩＣウエハを位置合わせした状態でダイシングし、非導電性フィルム１６ａおよび非導電性フィルム１５ａが貼り付けられたベアチップＩＣ１３ａを形成する。   Next, an IC wafer provided with electrodes (not shown) is prepared. On the protective film 18 of the IC wafer, a non-conductive film 16a made of epoxy resin and having a thickness of 25 to 75 μm is attached. The non-conductive film 16a generally has a thermal expansion coefficient of 10 to 40 ppm / ° C. because an epoxy resin is used. Next, a non-conductive film 15a made of epoxy resin and having a thickness of 25 to 75 μm is pasted on the non-conductive film 16a. The thermal expansion coefficient of the nonconductive film 15a is generally 10 to 40 ppm because an epoxy resin is used. For the non-conductive film 15a and the non-conductive film 16a, as in the second embodiment, an epoxy resin having a desired coefficient of thermal expansion is selected. Thereafter, dicing is performed in a state where the IC wafer is aligned to form a bare chip IC 13a to which the nonconductive film 16a and the nonconductive film 15a are attached.

次に、ベアチップＩＣ１３ａを反転させ、前記配線基板１１に形成された前記柱状電極１７の上に配置する。その後、加熱圧着にてベアチップＩＣ１３ａの電極を柱状電極１７と接合させるとともに、非導電性フィルム１５ａおよび非導電性フィルム１６ａを硬化させることで、第１の樹脂層１５および第２の樹脂層１６を形成する。なお、ベアチップＩＣ１３ａの電極と柱状電極１７の間の非導電性フィルム１５ａおよび非導電性フィルム１６ａは、加熱圧着することで溶融するため、ベアチップＩＣ１３ａの電極と柱状電極１７の接続が可能となる。
（第３の実施形態）
本発明の第３の実施形態の回路モジュールは、図４に示すように、電極２２および柱状電極２７を備えた配線基板２１と、バンプ２４を備えるとともに機能面を保護膜２８で覆われ、配線基板２１の上に配置されたベアチップＩＣ２３と、配線基板２１とベアチップＩＣ２３の間に第１の樹脂層２５と第２の樹脂層２６を備えている。 Next, the bare chip IC 13 a is inverted and placed on the columnar electrode 17 formed on the wiring substrate 11. Thereafter, the electrodes of the bare chip IC 13a are joined to the columnar electrodes 17 by thermocompression bonding, and the first and second resin layers 15 and 16 are cured by curing the nonconductive film 15a and the nonconductive film 16a. Form. Since the nonconductive film 15a and the nonconductive film 16a between the electrode of the bare chip IC 13a and the columnar electrode 17 are melted by thermocompression bonding, the electrode of the bare chip IC 13a and the columnar electrode 17 can be connected.
(Third embodiment)
As shown in FIG. 4, the circuit module according to the third embodiment of the present invention includes a wiring board 21 including electrodes 22 and columnar electrodes 27, bumps 24, and a functional surface covered with a protective film 28. A bare chip IC 23 disposed on the substrate 21, and a first resin layer 25 and a second resin layer 26 are provided between the wiring substrate 21 and the bare chip IC 23.

次に、第３の実施形態の回路モジュールの製造方法について説明する。まず、配線基板２１を用意する。この配線基板２１は低温焼成セラミック等からなるセラミック基板（熱膨張係数＝７〜１５ｐｐｍ／℃）やガラス・エポキシ等からなるプリント基板（熱膨張係数＝１５〜５０ｐｐｍ／℃）で構成される。この配線基板２１の上に金属箔を用いてまたは印刷等でＣｕやＡｇ等からなる膜状電極２２を形成する。この電極２２の上に、ハンダペーストを印刷、またはＡｕメッキする等で、柱状電極２７を形成する。   Next, a method for manufacturing the circuit module according to the third embodiment will be described. First, the wiring board 21 is prepared. The wiring board 21 is composed of a ceramic substrate (thermal expansion coefficient = 7 to 15 ppm / ° C.) made of low-temperature fired ceramic or the like, and a printed circuit board (thermal expansion coefficient = 15 to 50 ppm / ° C.) made of glass or epoxy. A film-like electrode 22 made of Cu, Ag, or the like is formed on the wiring substrate 21 using a metal foil or printing. A columnar electrode 27 is formed on the electrode 22 by printing a solder paste or Au plating.

次に、柱状電極２７が形成された配線基板２１の上に、エポキシ樹脂からなる非導電性ペースト２５ａを塗布し、半硬化させる。この非導電性ペースト２５ａの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。非導電性ペースト２５ａを塗布する際、配線基板２１に形成された柱状電極２７に対する濡れ上がりが生じるため、非導電性ペースト２５ａが柱状電極２７の上部にまで配置されることになる。   Next, a non-conductive paste 25a made of an epoxy resin is applied on the wiring substrate 21 on which the columnar electrodes 27 are formed and semi-cured. The thermal expansion coefficient of the non-conductive paste 25a is generally 10 to 40 ppm / ° C. because an epoxy resin is used. When the nonconductive paste 25a is applied, the columnar electrode 27 formed on the wiring substrate 21 is wetted, so that the nonconductive paste 25a is disposed even above the columnar electrode 27.

次に、バンプ２４を備えたＷＬＣＳＰ等のベアチップＩＣ２３を用意する。このベアチップＩＣ２３の機能面は、保護膜２８で覆われている。この保護膜２８はポリイミド樹脂膜等の有機膜やＳｉＮ等の無機膜で構成されている。この保護膜２８の熱膨張係数は１０〜６４ｐｐｍ／℃である。このベアチップＩＣ２３を前記非導電性ペースト２５ａの上に配置する。配置する位置は、配線基板２１上の柱状電極２７の位置である。その後、加熱圧着にてバンプ２４を柱状電極２７と接合させるとともに、非導電性ペースト２５ａを硬化させることで、第１の樹脂層２５を形成する。なお、バンプ２４と柱状電極２７の間の半硬化状態の非導電性ペースト２５ａは、加熱圧着することで溶融するため、バンプ２４と柱状電極２７の接続が可能となる。   Next, a bare chip IC 23 such as a WLCSP provided with bumps 24 is prepared. The functional surface of the bare chip IC 23 is covered with a protective film 28. The protective film 28 is composed of an organic film such as a polyimide resin film or an inorganic film such as SiN. The thermal expansion coefficient of the protective film 28 is 10 to 64 ppm / ° C. The bare chip IC 23 is disposed on the non-conductive paste 25a. The position to be arranged is the position of the columnar electrode 27 on the wiring board 21. Thereafter, the bumps 24 are joined to the columnar electrodes 27 by thermocompression bonding, and the first conductive layer 25 is cured to form the first resin layer 25. The semi-cured non-conductive paste 25a between the bump 24 and the columnar electrode 27 is melted by thermocompression bonding, so that the bump 24 and the columnar electrode 27 can be connected.

次に、前記第１の樹脂層２５と前記ベアチップＩＣ２３との間に、エポキシ樹脂からなる液状樹脂２６ａを充填する。この液状樹脂２６ａの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。液状樹脂２６ａおよび非導電性ペースト２５ａは、第２の実施形態と同様に、それぞれ所望の熱膨張係数となるようなエポキシ樹脂が選定されている。   Next, a liquid resin 26 a made of an epoxy resin is filled between the first resin layer 25 and the bare chip IC 23. The thermal expansion coefficient of the liquid resin 26a is generally 10 to 40 ppm / ° C. because an epoxy resin is used. As for the liquid resin 26a and the non-conductive paste 25a, an epoxy resin having a desired coefficient of thermal expansion is selected as in the second embodiment.

その後、加熱して液状樹脂２６ａを硬化させることで、第２の樹脂層２６を形成する。   Thereafter, the second resin layer 26 is formed by heating to cure the liquid resin 26a.

前述の通り、非導電性ペースト２５ａを塗布する際、柱状電極２７に対する濡れ上がりが生じる。その結果、柱状電極２７の周囲では第１の樹脂層２５が厚くなる。一方、柱状電極２７の間中央付近では、第２の樹脂層２６が厚くなる。   As described above, when the non-conductive paste 25a is applied, the columnar electrode 27 is wetted. As a result, the first resin layer 25 is thicker around the columnar electrode 27. On the other hand, in the vicinity of the center between the columnar electrodes 27, the second resin layer 26 is thick.

柱状電極２７と第１の樹脂層２５の熱膨張係数は近いため、第１の樹脂層２５が厚くなり柱状電極２７との接触面積が増えることで、柱状電極２７と第１の樹脂層２５の剥離不良が削減できる。
（第３の実施形態の変形例１）
第３の実施形態の回路モジュールの変形例１について、第３の実施形態との相違点についてのみ説明する。配線基板２１の上に塗布し、半硬化させたエポキシ樹脂からなる非導電性ペースト２５ａの上に、前記液状樹脂２６ａの代わりにエポキシ樹脂からなる非導電性ペースト２６ｂを塗布する。この非導電性ペースト２６ｂの熱膨張係数はエポキシ樹脂を用いているので一般的に１０〜４０ｐｐｍ／℃である。非導電性ペースト２５ａおよび非導電性ペースト２６ｂは、第２の実施形態と同様に、それぞれ所望の熱膨張係数となるようなエポキシ樹脂が選定されている。 Since the thermal expansion coefficients of the columnar electrode 27 and the first resin layer 25 are close, the first resin layer 25 becomes thicker and the contact area with the columnar electrode 27 increases, so that the columnar electrode 27 and the first resin layer 25 Debonding failure can be reduced.
(Modification 1 of 3rd Embodiment)
Only a difference from the third embodiment will be described in Modification 1 of the circuit module according to the third embodiment. A non-conductive paste 26b made of an epoxy resin is applied instead of the liquid resin 26a on a non-conductive paste 25a made of an epoxy resin which is applied and semi-cured on the wiring board 21. The thermal expansion coefficient of the non-conductive paste 26b is generally 10 to 40 ppm / ° C. because an epoxy resin is used. As for the non-conductive paste 25a and the non-conductive paste 26b, an epoxy resin having a desired coefficient of thermal expansion is selected as in the second embodiment.

次に、バンプ２４を備えたＷＬＣＳＰ等のベアチップＩＣ２３を非導電性ペースト２６ｂの上に配置する。配置する位置は、柱状電極２７の位置である。その後、加熱圧着にてバンプ２４を柱状電極２７と接合させるとともに、非導電性ペースト２５ａおよび非導電性ペースト２６ｂを硬化させることで、第１の樹脂層２５および第２の樹脂層２６を形成する。なお、バンプ２４と柱状電極２７の間の半硬化状態の非導電性ペースト２５ａと非導電ペースト２６ｂは、加熱圧着することで溶融するため、バンプ２４と柱状電極２７の接続が可能となる。
（実験例）
第１の実施形態から第３の実施形態（変形例１）のように、配線基板とベアチップＩＣの間に樹脂充填された製品について、吸湿リフロー試験を行った。各実施形態の条件は次の通りである。 Next, the bare chip IC 23 such as WLCSP provided with the bumps 24 is disposed on the non-conductive paste 26b. The position to arrange is the position of the columnar electrode 27. Thereafter, the bumps 24 are joined to the columnar electrodes 27 by thermocompression bonding, and the first resin layer 25 and the second resin layer 26 are formed by curing the nonconductive paste 25a and the nonconductive paste 26b. . The semi-cured non-conductive paste 25a and non-conductive paste 26b between the bump 24 and the columnar electrode 27 are melted by thermocompression bonding, so that the bump 24 and the columnar electrode 27 can be connected.
(Experimental example)
As in the first to third embodiments (Modification 1), a moisture absorption reflow test was performed on a product filled with resin between the wiring board and the bare chip IC. The conditions of each embodiment are as follows.

第１の実施形態：配線基板＝セラミック基板、配線基板の熱膨張係数＝１２ｐｐｍ／℃、エポキシ樹脂＝６０ｐｐｍ／℃、ベアチップＩＣ保護膜の熱膨張係数＝３０ｐｐｍ／℃
第２の実施形態：配線基板＝プリント基板、配線基板の熱膨張係数＝２５ｐｐｍ／℃、第１の樹脂層（非導電性フィルム）の厚さ＝５０μｍ、第１の樹脂層（非導電性フィルム）の熱膨張係数＝２５ｐｐｍ／℃、第２の樹脂層（非導電性フィルム）の厚さ＝５０μｍ、第２の樹脂層（非導電性フィルム）の熱膨張係数＝３０ｐｐｍ／℃、ベアチップＩＣ保護膜の熱膨張係数＝３０ｐｐｍ／℃
第２の実施形態の変形例１：配線基板＝プリント基板、配線基板の熱膨張係数＝２５ｐｐｍ／℃、第１の樹脂層（非導電性フィルム）の厚さ＝５０μｍ、第１の樹脂層（非導電性フィルム）の熱膨張係数＝２５ｐｐｍ／℃、第２の樹脂層（液状樹脂）の熱膨張係数＝３０ｐｐｍ／℃、ベアチップＩＣ保護膜の熱膨張係数＝３０ｐｐｍ／℃
第２の実施形態の変形例２：配線基板＝プリント基板、配線基板の熱膨張係数＝２５ｐｐｍ／℃、第１の樹脂層（非導電性フィルム）の厚さ＝５０μｍ、第１の樹脂層（非導電性フィルム）の熱膨張係数＝２５ｐｐｍ／℃、第２の樹脂層（非導電性フィルム）の厚さ＝５０μｍ、第２の樹脂層（非導電性フィルム）の熱膨張係数＝３０ｐｐｍ／℃、ベアチップＩＣ保護膜の熱膨張係数＝３０ｐｐｍ／℃
第３の実施形態：配線基板＝プリント基板、配線基板の熱膨張係数＝２５ｐｐｍ／℃、第１の樹脂層（非導電性ペースト）の熱膨張係数＝２５ｐｐｍ／℃、第２の樹脂層（液状樹脂）の熱膨張係数＝３０ｐｐｍ／℃、ベアチップＩＣ保護膜の熱膨張係数＝３０ｐｐｍ／℃
第３の実施形態の変形例１：配線基板＝プリント基板、配線基板の熱膨張係数＝２５ｐｐｍ／℃、第１の樹脂層（非導電性ペースト）の熱膨張係数＝２５ｐｐｍ／℃、第２の樹脂層（非導電性ペースト）の熱膨張係数＝３０ｐｐｍ／℃、ベアチップＩＣ保護膜の熱膨張係数＝３０ｐｐｍ／℃
試験の内容は次の通りである。１２５℃で２４時間ベーキングした後、温度６０℃、湿度６０％の状態で１２０時間維持した。その後、２６０℃のピークリフローを５回通した。各実施形態の製品について、超音波探傷観察による不良数を調べた結果を表１に示す。 First embodiment: wiring board = ceramic substrate, thermal expansion coefficient of wiring board = 12 ppm / ° C., epoxy resin = 60 ppm / ° C., thermal expansion coefficient of bare chip IC protective film = 30 ppm / ° C.
Second embodiment: wiring board = printed board, thermal expansion coefficient of wiring board = 25 ppm / ° C., first resin layer (non-conductive film) thickness = 50 μm, first resin layer (non-conductive film) ) Thermal expansion coefficient = 25 ppm / ° C., second resin layer (non-conductive film) thickness = 50 μm, second resin layer (non-conductive film) thermal expansion coefficient = 30 ppm / ° C., bare chip IC protection Thermal expansion coefficient of membrane = 30 ppm / ° C.
Modification Example of Second Embodiment 1: Wiring Board = Print Board, Thermal Expansion Coefficient of Wiring Board = 25 ppm / ° C., First Resin Layer (Non-Conductive Film) Thickness = 50 μm, First Resin Layer ( Non-conductive film) thermal expansion coefficient = 25 ppm / ° C., second resin layer (liquid resin) thermal expansion coefficient = 30 ppm / ° C., bare chip IC protective film thermal expansion coefficient = 30 ppm / ° C.
Variation 2 of the second embodiment: Wiring board = printed board, thermal expansion coefficient of the wiring board = 25 ppm / ° C., first resin layer (non-conductive film) thickness = 50 μm, first resin layer ( Non-conductive film) thermal expansion coefficient = 25 ppm / ° C., second resin layer (non-conductive film) thickness = 50 μm, second resin layer (non-conductive film) thermal expansion coefficient = 30 ppm / ° C. Coefficient of thermal expansion of bare chip IC protective film = 30 ppm / ° C.
Third embodiment: wiring board = printed board, thermal expansion coefficient of wiring board = 25 ppm / ° C., thermal expansion coefficient of first resin layer (non-conductive paste) = 25 ppm / ° C., second resin layer (liquid Resin) = 30 ppm / ° C, bare chip IC protective film = 30 ppm / ° C
Modification Example of Third Embodiment 1: Wiring board = printed board, thermal expansion coefficient of wiring board = 25 ppm / ° C., thermal expansion coefficient of first resin layer (non-conductive paste) = 25 ppm / ° C., second Thermal expansion coefficient of resin layer (non-conductive paste) = 30 ppm / ° C. Thermal expansion coefficient of bare chip IC protective film = 30 ppm / ° C.
The contents of the test are as follows. After baking at 125 ° C. for 24 hours, the temperature was maintained at 60 ° C. and humidity 60% for 120 hours. Then, the peak reflow of 260 degreeC was passed 5 times. Table 1 shows the results of examining the number of defects by ultrasonic flaw detection for the products of each embodiment.

Figure 2012028497
Figure 2012028497

この表１から明らかなように、実施例は不良率が０％となっている。   As is apparent from Table 1, the defect rate in the example is 0%.

１、１１、２１：配線基板
２、１２、２２：電極
３、１３、２３：ベアチップＩＣ
４、１４、２４：バンプ
５：樹脂
８、１８、２８：保護膜
１５、２５：第１の樹脂層
１６、２６：第２の樹脂層
１７、２７：柱状電極
１０１：ベアチップＩＣ
１０２：端子電極
１０３：半田バンプ
１０４：基板
１０５：配線パターン
１０６：ソルダーレジスト
１０７：アンダーフィル樹脂
１０８：保護膜 1, 11, 21: Wiring board 2, 12, 22: Electrode 3, 13, 23: Bare chip IC
4, 14, 24: Bump 5: Resin 8, 18, 28: Protective film 15, 25: First resin layer 16, 26: Second resin layer 17, 27: Columnar electrode 101: Bare chip IC
102: Terminal electrode 103: Solder bump 104: Substrate 105: Wiring pattern 106: Solder resist 107: Underfill resin 108: Protective film

Claims (4)

配線基板と、機能面を保護する保護膜を備え、前記配線基板の上に配置されたベアチップＩＣと、前記配線基板と前記ベアチップＩＣとを接続するバンプと、前記配線基板と前記ベアチップＩＣの間に充填された樹脂とを有する回路モジュールにおいて、
前記樹脂の熱膨張係数は、前記配線基板近傍では配線基板の熱膨張係数に近い状態となっており、前記ベアチップＩＣ保護膜近傍では前記配線基板近傍の樹脂の熱膨張係数と異なり、かつベアチップＩＣ保護膜の熱膨張係数に近い状態となっていることを特徴とする回路モジュール。 A wiring board, a protective film that protects the functional surface, a bare chip IC disposed on the wiring board, a bump that connects the wiring board and the bare chip IC, and between the wiring board and the bare chip IC In a circuit module having a resin filled in
The thermal expansion coefficient of the resin is close to the thermal expansion coefficient of the wiring board in the vicinity of the wiring board, is different from the thermal expansion coefficient of the resin in the vicinity of the wiring board near the bare chip IC protective film, and is bare chip IC. A circuit module having a state close to a thermal expansion coefficient of a protective film. 前記樹脂の前記配線基板近傍の熱膨張係数と、前記樹脂の前記ベアチップＩＣ保護膜近傍の熱膨張係数の差は、樹脂内のフィラー分布の変化によるものであることを特徴とする請求項１に記載の回路モジュール。   The difference between the thermal expansion coefficient of the resin in the vicinity of the wiring board and the thermal expansion coefficient of the resin in the vicinity of the bare chip IC protective film is due to a change in filler distribution in the resin. The circuit module as described. 前記樹脂内のフィラー分布は、前記配線基板近傍のフィラー密度がベアチップＩＣ保護膜近傍のフィラーの密度より高くなっていることを特徴とする請求項２に記載の回路モジュール。   3. The circuit module according to claim 2, wherein the filler distribution in the resin is such that the filler density in the vicinity of the wiring board is higher than the density of the filler in the vicinity of the bare chip IC protective film. 前記樹脂は、熱膨張係数の異なる第１の樹脂層と第２の樹脂層を含むことを特徴とする請求項１に記載の回路モジュール。   The circuit module according to claim 1, wherein the resin includes a first resin layer and a second resin layer having different thermal expansion coefficients.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013135204A (en) * 2011-12-27 2013-07-08 Sumitomo Bakelite Co Ltd Semiconductor device
JP2013190354A (en) * 2012-03-14 2013-09-26 Nippon Soken Inc Joint member and manufacturing method of the same
JP2016048804A (en) * 2015-12-04 2016-04-07 住友ベークライト株式会社 Semiconductor device
JP2016182699A (en) * 2015-03-25 2016-10-20 パナソニックＩｐマネジメント株式会社 Film material and electronic component using the same, and method for manufacturing electronic component
KR20210002350A (en) * 2017-06-30 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device and method of manufacture
US11121050B2 (en) 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286297A (en) * 1999-01-29 2000-10-13 Matsushita Electric Ind Co Ltd Mounting method for electronic component and its device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000286297A (en) * 1999-01-29 2000-10-13 Matsushita Electric Ind Co Ltd Mounting method for electronic component and its device

Cited By (8)

* Cited by examiner, † Cited by third party
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JP2013135204A (en) * 2011-12-27 2013-07-08 Sumitomo Bakelite Co Ltd Semiconductor device
JP2013190354A (en) * 2012-03-14 2013-09-26 Nippon Soken Inc Joint member and manufacturing method of the same
JP2016182699A (en) * 2015-03-25 2016-10-20 パナソニックＩｐマネジメント株式会社 Film material and electronic component using the same, and method for manufacturing electronic component
JP2016048804A (en) * 2015-12-04 2016-04-07 住友ベークライト株式会社 Semiconductor device
KR20210002350A (en) * 2017-06-30 2021-01-07 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device and method of manufacture
US11121050B2 (en) 2017-06-30 2021-09-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device
US11201097B2 (en) 2017-06-30 2021-12-14 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacture of a semiconductor device
KR102383909B1 (en) * 2017-06-30 2022-04-08 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 Semiconductor device and method of manufacture

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