JP2012024417A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of surely detecting a fraud done to a detecting unit for detecting game media without increasing the processing load of a game control unit.SOLUTION: In case a period during which a detection signal is continuously input from a switch for detecting the prizewinning by a game ball exceeds a prescribed threshold or a frequency of inputs of detection signals exceeds a prescribed threshold, a presentation control microcomputer for controlling a presentation display device determines an occurrence of malfunction based on a command indicating the state of an input port from a game control microcomputer.

Description

  In the present invention, a player can play a predetermined game using a game medium, and a prize game medium is given as a prize based on the passage of the game medium through a predetermined passage area provided in the game area. It relates to gaming machines such as pachinko machines to be paid out.

  As a gaming machine, a game medium such as a game ball is launched into a game area by a launching device, and when a game medium wins a prize area such as a prize opening provided in the game area, a predetermined number of game media are paid out to the player. There is something to be done.

  Game progress in the gaming machine is controlled by game control means such as a microcomputer. If the payout control means for controlling the payout of game media is mounted on a payout control board different from the game control board (main board) on which the game control means is mounted, the progress of the game is mounted on the main board Therefore, the number of prize game media based on the winning is determined by the game control means, and a control command indicating the number of prize game media is transmitted to the payout control board. Then, the payout control means performs a process of paying out the prize game medium based on the winning based on the control command from the game control means (see, for example, Patent Document 1).

  In the gaming machine described in Patent Document 1, for abnormality detection, the game control means causes the detection signal from the detection means for detecting the game medium provided in the winning area to be in a state corresponding to the game medium detection state. If the period of time exceeds the predetermined period, it is determined that an abnormality has occurred in the detection means. Patent Document 1 describes that the game control means detects an illegal act (an act of illegally acquiring a game medium as a prize) based on a detection signal from the detection means.

JP 2000-5408 A

  In the gaming machine described in Patent Document 1, since the game control means executes a determination process as to whether or not an illegal act is performed based on a detection signal from a detection means for detecting a game medium, the game control process is originally performed. There is a problem that the processing load (in other words, the program amount) of the game control means to be executed increases.

  Accordingly, an object of the present invention is to provide a gaming machine that can reliably detect an illegal act against a detection means for detecting a game medium without increasing the processing load of the game control means.

The gaming machine according to the present invention enables a player to perform a predetermined game using a game medium (for example, a game ball), and a predetermined passing area (for example, a variable winning ball apparatus provided in the game area). 15, a winning opening 29, 30 and a large winning opening), which is a gaming machine that pays out a prize gaming medium as a prize based on the passing of the gaming medium, and detects the gaming medium passing through the passing area and outputs a detection signal. Detection means for outputting (for example, start port switch 14a, count switch 23 and winning port switches 29a and 30a) and game control means for executing game control processing for controlling the progress of the game (for example, game control microcomputer 560) And an electric component for controlling the electrical components (for example, the effect display device 9 and the ball payout device 97) provided in the gaming machine based on the command output by the game control means. Component control means (for example, the production control microcomputer 100 and the payout control microcomputer 370), the game control means inputs a detection signal from the detection means, and commands (for example, the input state of the detection signal) Command output means (for example, a part for executing the processing of step S111 in the game control microcomputer 560) that outputs the input port state designation command) to the electrical component control means. Based on the output command, the detection signal input period or the detection signal input frequency is a predetermined threshold (for example, 1 second for the period, 10 / 0.5 second for the input frequency: FIG. 49 and An abnormality determining means (for example, for effect control) that determines that an abnormality has occurred when exceeding (see FIG. 52) (The part that executes the abnormality determination process shown in FIGS. 51, 54, and 56 in the microcomputer 100, or the part that executes the abnormality determination process shown in FIGS. 59, 60, and 61 in the payout control microcomputer 100) It is characterized by including.
According to such a configuration, it is possible to reliably detect an illegal act against the detection means for detecting the game medium without increasing the processing load on the game control means.

The game control means inputs detection signals from each of the plurality of detection means via one input port (for example, input port 0 shown in FIG. 11), and the command output means collectively inputs the input data of the input ports. And output as a command (for example, output as 1-byte data).
According to such a configuration, the game control means can collectively transmit the detection signals of the detection means to the electrical component control means including the abnormality determination means, so that the plurality of detection means are subject to abnormality detection. Even in this case, the processing load of the game control means does not increase.

The electrical component control means executes payout control means (for example, payout) for executing payout control processing (for example, processing in step S765 shown in FIG. 37) for controlling payout means (for example, ball payout device 97) for paying out the prize game medium. A control microcomputer 370), and when the abnormality determining means determines that an abnormality has occurred, the payout control means outputs an abnormal signal indicating that an abnormality has occurred to the outside of the gaming machine (for example, an abnormal signal output means) The payout control microcomputer 370 may be configured to include a portion for executing the processes of steps S914, S940, and S960.
According to such a configuration, it is possible to grasp outside the gaming machine that an abnormality has occurred with respect to the detection means, and it is possible to more reliably detect fraud.

The abnormality determination means detects the number of times of input of the detection signal (see step S732 in FIG. 54 and step S932 in FIG. 60), and the number of times of input detected in a predetermined period (for example, 0.5 seconds) is a predetermined number of times (for example, 10), it may be configured to determine that an abnormality has occurred (see step S736 in FIG. 54, step S936 in FIG. 60).
According to such a configuration, since it is possible to detect an illegal act that illegally turns on and off the detection signal of the detection means, it is possible to detect the illegal act more reliably.

The command output means may be configured to output a command indicating the input state of the detection signal only when the input state of the detection signal changes (see steps S109 to S111 in FIG. 23).
According to such a configuration, an illegal act based on grasping the control cycle of the game control means based on the command output cycle can also be prevented.

It is the front view which looked at the pachinko game machine from the front. It is a front view which shows the front surface of the game board in the state which removed the glass door frame. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram showing a circuit configuration example of an effect control board. It is explanatory drawing which shows the example of the data register with which a serial communication circuit is provided. It is explanatory drawing which shows the example of the table memory for jackpot determination. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows a serial communication circuit setting process. It is a flowchart which shows a 4 ms timer interruption process. It is a flowchart which shows an example of a special symbol process process. It is explanatory drawing which shows an example of the content of the control signal output with respect to the payout control means from a game control means. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is explanatory drawing which shows the example of the error information set to a connection OK command and a prize ball preparation command. It is explanatory drawing for demonstrating an example of a cheating. It is explanatory drawing which shows an example of the content of an effect control command. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows prize ball transmission processing 1. It is a flowchart which shows a prize ball connection confirmation process. It is a flowchart which shows the prize ball transmission process 2. FIG. It is a flowchart which shows a prize ball receipt confirmation process. It is a flowchart which shows a prize ball completion | finish confirmation process. It is a flowchart which shows a prize ball counter subtraction process. It is explanatory drawing which shows the bit allocation example of the output port in a payout control means. It is explanatory drawing which shows the example of bit allocation of the input port in a payout control means. It is a flowchart which shows the main process which CPU for payout control performs. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows a main control communication process. It is a flowchart which shows a main control command reception process. It is a flowchart which shows a main control connection confirmation process. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows main control communication normal processing. It is a flowchart which shows the process during main control communication. It is a flowchart which shows the process during main control communication. It is a flowchart which shows a main control communication end process. It is a flowchart which shows the main process which the microcomputer for production control performs. It is a flowchart which shows a command analysis process. It is a flowchart which shows production control process processing. It is explanatory drawing which shows an example of the detection method of winning abnormality. It is explanatory drawing which shows an example of the timer which the microcomputer for production control uses regarding the detection of winning abnormality. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is explanatory drawing which shows the other example of the detection method of winning abnormality. FIG. 10 is an explanatory diagram illustrating an example of a timer, a flag, and a counter that are used by the production control microcomputer for detection of a winning abnormality. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is explanatory drawing which shows the further another example of the detection method of winning abnormality. It is a flowchart which shows the abnormality determination process which the microcomputer for production control performs. It is explanatory drawing which shows an example of the content of the control command transmitted / received between a game control means and a payout control means. It is a flowchart which shows the timer interruption process which CPU for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is a flowchart which shows the abnormality determination process which the microcomputer for payout control performs. It is explanatory drawing for demonstrating a photosensor. It is explanatory drawing which shows the example of combined use of a proximity switch and a photosensor. It is explanatory drawing which shows the other example of the bit allocation of the input port in a game control means.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiment, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and the present invention can also be applied to other gaming machines such as a slot machine. .

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding game boards described later). Is a structure including

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

  In the vicinity of the center of the game area 7, there is provided an effect display device 9 including a plurality of variable display portions each variably displaying an effect decorative pattern. The effect display device 9 includes, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. The effect display device 9 performs variable display of decorative symbols as decorative (effect) symbols during the variable symbol variable display period of the special symbol indicator 8. The effect display device 9 that performs variable display of decorative symbols is controlled by an effect control microcomputer mounted on the effect control board.

  Below the effect display device 9, four special symbol hold memory indicators 18 are provided for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the number of hold memories (also called start memory or start prize memory). ing. The special symbol reservation storage display 18 displays up to four reservation storage numbers in the order of winning. The special symbol hold storage display 18 increases the number of LEDs in the lit state by 1 each time there is a start winning in the start winning opening 14. Then, each time the special symbol display 8 starts variable display, the special symbol hold storage indicator 18 reduces the number of LEDs in the lit state by 1 (that is, turns off one LED). Specifically, the special symbol hold storage display 18 shifts the lighting state each time variable display is started on the special symbol display 8. In this example, the upper limit number (up to 4) is provided for the number of starting memories by winning to the start winning opening 14, but the upper limit number may be four or more.

  A special symbol display (special symbol display device) 8 that variably displays a special symbol as identification information is provided on the top of the effect display device 9. In this embodiment, the special symbol display 8 is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9, for example. The special symbol display 8 may be configured to variably display a larger number of numbers such as 0 to 99 in order to make it difficult for the player to grasp a specific stop symbol. In addition, the effect display device 9 performs variable display of the decorative symbol as a symbol for decoration (for effect) during the variable symbol display period of the special symbol by the special symbol indicator 8.

  Below the effect display device 9, a variable winning ball device 15 that forms a start winning opening 14 is provided. The variable winning ball device 15 is in one of a state where the game ball is easy to win (open state) and a state where the game ball is difficult to win (closed state). The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. The variable winning ball device 15 is opened by a solenoid 16. The first winning prize opening may be provided directly above the variable winning ball apparatus 15, and the variable winning ball apparatus 15 may be used as the second starting prize opening.

  Below the variable winning ball apparatus 15, there is provided a special variable winning ball apparatus 20 using an opening / closing plate that is controlled to be opened by a solenoid 21 in a specific gaming state (big hit state). The special variable winning ball apparatus 20 is a means for opening and closing the big winning opening. The game ball that has won the big winning opening is detected by the count switch 23.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting left and right lamps (designs can be visually recognized when lit). For example, if the left lamp is lit at the end of variable display, it is a hit. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The game board 6 is provided with a plurality of winning holes 29 and 30, and winning of game balls to the winning holes 29 and 30 is detected by winning hole switches 29a and 30a, respectively. Each of the winning ports 29 and 30 constitutes a winning area provided on the game board 6 as an area for accepting game media and allowing winning. The start winning opening 14 and the big winning opening also constitute a winning area that accepts game media and allows winning. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is lit during award ball payout is provided in the vicinity of the left frame lamp 28b, and a ball break lamp 52 that is lit when the supply ball is cut in the vicinity of the top frame lamp 28a. Is provided. Further, a prepaid card unit (hereinafter referred to as “card unit”) 50 that enables lending a ball by inserting a prepaid card is installed adjacent to the pachinko gaming machine 1.

  The card unit 50 includes, for example, a usable display lamp that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator that indicates which side of the pachinko gaming machine 1 corresponds to the card unit, and a card unit. When checking the card insertion indicator lamp indicating that a card is inserted in the card, the card insertion slot into which the card as a recording medium is inserted, and the card reader / writer mechanism provided on the back of the card insertion slot A card unit lock for releasing the card unit is provided.

  A game ball launched from the ball striking device by the player's operation enters the game area 7 through the hit ball rail, and then descends the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol on the special symbol display 8 starts variable display (variation) if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the number of reserved memories is increased by one.

  The variable display of the special symbol on the special symbol display device 8 stops when a certain time has elapsed. If the special symbol (stop symbol) at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the special variable winning ball apparatus 20 is released until a predetermined time elapses or a predetermined number (for example, 10) of gaming balls wins. The number of times of opening is 15 times.

  When the special symbol on the special symbol display 8 at the time of stoppage is a jackpot symbol (probability variation symbol) with a probability variation, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball passes through the gate 32, the normal symbol display unit 10 enters a state in which the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side. As shown in FIG. 3, on the back side of the pachinko gaming machine 1, a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, and the like are provided. Various boards such as a mounted game control board (main board) 31, an audio output board 70, a lamp driver board 35, and a payout control board 37 mounted with a payout control microcomputer for performing ball payout control are installed. Yes. The main board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, a power supply substrate 910 and a touch sensor substrate 91 on which power supply circuits for generating various power supply voltages such as DC30V, DC21V, DC12V, and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. And a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided.

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like.

  A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. A payout number counting switch for counting prize balls and rental balls is also configured as part of the unit. In this embodiment, the payout detecting means is realized by the payout number count switch 301 and detects that a prize ball or a lending ball is actually paid out from the ball payout device 97. The payout count switch 301 outputs a detection signal every time one payout of a prize ball or a lending ball is detected.

  On the back side of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 is provided with, for example, a door opening signal terminal for externally outputting a door opening signal indicating that the game frame is in an open state.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail (in the storage tank 38). (Proximate part). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 4 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 4 also shows a payout control board 37, an effect control board 80, and the like. A game control microcomputer (corresponding to a game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the time of reading (extracting) the numerical data, it has a random number generation function in which the read numerical data becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads numerical data from the random number circuit 503 as a random R when a start winning to the start port switch 14a occurs, and performs a specific display based on the random R at the start of the variation of the special symbol and the decorative symbol. It is determined whether or not to make a jackpot display result as a result, that is, whether or not to make a jackpot. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  In addition, the game control microcomputer 560 has a built-in serial communication circuit 505 for inputting / outputting (transmitting / receiving) signals to / from the payout control board 37 (the payout control microcomputer 370) by serial communication. The payout control microcomputer 370 also includes a serial communication circuit for inputting / outputting signals through the game control microcomputer 560 through serial communication (see FIG. 5).

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (such as a special symbol process flag and the value of the pending storage number counter) and data indicating the number of unpaid prize balls are stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for restoring the control state before the occurrence of a power failure or the like based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid prize balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. When the reset signal becomes high level, the game control microcomputer 560 and the like become operable. Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Also, an input driver circuit 58 for supplying the basic circuit 53 with detection signals from the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a is also mounted on the main board 31, and the variable winning ball device 15 An output circuit 59 for driving the solenoid 16 for opening / closing and the solenoid 21 for opening / closing the special variable winning ball apparatus according to a command from the CPU 56 is also mounted on the main board 31, and an information output signal such as jackpot information indicating the occurrence of the jackpot gaming state Is also mounted on the main board 31 to output information to an external device such as a hall computer.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. Receive. Then, the effect control means receives the effect control command and performs display control of the effect display device 9 that variably displays the decorative symbols.

  FIG. 5 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 5, a payout control microcomputer 370 including a payout control CPU 371 is mounted on the payout control board 37. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication.

  The payout control microcomputer 370 receives, via the output port 372b, a prize ball information signal indicating the number of prize balls to be paid and a ball lending number signal indicating the number of balls to be rented to a terminal board (frame external terminal board and board external terminal board). Output to 160). A driver circuit is provided outside the output port 372b, but is not shown in FIG.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. Further, a signal for instructing turning on / off is output to the winning ball LED 51 and the ball running out LED 52 via the output port 372b. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. Although a driver circuit (motor drive circuit) is installed outside the output port 372a, the description is omitted in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. The interface board (relay board) 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. .

  FIG. 6 is a block diagram illustrating a circuit configuration example of the relay board 77 and the effect control board 80. FIG. 6 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 6, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 is equipped with an effect control microcomputer 100 including an effect control CPU 101a and a RAM for storing information related to effects such as an effect control process flag. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101a operates according to a program stored in a built-in or external ROM (not shown). The effect control microcomputer 100 has a built-in serial communication circuit 101b that inputs / outputs (transmits / receives) signals with the game control microcomputer 560 through serial communication. In addition, the effect control CPU 101a causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101a outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores in advance character image data and moving image data to be displayed on the effect display device 9, specifically, a person, characters, figures, symbols, etc. (including decorative symbols), and background image data. ROM. The VDP 109 reads the image data from the CGROM in response to the instruction from the effect control CPU 101a. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 a outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. In addition, the production control CPU 101 a outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, signals for driving LEDs and lamps are input to the lamp driver 352 via the input driver 351. The lamp driver 352 supplies current to light emitters provided on the frame side such as the top frame lamp 28a, the left frame lamp 28b, and the right frame lamp 28c based on a signal for driving the lamp. In addition, a current is supplied to the decorative lamp 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data indicating the sound effect or sound output mode in a time series in a predetermined period (for example, a decorative symbol variation period).

  FIG. 7 is an explanatory diagram showing an example of a data register built in the serial communication circuit 505. The data register is a register that stores data transmitted and received by the serial communication circuit 505. As shown in FIG. 7, the data register is an 8-bit register, and the initial value is set to “0 (= 00h)”. The data register is configured in a state where bits 0 to 7 can be written and read.

  In this embodiment, when the serial communication circuit 505 transmits transmission data, the data register is used as a transmission data register. When the serial communication circuit 505 receives received data, the data register is used as a received data register.

  An interrupt control circuit built in the serial communication circuit 505 makes various interrupt requests to the CPU 56. For example, when the transmission of the transmission data to the transmission data register is completed, the interrupt control circuit outputs an interrupt signal to the CPU 56 and sets “6” to the bit 6 (TC) of the status register built in the serial communication circuit 505. An interrupt request is made by setting “1”. The interrupt control circuit may output an interrupt signal different for each interrupt factor to the CPU 56 instead of making the interrupt factor identifiable by the set value of the status register bit.

  When the reception data register is stored in the reception data register (when reception data full is detected), the interrupt control circuit outputs an interrupt signal to the CPU 56 and sets “1” to bit 5 (RDRF) of the status register. ”Is set to make an interrupt request.

  Further, when various communication errors occur, the interrupt control circuit outputs an interrupt signal to the CPU 56 and sets an interrupt request by setting “1” in bits 0 to 3 of the status register according to the type of the communication error. I do.

  FIG. 8 is an explanatory diagram of an example of the jackpot determination table memory. The jackpot determination table memory stores a plurality of jackpot determination tables used by the CPU 56 to determine whether or not the display result of the special symbol display device 8 is a jackpot symbol. Specifically, as shown in FIG. 8A, the jackpot determination table memory stores a normal-time jackpot determination table used in a gaming state (referred to as a normal state) other than the probability variation state. Further, as shown in FIG. 8B, the jackpot determination table memory stores a probability change jackpot determination table used in the probability change state.

  9 and 10 are explanatory diagrams showing an example of output port assignment in the game control means. As shown in FIG. 9, the output port 0 is an output port of a payout control signal (a connection signal in this embodiment) transmitted to the payout control board 37. The output port 1 has a solenoid (large winning port door solenoid) 21 for opening and closing a variable winning ball device 20 for opening and closing the big winning port and a solenoid (normal electric accessory solenoid) for opening and closing the variable winning ball device 15. There are 16 output ports.

  Then, various information output signals from the output port 2 to the information terminal board 34 and the terminal board 160 through the information output circuit 64, that is, output data of information related to control are output.

  FIG. 11 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 11, detection signals from the count switch 23, the gate switch 32a, the winning port switches 29a and 30a, and the start port switch 14a are input to bits 0 to 4 of the input port 0, respectively. The winning ball information from the payout control board 70 is input to bit 7 of the input port 0. Also, the power-off signal from the power supply board 910 and the detection signal of the clear switch 921 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the gaming machine will be described. 12 and 13 show main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is a flowchart which shows. When the input level of the reset terminal to which the reset signal is input becomes a high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). Note that the CPU 56 starts outputting the connection signal in the process of step S4, and then supplies the payout control microcomputer 370 to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output becomes impossible due to some communication error. The connection signal is output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S4, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized). The game control microcomputer 560 used in this embodiment also includes an I / O port (PIO) and a timer / counter circuit (CTC). Further, the CPU 56 sets the RAM 55 in an accessible state (step S6).

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). If the clear switch is not on, it is confirmed whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped ( Step S8). In this embodiment, when the power supply is stopped, the CPU 56 performs a power supply stop process for protecting data in the backup RAM area. In the power supply stop process, a flag indicating that the power supply stop process has been executed is set in the backup flag area. In step S8, the CPU 56 determines that the power supply stop process has been performed after confirming that the flag is set.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check of the backup RAM area (in this example, checksum calculation) (step S9).

  The checksum is calculated even when the power supply is stopped, and the checksum is stored in the backup RAM area. In step S9, the CPU 56 compares the calculated checksum with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). If the check result is not normal, initialization processing (steps S10 to S14) is executed.

  If the check result is normal, the CPU 56 performs a game state restoration process for returning the internal state of the game control means and the control state of the electrical component control means such as the effect control means to the state when the power supply is stopped. Specifically, the start address of the backup setting table stored in the ROM 54 is set as a pointer (step S91), and the contents of the backup setting table are sequentially set in the work area (area in the RAM 55) (step S92). ). The work area is backed up by a backup power source. In the backup setting table, initialization data for an area that may be initialized in the work area is set. As a result of the processing in steps S91 and S92, the saved contents of the work area that should not be initialized remain. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S93), and proceeds to step S15. After the pointer is set in step S93, the backup command is transmitted after the serial communication circuit setting process in step S15a is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Also, the initial address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above. In addition, a bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set (corresponding to the ON state of the connection confirmation signal). When the bit corresponding to the output port that outputs the connection confirmation signal in the output port buffer is set, the bit corresponding to the output port 0 that outputs the connection confirmation signal is output by the output processing in step S31.

  Further, the CPU 56 sets the start address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After the pointer is set in step S13, the initialization command is transmitted after the serial communication circuit setting process in step S15a is performed.

  Further, the CPU 56 executes a random number circuit setting process for initially setting each random number circuit 503 (step S15). That is, the setting for causing each random number circuit 503 to update the value of the random R is performed.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 in accordance with the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  Next, FIG. 14 is a flowchart showing the serial communication circuit setting process. In the serial communication circuit setting process, the CPU 56 first sets the baud rate of the serial communication circuit 505 (step S1511). Further, the CPU 56 sets a data format of data transmitted / received by the serial communication circuit 505 (step S1512). For example, the data length (8 bits or 9 bits) of transmission / reception data and the use / nonuse of the parity function are set.

  In addition, the CPU 56 sets whether to permit each interrupt request generated by the serial communication circuit 505 (step S1513). For example, the CPU 56 sets whether or not to permit a transmission interrupt request (a transmission interrupt request that is an interrupt request that is performed when data is transmitted or a transmission completion interrupt request that is performed when transmission is completed) and a reception interrupt request.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 505 (step S15b). For example, the CPU 56 sets a higher priority for interrupt processing that causes the occurrence of a communication error as the cause of the interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  In addition, as display random numbers, there are a variation pattern determination random number for determining a variation pattern of a special symbol, and a reach determination random number for determining whether or not to reach when a big hit is not generated. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. When an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process, reception time interrupt, Load processing, transmission completion interrupt processing).

  It should be noted that the processing of step S15 and step S15a may be executed before the processing of step S1, and the microcomputer for game control is automatically set before the processing of step S1 is executed. 560 may be used.

  Next, the timer interrupt process will be described. FIG. 15 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) that detects whether or not a power-off signal has been output (whether or not it has been turned on) (step S21). Then, the CPU 56 inputs detection signals from the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a via the input driver circuit 58, and detects the input of each switch (switch processing). : Step S22). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S23). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S24).

  Next, the CPU 56 performs a process of transmitting an effect control command or the like related to a decorative symbol synchronized with the change of the special symbol to the effect control microcomputer 100 (command control process: step S25). It should be noted that the fact that the variation of the decorative symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  In addition, the CPU 56 executes a process of transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, the winning opening switch 29a, 30a. A prize ball process is performed for setting the number of prize balls based on the detection signal such as (step S26). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switch 29a, 30a being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  Further, the CPU 56 performs special symbol process processing (step S27). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S28). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes a test terminal process which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine (step S30). In this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. However, the CPU 56 determines the contents related to the connection confirmation signal in the RAM area of the output port 0 and the output port. The contents related to the solenoid in the RAM area 2 are output to the output port (step S31: output process).

  Thereafter, the interrupt permission state is set (step S32), and the process ends.

  With the above control, in this embodiment, the game control process is started every 4 ms. The game control process corresponds to the processes of steps S22 to S31 (except for steps S29 and S30) in the timer interrupt process. In this embodiment, the game control process is executed by the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process is performed by the main process. May be executed.

  Next, the control of the special symbol and the special winning opening will be described. FIG. 16 is a flowchart showing an example of a program for the special symbol process (step S27) executed by the CPU 56 of the game control microcomputer 560. The CPU 56 of the game control microcomputer 560 has the start opening switch 14a for detecting that a game ball has won the start winning opening 14 provided in the game board 6 turned on, that is, the game ball has a start winning prize. If the winning opening is received and the winning detection signal SS is input from the start opening switch 14a (step S311), after performing the start opening switch passing process (step S312) for extracting and storing random numbers, the internal state ( Specifically, any one of steps S300 to S306 is performed according to the value of the special symbol process flag.

  Special symbol normal processing (step S300): A state in which variable symbol special display can be started (for example, the symbol variation has not been made in the special symbol display 8, and the previous symbol variation in the special symbol display 8 has been completed. Waits for a predetermined period of time to elapse, and not a big hit game). When the special symbol variable display can be started, the start winning memory number for the special symbol is confirmed. If the number of starting winning prizes is not 0, it is determined whether or not the result of variable symbol special display is a big hit based on the random R generated by the random number circuit 503 stored in the special figure holding memory. Further, when it is determined to be a big hit, control for transmitting a display result designation command capable of specifying the determined display result to the microcomputer 100 for effect control is further determined, such as whether or not to make a probable big hit. I do. Then, the internal state (special symbol process flag) is updated so as to shift to step S301.

  Fluctuation time setting process (step S301): A variation pattern is determined, and a variation pattern in the variation pattern (variable display time: time from the start of variable display until the display result is derived and displayed (stop display)) is a special symbol. It is determined to be a variable display variable time. In addition, control is performed to transmit a variation pattern command specifying the determined variation pattern to the effect control microcomputer 100, and a variation time timer for measuring the variation time of the determined special symbol is started. Then, the internal state (special symbol process flag) is updated so as to shift to step S302.

  Special symbol variation processing (step S302): When a predetermined time (the time indicated by the variation time timer in step S301) elapses, the internal state (special symbol process flag) is updated to shift to step S303.

  Special symbol stop process (step S303): A symbol confirmation designation command for instructing stop of the decorative symbol is transmitted to the effect control board 80. Moreover, the special symbol in the special symbol display 8 is stopped. If the stop symbol of the special symbol is a jackpot symbol, the internal state (special symbol process flag) is updated to shift to step S304. If not, the internal state is updated to shift to step S300. It is not necessary to transmit the symbol confirmation designation command. In that case, the production control microcomputer 100 performs a process of stopping the decorative design when the variation time based on the variation pattern command received from the main board 31 has elapsed.

  Preliminary winning opening opening process (step S304): Control for opening the large winning opening is started. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the grand prize opening) and a flag (a flag used when detecting winning in the prize opening) are initialized, and the solenoid 21 is driven. Open the big prize opening. Also, the process timer sets the execution time of the big prize opening opening process and sets the big hit flag. Then, the internal state (special symbol process flag) is updated so as to shift to step S305.

  Processing for opening a special prize opening (step S305): control for sending a presentation control command for round display of the special prize opening to the production control board 80 and closing conditions for the special prize opening (for example, a predetermined number (for example, ten) for the special prize opening ) To confirm that the game ball has won a prize). If the closing condition for the big prize opening is satisfied, if there are still rounds, the internal state (special symbol process flag) is updated to shift to step S304. When all the rounds have been completed, the internal state (special symbol process flag) is updated to shift to step S306.

  Big hit end processing (step S306): Control for causing the effect control means to perform display control for notifying the player that the big hit gaming state has ended. Then, the internal state (special symbol process flag) is updated so as to shift to step S300.

  Next, payout control signals and payout control commands transmitted and received between the main board 31 and the payout control board 37 will be described. FIG. 17 is an explanatory diagram showing an example of the contents of a control signal output from the game control means to the payout control means. In this embodiment, a connection signal and prize ball information are transmitted and received as control signals between the main board 31 and the payout control board 37 in order to perform various controls relating to payout control and the like.

  As shown in FIG. 17, the connection signal is output when the main board 31 rises (when the game control means starts the game control process), and notifies the payout control board 37 that the main board 31 has risen. This is a signal (connection signal for the main board 31). The connection signal indicates that the prize ball can be paid out. The connection signal is output via the I / O port 57 and the output circuit 67A of the game control microcomputer 560, and is used for payout control via the input circuit 373A and the I / O port 372e of the payout control microcomputer 370. It is input to the microcomputer 370. The connection signal is 1-bit data and is transmitted through one signal line. Note that the connection signal is ready to be output by setting an initial value to a bit corresponding to the connection signal of the output port 0 by the process of step S4 executed at power-on (specifically, in step S31). Although it is output by processing, it may be output at the timing of step S4).

  Similarly to the game control microcomputer 560, the payout control microcomputer 370 includes a serial communication circuit 380. Various payout control commands are transmitted and received between the serial communication circuit 505 built in the game control microcomputer 560 and the serial communication circuit 380 built in the payout control microcomputer 370. The configuration and function of the serial communication circuit 380 built in the payout control microcomputer 370 are the same as the configuration and function of the serial communication circuit 505 built in the game control microcomputer 560.

  The prize ball information is information for notifying the main board 31 that ten prize balls have been detected each time ten prize balls are paid out on the payout control board 37 side. . The prize ball information is output via the I / O port 372a and the output circuit 373B of the payout control microcomputer 370, and the game control is performed via the input circuit 67B and the I / O port 57 of the game control microcomputer 560. To the microcomputer 560. The prize ball information is 1-bit data and is transmitted through one signal line.

  FIG. 18 is an explanatory diagram showing an example of the contents of control commands transmitted / received between the game control means and the payout control means. In this embodiment, various payout control commands are transmitted and received between the microcomputers of the main board 31 and the payout control board 37 in order to perform various controls related to payout control and the like.

  As described above, the payout control command is composed of 8-bit data (binary 8-digit data), and is output as a control command indicating predetermined contents depending on the contents of the set 8-bit data.

  The connection confirmation command is used for game control at regular intervals (1 second (1 s)) to confirm whether or not the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal. This is a control command transmitted from the microcomputer 560. The data content of the connection confirmation command is “A0 (H)”, that is, “10100000”.

  The connection OK command is a control command for notifying that the connection state between the game control microcomputer 560 and the payout control microcomputer 370 is normal, and the payout control microcomputer 370 issues a connection confirmation command. Is a control command that is transmitted as a response signal in response to the reception of. The data content of the connection OK command is “8x (H)”, that is, “1000xxxx”. Here, with respect to “xxxx” in the second byte of the connection OK command, as shown in FIG. 19, a winning ball error (a winning ball paying operation based on winning or a ball lending paying operation based on a ball lending request cannot be normally performed. When an abnormal state that has entered a state occurs, “1” is set to “x” of the first bit (bit 0). When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout amount error error occurs when the cumulative value of the number of award balls and rental balls is over a predetermined value (for example, 2000), the fourth bit (bit 3) “ “1” is set to “x”.

  In this manner, during the connection confirmation between the game control microcomputer 560 and the payout control microcomputer 370, the occurrence of a predetermined error in the payout control microcomputer 370 is detected. Can be notified. In the example shown in FIG. 19, the connection OK command is set to a value indicating a payout error (prize ball error, full tank error, out of ball error, payout number error error) as a control state. A control state other than an error may be set in the connection OK command. For example, the payout control microcomputer 370 sets a value indicating that a prize ball payout operation or a lending ball payout operation is in a control state to the connection OK command, and transmits it to the game control microcomputer 560. You may make it do.

  The award ball number command is a control command for notifying the number (0 to 15) of game balls for which a payout request is made, and is a control command transmitted by the game control microcomputer 560 based on the occurrence of a win. . The content of the prize ball number command data is “5x (H)”, that is, “0101xxx”. In this embodiment, three game balls are paid out when a game ball is detected by the start port switch 14a, and 10 game balls are paid out when a game ball is detected by any of the game port switches 29a and 30a. When a game ball is detected by the count switch 23, 15 prize balls are paid out. Therefore, when a game ball is detected by the start port switch 14a, a prize ball number command “01010011” for notifying the number of prize balls of 3 is transmitted, and the game ball is detected by one of the winning port switches 29a and 30a. If a prize ball number command “01011010” for notifying 10 prize balls is transmitted and a game ball is detected by the count switch 23, the number of prize balls for notifying 15 prize balls is sent. The command “0101111” is transmitted.

  The prize ball number acceptance command is a control command for notifying that the prize ball number specified by the prize ball quantity command has been accepted, and the payout control microcomputer 370 responds upon receipt of the prize ball quantity command. It is a control command transmitted as a signal. The content of the winning ball number acceptance command data is “70 (H)”, that is, “01110000”.

  The award ball end command is a control command indicating that the award ball operation (award ball payout operation) has ended, and is a control command that the payout control microcomputer 370 transmits based on the end of the award ball operation. The data content of the winning ball end command is “50 (H)”, that is, “01010000”.

  The command for preparing a prize ball is a control command for notifying that a prize ball movement has not been completed due to a long time for a prize ball movement, a rental ball movement or a predetermined error. is there. The content of the data of the winning ball preparation command is “4x (H)”, that is, “0100xxxx”. Here, with respect to “xxxx” of the second byte of the command for preparing a prize ball, as shown in FIG. 19, when a prize ball error occurs, “1” is set to “1” in the first bit (bit 0). Is set. When a full tank error occurs, “1” is set to “x” of the second bit (bit 1). When a ball break error occurs, “1” is set to “x” of the third bit (bit 2). In addition, when a payout amount error error occurs when the cumulative value of the number of award balls and rental balls is over a predetermined value (for example, 2000), the fourth bit (bit 3) “ “1” is set to “x”. In this way, the payout control microcomputer 370 receives a prize ball when the prize ball operation takes a long time, or during a lending ball operation or when a predetermined error occurs during the execution of the prize ball operation. The game control microcomputer 560 can be notified that the operation has not ended, and the contents of the error can also be notified to the game control microcomputer 560.

  In this embodiment, the connection confirmation signal is realized by a connection confirmation command of the payout control commands, the response signal is realized by a connection OK command, the payout number signal is realized by a prize ball number command, and the acceptance signal is It is realized by a prize ball number reception command, a payout end signal is realized by a prize ball end command, and a payout in progress signal is realized by a prize ball preparation command.

  FIG. 20 is an explanatory diagram for explaining an example of fraud. FIG. 20A shows a proximity switch that is an example of a detection unit that can detect a game ball. 20A shows an example in which a proximity switch is used as the count switch 23. FIG. One terminal of the count switch 23 is supplied with + 12V power supply voltage from the power supply substrate 910. A detection signal that is the voltage level of the other terminal of the count switch 23 is input to the main board 31. In the main board 31, the detection signal is input from the input driver circuit to the input port of the game control microcomputer. Further, a resistor R and a capacitor C, one end of which is grounded, are connected to the output side of the count switch 23.

  When a metal game ball passes through a hole provided in the count switch 23 that is a proximity switch, a counter electromotive force is generated in the coil L, and the equivalent resistance value of the coil L becomes extremely large. Therefore, the output of the count switch 23 becomes a low level close to 0V. That is, the detection signal is at a low level. When the metal game ball does not pass through the hole provided in the count switch 23, the output of the count switch 23 is a value obtained by dividing + 12V by the resistance value of the coil L and the resistance R, and the high A threshold level that is considered to be a level is exceeded. That is, the detection signal is at a high level. The level of the detection signal is logically inverted by the input driver circuit 58.

  When the detection signal from the input driver circuit 58 is at a high level, the game control microcomputer can determine that the game ball has passed through the switch.

  In this embodiment, in addition to the count switch 23, proximity switches are used as the winning port switches 29a and 30a and the starting port switch 14a.

  FIG. 20B is an explanatory diagram illustrating a specific example of fraud. In the example shown in FIG. 20B, a hole provided in the count switch 23 is closed with a metal sphere (for example, a sphere having a diameter larger than that of a normal game ball is used). Radio waves are emitted from the transmitter 50 toward the sphere.

  When the hole provided in the count switch 23 is closed with a metal sphere, the count switch 23 outputs a detection signal. Specifically, as shown in the upper part of FIG. 20C, the count switch 23 sets the detection signal to a low level.

  In this state, when a radio wave is emitted toward the sphere so as to turn on and off the detection signal of the count switch 23, as shown in the lower part of FIG. 20C, the detection input to the game control microcomputer 560 The signal repeats on and off. Then, the game control microcomputer 560 considers that the detection signal has been turned on many times, erroneously determines that the game ball has been won many times, and eventually the game ball is paid out as a large number of prizes.

  In this embodiment, as will be described later, when the detection signal is in a state as shown in the lower part of FIG. 20C, it is determined that there is a possibility of fraud, and a predetermined notification is made. Done. As will be described later, the game control microcomputer 560 checks the detection signal of the switch every 4 ms, and the detection signal level is L level (low level) and the detection is confirmed immediately before (4 ms before). When the signal level is the H level (high level), it is determined that the switch is turned on (the game ball is detected), but the radio wave transmitter 50 has a detection signal cycle as shown in the lower part of FIG. If the clock frequency for generating the radio wave of that cycle and the drive frequency of the game control microcomputer 560 are equal or have an integer multiple relationship, the game control micro There is an opportunity for the computer 560 to determine that the switch is turned on based on the detection signal in the state shown in the lower part of FIG. Even when the clock frequency of the radio wave transmitter 50 coincides with the driving frequency of the game control microcomputer 560 or coincides with an integral multiple, the period of the detection signal as shown in the lower part of FIG. Unless the (time from the falling edge of the signal to the next falling edge) is 4 ms or an integral fraction of 4 ms, the switch is turned on based on the detection signal in the state shown in the lower part of FIG. An opportunity to make a decision arises.

  FIG. 21 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 21, a command 80XX (H) is an effect control command (variation pattern command) for designating a variation pattern of a decorative symbol that is variably displayed on the effect display device 9 in response to variable display of a special symbol. (Corresponding to the variation pattern XX, respectively). “(H)” indicates a hexadecimal number. The effect control command for designating the variation pattern is also a command for designating the start of variation. Therefore, when the effect control microcomputer 100 receives the command 80XX (H), the effect display device 9 controls the effect display device 9 to start variable display of decorative symbols.

  Command 8CXX (H) is an effect control command indicating whether or not to make a big hit and the type of big hit. The effect control microcomputer 100 determines the display result of the decorative symbol in response to the reception of the command 8CXX (H), so the command 8CXX (H) is referred to as a display result designation command.

  Command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the variable display (fluctuation) of the decorative symbols is terminated and the display result (stop symbol) is derived and displayed.

  Command A001 (H) is an effect control command (also referred to as a jackpot start designation command or a fanfare designation command) for displaying the fanfare screen, that is, designating the start of a jackpot game.

  The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX.

  The command A301 (H) is an effect control command (a jackpot end designation command) for displaying the jackpot end screen, that is, designating the end of the jackpot game.

  In this embodiment, production control commands other than the production control commands shown in FIG. 21 are also used to perform production control. FIG. 21 shows main production control commands.

  The command D000 (H) is an input port state designation command that indicates the input state of the input port 0 (see FIG. 11) for detecting a game ball that passes through a predetermined passing area. As will be described later, when the state of the detection signal from the switch changes, an input port state designation command in which the input data of the input port 0 is set in the second byte is transmitted.

  Next, the switch process (step S22) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 22 is an explanatory diagram showing each 1-byte (8-bit) buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of port 0 inputted this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected.

  FIG. 23 is a flowchart illustrating a processing example of the switch processing in step S22 in the game control processing. In the switch process, the CPU 56 first inputs data input to the input port 0 (see FIG. 11) (step S101), and sets the input data in the port buffer (step S102).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S104 and S105).

  When the value of the wait counter becomes 0, the data of the input port 0 is input again (step S106), and a logical product is obtained for each bit between the input data and the data set in the port buffer (step S106). S107). Then, the logical product operation result is set in the port buffer (step S108). Of the two input data input from the input port 0 with a time interval of approximately [initial value of weight counter × (processing time of steps S104, S105)] by the processing of steps S103 to S108, both “ Only the bits that are “1” will be “1” in the port buffer. In other words, if the ON state of the switch detection signal continues for a predetermined period [initial value of wait counter × (processing time of steps S104 and S105)], the corresponding bit in the port buffer becomes “1”.

  Further, the CPU 56 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”.

  When the bit corresponding to one of the switches becomes “1” (when the state of the detection signal from the switch has changed) (step S110), the CPU 56 designates the effect control microcomputer 100 with the input port state. Control to transmit a command is performed (step S111).

  In step S111, the CPU 56 transmits an input port state designation command when the bit corresponding to the detection signals from the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a becomes “1”. When the bit corresponding to the detection signal from the gate switch 32a becomes “1”, the input port state designation command may not be transmitted. When it is configured not to transmit the input port state designation command when the bit corresponding to the detection signal from the gate switch 32a becomes “1”, the exclusive processing is performed between the processing of step S110 and step S111. When the logical product of the logical sum operation result and “1D (H)” (data that masks bit 1 of input port 0 shown in FIG. 11) becomes 0, a step that does not execute the process of step S111 is inserted. Good. In this embodiment, the production control microcomputer 100 uses the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a of the input port 0 in the abnormality determination process (see FIGS. 51, 54, and 56). Therefore, only the bit corresponding to the detection signal from the gate switch 32a is judged to be “1” or “0”, so that the abnormality judgment processing is not affected. In addition, when the input port state designation command is transmitted even when the bit corresponding to the detection signal from the gate switch 32a is “1” as in this embodiment, the abnormal state is determined by the gate switch 32a. A bit corresponding to the detection signal may also be determined, and abnormal passing of the game ball with respect to the gate 32 may be detected, and when abnormal passing is detected, abnormality notification may be performed.

  Further, in the process of step S111, the CPU 56 performs control to transmit an input port state designation command in which the port buffer data corresponding to the input data of the input port 0 is set to the second byte. That is, the CPU 56 collectively outputs the input data of the input port 0 as a command.

  When transmitting the effect control command to the effect control microcomputer 100, the CPU 56 sets the address of the command transmission table (preliminarily set for each command in the ROM 54) according to the type of the effect control command as a pointer. To do. Then, the effect control command is transmitted in the command control process (step S25). When transmitting non-fixed data such as input data of the input port 0, for example, MODE data (see FIG. 21) is set in the first byte of the command transmission table in the ROM 54, and the RAM 55 is set in the second byte. The address of the predetermined area is set. The CPU 56 sets the input data of the input port 0 in a predetermined area of the RAM 55, and then sets the address of the command transmission table corresponding to the input port state designation command as a pointer. The address of the RAM area may be stored in the command transmission table, and the data at the corresponding address may be set in the second byte.

  The CPU 56 further performs a logical product for each bit between the operation result of the exclusive OR and the data set in the port buffer (step S112). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the CPU 56 sets the operation result of the logical product in step S112 in the switch-on buffer (step S113), and sets the contents of the port buffer in which the operation result in step S108 is set in the previous port buffer (step S114). .

  Through the above processing, among the switches that have been on for a predetermined period of time, the switch that has been turned off last time (for example, 4 ms before), that is, the switch that has been turned off, that is, changed from the off state to the on state. The bit corresponding to the switched switch is “1” in the switch-on buffer.

  Next, the prize ball processing in step S26 will be described. FIG. 24 is a flowchart illustrating an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 25 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “4”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the lower address of the prize ball command output counter, and the number of prize balls are designated. Prize ball designation data is set in sequence. The prize ball command output counter is a counter that counts the number of prizes received at the prize opening. The prize ball command output counter is set for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 receives the prize ball corresponding to the number of prize balls “15”. Command output counter 1, prize ball command output counters 2 and 3 corresponding to the number of prize balls “10” (corresponding to two normal winning openings 29 and 30), and prize ball command output corresponding to the number of prize balls “3” Counter 4 is used.

  In the winning ball designation data (15), only bit 0 (bit corresponding to the count switch 23a) of the switch-on buffer in which the state of the input port 0 (see FIG. 11) is reflected is “1”. Data. One of the winning ball designation data (10) is data in which only bit 2 of the switch-on buffer (bit corresponding to the winning opening switch 29a) is “1”. The other of the winning ball designation data (10) is data in which only bit 3 of the switch-on buffer (bit corresponding to the winning opening switch 30a) is “1”. The winning ball designation data (three) is data in which only bit 4 (bit corresponding to the start port switch 14a) of the switch-on buffer is “1”.

  Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 sets data indicating the number of prize balls (15) in the lower 4 bits of the prize ball number command. The prize ball number command is transmitted to the payout control microcomputer 370. Further, the CPU 56 determines the prize ball if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counter 2 or the prize ball command output counter 3 is not 0. Data indicating the number (10) is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. Further, the CPU 56 determines that the values of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table are 0 and the value of the prize ball command output counter 4 is not 0. Data indicating the number of winning balls (3) is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370.

  FIG. 26 is a flowchart showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table to the pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded in the register and the prize ball designation data pointed to by the pointer (step S5109).

  If the calculation result in step S5109 is 0 (Y in step S5110), that is, if the detection signal of the switch to be inspected is not on, the number of processes is reduced by 1 (step S5114), and if the number of processes is 0 The process ends, and if the number of processes is not 0, the process returns to step S5103 (step S5115).

  If the calculation result in step S5109 is not 0 (N in step S5110), that is, if the detection signal of the switch to be inspected is on, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer. (Step S111). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5112, S5113). Then, the process proceeds to step S5113.

  FIG. 27 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  FIG. 28 is a flowchart showing the prize ball transmission process 1 (step S521) executed when the value of the prize ball process code is zero. In the prize ball transmission process 1, the CPU 56 performs control to transmit a connection confirmation command to the payout control microcomputer (step S5211). Specifically, the CPU 56 performs processing for outputting a connection confirmation command to the transmission data register of the serial communication circuit 505. Then, the CPU 56 sets a value “1” indicating a prize ball connection confirmation process in the prize ball process code (step S5212), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S5213). .

  If a connection OK command is not received even after 10 seconds have elapsed after transmitting the connection confirmation command based on the connection confirmation time 2 set in step S5213, the connection confirmation command is transmitted thereafter. It is controlled so as to extend the interval to 10 seconds. Specifically, the prize ball process timer set in step S5213 is measured in the process of step S5229, which will be described later, 10 seconds elapses without receiving a connection OK command, and the determination is Y in step S5227. Then, it returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S5228 and S5211).

  The prize ball process timer is set to a value (for example, an integer multiple of the interrupt period) in consideration of the interrupt period in the timer interrupt process executed by the game control microcomputer 560. This is because other timers used in the game control microcomputer 560, the payout control microcomputer 370, and the effect control microcomputer 100 (for example, a main control communication control timer, a payout control timer, a re-payout waiting timer, The same applies to the prize ball information output timer and prize ball signal output timer.

  FIG. 29 is a flowchart showing a prize ball connection confirmation process (step S522) executed when the value of the prize ball process code is 1. In the winning ball connection confirmation process, the CPU 56 first confirms whether there is data in the reception data register of the serial communication circuit 505 (step S5221). For example, the CPU 56 checks the value of bit 5 (RDRF) of the status register of the serial communication circuit 505. If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S5227.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether an error has occurred in the serial communication circuit 505 (step S5222). For example, the CPU 56 confirms whether or not the error bit value of any one of bits 0 to 4 of the status register of the serial communication circuit 505 is set. If an error has occurred, the CPU 56 reads data from the reception data register of the serial communication circuit 505 (step S5222A), and proceeds to step S5227. Note that reading the data in step S5222A clears the contents of the received data register of the serial communication circuit 505 and clears bit 5 of the status register. However, the received data read in step S5222A is discarded as it is. In other words, in this embodiment, the reception data read in step S5222A is read from the reception data register of the serial communication circuit 505 by the CPU 56 and written to the register of the CPU 56, and is not written to the RAM 55. It is not used for any subsequent processing. This also applies to other processes for discarding data by reading received data from the received data register in this embodiment.

  After reading the received data in step S5222A, the CPU 56 determines N in step S5221 until the next command is received, and when 10 seconds set in step S5213 have elapsed without receiving the command, the award is received in step S5227. The ball process timer times out. Then, the process proceeds to the prize ball transmission process 1 (see step S5228), and the connection confirmation command is transmitted again (see step S5211).

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a connection OK command (step S5223). If it is not a connection OK command, the process proceeds to step S5227.

  If the connection OK command has been received, the CPU 56 stores the error information (see FIG. 19) set in the lower 4 bits of the connection OK command in the frame state display buffer (step S5224).

  Next, the CPU 56 sets a value “2” indicating the prize ball transmission process 2 in the prize ball process code (step S5225), and sets a connection confirmation time 1 (for example, 1 second) in the prize ball process timer (step S5226). . Note that, based on the connection confirmation time 1 set in step S5226, control is performed to repeatedly transmit the next connection confirmation command every time one second elapses after reception of the connection OK command. Specifically, the prize ball process timer set in step S5226 is measured in the process of step S52315 described later, and a timeout occurs after 1 second has passed without sending a prize ball number command, and it is determined as Y in step S52313. Then, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Therefore, an interval period is provided between the end of the execution of the payout control by the payout control microcomputer 370 and the output of a new connection confirmation signal. The payout control microcomputer 370 executes the payout control. It is possible to prevent the processing at the end of the process from being concentrated and a new connection confirmation signal from being lost.

  In step S5227, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if the connection OK command has not been received even after 10 seconds have passed after sending the connection confirmation command), the CPU 56 sends a winning ball to the winning ball process code. A value “0” indicating the process 1 is set (step S5228), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S5229).

  FIG. 30 is a flowchart showing the prize ball transmission process 2 (step S523) executed when the value of the prize ball process code is 2. In the prize ball transmission process 2, the CPU 56 checks whether or not any prize ball command output counters 1 to 4 have a count value other than 0 (step S52301). If there is no count value other than 0, the process proceeds to step S52313.

  If any of the prize ball command output counters 1 to 4 has a count value other than 0 (that is, if the count value is 1 or more), the CPU 56 loads the contents of the frame state display buffer. Then, it is confirmed whether or not the content of the frame state display buffer is 0 (step S5232). If the content of the frame state display buffer is not 0, the processing is terminated as it is. By performing such control, when the connection OK command in which the error information is set is received and the payout control microcomputer 370 is controlled to be in the payout stop state, the process does not proceed to step S52303 and subsequent steps. Then, control is made so that transmission of the prize ball number command is suspended.

  If the content of the frame state display buffer is 0 (that is, if no error relating to payout has occurred), the payout control CPU 371 determines the number of prize balls corresponding to the prize ball command output counter whose count value is not 0. It is set in the buffer (step S52303). Specifically, in step S52301, the CPU 56 first checks whether or not the count value of the prize ball command output counter 1 is zero. If the count value of the prize ball command output counter 1 is 1 or more, in step S52303, the CPU 56 sets 15 prize balls in the number buffer. In step S52301, if the count value of the prize ball command output counter 1 is 0, the CPU 56 checks whether the count values of the prize ball command output counters 2 and 3 are 0 or not. If the count value of the prize ball command output counters 2 and 3 is 1 or more, the CPU 56 sets the number of prize balls in the number buffer in step S52303. In step S52301, if the count value of the prize ball command output counters 2 and 3 is also 0, the CPU 56 checks whether the count value of the prize ball command output counter 4 is 0 or not. If the count value of the prize ball command output counter 4 is 1 or more, in step S52303, the CPU 56 sets the number of prize balls to 3 in the number buffer.

  In addition, the CPU 56 sets the number of prize balls corresponding to the prize ball command output counter whose count value is not 0 in the prize ball number command (step S52304), and uses the prize ball number command in which the number of prize balls is set for payout control. Control to transmit to the microcomputer 370 is performed (step S52305). Specifically, the CPU 56 performs processing for outputting a prize ball number command in which the number of prize balls is set to the transmission data register of the serial communication circuit 505.

  By executing the processing of steps S52301 and S52305, in this embodiment, if there is a prize ball command output counter whose count value is not 0 regardless of the connection confirmation command transmission timing (ie, If there is a prize ball number storage and a predetermined payout condition is established), a prize ball number command is transmitted to the payout control microcomputer 370.

  Then, the CPU 56 sets a value “3” indicating the prize ball reception confirmation process in the prize ball process code (step S52306), and sets a connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52307). . It should be noted that, based on the connection confirmation time 2 set in step S52307, after transmitting the prize ball number command, it is confirmed whether a prize ball number acceptance command or a prize ball preparation command is received within 10 seconds. . Specifically, the prize ball process timer set in step S52307 is measured in the process of step S52411 to be described later, and 10 seconds elapses without receiving a prize ball number acceptance command or a prize ball preparation command. If it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  If the prize ball number command is transmitted in step S52305 by executing the process of step S52306, the process proceeds to the prize ball reception confirmation process without returning to the prize ball transmission process 1 including the connection confirmation command transmission process. Is done. Therefore, in this embodiment, the process of repeatedly transmitting the connection confirmation command is executed every predetermined time (for example, 1 second) until the prize ball number command is transmitted, but the prize ball number command is transmitted. In particular, the control for transmitting the connection confirmation command is stopped (more specifically, after the prize ball number command is transmitted, the process proceeds to the prize ball end confirmation process by receiving the prize ball number acceptance command described later. (See steps S52403 to S52405) or by receiving the winning ball preparation command and repeating the winning ball receipt confirmation process (see steps S52406 to S52408), without returning to the winning ball transmission process 1 In this case, the control for sending the confirmation command is stopped. Unless an abnormal state occurs in which no payout control command is returned, after the prize ball number command is transmitted, the game control microcomputer 560 is connected until the prize ball payout operation is finished and the prize ball end command is received. A confirmation command is never sent.

  Next, the CPU 56 adds the value of the number buffer set in step S52303 to the prize ball number counter (step S52308), and whether or not the added count value is equal to or greater than a predetermined prize ball shortage determination value (eg, 501). Is confirmed (step S52309). In this embodiment, the prize ball number counter is a counter used for grasping the number of prize balls that have not been paid out on the game control microcomputer 560 side, and when the prize ball number command is transmitted, The number of prize balls designated in (1) is added, and every time ten prize balls are paid out, 10 is subtracted based on the prize ball information output from the payout control microcomputer 370. Further, as described above, the prize ball number counter is set to “250” as an initial value in the initial setting process of the main process. When the count value of the prize ball counter reaches a predetermined prize ball shortage determination value (for example, 501) or more, the number of prize balls that have not been paid out is excessively large. Can be determined. Further, when the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), an abnormally large number of game balls are paid out exceeding the number to be paid out originally. Therefore, it can be determined that an excessive number of prize balls has occurred.

  Unauthorized acts caused by obstructing communication between the game control microcomputer 560 and the payout control microcomputer 370 (for example, the game control microcomputer 560 may not receive data transmitted from the payout control microcomputer 370) In this way, it is possible to effectively prevent the game control microcomputer 560 from being in a state of waiting for receiving a winning ball number reception command and causing the winning ball number command to be retransmitted).

  In this embodiment, the prize ball number counter is added (see step S52308) immediately after the prize ball number command is transmitted (see step S52305). However, the prize ball number command is transmitted. For example, a prize ball number command may be transmitted immediately after the addition process of the prize ball number counter is executed.

  When it is determined that there is a shortage of prize balls, the signal line for outputting the prize ball information is disconnected in addition to the case where some trouble occurs on the payout control microcomputer 370 side and the payout operation cannot be performed normally. Cases are also conceivable. On the other hand, when it is determined that the number of prize balls is excessive, a prize ball number command is transmitted in addition to the case where some kind of trouble occurs on the payout control microcomputer 370 side and the payout operation is performed more than necessary. It is also conceivable that some injustice is applied to the command line and the award ball number command is illegally input to the payout control microcomputer 370.

  When the count value of the prize ball number counter is equal to or greater than a predetermined prize ball shortage determination value (for example, 501), the CPU 56 displays a prize ball error flag indicating that a prize ball shortage or a prize ball excess has occurred. It is confirmed whether it has already been set (step S52310). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S52311) and controls to send a prize ball shortage error command to the effect control microcomputer 100 (step S52312). Specifically, the CPU 56 performs a process of setting the address of the winning ball shortage error command transmission table as a pointer. Then, based on the fact that the address of the winning ball shortage error command transmission table is set in the pointer in step S52312, in the command control processing in step S24, the serial communication circuit 505 of the channel for transmission / reception with the effect control board 80 is performed. A prize ball shortage error command is output to the transmission data register, and the prize ball shortage error command is transmitted to the production control microcomputer 100. Note that once the prize ball error flag is set, it is maintained without being cleared until the power supply to the gaming machine is turned on again after the power supply to the gaming machine is stopped. In this embodiment, regarding the communication between the game control microcomputer 560 and the effect control microcomputer 100, a command is transmitted from the game control microcomputer 560 to the effect control microcomputer 100. Only, not the other way around. Therefore, the game control microcomputer 560 may be equipped with a transmission-only serial communication circuit for communication with the effect control microcomputer 100.

  In this embodiment, based on the reception of a prize ball shortage error command or a prize ball excess error command, the effect control microcomputer 100 issues a prize ball shortage or prize ball excess error notification. However, error notification of insufficient prize balls or excessive prize balls may be recovered when a predetermined period has elapsed since the start of notification. Further, for example, when the value of the prize ball number counter returns to a range of a predetermined prize ball shortage determination value (for example, 501) or a predetermined prize ball excess determination value (for example, 0), the prize ball shortage or the prize ball is excessive. It is also possible to recover from the error notification.

  In this embodiment, the case where the prize ball number is added to the prize ball number counter at the timing at which the prize ball number command is transmitted in step S52308 is shown. For example, the number of prize balls may be subtracted instead of the one shown in the embodiment. In this case, for example, in the process of step S5311 to be described later, on the contrary, 10 may be added to the value of the winning ball counter based on the input of winning ball information. In the process of step S52309, if the value of the prize ball number counter is less than 0, it is determined that there is a prize ball shortage error. What is necessary is just to determine with an excess error.

  In step S52313, the CPU 56 checks whether or not the prize ball process timer has timed out. If the winning ball process timer has timed out (that is, if no winning ball has been stored and no new winning has occurred by the time one second has elapsed after receiving the connection OK command), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52314), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52315).

  FIG. 31 is a flowchart showing the winning ball reception confirmation process (step S524) executed when the value of the winning ball process code is 3. In the winning ball receipt confirmation process, the CPU 56 first checks whether or not there is data in the reception data register of the serial communication circuit 505 (step S52401). Specifically, the CPU 56 may confirm the value of bit 5 of the status register of the serial communication circuit 505. If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52409.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52402). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register of the serial communication circuit 505 is set. If an error has occurred, the CPU 56 reads data from the reception data register of the serial communication circuit 505 (step S52402A), and proceeds to step S52409. Note that reading the data in step S52402A clears the contents of the received data register of the serial communication circuit 505 and clears bit 5 of the status register. However, the received data read in step S52402A is discarded as it is. That is, in this embodiment, the received data read in step S52402A is read from the received data register of the serial communication circuit 505 by the CPU 56 and written to the register of the CPU 56, but not written to the RAM 55. It is not used for any subsequent processing.

  After reading the received data in step S52402A, the CPU 56 determines N in step S52401 until the next command is received, and when 10 seconds set in step S52307 have elapsed without receiving the command, the award is received in step S52409. The ball process timer times out. Then, the process proceeds to prize ball transmission processing 1 (see step S52410), and the connection confirmation command is transmitted again (see step S5211).

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether or not the received command is a prize ball number acceptance command (step S52403). . If the winning ball number reception command has been received, the CPU 56 subtracts 1 from the value of the winning ball command output counter corresponding to the winning ball number set by the transmitted winning ball number command (step S52404). In addition, the CPU 56 sets a value “4” indicating a prize ball end confirmation process in the prize ball process code (step S52405), and proceeds to step S52408.

  If the received command is not a prize ball number acceptance command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52406). If it is not a prize ball preparation command, the process advances to step S52409.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 25) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52407). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52408). In addition, after receiving the prize ball preparation command based on the connection confirmation time 2 set in step S52408, neither the prize ball number acceptance command nor the next prize ball preparation command can be received after 10 seconds. If it is, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52408 is measured in the processing of steps S52409 and S52411 described later, and 10 seconds are received without receiving a prize ball number acceptance command or a next prize ball preparation command. When the time-out occurs and it is determined as Y in step S52409, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52410 and S5211).

  In step S52409, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, if no prize ball number acceptance command or prize ball preparation command is received after 10 seconds have passed since the prize ball number command was transmitted), the CPU 56 Then, the value “0” indicating the prize ball transmission process 1 is set in the prize ball process code (step S52410), and the process ends. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52411).

  FIG. 32 is a flowchart showing the winning ball end confirmation process (step S525) executed when the value of the winning ball process code is 4. In the winning ball end confirmation process, the CPU 56 first confirms whether or not there is data in the reception data register of the serial communication circuit 505 (step S52501). Specifically, the CPU 56 may confirm the value of bit 5 of the status register of the serial communication circuit 505. If there is no data in the reception data register (that is, if no command is received), the process proceeds to step S52509.

  If there is data in the reception data register (that is, if a command is received), the CPU 56 checks whether or not an error has occurred in the serial communication circuit 505 (step S52502). Specifically, the CPU 56 may confirm whether or not any error bit value of bits 0 to 4 of the status register of the serial communication circuit 505 is set. If an error has occurred, the CPU 56 reads data from the reception data register of the serial communication circuit 505 (step S52502A), and proceeds to step S52509. Note that reading the data in step S52502A clears the contents of the reception data register of the serial communication circuit 505 and clears bit 5 of the status register. However, the received data read in step S52502A is discarded as it is. That is, in this embodiment, the received data read in step S52502A is read from the received data register of the serial communication circuit 505 by the CPU 56 and written to the register of the CPU 56, but not written to the RAM 55. It is not used for any subsequent processing.

  After reading the received data in step S52502A, the CPU 56 determines N in step S52501 until the next command is received, and when 10 seconds set in step S52408 have elapsed without receiving the command, the award is received in step S52509. The ball process timer times out. Then, the process shifts to prize ball transmission processing 1 (see step S52510), and the connection confirmation command is transmitted again (see step S5211).

  The game control microcomputer 560 discards the received data when a communication error occurs, but transmits a connection confirmation command every 10 seconds regardless of the presence or absence of the communication error. It is possible to prevent inconvenience due to communication stagnating more than necessary while preventing processing from being executed based on erroneous data when an abnormality occurs in communication during the period. Further, the game control microcomputer 560 can recognize the control state of the payout control microcomputer 370 without complicating the control.

  If no error has occurred in the serial communication circuit 505, the CPU 56 reads the command from the reception data register of the serial communication circuit 505, and checks whether the received command is a prize ball end command (step S52503). If the winning ball end command has been received, the CPU 56 sets a value “2” indicating the winning ball transmission process 2 in the winning ball process code (step S52504), and the connection check time 1 (for example, 1) is set in the winning ball process timer. Second) is set (step S52505). It should be noted that, based on the connection confirmation time 1 set in step S52505, the control for transmitting the connection confirmation command when the start winning prize does not occur even after one second has elapsed after receiving the prize ball end command. Return to. Specifically, the prize ball process timer set in step S52505 is measured by the processing in steps S52313 and S52315, and one second has elapsed without sending a prize ball number command without generating a new start prize. If the time-out occurs and it is determined as Y in step S52313, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52314 and S5211).

  Since the process of step S52504 is executed, when a prize ball end command is received, the process first proceeds to prize ball transmission process 2. Therefore, when the number of prize balls is stored, the next is immediately performed. Control is performed so that a winning ball number command is transmitted. On the other hand, after the transition to the prize ball transmission process 2, there is no memorized number of prize balls, and a new prize is also generated until the connection confirmation time 1 (for example, 1 second) set in step S52505 has elapsed. If not, the process further proceeds to a prize ball transmission process 1, and the process of repeatedly transmitting the connection confirmation command is resumed.

  If the received command is not a prize ball end command, the CPU 56 checks whether or not the received command is a prize ball preparation command (step S52506). If it is not a prize ball preparation command, the process advances to step S52509.

  If the winning ball preparation command has been received, the CPU 56 stores the error information (see FIG. 19) set in the lower 4 bits of the winning ball preparation command in the frame state display buffer (step S52507). Then, the CPU 56 sets the connection confirmation time 2 (for example, 10 seconds) in the prize ball process timer (step S52508). In addition, after receiving the winning ball preparation command based on the connection confirmation time 2 set in step S52508, neither the winning ball end command nor the next winning ball preparation command could be received after 10 seconds. In this case, the process returns to the control for transmitting the connection confirmation command. Specifically, the prize ball process timer set in step S52508 is measured in the process of step S52511 described later, and 10 seconds have elapsed without receiving a prize ball end command or a next prize ball preparation command. If time-out occurs and it is determined as Y in step S52509, the process returns to the prize ball transmission process 1 and the next connection confirmation command is transmitted (see steps S52510 and S5211).

  In step S52509, the CPU 56 checks whether or not the prize ball process timer has timed out. If the prize ball process timer has timed out (that is, the prize ball end command or the prize ball preparation command cannot be received even after 10 seconds have passed since the prize ball number acceptance command or prize ball preparation command is received) In this case, the CPU 56 sets a value “0” indicating the prize ball transmission process 1 in the prize ball process code (step S52510), and ends the process. If the winning ball process timer has not timed out, the CPU 56 subtracts 1 from the value of the winning ball process timer (step S52511).

  FIG. 33 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the input of the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on-counter by 1 to the number of processes (8 in this embodiment). ) Is repeatedly executed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the winning ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the winning ball information input invalid timer (step S5310) and sets the value of the winning ball number counter to 10 Subtraction is performed (step S5311).

  As described above, in this embodiment, it is determined that the prize ball information is inputted on the condition that the prize ball information is confirmed 6 times or more during the eight confirmation processes, and 10 prize balls are paid out. As a result, 10 is subtracted from the value of the prize ball number counter. By such processing, in this embodiment, the possibility that it is determined that the prize ball information is erroneously input is reduced, and the number of unpaid prize balls cannot be properly grasped on the game control microcomputer 560 side. To prevent.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets the prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the winning ball excess error command transmission table is set in the pointer in step S5315, in the command control processing in step S25, the serial communication circuit 505 of the channel for transmission / reception with the effect control board 80 is performed. A prize ball excess error command is output to the transmission data register, and the prize ball excess error command is transmitted to the production control microcomputer 100.

  Next, the operation of the payout control means (the payout control microcomputer 370) will be described. FIG. 34 is an explanatory diagram showing an example of output port assignment in the payout control means. As shown in FIG. 34, the output port 0 is an output port for outputting a signal of each phase supplied to the payout motor 289 by the stepping motor, and an EXS signal and a PRDY signal to the card unit 50. The output port 1 has a gaming machine error state signal indicating that the gaming machine is in an error state (in this embodiment, a ball running out error state or a full tank error state), and a prize ball signal indicating that a prize ball payout has been detected. Is an output port. The output port 2 is an output port for outputting each segment of the error display LED 374 using a 7-segment LED.

  The output port 2 also outputs prize ball information indicating that ten prize ball payouts have been detected. The prize ball information is output to the main board 31.

  FIG. 35 is an explanatory diagram showing an example of bit assignment of input ports in the payout control means. As shown in FIG. 35, the VL signal, the BRDY signal, and the BRQ signal from the card unit 50 are input to bits 0 to 2 of the input port 0, respectively. A connection signal from the main board 31 is input to bit 4 of the input port 0. In addition, the detection signal of the full switch 48, the detection signal of the ball break switch 187, and the detection signal of the payout motor position sensor 295 are input to bits 5 to 7 of the input port 0, respectively. In addition, the operation signal from the error release switch 375 and the detection signal of the payout number count switch 301 are input to the bits 0 and 1 of the input port 1, respectively.

  Next, the operation of the payout control means will be described. FIG. 36 is a flowchart showing main processing executed by the payout control means. In the main process, the payout control CPU 371 of the payout control microcomputer 370 first performs necessary initial settings. That is, the payout control CPU 371 first sets the interruption prohibition (step S701). Next, the interrupt mode is set to interrupt mode 2 (step S702), and a stack pointer designation address is set to the stack pointer (step S703).

  Next, the payout control CPU 371 sets a built-in device register (step S704). In the process of setting the internal device register in step S704, the payout control CPU 371 sets the CTC. In this embodiment, one channel of the built-in CTC is used in the timer mode. Therefore, the payout control CPU 371 performs register setting for setting the channel to be used to timer mode, register setting for permitting interrupt generation, and register setting for setting an interrupt vector. The interrupt by the channel is used as a timer interrupt. For example, when it is desired to generate a timer interrupt every 1 ms, a value corresponding to 1 ms is set as an initial value in a predetermined register (time constant register).

  In step S704, the payout control CPU 371 initializes the priority of interrupt processing to be executed in response to the interrupt request from the serial communication circuit 380. In this case, in this case, the payout control CPU 371 initializes the priority order of the interrupt process according to the same process as the priority order initial setting process (see step S15b) performed by the CPU 56 of the game control microcomputer 560.

  In step S <b> 704, the payout control CPU 371 sets the serial communication circuit 380. In this case, the payout control CPU 371 sets the baud rate of the receiving circuit, sets the receiving mode (either 8-bit or 9-bit data format), and sets the parity (the presence or absence of parity, even parity or odd parity). Set). In addition, the control registers of the receiving circuit are initialized and the status registers are initialized. Also, the payout control CPU 371 sets the baud rate of the transmission circuit, sets the transmission mode (either 8-bit or 9-bit data format), and sets the parity (the presence / absence of parity, even parity or odd parity) )I do. Also, each control register of the transmission circuit is initialized.

  The interrupt vector set for the channel set to the timer mode (channel 3 in this embodiment) corresponds to the start address of the timer interrupt process. Specifically, the start address of the timer interrupt process is specified by the value set in the I register and the interrupt vector. In the timer interruption process, a payout control process for controlling the payout means (including at least a process of driving the ball payout device 97 in response to a command signal related to award ball payout from the main board, and a ball payout device 97 in response to a ball lending request. A process for driving the program may be included.

  In this embodiment, the interruption mode 2 is also set in the payout control microcomputer 370. Therefore, an interrupt process based on counting up the built-in CTC can be used. Also, an interrupt processing start address can be set according to the interrupt vector sent by the CTC. The interrupt based on CTC channel 3 (CH3) count-up is an interrupt that occurs when the CPU internal clock (system clock) counts down and the register value becomes “0”, and is used as a timer interrupt. .

  Next, the payout control CPU 371 sets the RAM in an accessible state (step S705), and performs a RAM clear process (step S706). In addition, initial values are set in the flags and counters of the RAM area (step S707). Note that the processing in step S707 includes processing for setting the unpaid-off number counter initial value in the unpaid-out number counter. In the process of step S707, the payout control CPU 371 also performs a process of clearing an error flag indicating a detection state of a payout number abnormality error, a full tank error, and a ball breakage error. In this embodiment, when it is determined that there is a payout number error and the payout number error error specification bit is set in the error flag, the payout number error error specification bit is not cleared until the power is reset. Although it does not recover from the number abnormality error, specifically, when the process of step S707 is executed when the power is turned on, the payout number abnormality error designation bit in the error flag is cleared and the payout number abnormality error is recovered.

  The payout control CPU 371 executes serial communication circuit setting processing for initial setting of the serial communication circuit 380 (step S708). In this case, the payout control CPU 371 causes the serial communication circuit 380 to serially communicate with the game control microcomputer 560 according to the same process as the serial communication circuit setting process (see step S15a) performed by the CPU 56 of the game control microcomputer 560. Make settings for Further, as described above, a part of the initial setting of the serial communication circuit 380 is executed in the built-in device register setting process in step S704. Note that all the setting processing of the serial communication circuit 380 may be performed by the serial communication circuit setting processing in step S708.

  Since interruption is prohibited in step S701 of the initial setting process, interruption is permitted before the initialization process is completed (step S709). Thereafter, a loop process for monitoring the occurrence of a timer interrupt is entered.

  As described above, in this embodiment, the built-in CTC of the payout control microcomputer 370 is set so as to repeatedly generate a timer interrupt. When a timer interrupt occurs, the payout control CPU 371 of the payout control microcomputer 370 executes a timer interrupt process.

  FIG. 37 is a flowchart showing an example of timer interrupt processing executed by the payout control means. In the timer interruption process, the payout control CPU 371 of the payout control microcomputer 370 executes the following process. First, the payout control CPU 371 performs a switch check process (step S761). In the switch check process, the payout control CPU 371 performs a process of confirming the on / off state of the payout number count switch 301 and the error release switch 375 based on the input of the input port 1. Next, the payout control CPU 371 performs input determination processing (step S762). The input determination process is a process of detecting the state of bits 0 to 7 (see FIG. 35) of the input port 0 and reflecting the detection result in a predetermined 1 byte (referred to as a sensor input state flag) in the RAM. The payout control CPU 371 checks the state of the sensor input state flag instead of directly checking the state of the input port when performing control based on the state of bits 0 to 7 of the input port 0.

  Next, the payout control CPU 371 executes a prepaid card unit control process for communicating with the card unit 50 (step S763). Next, the payout control CPU 371 executes main control communication processing for communicating with the game control means of the main board 31 (step S764). Next, the payout control CPU 371 performs control for paying out the lent balls in response to a ball lending request from the card unit 50, and performs control for paying out the number of prize balls indicated by the prize ball number command from the main board 31. The payout control process to be executed is executed (step S765).

  Next, the payout control CPU 371 executes a payout motor control process (step S766). In the payout motor control process, when the payout motor 289 is to be driven, a process for outputting the patterns of the payout motors φ1 to φ4 to the output port 0 is performed.

  Next, the payout control CPU 371 executes error processing for detecting various errors (step S767). Next, the payout control CPU 371 executes prepaid card unit error control processing for performing error control of the card unit 50 (step S768). Next, the payout control CPU 371 performs information output processing for outputting prize ball information to the main board 31 and outputting a prize ball signal and a gaming machine error status signal indicating that a prize ball payout has been detected. This is executed (step S769). Further, display control processing for performing predetermined display on the error display LED 374 according to the result of the error processing is executed (step S770).

  In this embodiment, when various errors (for example, a payout number abnormality error, a full tank error, a ball shortage error, or a prepaid card unit unconnected error) are detected in error processing, an error bit corresponding to the detected error is displayed. Set. Then, in the display control process of step S770, the payout control CPU 371 performs a predetermined display on the error display LED 374 based on the error bit being set.

  In this embodiment, a RAM area (output port 0 buffer, output port 1 buffer) corresponding to the output state of the output port is provided. However, the payout control CPU 371 includes an output port 0 buffer and an output port. The contents of the port 1 buffer are output to the output port (step S771: output processing). The output port 0 buffer and the output port 1 buffer are prepaid card control processing (step S763), main control communication processing (step S764), payout motor control processing (step S766), information output processing (step S769), and display control processing ( It is updated in step S770).

  FIG. 38 is a flowchart showing the main control communication process in step S764. In the main control communication process, the payout control microcomputer 370 (specifically, the payout control CPU 371) executes a main control command reception process (step S740). Then, the payout control CPU 371 executes one of steps S741 to S744 according to the value of the main control communication control code.

  FIG. 39 is a flowchart showing the main control command reception process of step S740 in the main control communication process. In the main control command receiving process, the payout control CPU 371 first checks whether or not a connection signal is input (step S74001). If no connection signal is input, the payout control CPU 101a initializes the transmission circuit and the reception circuit of the serial communication circuit 380 (step S74002). As described above, when the connection signal cannot be received, the transmission circuit and the reception circuit of the serial communication circuit 380 are initialized, so that the command is transmitted even though the connection state with the main board 31 is under an abnormal state. It is possible to prevent a situation in which data is stored in the register or the reception data register. Next, the payout control CPU 371 loads the value of the main control communication control code (step S74003), and checks whether or not the value of the main control communication control code is a value “0” indicating the main control connection confirmation process. (Step S74004).

  In this embodiment, in the main control communication process, input of a connection signal from the game control microcomputer 560 is started after power supply to the gaming machine is started, and reception of the first connection confirmation command can be confirmed. The main control connection confirmation process in step S741 is executed. Then, when the reception of the connection confirmation command can be confirmed, the process proceeds to step S742 and subsequent steps, and transmission / reception processing of various payout control commands is executed. Thereafter, if the communication state with the game control microcomputer 560 is maintained normally, one of the processes of steps S742 to S744 is executed, and the main control connection confirmation process of step S741 is basically a game. It will be executed only when the machine is powered on. In step S74004, the fact that the value of the main control communication control code indicates a value other than the main control connection confirmation processing means that after shifting to the processing after step S742, some communication error occurs and the connection signal cannot be input. This is the case. Therefore, if the value of the main control communication control code indicates a value other than the main control connection confirmation process in step S74004, the payout control CPU 371 determines the main control communication error designation bit (game control microcomputer) of the error flag. A bit indicating that an abnormality has occurred in the communication state with 560) is set (step S74005). The error flag is a flag in which various prize ball errors are set, and is formed in a RAM provided in the payout control microcomputer 370. The payout control CPU 371 sets a value “0” indicating main control connection confirmation processing in the main control communication control code (step S74006). If the value of the main control communication control code is “0” indicating the main control connection confirmation process in step S74004, the process proceeds to step S74006.

  Note that the main control confirmation process in step S741 may be executed exceptionally even after the power is turned on to the gaming machine. Specifically, as described above, after determining that the connection signal is not input in step S74001, if the main control connection confirmation process is not being executed in step S74004, the connection signal is not displayed after the game machine is turned on. It is determined that there is a possibility of being disconnected, and the process returns to the main control connection confirmation process (see step S74006), and again confirms the connection state with the game control microcomputer 560 (specifically, a connection confirmation command is issued). Confirm that it can be received (see step S7412). Further, in the main control communication normal processing described later, even if a predetermined period (1050 ms in this embodiment) has elapsed since the connection OK command was transmitted, the connection confirmation command is also received from the game control microcomputer 560. If not received, it is determined that some kind of communication abnormality has occurred, and the process returns to the main control connection confirmation process (see steps S74202 and S74203), and again confirms the connection state with the game control microcomputer 560 (specifically, Confirms that the connection confirmation command can be received (see step S7412).

  If the connection signal is input, the payout control CPU 371 checks whether or not the reception error flag is set in the status register of the serial communication circuit 380 (step S74007). For example, if a flag indicating parity error, framing error, noise error, overrun error, or break code detection is set in the status register of the serial communication circuit 380, the payout control CPU 371 receives a reception error of the serial communication circuit 380. It is determined that it is in a state.

  If the reception error flag is set, the payout control CPU 371 initializes the reception circuit of the serial communication circuit 380 (step S74008). As described above, by initializing the reception circuit of the serial communication circuit 380 in the reception error state, the reception data is discarded, and the reception command is stored in the reception data register even though some reception abnormality has occurred. This can prevent the situation. As with the game control microcomputer 560, the payout control CPU 371 clears the contents of the reception data register by reading the data from the reception data register of the serial communication circuit 380, and discards the reception data. Good. Then, the payout control CPU 371 sets the main control communication error designation bit of the error flag (step S74009).

  Note that when the serial communication circuit 380 of the payout control microcomputer 370 is configured to clear the contents of the reception data register by reading the data from the reception data register of the serial communication circuit 380, the reception data is read out. If the status register bit 5 (RDRF) is not automatically cleared, the payout control microcomputer 370 reads the received data from the received data register each time the received data is read. Processing to clear bit 5 needs to be performed. Further, when the reception data register is not configured to be automatically cleared, the payout control microcomputer 370 clears the contents of the reception data register every time the reception data is read from the reception data register. There is a need.

  For example, the serial communication circuit 380 may clear the received data register contents and bit 5 of the status register in hardware based on reading the received data from the received data register. In this case, for example, based on the fact that the interrupt control circuit of the serial communication circuit 380 detects that the received data is read from the received data register, the contents of the received data register and bit 5 of the status register are cleared. It may be.

  In this embodiment, as described above, the game control microcomputer 560 performs control to transmit a connection confirmation command at intervals of 10 seconds even when the connection OK command cannot be received. Even if neither the winning ball number acceptance command nor the winning ball preparation command is received for the transmission of the winning ball number command, the connection OK command is received for the transmission of the connection confirmation command thereafter If possible, the control to retransmit the prize ball number command is performed again. Accordingly, when the error state of the serial communication circuit 380 is released, the connection confirmation command can be received again, and the missed prize ball number command is also retransmitted. Therefore, even if the received data is discarded in step S74008, the game Communication between the control microcomputer 560 and the payout control microcomputer 370 is not delayed, and there is no shortage of prize balls.

  If the reception error flag is not set, the payout control CPU 371 loads the contents of the reception buffer (step S74010) and checks whether or not a connection confirmation command is received (step S74011). Specifically, the payout control CPU 371 checks whether or not the content of the loaded reception buffer is “A0 (H)” (see FIG. 18). If the connection confirmation command has been received, the payout control CPU 371 proceeds to step S74014.

  If a connection confirmation command has not been received, the payout control CPU 371 checks whether or not a prize ball number command has been received. In this embodiment, as shown in FIG. 18, the content of the connection number command should be at least “51 (H)” and less than “60 (H)”. Accordingly, the payout control CPU 371 first checks whether or not the content of the loaded reception buffer is equal to or greater than the minimum prize ball number command value “51 (H)” (step S74012). Next, if the prize ball number command minimum judgment value is “51 (H)” or more, the payout control CPU 371 determines whether the content of the loaded reception buffer is less than the prize ball number command maximum judgment value “60 (H)”. It is confirmed whether or not (step S74013). If it is less than the winning ball number command maximum determination value “60 (H)”, the payout control CPU 371 determines that a winning ball number command has been received, and proceeds to step S74014.

  In step S74014, the payout control CPU 371 stores the contents of the reception buffer (connection confirmation command, prize ball number command) in the main control communication reception buffer. The main control communication reception buffer is composed of 1 byte and can store only one reception command at a time. Even with this configuration, in this embodiment, the timer interruption period (for example, 1 ms) in the payout control microcomputer 370 is shorter than the timer interruption period (4 ms) in the game control microcomputer 560. Therefore, a situation in which a plurality of payout control commands are received within one timer interrupt does not occur, and there is no inconvenience. In addition, even if the award ball number command is received before receiving the first connection confirmation command due to erroneous processing after turning on the power to the gaming machine, the connection confirmation command is subsequently issued. If it is received, it is overwritten and stored in the main control communication reception buffer. Therefore, there is a situation in which the connection confirmation command cannot be confirmed at all in the main control connection confirmation process (step S741) described later, and it becomes impossible to shift to the main control communication normal process. Can be prevented.

  FIG. 40 is a flowchart showing the main control connection confirmation process (step S741) executed when the value of the main control communication control code is 0. In the main control connection confirmation process, the payout control CPU 371 loads the contents of the main control communication reception buffer (step S7411), and confirms whether or not a connection confirmation command is received (step S7412). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S7413) and executes main control transmission command conversion processing (step S7414). In the main control transmission command conversion process in step S7414, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S7415). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. In this embodiment, an expression such as output to a register may be used. More specifically, a process of writing a command or data to the register is performed. For example, in step S7415, the payout control CPU 371 performs a process of writing a connection command to the transmission register of the serial communication circuit 380. This applies to other similar descriptions in this embodiment as well.

  By including information indicating an error state in the connection OK command, the game control microcomputer 560 can recognize a payout error that may occur due to an illegal act recognized by the payout control microcomputer 370. When the game control microcomputer 560 recognizes a payout error, the game control microcomputer 560 is configured to execute a process for the same, thereby strengthening countermeasures against fraud.

  The payout control CPU 371 clears the main control communication reception buffer when transmitting the connection OK command in step S7415. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S7416). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this embodiment) in the main control communication control timer (step S7417).

  41 and 42 are flowcharts showing the main control communication normal process (step S742) that is executed when the value of the main control communication control code is 1. FIG. In the main control communication normal process, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74201) and checks whether the main control communication control timer has timed out (step S74202).

  In this embodiment, as described above, every time one second elapses after the connection OK command is received from the payout control microcomputer 370, the next connection confirmation command is transmitted from the game control microcomputer 560. Therefore, if the main control communication control timer has timed out in step S74202, it means that the next connection confirmation command is issued even if 1050 ms (see steps S7417 and S74209) elapses after 1 second has passed since the connection OK command was transmitted. This is a case where reception was not possible. Therefore, the payout control CPU 371 sets a value “0” indicating the main control connection confirmation process in the main control communication control code (step S74203), returns to the main control connection confirmation process, and controls to wait for the recovery of the communication state. To do.

  The payout control CPU 371 clears the main control communication reception buffer if the main control communication control timer has timed out in step S74202. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not a reception command is stored in the main control communication reception buffer (step S74204). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74205). If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74206) and executes main control transmission command conversion processing (step S74207). In the main control transmission command conversion process in step S74207, a process for setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74208). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when the connection OK command is transmitted in step S74208. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Then, the payout control CPU 371 sets a predetermined value (1050 ms in this embodiment) in the main control communication control timer (step S74209).

  If the command received in step S74205 is not a connection confirmation command, it means that a prize ball number command has been received. In this case, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74210). If the value of the error flag is not 0 (that is, if it is in an error state and any error bit is set), the process proceeds to step S74219. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74211). If the BRDY signal is input, the process proceeds to step S74219.

  If no BRDY signal is input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74212), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74213). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is being performed, the process proceeds to step S74219. In this embodiment, since the next prize ball number command is transmitted after the prize ball payout operation is finished and the prize ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74213, it is not determined that the prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, the winning ball payout operation based on the received winning ball number command can be started immediately. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication reception buffer (that is, the number of winning balls set in the winning ball number command) in the unpaid-out number counter (step S74214). The unpaid-out number counter is a counter for counting the number of unpaid out prize balls and rental balls.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74215). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits a prize ball number acceptance command in step S74215. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74216). Then, the payout control CPU 371 sets a predetermined value (for example, 1 second) in the main control communication control timer (step S74218). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74218, a prize ball preparation command is transmitted.

  In step S74219, the payout control CPU 371 stores the lower 4 bits of the main control communication reception buffer (that is, the number of prize balls set with the prize ball number command) in the main control communication prize ball number buffer. That is, in this case, an error state has occurred, or during the winning ball payout operation, the ball lending payout operation, or during the ball lending preparation, the winning ball payout operation based on the received winning ball number command is immediately performed. Can't start. Therefore, the payout control CPU 371 suspends the reply of the prize ball number acceptance command and temporarily saves the prize ball number set in the prize ball number command in the main control communication prize ball number buffer.

  Next, the payout control CPU 371 sets a command for preparing a prize ball (step S74220), and executes main control transmission command conversion processing (step S74221). In the main control transmission command conversion process in step S74221, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74222). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Note that the payout control CPU 371 clears the main control communication reception buffer when the award ball preparing command is transmitted in step S74222. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “2” indicating the main control communication process to the main control communication control code (step S74223). Then, the payout control CPU 371 sets a predetermined value (1 second in this embodiment) in the main control communication control timer (step S74224). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74224, the command for preparing the next prize ball is transmitted if it is not ready to start the prize ball payout operation after one second has elapsed. Will be.

  43 and 44 are flowcharts showing the main control communication process (step S743) executed when the value of the main control communication control code is 2. FIG. In the main control communication process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74301). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S 74302). If it is not a connection confirmation command, the process proceeds to step S74306. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74303) and executes main control transmission command conversion processing (step S74304). In the main control transmission command conversion process in step S74304, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74305). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, the process proceeds to step S74306.

  In step S74306, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication process is a process that is executed after receiving the prize ball number command until the prize ball payout operation can be started based on the received prize ball number command. Since the response of the command is suspended, the game control microcomputer 560 is in a waiting state for receiving the award ball number reception command. During this time, a new payout control command is received from the game control microcomputer 560. There is no trap. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74306. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74307). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this embodiment) to the main control communication control timer (step S74308).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74309), and checks whether the main control communication control timer has timed out (step S74309). S74310).

  If the main control communication control timer has timed out (Y in step S74310), it means that one second or more has elapsed since the previous prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74311), and executes a main control transmission command conversion process (step S74312). In the main control transmission command conversion process of step S74312, the control state (error status such as a payout number error error, a ball outage error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74313). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this embodiment) in the main control communication control timer (step S74314). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74314, a command for preparing the next prize ball is issued if it is not yet ready to start a prize ball payout operation after one second has passed. Will be sent.

  If the main control communication control timer has not timed out, the payout control CPU 371 checks whether or not the value of the error flag is 0 (step S74315). If the value of the error flag is not 0 (that is, if it is in an error state and one of the error bits is set), the winning ball payout operation cannot be started yet, so the processing is ended as it is. If the value of the error flag is 0 (that is, if no error state is set and no error bit is set), the payout control CPU 371 checks whether a BRDY signal is input. (Step S74316). If the BRDY signal has been input, the winning ball payout operation cannot be started yet, and the process is terminated as it is.

  If the BRDY signal is not input, the payout control CPU 371 loads a payout control state flag indicating the payout control state (step S74317), and confirms whether the winning ball payout operation or the ball lending payout operation is in progress. (Step S74318). Specifically, the payout control CPU 371 specifies a prize ball payout operation designation bit (bit indicating that a prize ball payout operation is in progress) or a ball lending payout operation designation bit (in a ball lending payout operation) in the payout control state flag. It is confirmed whether or not a bit indicating that is set. If the winning ball payout operation or the ball lending payout operation is in progress, the winning ball payout operation cannot be started yet, so the processing is ended as it is. In this embodiment, since the next award ball number command is transmitted after the award ball payout operation is finished and the award ball end command is received, the step is performed unless an abnormality such as a communication error occurs. In S74318, it is not determined that a prize ball payout operation is in progress.

  If neither the winning ball payout operation nor the ball lending payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command can be started. In this case, the payout control CPU 371 sets the lower 4 bits of the main control communication prize ball number buffer (that is, the temporarily saved prize ball number) in the unpaid number counter (step S74319).

  In this embodiment, as described above, when the winning ball payout operation cannot be started immediately when the winning ball number command is received, the winning ball number specified by the winning ball number command is immediately set to the unpaid number. Instead of being set in the counter, it is temporarily saved in the main control communication award ball number buffer, but this control is performed, for example, by adding the award ball number to the unpaid number counter during the lending ball payout operation. This is to prevent inconvenience in processing related to payout control, such as preventing a situation where the number of winning balls cannot be accurately managed.

  Next, the payout control CPU 371 performs control to transmit a prize ball number acceptance command to the game control microcomputer 560 (step S74320). Specifically, the payout control CPU 371 performs processing for outputting a prize ball number acceptance command to the transmission register of the serial communication circuit 380.

  Next, the payout control CPU 371 sets a value “3” indicating the main control communication end process in the main control communication control code (step S74321). Then, the payout control CPU 371 sets a predetermined value (1 second in this embodiment) in the main control communication control timer (step S74322). It should be noted that if a prize ball payout operation is not completed after a lapse of one second after the prize ball number acceptance command is transmitted based on the value set in step S74322, a prize ball preparing command is transmitted.

  FIG. 45 is a flowchart showing a main control communication end process (step S744) executed when the value of the main control communication control code is 3. In the main control communication end process, the payout control CPU 371 first checks whether or not a reception command is stored in the main control communication reception buffer (step S74401). If a reception command is stored in the main control communication reception buffer, the payout control CPU 371 checks whether or not the received command is a connection confirmation command (step S74402). If it is not a connection confirmation command, the process proceeds to step S74406. If a connection confirmation command has been received, the payout control CPU 371 sets a connection OK command (step S74403) and executes main control transmission command conversion processing (step S74404). In the main control transmission command conversion process of step S74404, a process of setting a control state (an error state such as a payout number error error, a ball out error, a full tank error, a prize ball error) in the lower 4 bits of the connection OK command is performed. Done. Then, the payout control CPU 371 performs control to transmit the converted connection OK command to the game control microcomputer 560 (step S74405). Specifically, the payout control CPU 371 performs processing for outputting a connection OK command to the transmission register of the serial communication circuit 380. Then, control goes to a step S74406.

  In step S74406, the payout control CPU 371 sets a main control communication error designation bit in the error flag. That is, the main control communication end process is a process executed after receiving the prize ball number command and starting the prize ball payout operation until the prize ball payout operation based on the received prize ball number command is ended. Since the microcomputer for use 560 is in a waiting state for receiving the winning ball end command, it is unlikely that a new payout control command will be received from the game control microcomputer 560 during this period. Nevertheless, since receiving a new command can determine that some abnormality has occurred in the communication state, the payout control CPU 371 performs processing for setting a main control communication error designation bit.

  The payout control CPU 371 clears the main control communication reception buffer when the main control communication error designation bit is set in step S74406. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74407). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this embodiment) in the main control communication control timer (step S74408).

  If there is no reception command in the main control communication reception buffer, the payout control CPU 371 subtracts 1 from the value of the main control communication control timer (step S74409), and checks whether the main control communication control timer has timed out (step S74409). S74410).

  If the main control communication control timer has timed out (Y in step S74410), it means that one second or more has elapsed since the last time a prize ball acceptance command or a prize ball preparation command was transmitted. In this case, the payout control CPU 371 sets a prize ball preparing command in order to transmit the next prize ball preparing command (step S74411), and executes main control transmission command conversion processing (step S74412). In the main control transmission command conversion process in step S74412, a control state (error state such as a payout number error error, a ball runout error, a full tank error, a prize ball error, etc.) is set in the lower 4 bits of the command for preparing a prize ball. Processing is performed. Then, the payout control CPU 371 performs control to transmit the converted prize ball preparing command to the game control microcomputer 560 (step S74413). Specifically, the payout control CPU 371 performs processing for outputting a prize ball preparing command to the transmission register of the serial communication circuit 380.

  Then, the payout control CPU 371 sets a predetermined value (1 second in this embodiment) to the main control communication control timer (step S74414). It should be noted that, after the command for preparing a prize ball is transmitted based on the value set in step S74414, the command for preparing the next prize ball is transmitted if the prize ball payout operation is not yet completed after one second has passed. It will be.

  If the main control communication control timer has not timed out, the payout control CPU 371 loads a payout control state flag (step S74415), and checks whether or not a prize ball payout operation is in progress (step S74416). Specifically, the payout control CPU 371 checks whether or not a prize ball payout operation specifying bit is set in the payout control state flag. If the winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has not been finished yet, and the payout control CPU 371 ends the process as it is. If no winning ball payout operation is in progress, it means that the winning ball payout operation based on the received winning ball number command has ended. Therefore, the payout control CPU 371 performs control to transmit a prize ball end command to the game control microcomputer 560 (step S74417). Specifically, the payout control CPU 371 performs a process of outputting a prize ball end command to the transmission register of the serial communication circuit 380.

  The payout control CPU 371 clears the main control communication reception buffer when it transmits the winning ball end command in step S74417. By doing so, it is possible to prevent a situation in which the received command is erroneously recognized in the subsequent processing and the erroneous processing is executed.

  Next, the payout control CPU 371 sets a value “1” indicating the main control communication normal process in the main control communication control code (step S74418). Then, the payout control CPU 371 sets a predetermined value (1050 ms in this embodiment) to the main control communication control timer (step S74419).

  Next, the operation of the effect control means will be described. FIG. 46 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101a) as effect control means mounted on the effect control board 80. The effect control CPU 101a starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 2 ms) (step S781). .

  Thereafter, the effect control CPU 101a executes random number update processing for updating the counter value of the counter for generating a predetermined random number (step S782). Then, the timer interrupt flag is monitored (step S783). If the timer interrupt flag is not set, the process proceeds to step S782. When a timer interrupt occurs, the effect control CPU 101a sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set, the effect control CPU 101a clears the flag (step S784), and detects an abnormality in the effect control processing in steps S785 to S786 and the detection signal state of the winning opening switch. The abnormality determination process (step S787) is executed.

  In the effect control process, the effect control CPU 101a first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S785).

  Next, the effect control CPU 101a performs effect control process processing (step S786). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  FIG. 47 is a flowchart illustrating a specific example of command analysis processing (step S785). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101a checks the content of the command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101a first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101a reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is an input port state designation command (see FIG. 21) (step S614), the effect control CPU 101a stores the received variation pattern command in the input port state designation command storage area formed in the RAM. (Step S615). Then, an input port state designation command reception flag is set (step S616).

  If the received effect control command is another command, the effect control CPU 101a sets a flag according to the received effect control command (step S621). Then, control goes to a step S611.

  As commands other than the input port state designation command, there are commands relating to variations in decorative symbols as shown in FIG.

  FIG. 48 is a flowchart showing the effect control process (step S786) in the main process shown in FIG. In the effect control process, the effect control CPU 101a performs one of steps S800 to S806 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled and variable display of decorative symbols is realized.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not a variation pattern command reception flag (a flag indicating that a variation pattern command has been received) set in the command analysis processing is set. If the variation pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the decorative symbol variation start process (step S801).

  Decoration symbol variation start processing (step S801): Control is performed so that the variation of the ornament symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol changing process (step S802).

  Decoration symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S803).

  Decoration symbol variation stop processing (step S803): Control is performed to stop the variation of the ornament symbol and derive and display the display result (stop symbol). Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): When the big hit is reached, after the variation time is over, the effect display device 9 is controlled to display a screen for notifying the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the big hit game processing (step S805).

  Big hit game processing (step S805): Control during big hit game is performed. For example, when a special winning opening opening designation command or a special winning opening open designation command is received, display control of the number of rounds in the effect display device 9 is performed. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot end effect process (step S806).

  Big hit end effect processing (step S806): In the effect display device 9, display control is performed to notify the player that the big hit gaming state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  Next, the winning abnormality processing executed by the production control microcomputer 100 will be described. FIG. 49 is an explanatory diagram illustrating an example of a method for detecting a prize abnormality. In the example shown in FIG. 49, for each of the prize opening switches (start opening switch 14a, count switch 23, and each prize opening switch 29a, 30a), a prize abnormality occurs if the ON state of the detection signal continues for more than 1 second. It is determined that The time of 1 second is an example, and the time for detecting an abnormality is not limited to 1 second. Also, the winning abnormality is an abnormality in the state of the detection signal of the winning opening switch.

  FIG. 50 is an explanatory diagram showing an example of a timer used by the production control microcomputer 100 for detection of a winning abnormality. As shown in FIG. 50, the timer used for detecting the winning abnormality is a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a count switch 23. There is a timer. Each timer is formed in the RAM.

  FIG. 51 is a flowchart showing the abnormality determination process in step S787. In the abnormality determination process, the effect control CPU 101a is one of a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23. It is checked whether the timer value is a value other than 0 (corresponding to being in operation) (step S711). If there is an operating timer, the timer value is incremented by 1 (step S712). It should be noted that a timer operating flag is used as in another example of the winning abnormality detection method (see FIGS. 52 to 54), and whether or not the timer is operating is confirmed by the timer operating flag. Good.

  In addition, the effect control CPU 101a checks whether or not the value of any timer exceeds 500 (corresponding to 1 second) (step S713). If there is a timer exceeding 500, the effect display device 9 displays “A prize abnormality has occurred” (step S714). Further, the sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S715).

  Through the processing in steps S714 and S715, an abnormality notification is displayed on the effect display device 9, and an abnormality notification sound is output from the speaker 27. In addition, in the process of step S714, S715, you may perform the display and sound output which can distinguish which switch has a prize abnormality.

  In addition, the effect control CPU 101a checks whether or not an input port state designation command reception flag indicating that the input port state designation command has been received is set (step S716). If the input port state designation command reception flag is not set, the process ends. If the input port status designation command reception flag is set, the input port status designation command reception flag is reset (step S717), and the input port status designation command data stored in the input port status designation command storage area In the data indicating the state of the input port 0 (input port 0 in the game control means), it is confirmed whether or not any one or more of the bits 0, 2, 3, 4 has changed to “1” (step S718). ).

  In step S718, the production control CPU 101a compares the previous value stored in the RAM in the process of step S721 with the data of the input port state designation command.

  If there is a bit that is “1”, the timer corresponding to that bit (the timer corresponding to the start port switch 14a, the timer corresponding to the winning port switch 30a, the timer corresponding to the winning port switch 29a, or the count switch 23) “1” is set in the corresponding timer) (step S720).

  If there is no bit that is “1” in the data indicating the state of the input port 0, the timer value corresponding to the bit that is “0” is initialized to 0 (step S719). Note that the game control microcomputer 560 transmits an input port state designation command when any bit of the input port 0 changes, so that there is no bit changed to “1”. Means that there are changed bits.

  When the value of any bit of input port 0 (any one of bits 0, 2, 3 and 4 of input port 0 shown in FIG. 11) changes (the state of the detection signal of the switch) Since the input port state designation command in which the state of each bit of the input port 0 is set is output, the timer corresponding to the switch changed to the on state is operated by the processing of steps S718 and S719. Become inside. Since the timer value advances unless the value of the bit corresponding to the timer that is in operation becomes “0” (by the processing of steps S711 and S712), the timer value exceeds 500. This means that the state of the detection signal of the switch was an on state that continued for more than 1 second.

  The effect control CPU 101a can execute the processes of steps S713, S714, and S715 to perform the abnormality determination as shown in FIG.

  FIG. 52 is an explanatory diagram showing another example of a method for detecting a prize abnormality. In the example shown in FIG. 52, each of the prize opening switches (starting opening switch 14a, count switch 23, and each prize opening switch 29a, 30a) is within a predetermined time (0.5 seconds in the example shown in FIG. 52). When the state of the detection signal is turned on more than a predetermined number of times (more than 10 times in the example shown in FIG. 52) (specifically, changed from off to on), it is determined that a winning abnormality has occurred. Note that 0.5 seconds is an example, and the predetermined time for detecting an abnormality is not limited to 0.5 seconds. Another example is exceeding 10 times.

  FIG. 53 is an explanatory diagram showing an example of a timer, a flag, and a counter that the production control microcomputer 100 uses for detection of a winning abnormality. As shown in FIG. 53, as timers used for detection of a winning abnormality, a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a count switch 23 are used. There is a timer. In addition, as flags used for detection of a winning abnormality, a timer operating flag corresponding to the start port switch 14a, a timer operating flag corresponding to the winning port switch 30a, a timer operating flag corresponding to the winning port switch 29a, a count switch There is a timer operating flag corresponding to 23. Further, as counters used for detection of a winning abnormality, there are a counter corresponding to the start port switch 14a, a counter corresponding to the winning port switch 30a, a counter corresponding to the winning port switch 29a, and a counter corresponding to the count switch 23. Each counter is formed in the RAM.

  FIG. 54 is a flowchart showing the abnormality determination process in step S787 when the abnormality detection illustrated in FIG. 52 is performed. In the abnormality determination process, the effect control CPU 101a is one of a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23. It is confirmed whether or not the timer value is operating (timer operating flag is on) (step S711). If there is an operating timer, the timer value is incremented by 1 (step S712).

  In addition, the effect control CPU 101a checks whether or not an input port state designation command reception flag indicating that the input port state designation command has been received is set (step S716). If the input port state designation command reception flag is not set, the process proceeds to step S735. If the input port status designation command reception flag is set, the input port status designation command reception flag is reset (step S717), and the input port status designation command data stored in the input port status designation command storage area In the data indicating the state of input port 0 (input port 0 in the game control means), it is confirmed whether or not any one or more of bits 0, 2, 3, and 4 has changed to “1” (step S731). ).

  In step S731, the effect control CPU 101a compares the previous value stored in the RAM in the process of step S739 with the data of the input port state designation command.

  If there is a bit changed to “1”, the counter corresponding to that bit (the counter corresponding to the start port switch 14a, the counter corresponding to the winning port switch 30a, the counter corresponding to the winning port switch 29a, or the count switch 23) The value of the corresponding counter) is incremented by 1 (step S732). If the timer corresponding to the bit changed to “1” is not operating (step S733), the timer operating flag corresponding to the bit is set (turned on) (step S734).

  Further, the production control CPU 101a has one of the timers (a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, or a timer corresponding to the count switch 23). It is confirmed whether or not the value exceeds 250 (corresponding to 0.5 seconds) (step S735). If there is no timer exceeding 250, the process proceeds to step S739. If there is a timer exceeding 250, the value of the counter corresponding to the timer is confirmed (step S736). If the value of the counter exceeds 10, the effect display device 9 displays “A prize abnormality has occurred” (step S740). Further, the sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S741).

  If there is a counter with a value of 10 or less, the effect control CPU 101a clears the counter value to 0 (step S737). In addition, the corresponding timer operating flag is reset (turned off), and the corresponding timer value is initialized to 0 (step S738).

  Then, the data in the input port state designation command storage area is stored in the RAM as the previous value (step S739).

  When the value of any bit of input port 0 (any one of bits 0, 2, 3 and 4 of input port 0 shown in FIG. 11) changes (the state of the detection signal of the switch) The input port state designation command that sets the state of each bit of the input port 0 is output, but the fact that there is a bit that has changed to “1” in the process of step S731 This means that the state of the bit of the port has changed from “0” to “1” (corresponding to the switch detection signal changing from the off state to the on state). Therefore, the process of step S732 is a process of counting the number of times the switch detection signal has changed from the off state to the on state.

  Also, checking the value of the counter when 0.5 seconds have elapsed in the processes of steps S735 and S736 is equivalent to confirming the number of times the switch detection signal has changed to the ON state for 0.5 seconds. . That is, the abnormality determination as shown in FIG. 52 is executed.

  When an illegal act as illustrated in FIG. 20B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 20C. When the signal state as shown in the lower part of FIG. 20C is generated by the processing shown, an abnormality is detected (see FIG. 52). That is, the process shown in FIG. 54 is a process that can detect an illegal act illustrated in FIG.

  FIG. 55 is an explanatory diagram showing still another example of a winning abnormality detection method. In the example shown in FIG. 55, when the game ball normally passes the winning opening switch, the detection signals of the winning opening switches (start opening switch 14a, count switch 23, and winning opening switches 29a, 30a) are at least Assume that a proximity switch is used that continues to be on for 50 milliseconds (50 ms).

  As shown in FIG. 55, when the game ball passes through the switch, the on state should normally continue for, for example, 50 ms or longer, whereas the detection signal is in the on state (for example, 50 ms) halfway. In the case where the switch is forcibly turned off, it is determined that the switch is turned on a plurality of times even though one game ball is actually detected by the switch. Therefore, the production control microcomputer 100 measures the time until the switch enters the off state when the detection signal of each switch changes to the on state based on the input port state designation command, and the measured time is, for example, more than 50 ms. In the case where it is short, it is preferable to determine that an abnormality has occurred (for example, an illegal act has been received). Note that 50 ms is an example, and may vary depending on the characteristics of the switch used.

  In addition, even when the game ball passes through the switch continuously, the switch detects the completion of the passage of the first game ball (corresponding to when the detection signal is turned off) and then detects the second game ball. There is at least a predetermined time (for example, 30 ms) until the start is detected (corresponding to when the detection signal is turned on). Therefore, when the detection signal OFF period (the period from when the ON state is changed to the OFF state until the ON state is again turned on) is shorter than the predetermined period (that is, 30 ms in this example), an abnormality has occurred. (For example, a cheating is received.) In this example, it is determined that an abnormality has occurred when the off period is 30 ms or less. In addition, 30 ms is an example, and the predetermined period for detecting an abnormality is not limited to 30 milliseconds.

  Further, in this example, as in the example shown in FIG. 53, regarding detection of a winning abnormality, a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, A timer corresponding to the count switch 23 is used. In addition, as flags used for detection of a winning abnormality, a timer operating flag corresponding to the start port switch 14a, a timer operating flag corresponding to the winning port switch 30a, a timer operating flag corresponding to the winning port switch 29a, a count switch The timer operating flag corresponding to 23 is used. However, the counter is not used.

  FIG. 56 illustrates the abnormality determination process in step S787 when performing abnormality detection as illustrated in FIG. 55 (determining that an abnormality has occurred when the detection signal OFF period is equal to or shorter than a predetermined period (eg, 30 ms)). It is a flowchart to show. In the abnormality determination process, the effect control CPU 101a is one of a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23. It is confirmed whether or not the timer value is operating (timer operating flag is on) (step S711). If there is an operating timer, the timer value is incremented by 1 (step S712).

  In addition, the effect control CPU 101a checks whether or not an input port state designation command reception flag indicating that the input port state designation command has been received is set (step S716). If the input port state designation command reception flag is not set, the process ends. If the input port status designation command reception flag is set, the input port status designation command reception flag is reset (step S717), and the input port status designation command data stored in the input port status designation command storage area In the data indicating the state of the input port 0 (input port 0 in the game control means), it is confirmed whether or not any one or more of the bits 0, 2, 3, 4 has changed to “0” (step S751). ).

  In the process of step S751, the effect control CPU 101a compares the previous value stored in the RAM in the process of step S756 with the data of the input port state designation command.

  If there is a bit changed to “0”, the timer operating flag corresponding to the bit is set (turned on) (step S752).

  In addition, the effect control CPU 101a uses any one of bits 0, 2, 3, and 4 in the data indicating the state of the input port 0 that is the data of the input port state specifying command stored in the input port state specifying command storage area. It is confirmed whether one or more has changed to “1” (step S753). If there is no bit changed to “1”, the process proceeds to step S756.

  In the process of step S753, the effect control CPU 101a compares the previous value stored in the RAM in the process of step S756 with the data of the input port state designation command.

  If there is a bit changed to “1”, the value of the timer corresponding to the bit is confirmed (step S754). In step S754, the effect control CPU 101a checks whether or not the timer value is 15 or less (corresponding to 30 ms or less). When the timer value exceeds 15, the timer operating flag corresponding to the bit is reset (turned off), and the corresponding timer value is initialized to 0 (step S755). Further, the data in the input port state designation command storage area is stored in the RAM as the previous value (step S756).

  When the value of the timer is 15 or less, the effect control CPU 101a displays on the effect display device 9 that “the winning abnormality has occurred” (step S757). In addition, sound number data corresponding to the abnormality notification sound is output to the sound output board 70 (step S758).

  When the value of any bit of input port 0 (any one of bits 0, 2, 3 and 4 of input port 0 shown in FIG. 11) changes (the state of the detection signal of the switch) The input port state designation command in which the state of each bit of the input port 0 is set is output, but the fact that there is a bit that has changed to “0” in the process of step S751 This means that the state of the bit of the port has changed from “1” to “0” (corresponding to the switch detection signal changing from the on state to the off state). Therefore, the process of step S752 corresponds to a process of starting a timer when the switch detection signal changes from the on state to the off state.

  In addition, when there is a bit that has changed to “1” in the process of step S753, the state of the bit of the input port has changed from “0” to “1” (the switch detection signal has changed from the OFF state to the ON state) Equivalent to the change to Therefore, the process of step S753 is a process of determining whether or not the switch detection signal has changed from the off state to the on state. And checking the value of the timer in the process of step S754 corresponds to determining whether or not the period in which the detection signal is in the off state is 30 ms or less. That is, the abnormality determination as shown in FIG. 55 is executed.

  When an illegal act as illustrated in FIG. 20B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 20C. When the signal state as shown in the lower part of FIG. 20C is generated by the processing shown in FIG. 20C, if the detection signal is off for a predetermined period (30 ms in this example) or less, an abnormality is It is detected (see FIG. 55). That is, the process illustrated in FIG. 56 is a process capable of detecting an illegal act illustrated in FIG.

  It should be noted that the effect control CPU 101a may execute any one of the processing shown in FIG. 51, the processing shown in FIG. 54, and the processing shown in FIG. 56 in the abnormality determination processing in step S787. However, two or more of the processes may be executed.

  Also, in this embodiment, when the effect control CPU 101a determines that a prize abnormality has occurred, the effect display device 9 displays “notice that a prize abnormality has occurred” and an abnormality notification sound on the audio output board 70. Although the sound number data for outputting is output, abnormality notification may be performed by a light emitter (such as an LED) provided in the gaming machine. In addition, you may use any one or two of the display of the production | presentation display apparatus 9, the output of an abnormality notification sound, and alerting | reporting by a light-emitting body.

  Also, the end timing of the abnormality notification is arbitrary, for example, until a predetermined time elapses from when it is determined that a winning abnormality has occurred, until the effect control CPU 101a does not determine that a winning abnormality has occurred, or It is conceivable that the abnormality notification is continued until the power supply is stopped.

  In this embodiment, the production control CPU 101a adds the timer value, and the timer value becomes a predetermined value (500 in the example shown in FIG. 51, 250 in the example shown in FIG. 54). If it is determined that a winning abnormality has occurred (see steps S713 and S714 in FIG. 51), it is determined that a winning abnormality has occurred on condition that the counter value is equal to or greater than a predetermined value (step in FIG. 54). S735, S736, S740), when the timer value is equal to or less than a predetermined value (15 or less in the example shown in FIG. 56), it is determined that a winning abnormality has occurred (step S754 in FIG. 56). , S757), the timer value may be subtracted.

  For example, the production control CPU 101a sets 500 to the timer in the process of step S720 in FIG. 51 and subtracts 1 from the timer value in the process of step S712, or initially sets 250 in the timer in the process of step S738 in FIG. The timer value is decremented by 1 in the process of step S712, or 15 is initially set in the process of step S755 in FIG. 56, and the timer value is decremented by 1 in the process of step S712. In that case, the CPU 101a for effect control confirms whether or not the timer value has become 0 in the process of step S713 in FIG. 51 and the process of step S734 in FIG. Also, in the process of step S752 in FIG. 56, it is confirmed whether or not the timer value is 0 or a negative value.

  In this embodiment, the game control microcomputer 560 transmits the input port state designation command only when the state of the detection signal from any one of the prize opening switches changes, but the state of the detection signal changes. Regardless of whether or not it is performed, the input port state designation command may be transmitted every start period of the game control process (in this embodiment, 4 ms).

  When the input port state designation command is transmitted at each start period of the game control process, the game control microcomputer 560 designates the input port state in the switch process (see FIG. 23) regardless of the calculation result of step S109. Controls sending commands.

  If the CPU 101a for effect control confirms that there is no bit changed to “1” in the data indicating the state of the input port 0 in the process of step S718 shown in FIG. 51, the previous value stored in the RAM. Is compared with the data of the input port state designation command to check whether there is a bit that has changed to “0” in the data indicating the state of the input port 0 and that there is a bit that has changed to “0”. If it is confirmed, the process of step S719 is executed. In the processing shown in FIG. 51, whether or not there is a bit changed to “0” in the data indicating the state of the input port 0 is determined by the game control microcomputer 560 by any bit of the input port 0. In contrast to the assumption that the input port state designation command is transmitted when the change occurs, the input port state designation command is set at each start period of the game control process regardless of whether the state of the detection signal changes. This is because there may be neither a bit changed to “1” nor a bit changed to “0” in the data indicating the state of the input port 0.

  Note that the process shown in FIG. 54 and the process shown in FIG. 56 are performed even when an input port status designation command is transmitted every start period of the game control process regardless of whether the state of the detection signal changes. The effect control CPU 101a may perform similar processing.

  Next, a second embodiment will be described. In the first embodiment, the effect control means performs the abnormality detection process for the winning opening switch. In the second embodiment, the payout control means performs the abnormality detection process for the winning opening switch.

  FIG. 57 is an explanatory diagram showing an example of the contents of a control command transmitted and received between the game control unit and the payout control unit in the second embodiment. As shown in FIG. 57, the second embodiment indicates that the subsequent 8-bit data is input port state designation data for the control command (see FIG. 18) in the first embodiment. An input port state designation command (“30 (H)”) has been added.

  In the second embodiment, the game control microcomputer 560 indicates the state of the input port state designation command and the input port 0 in place of the control for transmitting the effect control command in the process of step S111 shown in FIG. Control is performed to transmit data (data specifying the input port state) to the payout control microcomputer 370 via the serial communication circuit 505. That is, when an input port state designation command is set in the data register of the serial communication circuit 505 and bit 6 (TC) of the status register is set to “1” (meaning the completion of transmission of the “input port state designation command”). Data specifying the input port state is set in the data register of the serial communication circuit 505.

  It should be noted that the input port state designation data is not transmitted as 8-bit data following the input port state designation command (“30 (H)”), but the input port state designation data is subordinate to the input port state designation command. It may be set to 4 bits. In that case, the game control microcomputer 560, for example, sets the values of bits 4, 3, 2, 0 of the input port 0 (see FIG. 11) to bits 3, 2, 1, 0 of the input port state designation command. Or change the assignment of the detection signal of the start port switch 14a, the winning port switches 30a and 29a, and the count switch 23 to the input port 0 (for example, change to the bits 3, 2, 1, 0 of the input port 0) To do.)

  Alternatively, the data indicating the state of the input port 0 may be transmitted using an existing command without using the input port state designation command (“30 (H)”). For example, the lower 4 bits of the connection confirmation command (see FIG. 57) are set.

  FIG. 58 is a flowchart showing a timer interrupt process executed by the payout control CPU of the payout control microcomputer 370 in the second embodiment. In contrast to the timer interrupt process in the first embodiment shown in FIG. 37, the abnormality determination process in step S772 is added in the second embodiment.

  In the second embodiment, the production control microcomputer 100 does not execute the process of step S787 shown in FIG. 46, but may execute the process of step S787.

  In the second embodiment, the payout control microcomputer 370 confirms that the input port state designation command is received by the serial communication circuit 380 in the main control command reception process shown in FIG. The data received by the serial communication circuit 380 is also stored in the input port state designation command storage area in the RAM.

  FIG. 59 is a flowchart showing an example of the abnormality determination process in step S772 when the abnormality determination as shown in FIG. 49 is executed. As shown in FIG. 50, the payout control microcomputer 370 corresponds to the timer corresponding to the start port switch 14a, the timer corresponding to the winning port switch 30a, and the winning port switch 29a as timers used for detection of the winning abnormality. A timer corresponding to the timer and count switch 23 is used. Each timer is formed in the RAM.

  The payout control CPU 371 has one of the timer values corresponding to the start port switch 14a, the timer corresponding to the winning port switch 30a, the timer corresponding to the winning port switch 29a, and the timer corresponding to the count switch 23. It is confirmed whether the value is other than 0 (equivalent to being in operation) (step S911). If there is an operating timer, the timer value is incremented by 1 (step S912). It should be noted that a timer operating flag is used as in another example of the winning abnormality detection method (see FIGS. 60 and 61), and whether or not the timer is operating is confirmed by the timer operating flag. Good.

  Further, the payout control CPU 371 checks whether or not the value of any one of the timers exceeds 1000 (corresponding to 1 second) (step S913). If there is a timer exceeding 1000, a signal indicating a prize abnormality is output to the terminal board 160 (see FIG. 5) (step S914). The signal is output to a hall computer or the like outside the gaming machine.

  In the process of step S914, a signal that can distinguish which switch has a prize abnormality may be output.

  Also, the payout control CPU 371 checks whether or not an input port state designation command reception flag indicating that an input port state designation command has been received is set (step S916). If the input port state designation command reception flag is not set, the process ends. If the input port status designation command reception flag is set, the input port status designation command reception flag is reset (step S917), and the input port status designation command data stored in the input port status designation command storage area In the data indicating the state of the input port 0 (input port 0 in the game control means), it is confirmed whether or not any one or more of the bits 0, 2, 3, 4 has changed to “1” (step S918). ).

  In step S918, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S921 with the data of the input port state designation command.

  If there is a bit that is “1”, the timer corresponding to that bit (the timer corresponding to the start port switch 14a, the timer corresponding to the winning port switch 30a, the timer corresponding to the winning port switch 29a, or the count switch 23) “1” is set in the corresponding timer) (step S920).

  If there is no bit that is “1” in the data indicating the state of the input port 0, the timer value corresponding to the bit that is “0” is initialized to 0 (step S919). Note that the game control microcomputer 560 transmits an input port state designation command when any bit of the input port 0 changes, so that there is no bit changed to “1”. Means that there are changed bits.

  When the value of any bit of input port 0 (any one of bits 0, 2, 3 and 4 of input port 0 shown in FIG. 11) changes (the state of the detection signal of the switch) Since the input port state designation command in which the state of each bit of the input port 0 is set is output, the timer corresponding to the switch changed to the ON state is operated by the processing of steps S918 and S919. Become inside. Since the timer value advances unless the value of the bit corresponding to the timer that is in operation becomes “0” (by the processing in steps S911 and S912), the timer value has exceeded 1000. This means that the state of the detection signal of the switch was an on state that continued for more than 1 second.

  The payout control CPU 371 can perform the abnormality determination as shown in FIG. 49 by executing the processes of steps S913, S914, and S915.

  Note that the processing of steps S911 to S921 (excluding step S914) shown in FIG. 59 is the same as the processing of steps S711 to S721 (excluding steps S714 and S715) shown in FIG. However, since the timer control is interrupted every 2 ms in the production control means, the timer interrupt is applied every 1 ms in the payout control means, so the value for the determination in step S913 is the value for the determination in step S713. Different from the value.

  FIG. 60 is a flowchart illustrating another example of the abnormality determination process in step S772. In this example, the payout control microcomputer 370 executes the abnormality determination as shown in FIG.

  Further, as shown in FIG. 53, the payout control microcomputer 370 has a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, and a winning port switch 29a as timers used for detection of a winning abnormality. A corresponding timer and a timer corresponding to the count switch 23 are used. In addition, as flags used for detection of a winning abnormality, a timer operating flag corresponding to the start port switch 14a, a timer operating flag corresponding to the winning port switch 30a, a timer operating flag corresponding to the winning port switch 29a, a count switch The timer operating flag corresponding to 23 is used. In addition, as counters used for detection of winning abnormality, a counter corresponding to the start port switch 14a, a counter corresponding to the winning port switch 30a, a counter corresponding to the winning port switch 29a, and a counter corresponding to the count switch 23 are used. Each counter is formed in the RAM.

  In the abnormality determination process, the payout control CPU 371 is one of a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23. It is checked whether the timer value is operating (timer operating flag is on) (step S911). If there is an operating timer, the timer value is incremented by 1 (step S912).

  Also, the payout control CPU 371 checks whether or not an input port state designation command reception flag indicating that an input port state designation command has been received is set (step S916). If the input port state designation command reception flag is not set, the process proceeds to step S935. If the input port status designation command reception flag is set, the input port status designation command reception flag is reset (step S917), and the input port status designation command data stored in the input port status designation command storage area In the data indicating the state of the input port 0 (input port 0 in the game control means), it is confirmed whether or not any one or more of the bits 0, 2, 3, and 4 has changed to “1” (step S931). ).

  In step S931, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S939 with the data of the input port state designation command.

  If there is a bit changed to “1”, the counter corresponding to that bit (the counter corresponding to the start port switch 14a, the counter corresponding to the winning port switch 30a, the counter corresponding to the winning port switch 29a, or the count switch 23) The value of the corresponding counter) is incremented by 1 (step S932). If the timer corresponding to the bit changed to “1” is not operating (step S933), the timer operating flag corresponding to the bit is set (turned on) (step S934).

  In addition, the payout control CPU 371 has one of the timers (a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, or a timer corresponding to the count switch 23). It is confirmed whether or not the value exceeds 500 (corresponding to 0.5 seconds) (step S935). If there is no timer exceeding 500, the process proceeds to step S939. If there is a timer exceeding 500, the value of the counter corresponding to the timer is confirmed (step S936). If the value of the counter exceeds 10, a signal indicating a prize abnormality is output to the terminal board 160 (see FIG. 5) (step S940). The signal is output to a hall computer or the like outside the gaming machine.

  If there is a counter having a value of 10 or less, the payout control CPU 371 clears the counter value to 0 (step S937). Further, the corresponding timer operating flag is reset (turned off), and the value of the corresponding timer is initialized to 0 (step S938).

  Then, the data in the input port state designation command storage area is stored in the RAM as the previous value (step S939).

  When the value of any bit of input port 0 (any one of bits 0, 2, 3 and 4 of input port 0 shown in FIG. 11) changes (the state of the detection signal of the switch) The input port state designation command in which the state of each bit of the input port 0 is set is output. However, the fact that there is a bit that has changed to “1” in the process of step S931 indicates that the input port This means that the state of the bit of the port has changed from “0” to “1” (corresponding to the switch detection signal changing from the off state to the on state). Therefore, the process of step S932 is a process of counting the number of times the switch detection signal has changed from the off state to the on state.

  Also, checking the value of the counter when 0.5 seconds have elapsed in the processes of steps S935 and S936 is equivalent to confirming the number of times that the switch detection signal has changed to the ON state for 0.5 seconds. . That is, the abnormality determination as shown in FIG. 52 is executed.

  When an illegal act as illustrated in FIG. 20B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 20C. When the signal state as shown in the lower part of FIG. 20C is generated by the processing shown, an abnormality is detected (see FIG. 52). That is, the process shown in FIG. 60 is a process that can detect an illegal act illustrated in FIG.

  Note that the processing in steps S911 to S939 shown in FIG. 60 is the same as the processing in steps S711 to S739 shown in FIG. However, while the production control means takes a timer interrupt every 2 ms, the payout control means takes a timer interruption every 1 ms, so the value for the determination in step S935 is the value for the determination in step S735. Different from the value.

  FIG. 61 is a flowchart showing still another example of the abnormality determination process in step S772. In this example, the payout control microcomputer 370 executes an abnormality determination (determined that an abnormality has occurred when the detection signal OFF period is equal to or shorter than a predetermined period (for example, 30 ms)) as shown in FIG. .

  Similarly to the example shown in FIG. 53, the payout control microcomputer 370 is connected to the timer corresponding to the start port switch 14a, the timer corresponding to the winning port switch 30a, and the winning port switch 29a with respect to detection of a winning abnormality. A corresponding timer and a timer corresponding to the count switch 23 are used. In addition, as flags used for detection of a winning abnormality, a timer operating flag corresponding to the start port switch 14a, a timer operating flag corresponding to the winning port switch 30a, a timer operating flag corresponding to the winning port switch 29a, a count switch The timer operating flag corresponding to 23 is used. However, the counter is not used.

  In the abnormality determination process, the payout control CPU 371 is one of a timer corresponding to the start port switch 14a, a timer corresponding to the winning port switch 30a, a timer corresponding to the winning port switch 29a, and a timer corresponding to the count switch 23. It is checked whether the timer value is operating (timer operating flag is on) (step S911). If there is an operating timer, the timer value is incremented by 1 (step S912).

  Also, the payout control CPU 371 checks whether or not an input port state designation command reception flag indicating that an input port state designation command has been received is set (step S916). If the input port state designation command reception flag is not set, the process ends. If the input port status designation command reception flag is set, the input port status designation command reception flag is reset (step S917), and the input port status designation command data stored in the input port status designation command storage area In the data indicating the state of the input port 0 (input port 0 in the game control means), it is confirmed whether or not any one or more of the bits 0, 2, 3, and 4 has changed to “0” (step S951). ).

  In the process of step S951, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S956 with the data of the input port state designation command.

  If there is a bit changed to “0”, the timer operating flag corresponding to the bit is set (turned on) (step S952).

  In addition, the payout control CPU 371 selects one of bits 0, 2, 3 and 4 in the data indicating the state of the input port 0 which is the data of the input port state specifying command stored in the input port state specifying command storage area. It is checked whether one or more has changed to “1” (step S953). If there is no bit changed to “1”, the process proceeds to step S956.

  In the process of step S953, the payout control CPU 371 compares the previous value stored in the RAM in the process of step S956 with the data of the input port state designation command.

  If there is a bit changed to “1”, the value of the timer corresponding to the bit is confirmed (step S954). In step S954, the payout control CPU 371 checks whether the timer value is 30 or less (corresponding to 30 ms or less). If the timer value exceeds 15, the timer operating flag corresponding to the bit is reset (turned off), and the corresponding timer value is initialized to 0 (step S955). Further, the data in the input port state designation command storage area is stored in the RAM as the previous value (step S956).

  When the value of the timer is 30 or less, the payout control CPU 371 outputs a signal indicating a prize abnormality to the terminal board 160 (see FIG. 5) (step S960). The signal is output to a hall computer or the like outside the gaming machine.

  When the value of any bit of input port 0 (any one of bits 0, 2, 3 and 4 of input port 0 shown in FIG. 11) changes (the state of the detection signal of the switch) The input port state designation command in which the state of each bit of the input port 0 is set is output, but the fact that there is a bit that has changed to “0” in the process of step S951 This means that the state of the bit of the port has changed from “1” to “0” (corresponding to the switch detection signal changing from the on state to the off state). Therefore, the process of step S952 corresponds to a process of starting a timer when the switch detection signal changes from the on state to the off state.

  In addition, when there is a bit that has changed to “1” in the process of step S953, the state of the bit of the input port has changed from “0” to “1” (the switch detection signal has changed from the OFF state to the ON state) Equivalent to the change to Therefore, the process of step S953 is a process of determining whether or not the switch detection signal has changed from the off state to the on state. Checking the value of the timer in the process of step S954 corresponds to determining whether or not the period in which the detection signal is in the off state is 30 ms or less. That is, the abnormality determination as shown in FIG. 55 is executed.

  When an illegal act as illustrated in FIG. 20B is performed, the state of the detection signal of the switch may be as illustrated in the lower part of FIG. 20C. When the signal state as shown in the lower part of FIG. 20C is generated by the processing shown in FIG. 20C, if the detection signal is off for a predetermined period (30 ms in this example) or less, an abnormality is It is detected (see FIG. 55). That is, the process shown in FIG. 61 is a process capable of detecting an illegal act as exemplified in FIG.

  Note that the processing in steps S911 to S956 shown in FIG. 61 is the same as the processing in steps S711 to S756 shown in FIG. However, the production control means takes a timer interrupt every 2 ms, whereas the payout control means takes a timer interruption every 1 ms. Therefore, the value for the determination in step S954 is the same as that for the determination in step S754. Different from the value.

  Further, the payout control CPU 370 may execute any one of the processing shown in FIG. 59, the processing shown in FIG. 60, and the processing shown in FIG. 61 in the abnormality determination processing in step S772. However, two or more of the processes may be executed.

  Further, in this embodiment, the payout control CPU 371 adds the timer value, and the timer value becomes a predetermined value (1000 in the example shown in FIG. 59, 500 in the example shown in FIG. 60). If it is determined that a winning abnormality has occurred (see steps S913 and S914 in FIG. 59), it is determined that a winning abnormality has occurred on condition that the counter value is equal to or greater than a predetermined value (step in FIG. 60). S935, S936, S940), it is determined that a winning abnormality has occurred when the timer value is equal to or less than a predetermined value (30 or less in the example shown in FIG. 61) (step S954 in FIG. 61). , S957), the timer value may be subtracted.

  For example, the payout control CPU 371 sets 1000 to the timer in the process of step S920 in FIG. 59 and subtracts 1 from the timer value in the process of step S912, or initializes the timer to 500 in the process of step S938 in FIG. The timer value is decremented by 1 in the process of step S912, or 30 is initially set in the process of step S955 in FIG. 61, and the timer value is decremented by 1 in the process of step S912. In that case, the payout control CPU 371 checks whether or not the timer value has become 0 in the process of step S913 in FIG. 59 and the process of step S934 in FIG. In step S952 in FIG. 61, it is checked whether the timer value is 0 or a negative value.

  In this embodiment, the game control microcomputer 560 transmits the input port state designation command only when the state of the detection signal from any one of the prize opening switches changes, but the state of the detection signal changes. Regardless of whether or not it is performed, the input port state designation command may be transmitted every start period of the game control process (in this embodiment, 4 ms).

  When the input port state designation command is transmitted at each start period of the game control process, the game control microcomputer 560 designates the input port state in the switch process (see FIG. 23) regardless of the calculation result of step S109. Controls sending commands.

  When the payout control CPU 371 confirms that there is no bit changed to “1” in the data indicating the state of the input port 0 in the process of step S918 shown in FIG. 59, the previous value stored in the RAM. Is compared with the data of the input port state designation command to check whether there is a bit that has changed to “0” in the data indicating the state of the input port 0 and that there is a bit that has changed to “0”. If it is confirmed, the process of step S919 is executed. In the processing shown in FIG. 59, whether or not there is a bit changed to “0” in the data indicating the state of the input port 0 is determined by the game control microcomputer 560 by any bit of the input port 0. In contrast to the assumption that the input port state designation command is transmitted when the change occurs, the input port state designation command is set at each start period of the game control process regardless of whether the state of the detection signal changes. This is because there may be neither a bit changed to “1” nor a bit changed to “0” in the data indicating the state of the input port 0.

  It should be noted that the process shown in FIG. 60 and the process shown in FIG. 61 are performed even when the input port status designation command is transmitted every start period of the game control process regardless of whether the state of the detection signal changes. The payout control CPU 371 may execute similar processing.

  In the processing shown in FIGS. 59 to 61, when the payout control CPU 370 determines that a winning abnormality has occurred, it outputs a signal indicating a winning abnormality to the terminal board 160. You may make it transmit to 31.

  When a signal indicating a winning abnormality is transmitted to the main board 31, as an example, a signal indicating a winning abnormality is assigned to bit 4 in the connection OK command and the winning ball preparation command shown in FIGS. . That is, when bit 4 is “1”, it indicates that a winning abnormality has occurred. Note that a signal indicating a prize abnormality may be assigned only to the connection OK command.

  When the payout control CPU 370 determines that a winning abnormality has occurred (in the case of “Y” in steps S913, S940, and S960), instead of outputting a signal indicating a winning abnormality to the terminal board 160, the RAM In the predetermined area, data indicating that a prize abnormality has occurred is set.

  Then, the payout control CPU 370 transmits the main control of Step S7414, Step S74207, Step S74221, Step S74304, Step S74312, Step S74404, and Step S74412 shown in FIGS. 40, 41, 42, 43, and 45. In the command conversion process, when data indicating that a winning abnormality has occurred is set in a predetermined area of the RAM, a process of setting bit 4 of the connection OK command to “1” is also performed.

  The CPU 56 in the game control microcomputer 560 checks the bit 4 of the connection OK command in the process of step S5224 when it is confirmed that the connection OK command is received in the process of step S5223 shown in FIG. When bit 4 is “1”, a process of outputting a signal indicating a prize abnormality to the terminal board 160 is also performed. Further, when it is confirmed that the command for preparing a prize ball is received in the process of step S52406 shown in FIG. 31 and the process of step S52506 shown in FIG. 32, in the process of step S52407 and step S52507, A process of outputting a signal indicating a prize abnormality to the terminal board 160 when the bit 4 of the command for preparing a winning ball is confirmed and the bit 4 is “1” is also performed.

  Further, when a signal indicating a winning abnormality is output to the terminal board 160 or a signal indicating a winning abnormality is transmitted to the main board 31, the payout control microcomputer 370 receives a winning ball payout process (in addition to the winning ball payout process). It is also possible to shift to a state in which the ball lending process is not executed) or to output an error signal to the error display LED 374 to display a predetermined error code. Further, the transition to the state where the payout process is not executed and the display of the error code may be executed together. Further, the game control microcomputer 560 executes at least one of the transition to a state where the payout control microcomputer 370 does not execute the payout process and the display of the error code, or without executing them. As described above, when a signal indicating a prize abnormality is received from the payout control microcomputer 370 by a connection OK command or a winning ball preparation command, a command indicating a prize abnormality is transmitted to the effect control microcomputer 100. Good. When the effect control microcomputer 100 receives a command indicating an award abnormality, for example, the effect display device 9 performs an abnormality notification.

  As described above, in the second embodiment, whether or not a winning abnormality has occurred is determined by the payout control microcomputer 370, and when it is determined that a winning abnormality has occurred, the payout control microcomputer 370 directly Alternatively, a signal indicating an award abnormality is output to the outside of the gaming machine via the gaming control microcomputer 560. Therefore, it is confirmed that a prize abnormality has occurred outside the gaming machine (for example, a hall computer).

  In the second embodiment, when a signal indicating a prize abnormality is not directly output from the game control microcomputer 370 to the outside of the gaming machine, a signal indicating a prize abnormality is played through the game control microcomputer 560. Although it is output to the outside of the machine, a signal indicating a winning abnormality may be output to the outside of the gaming machine by passing through the main board 31 but not via the game control microcomputer 560. In this case, the payout control microcomputer 370 outputs a signal indicating a winning abnormality to the main board 31 with one signal line. Then, the input is connected to the wiring to the connector reaching the terminal board 160 inside the main board 31 by the signal line.

  As described above, in the first embodiment and the second embodiment, the electrical components (the effect display device 9 and the ball payout) provided in the gaming machine based on the command output by the game control means. The period during which the input of the detection signal from the switch for detecting the winning is performed by the electrical component control means (effect control means and payout control means) for controlling the device 97) based on the command from the game control means (see FIG. 49) or if the input frequency of the detection signal exceeds a predetermined threshold (see FIG. 52), it is determined that an abnormality has occurred. Actions can be detected reliably.

  Also, since the game control means outputs a command indicating the detection signal input state only when the detection signal input state changes, an illegal act based on grasping the control cycle of the game control means by the command output cycle Can also be prevented. That is, for example, when a command is always output for each control cycle of the game control means, the control cycle of the game control means is set by monitoring the command between the game control means and the electrical component control means. Although it is possible to grasp, it is difficult to grasp the control cycle of the game control means based on the command by configuring the command indicating the detection signal input state only when the detection signal input state changes. .

  In each of the above embodiments, the proximity switch is used as the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a. However, a photo sensor may be used. FIG. 62A is an explanatory diagram showing a reflective photosensor that can be used as the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a. The photosensor illustrated in FIG. 62A includes a light-emitting diode (LED) 341 that emits light and a phototransistor 342 that receives light and outputs current. When the game ball passes in the vicinity of the light-emitting diode 341 and the phototransistor 342, the phototransistor 342 receives light from the light-emitting diode 341 reflected by the game ball and causes a current to flow to the output side. The output side is connected to the main board 31, and the detection signal of the photo sensor is input from the input driver circuit to the input port of the game control microcomputer. When a current flows to the output side of the photosensor (specifically, the output side of the phototransistor 342), the input driver circuit outputs a high level detection signal to the game control microcomputer.

  FIG. 62B is an explanatory diagram showing a transmissive photosensor that can be used as the start port switch 14a, the count switch 23, and the winning port switches 29a and 30a. The photosensor illustrated in FIG. 62B is provided with a light-emitting element (LED 341) and a light-receiving element (phototransistor 342) facing each other across a winning ball path so that the game ball blocks light from the light-emitting element. A transmission type photosensor that detects a game ball that has passed between the light emitting element and the light receiving element may be used by preventing the light receiving element from detecting light. When a transmissive photosensor is used, as shown in the lower part of FIG. 62B, the optical axis of the light emitting element (illustrated by a black circle in FIG. 62B) is a game ball path (winning ball). It is preferable to install the light emitting element and the light receiving element so as to deviate from the center of the game ball passing through the route. Compared to the case where the optical axis corresponds to the central portion of the game ball, a portion where the interval between two game balls that pass continuously is relatively wide (the portion of “void” in FIG. 62B) This is because the game ball can be detected at, and the two game balls can be easily detected separately. For the same reason, when using the reflective photosensor illustrated in FIG. 62A, the light emitting element and the light receiving element are installed so that the reflection point of the light from the light emitting element is shifted from the center of the game ball. It is preferable to do.

  Further, a proximity switch and a photo sensor may be used in combination. FIG. 63 is an explanatory diagram showing a combination example of a proximity switch and a photosensor. FIG. 63 shows an example applied to the count switch 23. In the example shown in FIG. 63A, the count switch 23 includes a proximity switch 23a and a photosensor 23b. In the count switch 23, the proximity switch 23a and the photosensor 23b are arranged so that the game ball first passes through the proximity switch 23a and then passes through the photosensor 23b.

  As shown in FIG. 63A, an electromagnetic proximity switch is provided in the upper part (upstream side of the game ball flow path) in the switch, and an optical photosensor is provided in the lower part (downstream side of the game ball flow path). Therefore, when a switch for detecting a game ball receives a fraudulent act by radio waves, the fraudulent act can be reliably detected. As shown in FIG. 63B, a photo sensor may be provided in the upper portion and a proximity switch may be provided in the lower portion. In such a configuration, when a switch for detecting a game ball receives a fraudulent act of light, the fraudulent act can be reliably detected.

  The switch is preferably formed as a switch module (sensor unit) in which the proximity switch 23a and the photosensor 23b are housed in one package.

  FIG. 64 is an explanatory diagram showing another example of bit assignment of input ports in the game control means. In the example shown in FIG. 64, the bits 0 to 4 of the input port 0 have a count switch a, a gate switch b, a left drop winning opening switch a, a right drop winning opening switch a, and a start opening switch a (“a”), respectively. Represents a proximity switch.) Is input. The input port 1 is the same as the bit assignment shown in FIG.

  The detection signals of the count switch b and the start port switch b (“b” means a photo sensor) are input to bits 0 and 4 of the input port 0 ′, respectively.

  That is, the count switch 23 and the start port switch 14a are composed of two switches as shown in FIG. The gaming control microcomputer 560 determines that an illegal act has occurred when the detection signal of one of the two switches is turned on but the detection signal of the other switch is not turned on. The count switch 23 and the start port switch 14a can reliably detect fraudulent acts. Since it is difficult to provide two switches so as to detect the same game ball at the same time, the game control microcomputer 560 naturally has to be within a predetermined time after the detection signal of one switch is turned on (installation position). However, it is determined that an illegal act has occurred when the detection signal of the other switch does not turn on in 0.5 second). In addition, it is not determined whether an illegal act has occurred for each game ball, but the count value (cumulative value) of the number of times the detection signal of one switch is turned on and the detection signal of the other switch are When the difference from the count value (cumulative value) of the number of times of the on state exceeds a predetermined value (for example, 10), it is determined that an illegal act has occurred, or based on the detection signal of one switch. The counter value is incremented by +1, the counter value is decremented by -1 based on the detection signal of the other switch, and the counter value is invalid if it exceeds a predetermined value (for example, -5 to +5). It may be determined that an action has occurred.

  Further, only the count switch 23 may be constituted by two switches as shown in FIG.

  In the first embodiment and the second embodiment, since it is determined whether or not a winning abnormality has occurred by comparing the detection signals from one switch, a switch that does not use a proximity switch and a photosensor (for example, winning a prize). The mouth switch 29a, 30a) can also reliably detect fraud. In other words, it is illegal to use a switch that uses a proximity switch and a photo sensor as a count switch 23 for detecting a prize at a large prize opening with a large number of winning balls for a prize or a start opening switch 14a provided in a start area for fluctuation of special symbols. Although it is possible to reliably detect the action, the winning opening switches 29a and 30a may be switches that do not use a proximity switch and a photosensor in order to suppress an increase in cost, in the first embodiment and the second embodiment. By configuring as in the form, it is possible to reliably detect fraud.

  The present invention can be applied to a gaming machine such as a pachinko gaming machine that pays out a prize gaming medium as a prize based on the passing of a gaming medium through a predetermined passing area.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 9 Production display device 14 Start winning opening 14a Start opening switch 15 Variable winning ball apparatus 23 Count switch 23a Proximity switch 23b Photo sensor 29a, 30a Winning opening switch 31 Game control board (main board)
37 Dispensing control board 56 CPU
80 Production control board 100 Production control microcomputer 100a Production control CPU
370 Microcomputer for payout control 371 CPU for payout control
505 Serial communication circuit 560 Microcomputer for game control

Claims (1)

A gaming machine in which a player can play a predetermined game using a game medium and pays out a prize game medium as a prize based on the passage of the game medium through a predetermined passage area provided in the game area Because
Detecting means for detecting a game medium passing through the passage area and outputting a detection signal;
Game control means for executing a game control process for controlling the progress of the game;
Electric component control means for controlling electric components provided in the gaming machine based on the command output by the game control means;
The game control means includes command output means for inputting the detection signal from the detection means and outputting a command indicating an input state of the detection signal to the electrical component control means,
The electrical component control means, based on the command output from the command output means, that an abnormality has occurred in a period during which the input of the detection signal continues or when the input frequency of the detection signal exceeds a predetermined threshold A gaming machine comprising an abnormality determining means for determining.

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