JP2012015187A - Semiconductor light emission element and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor light emission element and a manufacturing method of the same which can omit a protective element that is sometimes mounted on a circuit board with an LED element because the LED element is easy to break due to static electricity, and though it is favorable to mount the LED element and the protective element by flip chip bonding in view of heat radiation performance, productivity and mount area efficiency, circumference of the protective element becomes dark when the protective element is mounted on the circuit board by flip chip bonding.SOLUTION: An LED element 13 mounted on a circuit board 12 by flip chip bonding comprises an n-side bump 23 connected to an n-type semiconductor layer 21 and a p-side bump 24 connected to a p-type semiconductor layer 22. A varistor 26 is formed on a region where an under bump metal layer 23a extended from the n-side bump 23 faces an under bump metal layer 24a extended from the p-side bump 24. Consequently, since the varistor 26 is advantageous to static electricity prevention of the LED element 13, the protective element can be omitted from the circuit board 12.

Description

  The present invention relates to a semiconductor light emitting device that includes a protection means against breakdown due to static electricity and is flip-chip mounted on a circuit board, and a method for manufacturing the same.

  2. Description of the Related Art A semiconductor light emitting device (hereinafter referred to as an LED device unless otherwise specified) in which a semiconductor light emitting element (hereinafter referred to as an LED element unless otherwise specified) is mounted on a circuit board and packaged is known. As LED device mounting methods, there are a face-up mounting method in which the LED device and the circuit board electrodes are connected by wire bonding, and a flip chip mounting method in which the respective electrodes are directly connected via bumps or the like. . In these LED devices, since the LED element is vulnerable to static electricity and high voltage surges, a protection element may be mounted on the circuit board together with the LED element.

  For example, FIG. 2 of Patent Document 1 shows a state where the light-emitting element 1 (LED element) is flip-chip mounted on a Si diode element 7 (circuit board) that also serves as a protection element against static electricity. Further, in FIG. 3 of Patent Document 2, an LED chip 3 (LED element) is arranged on the upper surface of the insulating substrate 10 (circuit board) in order to cope with the problem that the area efficiency is reduced when the protective element is arranged on the circuit board. A state in which the zener diode chip 5 is mounted on the lower surface is shown.

  Generally, when any element is connected in parallel or in series with the LED element, the electrostatic withstand voltage is often improved. This element is also effective with resistors and capacitors. In Patent Documents 1 and 2, the (protection) element is a Zener diode. For example, in claims 1 and 2 of Patent Document 3, both of the protective elements connected in parallel with the LED element are diodes that conduct at a voltage equal to or higher than the forward voltage of the LED element. It is described that the transistor may be a transistor, a varistor, and a Zener diode connected in series in the reverse direction.

  In the LED device shown in FIG. 2 of Patent Document 1, the Si diode element 7 on which the light emitting element 1 is mounted is mounted again on the lead frame. If the LED device shown in FIG. 3 of Patent Document 2 is sealed with a resin, the package is completed. However, re-mounting to the lead frame or providing a protective element on the back of the circuit board results in a large LED device and a complicated manufacturing process. Considering mounting area efficiency and productivity as well as heat dissipation, it seems preferable to flip-chip mount the LED element and the protective element on the same surface of the circuit board. However, when the protective element is flip-chip mounted on the circuit board, the light emitting efficiency of the LED device is lowered due to the low reflectance or shadow of the protective element.

  For example, FIG. 1 of Patent Document 4 shows an LED portion (LED device) of an LED light source having a capacitive protection member between bumps as a measure for protecting itself from electrostatic breakdown while eliminating the need for a protective element. Has been. This protective member is a silicone resin containing a material having a relative dielectric constant of 10 or more, such as TiO2 (titanium oxide) or BaTiO3 (barium titanate), and acts as a capacitor.

Japanese Patent Laid-Open No. 11-191641 (FIG. 2) JP 2001-36140 A (FIG. 3) JP 2002-335012 A (Claims 1, 2) Japanese Patent Laying-Open No. 2005-294779 (FIG. 1)

  If an appropriate protective member is provided between the bumps connecting the circuit board and the LED element as shown in FIG. 1 of Patent Document 4, the LED device in which the LED element is flip-chip mounted does not require a protective element against static electricity. In Patent Document 4, there is no description relating to the manufacturing method of the LED device of FIG. 1 (the LED portion of the LED light source), but since the resin 106 exists between the electrodes 104 and 105 as well as between the bumps 102, the bump 102 Is formed on the substrate 103, and it is presumed that the resin 101 is applied to the substrate 10 at a predetermined position and then the LED 101 is flip-chip mounted. In this case, the LED 101 is not an LED element in which bump formation is improved by forming bumps on a wafer in which LED dies (LED elements not formed with bumps) are densely arranged, that is, an LED element having bumps. . Further, the method of applying a protective member to the circuit board cannot keep the electrode surface of the circuit board clean, and therefore cannot be applied to a method of manufacturing an LED device by flip-chip mounting LED elements having bumps.

  Therefore, the present invention has been made in view of this problem, and it is possible to eliminate the need to mount a protective element on a semiconductor light-emitting device even when a flip-chip bump is provided, and to provide a semiconductor light-emitting element with good manufacturing efficiency. It aims at providing the manufacturing method.

In order to solve the above problems, the present invention provides a semiconductor light emitting device including an n-side bump connected to an n-type semiconductor layer and a p-side bump connected to a p-type semiconductor layer.
An under bump metal layer extending from the n-side bump;
A protective member is provided in a region facing the under bump metal layer extending from the p-side bump.

  The protective member is preferably a varistor obtained by sintering paste containing varistor powder.

  The n-side bump and the p-side bump are preferably gold bumps, and a gold-tin eutectic layer, a tin layer, or a laminate of tin and gold is preferably provided on the gold bump.

In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor light-emitting element that is flip-chip mounted on a circuit board.
A wafer preparation step of preparing a wafer in which a plurality of semiconductor layers of the semiconductor light emitting element are arranged;
A first resist film forming step for forming a resist film in which a region for forming a bump is opened;
A bump growth step of immersing the wafer in a plating solution to grow the bump;
A first resist film removing step for exposing a plating electrode other than a region occupied by the bump;
A second resist film forming step for masking a region of the plated electrode that is an extension of the under bump metal layer;
An etching step of removing a portion of the plating electrode that is not masked;
A second resist film removing step for exposing the extended portion of the under bump metal layer;
A protective member forming step of disposing a paste-like protective member on the extending portion and solidifying the paste-like protective member;
And a singulation step of dividing the semiconductor light emitting element into individual pieces.

In the protective member forming step, the wafer may be polished after filling the protective member by photolithography and solidifying the protective member.

  The semiconductor light emitting device of the present invention and the semiconductor light emitting device obtained by the manufacturing method of the present invention include an under bump metal layer extending from an n-side bump serving as a cathode and an under bump metal layer extending from a p side bump serving as an anode. Since a protective member is provided so as to connect to the n-side or p-side bump, a surge current due to static electricity that has entered the n-side or p-side bump passes through the under bump metal layer and the protective member instead of the semiconductor light emitting element, so that the semiconductor light emitting element is destroyed. It becomes difficult. As a result, the semiconductor light emitting device in which the semiconductor light emitting element of the present invention is flip-chip mounted does not require a protective element.

  In addition, since the protective member is integrally formed in the semiconductor light emitting device of the present invention, there is a concern about the influence of static electricity such as a step of dicing the wafer to separate the semiconductor light emitting device and a step of placing and bonding the circuit light on the circuit board. It is easy to handle because the electrostatic withstand voltage is improved even in the environment where Furthermore, a protective member can be formed on a wafer in which semiconductor light emitting elements are densely packed during the manufacture. That is, the protective member can be formed on a large number of semiconductor light emitting elements at a time, which is efficient. Since the under bump metal layer extended as an electrode connected to the protective member is also the remaining plating electrode at the time of bump formation, the number of members of the semiconductor light emitting element is not increased except for the protective member. As described above, the semiconductor light emitting device and the manufacturing method thereof of the present invention have high manufacturing efficiency.

The perspective view of the LED device in 1st Embodiment of this invention. The perspective view of the LED apparatus of FIG. The top view which looked at the LED element of FIG. 2 from the bump surface. Sectional drawing of the LED element of FIG. Sectional view of the LED device of FIG. The enlarged view of the area | region shown by C of FIG. Explanatory drawing for manufacturing the LED element of FIG. Explanatory drawing for manufacturing the LED element of FIG. The top view which looked at the LED element in 2nd Embodiment of this invention from the bump surface. Sectional drawing of the LED element of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description will be omitted. For the sake of explanation, the scale of the members is changed as appropriate.
(First embodiment)

  A first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a perspective view of an LED device 10 drawn for explaining the appearance of the LED device (semiconductor light emitting device) of the present embodiment. In the LED device 10, a resin layer 11 containing a phosphor is laminated on a circuit board 12. The resin layer 11 is made of a silicone resin containing a phosphor.

  A mounting state of the LED element 13 mounted on the LED device 10 of FIG. 1 will be described with reference to FIG. FIG. 2 is a perspective view of the LED device 10 in a state where the resin layer 11 is peeled off from the LED device 10 of FIG. As shown in FIG. 2, the circuit board 12 includes a plate material 16, and a − electrode 14 and a + electrode 15 formed on the plate material 16. The LED element 13 flip-chip mounted on the circuit board 12 has an n-side bump (cathode, not shown) and a p-side bump (anode, not shown) connected to the negative electrode 14 and the positive electrode 15, respectively. .

  The bump surface of the LED element 13 will be described with reference to FIG. FIG. 3A is a plan view of the LED element 13 viewed from the bump surface side. A part of the n-type semiconductor layer 21 is exposed from the p-type semiconductor layer 22 in the upper layer. There is an n-side bump 23 on the exposed portion of the n-type semiconductor layer 21, and a p-side bump 24 on the p-type semiconductor layer 22. A varistor 26 (protective member) exists between the n-side bump 23 and the p-side bump 24. The n-side bump 23 has a smaller plane area than the p-side bump 24, and the n-side bump 23 and the p-side bump 24 are gold bumps formed by electrolytic plating. The protective film is not shown.

  The extension part of the protective film and the under bump metal layer will be described with reference to FIG. FIG. 3B is a plan view showing a state in which the n-side and p-side bumps 22 and 23 and the varistor 26 are removed from the LED element 13 of FIG. In the drawing, the outer shape of the p-type semiconductor layer 22, the n-side bump 23, the p-side bump 24, and the varistor 26 is indicated by a dotted line, the outer shape of the protective film 27 is a solid line, and the extension portion of the under bump metal layer is filled. The protective film 27 exists in a region excluding the outer peripheral portion of the LED element 13, and includes openings 27 a and 27 b inside the region occupied by the n-side bump 23 and the p-side bump 24. An under bump metal (hereinafter referred to as UBM) layer 23a of the n-side bump 23 extends in the central direction of the figure. On the other hand, the UBM layer 24a of the p-side bump 24 extends obliquely upward to the right in the figure. The extended portions of the UBM layer 23a and the UBM layer 24a face each other at the exposed portion of the n-type semiconductor layer 21, and the gap is about 50 μm. Here, the UBM layers 23a and 24a are left when a part of the plating electrode for growing the n-side and p-side bumps 23 and 24 is electrically separated from the n-side and p-side bumps 23 and 24. It is. In general, the UBM layer and the n-side or p-side bumps 23 and 24 are laminated in substantially the same planar shape. However, in the present embodiment, unlike the usual case, the UBM layers 23a and 24a are formed on the n-side and p-side bumps 23. , 24.

  The varistor 26 is made by baking a paste in which zinc oxide (ZnO) particles having a diameter of 5 to 10 μm are coated with an inorganic insulating film such as Mn or Co oxide and a binder such as organopolysiloxane or silicone resin. It is a result. Since the gap between the UMB layers 23a and 23b is about 50 μm and a threshold voltage of about 3 V is obtained for one varistor particle, 5 to 10 varistor particles are arranged in series in this gap. The threshold is about 15-30V.

  The cross section of the LED element 13 will be described with reference to FIG. FIG. 4 is a cross-sectional view of the LED element 13 taken along line BB in FIG. In addition, in order to show simultaneously the opposing location of n side and p side bumps 23 and 24 and UBM layers 23a and 24a, the BB line is bent in FIG. As shown in FIG. 4, an n-type semiconductor layer 21 is provided under the sapphire substrate 25, and a p-type semiconductor layer 22 is formed on the lower surface of the n-type semiconductor layer 21. The protective film 27 is formed on the surface of the n-type semiconductor element and the p-type semiconductor element excluding the outer peripheral part of the LED element 13, and has openings 27 a in the area occupied by the n-type semiconductor layer 21 and the area occupied by the p-type semiconductor layer 22, respectively. , 27b (numbers not shown). In each of the openings 27a and 27b, the n-type semiconductor layer 21 and the n-side bump 23, and the p-type semiconductor layer 22 and the p-side bump 24 are electrically connected. The UBM layer 23 a is laminated on the n-side bump 23, and a part extends from the n-side bump 23. The UBM layer 24a is laminated on the p-side bump 24, a part of the UBM layer 24a extends from the p-side bump 24, and the tip of the UBM layer 24a reaches the exposed portion of the n-type semiconductor region. The UBM layer 24 a existing in the exposed part of the n-type semiconductor layer 21 is insulated from the n-type semiconductor layer 21 by the protective film 27. The varistor 26 is filled between the n-side bump 23 and the p-side bump 24 and covers the extended portions of the UBM layers 23 and 24 a together with a part of the protective film 27.

The sapphire substrate 25 has a thickness of 100 to 300 μm, and the n-type semiconductor layer 21 has a thickness of about 5 μm. The p-type semiconductor layer 22 has a total thickness of about 1 μm and includes a p-type GaN layer having a thickness of 100 to 200 nm. The protective film has a thickness of about 300 nm and is made of SiO2. The n-side bumps and the p-side bumps 23 and 24 have a thickness of 10 to 30 μm. The light emitting layer (not shown) is at the boundary between the n-type semiconductor layer 21 and the p-type semiconductor layer 22, and the planar shape is substantially equal to the p-type semiconductor layer 22.

  The laminated structure of the LED device 10 will be described with reference to FIG. 5 is a cross-sectional view of the LED device 10 of FIG. 1 drawn along the line AA of FIG. The AA line in FIG. 2 is bent so that the n-side and p-side bumps 23 and 24 of the LED element 13, the UBM layers 23 a and 24 a, and the through holes 14 a and 15 a of the circuit board 12 can be illustrated simultaneously. Further, the cross section of the LED element 13 is illustrated in a simplified manner in FIG. 4 (the protective film 27 is omitted).

  As shown in FIG. 5, the circuit board 12 is composed of a plate material 16, negative and positive electrodes 14, 15, through-hole electrodes 14a, 15a, and output electrodes 14b, 15b. A negative electrode 14 and a positive electrode 15 formed on the upper surface of the plate material 16 are connected to output electrodes 14b and 15b formed on the lower surface of the plate material 16 for connection with electrodes of a mother substrate (not shown), respectively, and through holes 14a and 15a, respectively. Connected with. The LED element 13 is flip-chip mounted, and the n-side bump 23 and the p-side bump 24 are connected to the − and + electrodes 14 and 15, respectively. A resin layer 11 containing a phosphor covers the upper surface of the circuit board 12 and the periphery of the LED element 13. The plate 16 of the circuit board 12 has a thickness of 300 μm and is made of alumina. The − and + electrodes 14 and 15 and the output electrodes 14b and 15b are copper foils having a thickness of 10 to 30 μm and laminated with nickel and gold. The through holes 14a and 15a have a diameter of 200 μm and are filled with a copper paste. The resin layer 11 has a thickness of about 400 μm and is made of silicone.

  The laminated structure from the circuit board 12 to the n-type semiconductor layer 21 will be described in detail with reference to FIG. FIG. 6 is an enlarged view of a region surrounded by C in FIG. On the plate material 16 of the circuit board 12, the + electrode 15, the gold tin eutectic layer 24c, the gold bump portion 24b, the UBM (under bump metal) layer 24a, the metal layer 22b, the p-type GaN layer 22a, the light emitting layer 21a, n A type semiconductor layer 21 is laminated. The p-side bump 24 is a laminate of a gold-tin eutectic layer 24c, a gold bump portion 24b, and a UBM layer 24a. The p-type semiconductor layer 22 is a laminate of a metal layer 22b and a p-type GaN layer 22a.

  The + electrode 15 has a structure in which a copper foil having a thickness of 10 to 30 μm, a Ni layer having a thickness of about 2 μm, and an Au layer having a thickness of about 0.3 μm are stacked. The gold-tin eutectic layer 24c has a thickness of 2 to 3 μm and bonds the p-side bump 24 and the + electrode 15 together. Gold-tin eutectic bonding with a melting point of 300 ° C. to 420 ° C. can be maintained at a reflow temperature of around 250 ° C. even though it can be bonded at a relatively low temperature. This is an advantageous joining method. The gold bump portion 24b has a thickness of 10 to 30 μm. The UBM layer 24a is left when a part of the common electrode (also referred to as a plating electrode) when the gold bump portion 24b is formed by electrolytic plating is electrically isolated from the gold bump portion 24b. Is 0.3 μm and has a two-layer structure of TiW and Au.

  The metal layer 22b is formed by laminating a plurality of metal thin films such as an ITO layer, an Ag layer, and a gold layer in order to achieve various purposes such as improvement of current distribution, ohmic contact, reflection function, and prevention of atomic diffusion. The p-type semiconductor layer 22 composed of the metal layer 22b and the p-type GaN layer 22a has a thickness of about 1 μm. The light emitting layer 21a made of the GaN barrier layer and the InGaN well layer has a thickness of 60 nm, and the n-type semiconductor layer 21 made of n-type GaN has a thickness of about 5 μm.

  The manufacturing method of the LED element 13 of this embodiment is demonstrated with FIG. 7 and FIG. FIG. 7 is an explanatory diagram of the process from wafer preparation to bump formation, and FIG. 8 is an explanatory diagram of the process from arrangement of the protective member to separation.

In FIG. 7, (a) is a wafer preparation process. In the wafer 71, the n-type semiconductor layer 21 is stacked on the sapphire substrate 25, and a plurality of p-type semiconductor layers 22 are formed on the n-type semiconductor layer 21. A protective film 27 (not shown) has also been formed. (B) is a plating electrode forming step in which the plating electrode 72 is formed on the entire upper surface of the wafer 71 by sputtering. (C) is a first resist film forming step for forming a resist film 73 having an opening in which a bump is formed. (D) is a bump growth step in which the wafer 71 is immersed in a plating solution (not shown) to grow the gold bump portions 23b and 24b. (E) is a first resist film removing step of exposing the plating electrode 72 other than the region occupied by the gold bump portions 23b and 24b. (F) is a second resist film forming step of forming a resist film 74 in order to mask the region of the plating electrode 72 that becomes the extended portion of the UBM layer. (G) is an etching process in which the plating electrode 72 not masked by the resist film 74 (and the gold bump portions 23b and 24b) is removed to form the UBM layers 23a and 24a (including the extended portions). (H) is a second resist film removing step for removing the resist film 74 in order to expose the extending portions of the UBM layers 23a and 24a.

  8A is the same view as FIG. 7H, and shows a state in which the gold bump portions 23 b and 24 b and the UBM layers 23 a and 24 a are formed on the wafer 71. (B) is a step of forming a resist film 75 in which a region filled with the protective member is opened in the protective member forming step. (C) shows a step of applying a paste-like varistor 26 from the upper surface of the wafer 71 in the protective member forming step, and then sintering and solidifying the varistor 26. When the varistor 26 is applied, it is preferable to press the varistor 26 in order to improve the alignment state of the varistor particles. (D) is a step of polishing the top surfaces of the varistor 26 and the resist film 72 to expose the surfaces of the n-side and p-side gold bump portions 23b, 24b in the protective member forming step. At this time, some of the gold bump portions 23b and 24b are also polished. In this way, the varistor 26 is disposed at a desired position between the n-side and p-side bumps 23 and 24.

(E) shows a step of disposing a resist film 78 for forming a gold-tin co-crystal layer on the upper surfaces of the n-side and p-side gold bump portions 23b, 24b. At this time, the resist film 76 is preferably opened slightly narrower than the upper surfaces of the n-side and p-side gold bump portions 23b, 24b. This is because the gold-tin eutectic layers 23c and 24c are widened at the time of eutectic bonding, so that a region for escape is secured. (F) shows a step of forming the gold-tin eutectic layers 23c and 24c by sputtering. (G) shows a step of removing the resist films 75 and 76. (H) shows a singulation process in which the wafer 71 is cut and the LED elements 13 are singulated.
(Second Embodiment)

  The second embodiment of the present invention will be described in detail with reference to FIGS. The appearance of the LED device and the circuit board 12 are the same as those shown in FIGS. In the present embodiment, the LED element 13b is flip-chip mounted on the circuit board 12.

  The bump surface of the LED element 13b will be described with reference to FIG. FIG. 9 is a plan view of the LED element 13b viewed from the bump surface side. An n-side bump 23 and a p-side bump 24 exist on the electrode surface of the LED element 13b, and a varistor 26b covers the area other than the area occupied by the n-side and p-side bumps 23, 24. The LED element 13b and the LED element 13 of the first embodiment are the same except for the varistor 26b and the varistor 26. Further, the threshold value of the varistor 26b is about 15 to 30 V as in the LED element 1 of the first embodiment.

  The cross section of the LED element 13b will be described with reference to FIG. FIG. 10 is a cross-sectional view of the LED element 13b taken along line DD in FIG. As described above, the sapphire substrate 25, the n-type and p-type semiconductor layers 21 and 22, the n-side and p-side bumps 23 and 24, and the protective film 27 are the same as those of the LED element 13 of the first embodiment. The LED element 13b is different from the LED element 13 in that a varistor 26b is also present in the peripheral portion.

  In the present embodiment, since the varistor 26b is not localized between the n-side and p-side bumps 23 and 24, the protection of (b) is protected against the manufacturing process of the LED element 13 of the first embodiment shown in FIG. In the member forming step, the step of forming the resist film 75 in which the region filled with the protective member and the surrounding region are opened can be omitted.

  In the first and second embodiments, the protective members are varistors 26 and 26b. However, the protective member is not limited to a varistor, and may be any electrostatic protective member that can be solidified after filling in a paste state. Resistive pastes in which carbon is kneaded in a binder, capacitive pastes in which particles of high dielectric constant are kneaded in a binder, and electrostatic protection pastes in which metal particles having a nonconductive layer on the surface are kneaded in a binder can be used.

  In the first and second embodiments, the binder is resin, but glass frit may be contained. When glass frit is contained, the sintering temperature must be increased, but the strength of the electrostatic protection member can be increased.

  In the first and second embodiments, the n-side and p-side bumps 23 and 24 are gold bumps formed by electrolytic plating. However, the member that becomes the core of the bump is not limited to gold, and may be another alloy or metal material such as solder, copper, or aluminum. In the case of gold bumps, bonding by gold-tin eutectic can be applied as described above, so that stability during reflow is guaranteed.

  In the first and second embodiments, the gold-tin eutectic layers 23c and 24c are formed after the polishing step of FIG. If it is not necessary to polish the gold bump portions 23b and 24b (for example, the filling amount of the varistor 26 is reduced in FIG. 8C), the resist film 73 is attached immediately after the bump growth step of FIG. Alternatively, the gold-tin eutectic layers 23c and 24c may be formed on the gold bump portions 23b and 24b. In this case, the gold-tin eutectic layers 23c, 24c may be formed by sputtering, vapor deposition, or CVD, but the gold-tin eutectic layers 23c, 24c are tin (the gold is melted from the gold bump portion to the tin layer at the time of bonding). When it becomes a gold-tin alloy) or a laminate of tin and gold, the gold-tin eutectic layers 23c and 24c can be formed by an electrolytic plating method. The electrolytic plating method is easy because it can be manufactured in the air.

  In the first and second embodiments, the gold-tin eutectic layers 23c and 24c are formed on the n-side and p-side bumps 23 and 24, respectively. The gold-tin eutectic layer may be formed on the − and + electrodes 14 and 15 of the circuit board 12. However, since the LED elements 13 and 13b have a smaller plane area than the circuit board 12, it is easier to handle if the gold-tin eutectic layer is formed on the LED elements 13 and 13b side. Use efficiency becomes high.

  In the first and second embodiments, the varistors 26 and 26b are arranged by photolithography. However, the arrangement method of the protective member is not limited to the photolithography method, and may be a coating method using a dispenser or a printing method using a mask. In addition, since the photolithography method has high positional accuracy, the protective member can be accurately disposed on the facing portion of the UBM layers 23a and 24a even when the facing portion of the n-type semiconductor layer is in the exposed portion (near the n-side bump 23). Here, the opposing part of the UBM layers 23a and 24a is provided in the exposed part of the n-type semiconductor layer 21 because the heat generated when static electricity passes through the varistors 26 and 26b is localized in the exposed part of the n-type semiconductor layer 21. And to reduce the damage caused by heat.

  When a coating method or a printing method is applied, a facing region of the UBM extension may be provided near the middle of the n-side bump and the p-side bump to ease the required positional accuracy. At this time, even if the extended portion of the UBM layer is not covered with the protective member, the reliability is not impaired because the surface of the UBM layer is plated with gold.

10 ... LED device (semiconductor light-emitting device),
11 ... resin layer,
12 ... circuit board,
13, 13b ... LED element (semiconductor light emitting element),
14 ...- electrodes,
14a, 15a ... through hole,
14b, 15b ... output electrodes,
15 ... + electrode,
16 ... plate material,
21 ... n-type semiconductor layer,
21a ... light emitting layer,
22 ... p-type semiconductor layer,
22a ... p-type GaN layer,
22b ... metal layer,
23 ... n-side bump,
23a, 24a ... UBM layer,
23b, 24b ... gold bump part,
23c, 24c ... gold-tin eutectic layer,
24 ... p-side bump,
25 ... sapphire substrate,
26, 26b ... Varistor,
27 ... Protective film,
27a ... opening,
71 ... wafer,
72 ... Plating electrode,
73, 74, 75, 76... Resist film.

Claims (5)

In a semiconductor light emitting device comprising an n-side bump connected to an n-type semiconductor layer and a p-side bump connected to a p-type semiconductor layer,
An under bump metal layer extending from the n-side bump;
A semiconductor light emitting device comprising a protective member in a region facing an under bump metal layer extending from the p-side bump.   The semiconductor light-emitting element according to claim 1, wherein the protective member is a varistor obtained by sintering a paste containing varistor powder.   The n-side bump and the p-side bump are gold bumps, and a gold-tin eutectic layer, a tin layer, or a laminate of tin and gold is provided on the gold bump. The semiconductor light emitting device according to one item. In a method of manufacturing a semiconductor light emitting device that is flip-chip mounted on a circuit board,
A wafer preparation step of preparing a wafer in which a plurality of semiconductor layers of the semiconductor light emitting element are arranged;
A first resist film forming step for forming a resist film in which a region for forming a bump is opened;
A bump growth step of immersing the wafer in a plating solution to grow the bump;
A first resist film removing step for exposing a plating electrode other than a region occupied by the bump;
A second resist film forming step for masking a region of the plated electrode that is an extension of the under bump metal layer;
An etching step of removing a portion of the plating electrode that is not masked;
A second resist film removing step for exposing the extended portion of the under bump metal layer;
A protective member forming step of disposing a paste-like protective member on the extending portion and solidifying the paste-like protective member;
A method of manufacturing a semiconductor light emitting device, comprising: a step of dividing the semiconductor light emitting device into pieces. 5. The method of manufacturing a semiconductor light emitting element according to claim 4, wherein, in the protection member forming step, the wafer is polished after filling the protection member by photolithography and solidifying the protection member.

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