JP5809965B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device Download PDF

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JP5809965B2
JP5809965B2 JP2011285387A JP2011285387A JP5809965B2 JP 5809965 B2 JP5809965 B2 JP 5809965B2 JP 2011285387 A JP2011285387 A JP 2011285387A JP 2011285387 A JP2011285387 A JP 2011285387A JP 5809965 B2 JP5809965 B2 JP 5809965B2
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side protruding
protruding electrode
semiconductor layer
light emitting
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JP2013135125A (en
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篤 白石
篤 白石
嘉将 木下
嘉将 木下
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Citizen Holdings Co Ltd
Citizen Electronics Co Ltd
Citizen Watch Co Ltd
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Citizen Watch Co Ltd
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Description

本発明はフリップチップ実装用の半導体発光素子に関する。   The present invention relates to a semiconductor light emitting device for flip chip mounting.

ウェハーから切り出された半導体発光素子(以後とくに断らない限りLEDダイと呼ぶ)は、インターポーザ用の回路基板にフリップチップ実装し、この回路基板とともに樹脂などの被覆部材で被覆しパッケージ化することがある。このようにLEDダイをパッケージ化した半導体発光装置(以後とくに断らない限りLED装置と呼ぶ)は、他の電子部品と共にマザー基板に半田リフローで半田付けされることが多い。   A semiconductor light-emitting device cut out from a wafer (hereinafter referred to as an LED die unless otherwise specified) may be flip-chip mounted on a circuit board for an interposer, and coated with a covering member such as a resin together with the circuit board to be packaged. . A semiconductor light emitting device in which an LED die is packaged in this manner (hereinafter referred to as an LED device unless otherwise specified) is often soldered to a mother substrate by solder reflow together with other electronic components.

被覆部材が樹脂からなる場合、このLED装置の内部ではLEDダイと回路基板の隙間に被覆用樹脂が入り込み、半田リフロー時及びその直後に隙間に入り込んだ被覆用樹脂が膨張及び収縮し、LEDダイの底面周辺で剥離を起こすことがある。   When the covering member is made of a resin, the coating resin enters the gap between the LED die and the circuit board inside the LED device, and the coating resin that has entered the gap expands and contracts during and after solder reflow. May cause delamination around the bottom.

剥離箇所を説明するため図6に従来のLED装置60の断面図を示す。LED装置60は、LEDダイ69と回路基板68と被覆用61からなる。LEDダイ69は、サファイア基板62と、その下面に形成された半導体層63と、半導体層63に接続する突起電極64,65とからなる。回路基板68は上面に内部接続電極66,67を備え、内部接続電極66,67はそれぞれ突起電極64,65と接続している。被覆用樹脂61は、蛍光体を含有した透光性樹脂であり、回路基板68の表面とLEDダイ69を被覆し、一部はLEDダイ69と回路基板68の隙間に入り込んでいる。   FIG. 6 shows a cross-sectional view of a conventional LED device 60 in order to explain the peeled portion. The LED device 60 includes an LED die 69, a circuit board 68, and a covering 61. The LED die 69 includes a sapphire substrate 62, a semiconductor layer 63 formed on the lower surface thereof, and protruding electrodes 64 and 65 connected to the semiconductor layer 63. The circuit board 68 includes internal connection electrodes 66 and 67 on the upper surface, and the internal connection electrodes 66 and 67 are connected to the protruding electrodes 64 and 65, respectively. The coating resin 61 is a translucent resin containing a phosphor, and covers the surface of the circuit board 68 and the LED die 69, and part of the resin enters the gap between the LED die 69 and the circuit board 68.

前述のようにLED装置60はマザー基板に実装するとき半田リフローにかけられる。このときLEDダイ69と回路基板68の隙間に入り込んだ被覆用樹脂61が膨張する。このため図中、Aで示した突起電極65と半導体層63の界面や、Cで示した突起電極64と内部接続電極66との界面、Dで示した内部接続電極67と回路基板68の界面などで剥離が起きる。またリフローの直後、LEDダイ69と回路基板68の隙間に入り込んだ被覆用樹脂61が急激に収縮すると、図中、Bで示したサファイア基板62と半導体層63の界面や、この界面に隣接する半導体層63の内部において剥離が起こる。A及びCで示した部分で起こる突起電極64,65に係る剥離は、断線によるLED装置60の不点灯原因となることがある。またBに示した部分で起こる半導体層63に係る剥離は、不点灯となったりリーク電流を増大させたりする。   As described above, the LED device 60 is subjected to solder reflow when mounted on the mother board. At this time, the coating resin 61 that has entered the gap between the LED die 69 and the circuit board 68 expands. Therefore, in the figure, the interface between the protruding electrode 65 and the semiconductor layer 63 indicated by A, the interface between the protruding electrode 64 and the internal connection electrode 66 indicated by C, and the interface between the internal connection electrode 67 and the circuit board 68 indicated by D. Peeling occurs. Further, immediately after the reflow, when the coating resin 61 that has entered the gap between the LED die 69 and the circuit board 68 contracts rapidly, the interface between the sapphire substrate 62 and the semiconductor layer 63 indicated by B in FIG. Separation occurs inside the semiconductor layer 63. Separation of the protruding electrodes 64 and 65 that occurs in the portions indicated by A and C may cause the LED device 60 to be unlit due to disconnection. In addition, peeling related to the semiconductor layer 63 that occurs in the portion indicated by B results in non-lighting or increased leakage current.

以上のようにLEDダイ69と回路基板68の間に入り込んだ被覆用樹脂61にまつわる剥離に対し、類似した事例がフリップチップ実装した半導体素子のアンダーフィルについて知られている。アンダーフィルは半導体素子の下面と回路基板との間にアンダーフィル樹脂を配したものであり、アンダーフィルの膨張収縮による剥離は現在でも継続的な課題となっている。この対策として、各界面の接着力の強化、加熱プロファイルの最適化、各部材の熱膨張率の調整、熱による応力を緩和する機構の設置等が提案されており、これらの対策を組合せて信頼性を高めている。このなかで半導体素子が熱による応力を緩和する機構を持っていれば、回路基板やアンダーフィル材料及び製造工程を変更しても共通使用する半導体素子自体が剥離対策されているので、他の対策に比べこの応力緩和機構は汎用化した対策といえる。   As described above, a similar case is known for the underfill of a semiconductor element mounted on a flip chip with respect to the peeling related to the coating resin 61 that has entered between the LED die 69 and the circuit board 68. Underfill is an underfill resin disposed between a lower surface of a semiconductor element and a circuit board, and peeling due to expansion and contraction of the underfill is still an ongoing problem. As measures against this, strengthening the adhesive strength of each interface, optimizing the heating profile, adjusting the coefficient of thermal expansion of each member, installing a mechanism to relieve the stress caused by heat, etc. have been proposed. Increases sex. If the semiconductor element has a mechanism to relieve the stress caused by heat, the common use of the semiconductor element itself is a countermeasure against peeling even if the circuit board, underfill material, and manufacturing process are changed. Compared to this, this stress relaxation mechanism is a generalized measure.

例えば特許文献1の図1(a)には応力緩和層102a,102bを備えた半導体チップ102(半導体素子)が示されている。特許文献1の図1(a)を図7に再掲示する。図7は従来例として示す半導体装置の断面図である。この半導体装置は、半導体チップ1
02がリードフレーム101等の導電パターンを有する配線基板に搭載され、少なくとも半導体チップ102の回路形成面の裏面に応力緩和層102aを形成し、この半導体チップ102を覆うように絶縁樹脂105で封止していることを特徴としている。また半導体チップ102は、リードフレーム101にバンプ107を介してフリップチップ実装されており、応力緩和層102bを備えた底面がアンダーフィル樹脂104で封止されている。特許文献1の段落0019においては、この応力緩和層102bが半導体チップ102の接続部分での断線を防ぐことができると記載されており、さらに応力緩和層102bが半導体チップ102とアンダーフィル樹脂104との熱膨張差によるクラックの発生を防止できるとも記載されている。
For example, FIG. 1A of Patent Document 1 shows a semiconductor chip 102 (semiconductor element) including stress relaxation layers 102a and 102b. FIG. 1A of Patent Document 1 is re-posted in FIG. FIG. 7 is a cross-sectional view of a conventional semiconductor device. This semiconductor device includes a semiconductor chip 1
02 is mounted on a wiring board having a conductive pattern such as a lead frame 101, a stress relaxation layer 102 a is formed at least on the back surface of the circuit formation surface of the semiconductor chip 102, and sealed with an insulating resin 105 so as to cover the semiconductor chip 102 It is characterized by that. The semiconductor chip 102 is flip-chip mounted on the lead frame 101 via bumps 107, and the bottom surface provided with the stress relaxation layer 102 b is sealed with the underfill resin 104. In paragraph 0019 of Patent Document 1, it is described that the stress relaxation layer 102b can prevent disconnection at the connection portion of the semiconductor chip 102, and the stress relaxation layer 102b further includes the semiconductor chip 102, the underfill resin 104, and the like. It is also described that generation of cracks due to the difference in thermal expansion can be prevented.

特開2009−188392号公報 (図1(a)、段落0019)JP2009-188392A (FIG. 1 (a), paragraph 0019)

前述したように図7に示した応力緩和層102bは、半導体チップ102とアンダーフィル樹脂104との熱膨張差によるクラックの発生防止に寄与していると記載されているので、ずり応力を緩和し半導体チップ102の底面部の剥離や破壊を防ごうとしているものと推定できる。しかしながら図6に示した剥離は、LEDダイ69の底部に存在する被覆用樹脂61の膨張・収縮によってLEDダイ69が押し上げられたり引き下げられたりすることで起こる。特に図6のBで示した部分で起こる剥離は被覆用樹脂61の収縮により起こり、半導体層63の破壊につながる。すなわち特許文献1に示された応力緩和機構(図7の応力緩和層102b)を図6のLED装置60に適用しても、図6のBで示される部分の剥離による破壊に対応できない。   As described above, the stress relaxation layer 102b shown in FIG. 7 is described as contributing to the prevention of cracks due to the difference in thermal expansion between the semiconductor chip 102 and the underfill resin 104. It can be presumed that the bottom surface portion of the semiconductor chip 102 is to be prevented from peeling or breaking. However, the peeling shown in FIG. 6 occurs when the LED die 69 is pushed up or pulled down by the expansion / contraction of the coating resin 61 present at the bottom of the LED die 69. In particular, the peeling that occurs at the portion indicated by B in FIG. 6 occurs due to the shrinkage of the coating resin 61, leading to the destruction of the semiconductor layer 63. That is, even if the stress relaxation mechanism (stress relaxation layer 102b in FIG. 7) shown in Patent Document 1 is applied to the LED device 60 in FIG. 6, it cannot cope with the breakdown due to peeling of the portion shown in FIG.

そこで本発明は、この課題を解決するため、半導体装置の回路基板にフリップチップ実装する半導体素子において、半導体発光素子の底部の被覆用樹脂がリフロー直後で収縮しても半導体発光装置が破壊しにくい半導体発光素子を提供することを目的とする。   Therefore, in order to solve this problem, the present invention provides a semiconductor device that is flip-chip mounted on a circuit board of a semiconductor device. An object is to provide a semiconductor light emitting device.

上記課題を解決するため本発明の半導体発光素子は、半導体発光装置の回路基板にフリップチップ実装し被覆用樹脂で被覆する半導体発光素子において、p型半導体層及びn型半導体層と、前記p型半導体層及び前記n型半導体層を被覆する絶縁膜と、前記絶縁膜の開口部を介して前記p型半導体層及び前記n型半導体層と接続するp側突起電極及びn側
突起電極と、前記p側突起電極と前記n側突起電極の間に前記絶縁膜に接するようにして設けられた剥離部材とを備え、前記p側突起電極及び前記n側突起電極は前記絶縁膜から突出し、前記p側突起電極又は前記n側突起電極の少なくとも一方が部分的に前記絶縁膜と平面的に重なり、前記剥離部材は、前記絶縁膜の周辺部に存在せず、且つ前記p側突起電極及び前記n側突起電極と平面的に重ならないことを特徴とする。
In order to solve the above problems, a semiconductor light emitting device of the present invention is a semiconductor light emitting device that is flip-chip mounted on a circuit board of a semiconductor light emitting device and covered with a coating resin, and a p-type semiconductor layer and an n-type semiconductor layer, An insulating film covering the semiconductor layer and the n-type semiconductor layer; a p-side protruding electrode and an n-side protruding electrode connected to the p-type semiconductor layer and the n-type semiconductor layer through an opening of the insulating film; and a peeling member provided so as to contact with the insulating film between the p-side protruding electrode and the n-side protruding electrode, the p-side protruding electrode and the n-side protruding electrode protrudes from the insulating layer, the p At least one of the side protruding electrode or the n-side protruding electrode partially overlaps the insulating film in a planar manner, the peeling member does not exist in the peripheral portion of the insulating film, and the p-side protruding electrode and the n-side protruding electrode Side protrusion electrode and flat Characterized in that it does not overlap manner.

本発明の半導体発光素子を回路基板にフリップチップ実装し被覆用樹脂で被覆すると、実装部では突起電極及び回路基板の電極により形成される隙間に被覆用樹脂が入り込む。半田リフローの直後においてこの被覆用樹脂が急激に収縮しても、半導体発光素子若しくは被覆用樹脂から剥離部材が剥がれ、被覆用樹脂から半導体発光装置の半導体層に応力が伝達しなくなる。この結果、半導体層が半導体発光装置の透明絶縁基板から剥離したり、半導体層内での剥離・クラックが発生したりすることが防止され、半導体発光装置の全体的な破壊を防止できる。   When the semiconductor light emitting device of the present invention is flip-chip mounted on a circuit board and covered with a coating resin, the coating resin enters a gap formed by the protruding electrode and the electrode of the circuit board in the mounting portion. Even if the coating resin contracts rapidly immediately after the solder reflow, the peeling member is peeled off from the semiconductor light emitting element or the coating resin, and stress is not transmitted from the coating resin to the semiconductor layer of the semiconductor light emitting device. As a result, it is possible to prevent the semiconductor layer from being peeled off from the transparent insulating substrate of the semiconductor light emitting device, or to cause peeling / cracking in the semiconductor layer, thereby preventing the entire semiconductor light emitting device from being destroyed.

前記剥離部材は、厚さが0.5μmから1μmであっても良い。The peeling member may have a thickness of 0.5 μm to 1 μm.

一個の前記n側突起電極と複数個の前記p側突起電極を備え、前記n側突起電極を前記p側突起電極が囲み、前記n側突起電極と前記p側突起電極の間に前記剥離部材が配置されていても良い。   One n-side protruding electrode and a plurality of p-side protruding electrodes, the p-side protruding electrode surrounding the n-side protruding electrode, and the peeling member between the n-side protruding electrode and the p-side protruding electrode May be arranged.

以上のように本発明の半導体発光素子は、突起電極の間に剥離層を備えているので、この半導体発光素子を含む半導体発光装置をマザー基板に実装したとき、半導体発光素子と回路基板の間の被覆用樹脂が収縮しても剥離部材の部分的な剥離により半導体発光素子の全体的な破壊を防ぐことができる。   As described above, since the semiconductor light emitting device of the present invention includes the release layer between the protruding electrodes, when the semiconductor light emitting device including the semiconductor light emitting device is mounted on the mother substrate, the semiconductor light emitting device is interposed between the semiconductor light emitting device and the circuit substrate. Even if the coating resin shrinks, partial peeling of the peeling member can prevent the semiconductor light emitting element from being totally destroyed.

本発明の第1実施形態におけるLEDダイの構造を示す図。The figure which shows the structure of the LED die in 1st Embodiment of this invention. 図1に示したLEDダイを回路基板に実装した状態の断面図。Sectional drawing of the state which mounted the LED die shown in FIG. 1 on the circuit board. 本発明の第2実施形態におけるLEDダイの外形を示す図。The figure which shows the external shape of the LED die in 2nd Embodiment of this invention. 図3に示したLEDダイを回路基板に実装した状態の断面図。Sectional drawing of the state which mounted the LED die shown in FIG. 3 on the circuit board. 図3に示したLEDダイの底面と図4に示した回路基板の 内部接続電極の位置関係を示す図。The figure which shows the positional relationship of the bottom face of the LED die shown in FIG. 3, and the internal connection electrode of the circuit board shown in FIG. 従来のLED装置の断面図。Sectional drawing of the conventional LED device. 従来の半導体装置の断面図。Sectional drawing of the conventional semiconductor device.

以下、添付図1〜5を参照しながら本発明の好適な実施形態について詳細に説明する。なお図面の説明において、同一または相当要素には同一の符号を付し、重複する説明は省略する。また説明のため部材の縮尺は適宜変更している。さらに特許請求の範囲に記載した発明特定事項との関係をカッコ内に記載している。
(第1実施形態)
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. In the description of the drawings, the same or equivalent elements will be denoted by the same reference numerals, and redundant description will be omitted. For the sake of explanation, the scale of the members is changed as appropriate. Furthermore, the relationship with the invention specific matter described in the claims is described in parentheses.
(First embodiment)

図1と図2により本発明の第1実施形態におけるLEDダイ10(半導体発光素子)を説明する。図1はLEDダイ10の構造を示す図であり、(a)が断面図、(b)が底面図である。なお(a)は(b)のEE線に沿って描いたLEDダイ10の断面図である。(a)に示すようにサファイア基板11の下にはn型半導体層12が形成され、n型半導体層12の下面の一部にp型半導体層13が形成されている。n型半導体層12とp型半導体層13は二つの開口部を有する絶縁膜14で被覆されている。絶縁膜14の開口部には、p型半導体層13に接続するp側突起電極16と、n型半導体層12に接続するn側突起電極17とが設けられている。n側突起電極17は、平面サイズを大きくするため、その一部分が絶縁膜14を介して平面的にp型半導体層13と重なっている。またp側突起電極16とn側突起電極17の間であって、絶縁膜14の下面には剥離部材15が配置されている。   The LED die 10 (semiconductor light emitting element) in the first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a view showing the structure of the LED die 10, where (a) is a cross-sectional view and (b) is a bottom view. (A) is a sectional view of the LED die 10 drawn along the EE line of (b). As shown in (a), an n-type semiconductor layer 12 is formed under the sapphire substrate 11, and a p-type semiconductor layer 13 is formed on a part of the lower surface of the n-type semiconductor layer 12. The n-type semiconductor layer 12 and the p-type semiconductor layer 13 are covered with an insulating film 14 having two openings. A p-side protruding electrode 16 connected to the p-type semiconductor layer 13 and an n-side protruding electrode 17 connected to the n-type semiconductor layer 12 are provided in the opening of the insulating film 14. The n-side protruding electrode 17 partially overlaps the p-type semiconductor layer 13 via the insulating film 14 in order to increase the planar size. A peeling member 15 is disposed on the lower surface of the insulating film 14 between the p-side protruding electrode 16 and the n-side protruding electrode 17.

次に(b)の底面図を説明する。LEDダイ10を底面側から眺めると、外周部に絶縁膜14が見える。絶縁膜14の内側の領域にはp側突起電極16とn側突起電極17があり、p側突起電極16とn側突起電極17の間に剥離部材15がある。なお(a)で示したp型半導体層13及びn型半導体層12は絶縁膜14で被覆されているので、直接的には図示していないがp型半導体層13及びn型半導体層12からなる半導体層の周辺部には剥離部材15がない。   Next, a bottom view of (b) will be described. When the LED die 10 is viewed from the bottom side, the insulating film 14 can be seen on the outer periphery. A p-side protruding electrode 16 and an n-side protruding electrode 17 are provided in a region inside the insulating film 14, and a peeling member 15 is provided between the p-side protruding electrode 16 and the n-side protruding electrode 17. Note that since the p-type semiconductor layer 13 and the n-type semiconductor layer 12 shown in (a) are covered with the insulating film 14, the p-type semiconductor layer 13 and the n-type semiconductor layer 12 are not shown directly. There is no peeling member 15 in the periphery of the resulting semiconductor layer.

サファイア基板11は透明絶縁基板であり厚さが80〜120μmである。n型半導体層12はGaNバッファ層とn型GaN層からなり厚さが5μm程度である。p型半導体層13は、反射層や原子拡散防止層などを含む金属多層膜とp型GaN層からなり厚みが1μm程度である。図示していないが発光層はp型半導体層13とn型半導体層12の境
界部にあり、平面形状はp型半導体層13とほぼ等しい。絶縁膜14はSiO2であり厚さが数100nm〜1μm程度である。p側及びn側の突起電極16,17はAu又はCuをコアとするバンプであり、電解メッキ法で形成し厚さが10〜30μm程度である。p側及びn側の突起電極16,17は印刷法と熱処理により形成した半田バンプであっても良い。剥離部材15はポリイミド樹脂であり、厚さを0.5〜1μm程度とすると剥離しやすくできる。剥離部材15は、LEDダイ10に切断する前のウェハーに対しマスクを使って印刷若しくは噴霧により形成する。また剥離部材15はシリコーン樹脂を主成分とする離型剤であっても良い。
The sapphire substrate 11 is a transparent insulating substrate and has a thickness of 80 to 120 μm. The n-type semiconductor layer 12 includes a GaN buffer layer and an n-type GaN layer and has a thickness of about 5 μm. The p-type semiconductor layer 13 includes a metal multilayer film including a reflective layer, an atomic diffusion preventing layer, and the like and a p-type GaN layer, and has a thickness of about 1 μm. Although not shown, the light emitting layer is at the boundary between the p-type semiconductor layer 13 and the n-type semiconductor layer 12, and the planar shape is substantially the same as that of the p-type semiconductor layer 13. The insulating film 14 is made of SiO2, and has a thickness of about several hundred nm to 1 μm. The p-side and n-side protruding electrodes 16 and 17 are bumps having Au or Cu as a core, and are formed by electrolytic plating and have a thickness of about 10 to 30 μm. The p-side and n-side protruding electrodes 16 and 17 may be solder bumps formed by printing and heat treatment. The peeling member 15 is a polyimide resin, and can be easily peeled when the thickness is about 0.5 to 1 μm. The peeling member 15 is formed by printing or spraying on the wafer before cutting into the LED die 10 using a mask. Further, the release member 15 may be a release agent mainly composed of a silicone resin.

図2によりLED装置20を説明する。図2はLED装置20の断面図である。LED装置20においてLEDダイ10は、回路基板28にフリップチップ実装され、回路基板28の上面とともに蛍光樹脂21(被覆用樹脂)で被覆されている。回路基板28の上面及び下面にはそれぞれ内部接続電極22,25及び外部接続電極24,27が形成されている。内部接続電極22,25は、LEDダイ10のp側及びn側の突起電極16,17と接続し、さらにスルーホール電極23,26を介して外部接続電極24,27と接続している。   The LED device 20 will be described with reference to FIG. FIG. 2 is a cross-sectional view of the LED device 20. In the LED device 20, the LED die 10 is flip-chip mounted on a circuit board 28 and covered with a fluorescent resin 21 (covering resin) together with the upper surface of the circuit board 28. Internal connection electrodes 22 and 25 and external connection electrodes 24 and 27 are formed on the upper and lower surfaces of the circuit board 28, respectively. The internal connection electrodes 22 and 25 are connected to the p-side and n-side protruding electrodes 16 and 17 of the LED die 10 and further connected to the external connection electrodes 24 and 27 through the through-hole electrodes 23 and 26.

回路基板28の材料は、反射率、熱伝導性、耐熱性及び耐光性等を考慮し、セラミクス、金属、樹脂から選ぶ。内部接続電極22,25及び外部接続電極24,27はNi及びAuメッキした銅箔である。とくに回路基板28の材料を樹脂とした場合、熱伝導性を高くするため、内部接続電極22,25は厚さを30〜50μm程度にし、スルーホール電極23,26内に金属ペーストを充填すると良い。なおスルーホール電極23,26の直径は100〜200μm程度である。蛍光樹脂21はシリコーン樹脂に蛍光体を混練したものである。   The material of the circuit board 28 is selected from ceramics, metal, and resin in consideration of reflectivity, thermal conductivity, heat resistance, light resistance, and the like. The internal connection electrodes 22 and 25 and the external connection electrodes 24 and 27 are Ni and Au plated copper foils. In particular, when the circuit board 28 is made of resin, the internal connection electrodes 22 and 25 should be about 30 to 50 μm thick and the through-hole electrodes 23 and 26 should be filled with a metal paste in order to increase thermal conductivity. . The diameters of the through-hole electrodes 23 and 26 are about 100 to 200 μm. The fluorescent resin 21 is obtained by kneading a phosphor in a silicone resin.

次に図2により剥離部材15によるLEDダイ10の破壊防止メカニズムを説明する。半田リフローなどで加熱され、その後冷却すると、剥離部材15の下部に存在する蛍光樹脂21は、先ず膨張しようとし、その後収縮しようとする。LEDダイ10や回路基板28に含まれる界面が蛍光樹脂21の膨張に耐えられれば、収縮時は剥離部材15が絶縁膜14若しくは蛍光樹脂21から剥離する。この結果、LEDダイ10の底面においてp型及びn型の半導体層13,12に係る剥離は起こらない。本実施形態では剥離部材15をポリイミド樹脂としていたが、いっぱんに予め硬化させておいたシリコーン樹脂と新たに塗布したシリコーン樹脂の界面は接着力が弱いので、剥離部材15をシリコーン樹脂とすることも可能である。   Next, a mechanism for preventing destruction of the LED die 10 by the peeling member 15 will be described with reference to FIG. When heated by solder reflow or the like and then cooled, the fluorescent resin 21 present under the peeling member 15 first tries to expand and then contracts. If the interface included in the LED die 10 or the circuit board 28 can withstand the expansion of the fluorescent resin 21, the peeling member 15 peels from the insulating film 14 or the fluorescent resin 21 when contracting. As a result, the p-type and n-type semiconductor layers 13 and 12 do not peel at the bottom surface of the LED die 10. In this embodiment, the release member 15 is made of polyimide resin. However, since the adhesive force is weak at the interface between the previously cured silicone resin and the newly applied silicone resin, the release member 15 should be made of silicone resin. Is also possible.

本実施形態のLEDダイ10は、LEDダイ10の底面において蛍光樹脂21の収縮が起きても、剥離部材15でLEDダイ10底面と蛍光樹脂21が分離することによりLED装置20の破壊を防止していた。剥離による破壊を防止する別の手段として、図2において剥離部材15を回路基板28と蛍光樹脂21の間に配置しても良い。しかしながらこのとき回路基板28から別の回路基板に交換する場合、剥離部材の形状や配置位置を再設計せざるを得ない。すなわち本実施形態のようにLEDダイ10側に剥離部材15を備えていたほうが、回路基板変更に対して剥離部材15の再設計が不要な分、汎用性が高い。   In the LED die 10 of this embodiment, even if the fluorescent resin 21 contracts on the bottom surface of the LED die 10, the LED die 10 bottom surface and the fluorescent resin 21 are separated by the peeling member 15 to prevent the LED device 20 from being broken. It was. As another means for preventing destruction due to peeling, the peeling member 15 may be disposed between the circuit board 28 and the fluorescent resin 21 in FIG. However, in this case, when the circuit board 28 is replaced with another circuit board, the shape and arrangement position of the peeling member must be redesigned. In other words, the provision of the peeling member 15 on the LED die 10 side as in the present embodiment is more versatile because the redesign of the peeling member 15 is not required for changing the circuit board.

フリップチップ実装時のLEDダイ10底面の剥離を防止する別の手段として、p側及びn側の突起電極16,17若しくは回路基板28の内部接続電極22,25の厚みを減らし、LEDダイ10の底面における蛍光樹脂21の膨張収縮量を小さくしても良い。本実施形態の手段とこれらの手段を組合せれば高い効果が得られる。しかしながらp側及びn側の突起電極16,17を薄くするとゴミや応力への余裕度が減ってしまう。また前述したように内部接続電極22,25の厚みを減らすと熱伝導性が悪化する場合がある。   As another means for preventing peeling of the bottom surface of the LED die 10 at the time of flip chip mounting, the thicknesses of the p-side and n-side protruding electrodes 16 and 17 or the internal connection electrodes 22 and 25 of the circuit board 28 are reduced. The amount of expansion / contraction of the fluorescent resin 21 on the bottom surface may be reduced. A high effect can be obtained by combining the means of this embodiment and these means. However, if the p-side and n-side protruding electrodes 16 and 17 are thinned, the margin for dust and stress is reduced. As described above, when the thickness of the internal connection electrodes 22 and 25 is reduced, the thermal conductivity may be deteriorated.

図1(b)で示したようにLEDダイ10の底面の周辺部には剥離部材がない。p側及びn側の突起電極16,17を除く底面全体に剥離部材があっても破壊を防止する機能は保持できる。しかしながらLEDダイ10の底面周辺部に剥離部材がないと、蛍光樹脂21と絶縁膜14の密着性が向上するため、外部から侵入しようとする水分など有害な物資に対する防御性を高くできる。   As shown in FIG. 1B, there is no peeling member in the periphery of the bottom surface of the LED die 10. Even if there is a peeling member on the entire bottom surface excluding the p-side and n-side protruding electrodes 16 and 17, the function of preventing breakage can be maintained. However, if there is no peeling member around the bottom surface of the LED die 10, the adhesion between the fluorescent resin 21 and the insulating film 14 is improved, so that the protection against harmful substances such as moisture entering from the outside can be enhanced.

本実施形態のようにLEDダイ10の底面に剥離部材15を設けるという手法は、シリコン基板に多数の素子を形成した半導体素子に対しても有効である。しかしながらLEDダイ10はサファイア基板11の下面に半導体層を形成しているので、半導体層が剥離若しくは破壊しやすいため剥離部材15の効果が大きく現れる。
(第2実施形態)
The method of providing the peeling member 15 on the bottom surface of the LED die 10 as in this embodiment is also effective for a semiconductor element in which a large number of elements are formed on a silicon substrate. However, since the LED die 10 has a semiconductor layer formed on the lower surface of the sapphire substrate 11, the semiconductor layer is easily peeled off or broken, so that the effect of the peeling member 15 appears greatly.
(Second Embodiment)

LEDダイの平面サイズが大きくなると、電流分布を平準化し発光効率を向上させるためn側突起電極の周囲に複数のp側突起電極を配置することがある。そこで図3〜5により本発明の第2実施形態として小型のn側突起電極37を4個のp側突起電極36a〜36dが取り囲むLEDダイ30について説明する。   When the planar size of the LED die is increased, a plurality of p-side protruding electrodes may be arranged around the n-side protruding electrode in order to level the current distribution and improve the light emission efficiency. Therefore, an LED die 30 in which a small n-side protruding electrode 37 is surrounded by four p-side protruding electrodes 36a to 36d will be described as a second embodiment of the present invention with reference to FIGS.

先ず図3によりLEDダイ30の構造を説明する。図3はLEDダイ30の構造を示す図であり、(a)が断面図、(b)が底面図である。なお(a)は(b)のFF線に沿って描いたLEDダイ30の断面図である。(a)に示すようにサファイア基板31の下にはn型半導体層32が形成され、n型半導体層32の下面の一部にp型半導体層33が形成されている。なおp型半導体層33は中央部に開口を有する。n型半導体層32とp型半導体層33は絶縁膜34で被覆され、絶縁膜34には三つの開口部が見える。絶縁膜34の左右の開口部ではp側突起電極36a,36bがp型半導体層33と接続し、中央部の開口部ではn側突起電極37がn型半導体層32と接続している。またp側突起電極36a,36bとn側突起電極37の間であって、絶縁膜34の下面には剥離部材35が配置されている。なおn側突起電極37と絶縁膜34の間にある隙間に剥離部材が入り込んでいる。   First, the structure of the LED die 30 will be described with reference to FIG. 3A and 3B are diagrams showing the structure of the LED die 30, wherein FIG. 3A is a cross-sectional view and FIG. 3B is a bottom view. Note that (a) is a cross-sectional view of the LED die 30 drawn along the FF line of (b). As shown in (a), an n-type semiconductor layer 32 is formed under the sapphire substrate 31, and a p-type semiconductor layer 33 is formed on a part of the lower surface of the n-type semiconductor layer 32. The p-type semiconductor layer 33 has an opening at the center. The n-type semiconductor layer 32 and the p-type semiconductor layer 33 are covered with an insulating film 34, and three openings can be seen in the insulating film 34. The p-side protruding electrodes 36 a and 36 b are connected to the p-type semiconductor layer 33 in the left and right openings of the insulating film 34, and the n-side protruding electrode 37 is connected to the n-type semiconductor layer 32 in the central opening. A peeling member 35 is disposed between the p-side protruding electrodes 36 a and 36 b and the n-side protruding electrode 37 and on the lower surface of the insulating film 34. Note that a peeling member enters a gap between the n-side protruding electrode 37 and the insulating film 34.

次に(b)の底面図を説明する。LEDダイ30を底面側から眺めると、外周部に絶縁膜34が見える。絶縁膜34の内側の領域の角部には4個のp側突起電極36a,36b,36c,36dがあり、底面の中央にはn側突起電極37がある。p側突起電極36a〜36dはn側突起電極37を取り囲み、p側突起電極36a〜36dとn側突起電極37の間に剥離部材35がある。LEDダイ30の各部材は、図1で示したLEDダイ10に対し材料や厚さが等しく、平面形状が異なる。   Next, a bottom view of (b) will be described. When the LED die 30 is viewed from the bottom side, the insulating film 34 can be seen on the outer periphery. There are four p-side protruding electrodes 36a, 36b, 36c, 36d at the corners of the inner region of the insulating film 34, and an n-side protruding electrode 37 at the center of the bottom surface. The p-side protruding electrodes 36 a to 36 d surround the n-side protruding electrode 37, and the peeling member 35 is provided between the p-side protruding electrodes 36 a to 36 d and the n-side protruding electrode 37. Each member of the LED die 30 has the same material and thickness as the LED die 10 shown in FIG.

次に図4によりLED装置40を説明する。図4はLED装置40の断面図である。LED装置40においてLEDダイ30は、回路基板48にフリップチップ実装され、回路基板48の上面とともに蛍光樹脂41(被覆用樹脂)で被覆されている。回路基板48の上面及び下面にはそれぞれ内部接続電極42,45及び外部接続電極44,47が形成されている。内部接続電極42は、LEDダイ30のp側突起電極36a,36bと接続し、内部接続電極45はn側突起電極37と接続している。内部接続電極42は図中で分離しているが紙面前方で接続している。さらに内部接続電極42と外部接続電極44はスルーホール電極43で接続し、内部接続電極45と外部接続電極47は図示していないスルーホール電極を介して接続している。なお、回路基板48及び回路基板48に形成した電極の材料及び厚さは、図2に示した回路基板28及び回路基板28に形成した電極の材料及び厚さと等しく、平面形状や個数が異なる。   Next, the LED device 40 will be described with reference to FIG. FIG. 4 is a cross-sectional view of the LED device 40. In the LED device 40, the LED die 30 is flip-chip mounted on the circuit board 48 and covered with a fluorescent resin 41 (covering resin) together with the upper surface of the circuit board 48. Internal connection electrodes 42 and 45 and external connection electrodes 44 and 47 are formed on the upper and lower surfaces of the circuit board 48, respectively. The internal connection electrode 42 is connected to the p-side protruding electrodes 36 a and 36 b of the LED die 30, and the internal connection electrode 45 is connected to the n-side protruding electrode 37. Although the internal connection electrode 42 is separated in the drawing, it is connected in front of the drawing. Further, the internal connection electrode 42 and the external connection electrode 44 are connected by a through-hole electrode 43, and the internal connection electrode 45 and the external connection electrode 47 are connected through a through-hole electrode (not shown). The material and thickness of the circuit board 48 and the electrode formed on the circuit board 48 are the same as the material and thickness of the circuit board 28 and the electrode formed on the circuit board 28 shown in FIG.

次に図5により剥離部材35によるLEDダイ30の破壊防止メカニズムを説明する。図5は、図4で示したLED装置40から、外部接続電極44,47、スルーホール電極
43、回路基板48を除いた状態の底面図であり、LEDダイ30とその周辺部を内部接続電極42,45越しに眺めたものである。図中、LEDダイ30の外形、p側突起電極36a〜36d、n側突起電極37、剥離部材35の外形を点線で示している。図5ではp側の内部接続電極42が広い面積を占め、中央部及びその上方に切り欠き部がある。この切り欠き部にはn側の内部接続電極45がある。図中、切り欠き部から剥離部材35が見え、その上部に絶縁膜34と蛍光樹脂41が見える。なお切り欠き部においてLEDダイ30(図4参照)と回路基板48(図4参照)の間に存在する蛍光樹脂41は図示していない。
Next, a mechanism for preventing the destruction of the LED die 30 by the peeling member 35 will be described with reference to FIG. FIG. 5 is a bottom view of the LED device 40 shown in FIG. 4 with the external connection electrodes 44 and 47, the through-hole electrode 43, and the circuit board 48 removed, and the LED die 30 and its peripheral portion are connected to the internal connection electrodes. It was seen over 42,45. In the drawing, the outer shape of the LED die 30, the outer shapes of the p-side protruding electrodes 36a to 36d, the n-side protruding electrode 37, and the peeling member 35 are indicated by dotted lines. In FIG. 5, the p-side internal connection electrode 42 occupies a large area, and there is a central portion and a cutout portion thereabove. The notch has an n-side internal connection electrode 45. In the drawing, the peeling member 35 can be seen from the notch, and the insulating film 34 and the fluorescent resin 41 can be seen on the upper part. Note that the fluorescent resin 41 existing between the LED die 30 (see FIG. 4) and the circuit board 48 (see FIG. 4) in the notch is not shown.

半田リフローで加熱されると切り欠き部から見える領域にある蛍光樹脂(図示していない)は内部接続電極42,45がないため大きく膨張し、その後冷却するとその蛍光樹脂は大きく収縮する。このとき剥離部材35で剥離が生じることがあるが、半導体層(n型半導体層32及びp型半導体層33、図4参照)は破壊しない。LEDダイ30の周辺部であって絶縁膜34が見える領域おいても内部接続電極42,45がないため、蛍光樹脂21(図示せず)は大きめな膨張収縮を行おうとするが、LEDダイ30の底面のない領域に近いため応力が分散する。   When heated by solder reflow, the fluorescent resin (not shown) in the region seen from the notch expands greatly due to the absence of the internal connection electrodes 42 and 45, and when cooled, the fluorescent resin contracts greatly. At this time, peeling may occur in the peeling member 35, but the semiconductor layers (the n-type semiconductor layer 32 and the p-type semiconductor layer 33, see FIG. 4) are not destroyed. Even in the area around the LED die 30 where the insulating film 34 can be seen, the internal connection electrodes 42 and 45 are not present, so that the fluorescent resin 21 (not shown) tends to expand and contract. The stress disperses because it is close to the region without the bottom surface.

10,30…LEDダイ(半導体発光素子)、
11,31…サファイア基板、
12,32…n型半導体層、
13,33…p型半導体層、
14,34…絶縁膜、
16,36a,36b,36c,36d…p側突起電極、
17,37…n側突起電極、
20,40…LED装置(半導体発光装置)、
21,41…蛍光樹脂(被覆用樹脂)、
22,25,42,45…内部接続電極、
23,26,43…スルーホール電極、
24,27,44,47…外部接続電極、
28,48…回路基板。
10, 30 ... LED die (semiconductor light emitting element),
11, 31 ... sapphire substrate,
12, 32 ... n-type semiconductor layer,
13, 33 ... p-type semiconductor layer,
14, 34 ... insulating film,
16, 36a, 36b, 36c, 36d ... p-side protruding electrode,
17, 37 ... n-side protruding electrode,
20, 40 ... LED device (semiconductor light emitting device),
21, 41 ... fluorescent resin (coating resin),
22, 25, 42, 45 ... internal connection electrodes,
23, 26, 43 ... through-hole electrodes,
24, 27, 44, 47 ... external connection electrodes,
28, 48 ... Circuit board.

Claims (3)

半導体発光装置の回路基板にフリップチップ実装し被覆用樹脂で被覆する半導体発光素子において、
p型半導体層及びn型半導体層と、
前記p型半導体層及び前記n型半導体層を被覆する絶縁膜と、
前記絶縁膜の開口部を介して前記p型半導体層及び前記n型半導体層と接続するp側突起電極及びn側突起電極と、
前記p側突起電極と前記n側突起電極の間に前記絶縁膜に接するようにして設けられた剥離部材とを備え、
前記p側突起電極及び前記n側突起電極は前記絶縁膜から突出し、前記p側突起電極又は前記n側突起電極の少なくとも一方が部分的に前記絶縁膜と平面的に重なり、
前記剥離部材は、前記絶縁膜の周辺部に存在せず、且つ前記p側突起電極及び前記n側突起電極と平面的に重ならない
ことを特徴とする半導体発光素子。
In a semiconductor light emitting device that is flip-chip mounted on a circuit board of a semiconductor light emitting device and covered with a coating resin,
a p-type semiconductor layer and an n-type semiconductor layer;
An insulating film covering the p-type semiconductor layer and the n-type semiconductor layer;
A p-side protruding electrode and an n-side protruding electrode connected to the p-type semiconductor layer and the n-type semiconductor layer through the opening of the insulating film;
A peeling member provided so as to contact the insulating film between the p-side protruding electrode and the n-side protruding electrode;
The p-side protruding electrode and the n-side protruding electrode protrude from the insulating film, and at least one of the p-side protruding electrode or the n-side protruding electrode partially overlaps the insulating film in a plane,
The semiconductor light emitting element, wherein the peeling member does not exist in a peripheral portion of the insulating film and does not overlap with the p-side protruding electrode and the n-side protruding electrode in a planar manner.
前記剥離部材は、厚さが0.5μmから1μmであることを特徴とする請求項1に記載の半導体発光素子。The semiconductor light emitting element according to claim 1, wherein the peeling member has a thickness of 0.5 μm to 1 μm. 一個の前記n側突起電極と複数個の前記p側突起電極を備え、前記n側突起電極を前記p側突起電極が囲み、前記n側突起電極と前記p側突起電極の間に前記剥離部材が配置されていることを特徴とする請求項1又は2に記載の半導体発光素子。
One n-side protruding electrode and a plurality of p-side protruding electrodes, the p-side protruding electrode surrounding the n-side protruding electrode, and the peeling member between the n-side protruding electrode and the p-side protruding electrode The semiconductor light emitting element according to claim 1, wherein the semiconductor light emitting element is arranged.
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