JP2012014353A - Controller, information processor, control program and control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance availability of an input-output processor that controls plural ports with a single programmable logic circuit.SOLUTION: An I/O card 10 having plural input-output ports 30A and 30B and a single FPGA 40 includes: a determination unit 222 for, when an error is detected at one of the plural input-output ports 30A and 30B, determining whether the detected error is a soft error of a configuration RAM 401; a setting unit 223 for, when the detected error is the soft error of the configuration RAM 401, setting a state of the input-output port where no error is detected to a busy state; and an instruction unit 224 for, after the setting unit 223 sets the busy state, instructing the FPGA 40 to perform reconfiguration.

Description

  The present invention relates to a control device, an information processing device, a control program, and a control method.

  An FPGA (Field Programmable Gate Array) is known as a device that can electrically change the circuit design of a digital circuit. The FPGA is an LSI (Large Scale Integration circuit) having a large number of logic gates. The FPGA functions as a predetermined logic circuit by writing configuration data describing a logical relationship and a connection relationship between logic gates to a configuration RAM included in the FPGA. Therefore, by using the FPGA for circuit components of various electronic devices, it is possible to implement the circuit design in a shorter period of time than when manufacturing circuit components according to the design. In addition, since the circuit design can be easily changed without changing the hardware by changing the configuration data, it is used in various products including electronic devices.

  For example, an FPGA is used for port control of an I / O card for inputting / outputting information to / from an external device such as a memory card for storing information, a wireless card or a modem card. A technique using this is proposed (for example, Patent Document 1).

  By the way, errors occurring in the configuration RAM include a “hard error” in which the circuit itself is damaged and a “soft error” in which data in the RAM is destroyed by radiation such as cosmic rays. When a “hard error” occurs, it is necessary to replace the FPGA itself. On the other hand, when a “soft error” occurs, it can be recovered by reconfiguring the FPGA. Reconfiguration is performed by reloading configuration data into the configuration RAM. Therefore, input / output processing cannot be performed at the port while the configuration data is being reloaded. In other words, in an I / O card (FIG. 1A) in which one port is controlled by one FPGA, no input / output processing can be performed while the configuration data is reloaded.

  Therefore, in order to increase the availability of the I / O card, a configuration in which a single port is controlled by a plurality of FPGAs (FIG. 1B), a configuration having a plurality of ports and an FPGA corresponding to each port (FIG. 1). 1 (C)) has been proposed. In addition, a configuration in which a plurality of ports are provided and each port is controlled by a plurality of FPGAs (FIG. 1D) has been proposed. However, with the above-described configuration, the cost may be high, and it may be difficult to fit a device such as an FPGA in the card. Therefore, there is a case where a configuration (FIG. 1E) in which a plurality of ports are controlled by a single FPGA is selected depending on a trade-off between cost and availability.

JP 2002-169602 A

  Here, in an I / O card in which a plurality of ports are controlled by a single FPGA, an error occurs in one port while each port is executing input / output processing, and the cause is the configuration RAM. Suppose it was due to a soft error. In this case, the FPGA needs to be reconfigured in order to recover the error. However, while the contents of the configuration RAM are being rewritten, other ports without error cannot execute the input / output processing. In other words, when reloading of configuration data is started, I / O processing at other ports where no error has occurred will be interrupted, and the impact of the error will extend to other ports where no error has occurred. There is a risk that.

  In one aspect, an object of the present invention is to provide a control device, an information processing device, a control program, and a control method that increase the availability of an input / output processing device that controls a plurality of ports with a single programmable logic circuit. To do.

  In order to solve the above-described problem, a control device disclosed in the specification is an input / output processing device including a plurality of input / output ports and a single programmable logic circuit that controls the plurality of input / output ports. A determination unit that determines whether or not the detected error is a soft error in a circuit arrangement data memory included in the programmable logic circuit when an error is detected from any one of the input / output ports. And when the detected error is a soft error in the memory for circuit arrangement data, the busy state indicating that the input / output processing is impossible for the state of the other input / output port in which the error is not detected And a setting unit for instructing the programmable logic circuit to reset circuit arrangement data after the setting unit sets the busy state. It comprises a part, a.

  In order to solve the above problems, an information processing device disclosed in the specification includes an input / output processing device including a plurality of input / output ports and a single programmable logic circuit that controls the plurality of input / output ports; The disclosed control device.

  In order to solve the above-described problem, a control program disclosed in the specification includes: a plurality of input / output ports; and a single programmable logic circuit that controls the plurality of input / output ports. A determination step of determining whether or not the detected error is a soft error in a circuit arrangement data memory included in the programmable logic circuit when an error is detected from any one of the input / output ports. And when the detected error is a soft error in the memory for circuit arrangement data, the busy state indicating that the input / output processing is impossible for the state of the other input / output port in which the error is not detected And after the setting of the busy state in the setting step is completed, circuit arrangement is performed on the programmable logic circuit. To execute the instruction step for instructing the resetting of the data, to the computer.

  In order to solve the above problems, a control method disclosed in the specification includes an input / output processing device including a plurality of input / output ports and a single programmable logic circuit that controls the plurality of input / output ports. A determination step of determining whether or not the detected error is a soft error in a circuit arrangement data memory included in the programmable logic circuit when an error is detected from any one of the input / output ports. And when the detected error is a soft error in the memory for circuit arrangement data, the busy state indicating that the input / output processing is impossible for the state of the other input / output port in which the error is not detected And after the setting of the busy state in the setting step is completed, the circuit arrangement data is stored in the programmable logic circuit. Having, an instruction step of instructing the re-configuration.

  According to the control device, information processing device, control program, and control method disclosed in the specification, the availability of an input / output processing device that controls a plurality of ports with a single programmable logic circuit is increased.

It is a figure which shows the structural example of the I / O card proposed conventionally. It is a figure which shows an example of the system configuration | structure of information processing apparatus containing the control apparatus of this case. It is a figure which shows an example of the software structure of a control apparatus. FIG. 11 is a sequence diagram illustrating an example of processing executed by the information processing apparatus when an error occurs in the I / O card. It is a functional block diagram which shows an example of the function with which a control apparatus is provided in order to implement | achieve the process shown to the sequence diagram. It is a flowchart which shows an example of the process which a control apparatus performs. It is a figure which shows another example of the system configuration | structure of information processing apparatus containing the control apparatus of this case.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  First, an example of a system configuration of an information processing apparatus including the control device of the present case will be described with reference to FIG. As illustrated in FIG. 2, the information processing apparatus 100 includes an I / O card 10 and a control device 20.

  The I / O card 10 inputs and outputs data with an external device based on the control of the control device 20. The I / O card 10 includes input / output ports 30A and 30B as data input / output interfaces. The I / O card 10 includes one FPGA (programmable logic circuit) 40 that controls the input / output ports 30A and 30B. Further, the I / O card 10 includes a soft error determination register 50.

  The FPGA 40 includes a configuration RAM (memory for circuit arrangement data) 401 and a user RAM 402. The configuration RAM 401 stores configuration data (circuit arrangement data) describing the logical relationship and connection relationship between the logic gates. The user RAM 402 is a memory that can be freely used by the user, and stores a program and the like for realizing processing executed by the FPGA 40.

  The soft error determination register 50 is a register that stores a flag indicating whether or not a soft error has occurred in the configuration RAM 401. A soft error in the configuration RAM 401 is found by a well-known patrol technique. When a soft error is found, the flag of the soft error determination register 50 is changed from “0” to “1”, for example.

  The control device 20 controls the I / O card 10. The control device 20 performs error recovery processing when an error occurs in the I / O card 10. The control device 20 includes, for example, an input / output unit 201, a ROM (Read Only Memory) 202, a central processing unit (CPU) 203, and a RAM (Random Access Memory) 204 as hardware configurations.

  The input / output unit 201 transmits / receives data to / from the I / O card 10. The ROM 202 stores a program (details will be described later) for executing a recovery process for an error that has occurred in the FPGA 40. The CPU 203 reads and executes a program stored in the ROM 202. Further, the functions of the determination unit 222, the setting unit 223, the instruction unit 224, and the restarting unit 225 shown in FIG. 5 are realized by calculation by the CPU 203 of the program stored in the ROM 202. The RAM 204 stores temporary data used when executing the program.

  Next, an example of the software configuration of the control device 20 will be described. FIG. 3 is a diagram illustrating an example of a software configuration of the control device 20. As illustrated in FIG. 3A, the control device 20 includes an application 211, an OS (Operating System) 212, an I / O library 213, and a device driver 214.

  The application 211 is realized by a calculation performed by the CPU 203 of an application program operating on the OS 212, and provides a predetermined function such as a function of transmitting data to an external device, for example. The application 211 requests the OS 212 to input / output data when data input / output with an external device is required.

  When the OS 212 receives a data input / output request from the application 211, the OS 212 confirms management data (bus data) managed by the I / O library 213. Here, management data managed by the I / O library 213 will be described. FIG. 3B is an example of management data managed by the I / O library 213.

  The management data is registered for each port included in the I / O card 10, for example. In FIG. 3B, management data 1 stores information related to port 1 (input / output port 30A), and management data 2 stores information related to port 2 (input / output port 30B). The management data includes items of a port number, a busy flag, and a device.

  The “port number” is a number for uniquely identifying a management target port from a plurality of ports provided in the I / O card 10. The “busy flag” is a flag indicating whether or not the port with the port number is in a state where input / output processing can be executed. When the port is in a state where input / output processing can be executed, “not busy” is set in the busy flag. When the port cannot execute input / output processing, “busy” is set in the busy flag.

  “Device” designates a device file path for indicating which port of the plurality of ports of the I / O card 10 is controlled by the device driver.

  In the management data 1 of FIG. 3B, “1” is input to the “port number” and “busy” is set to the “busy flag”, so that the port of the port number 1 cannot execute input / output processing. It shows that it is in a state. The management data 1 indicates that “device file path 1” is input in “device”, so that the device file path for port 1 control is used for controlling the port of port number 1. Yes. In the management data 2, “2” is input to the “port number” and “non-busy” is set to the “busy flag”, so that the port of the port number 2 is in a state where input / output processing can be executed. Is shown. The management data 2 indicates that the device file path for port 2 control is used for controlling the port of port number 2 because “device file path 2” is input in “device”. Yes.

  The OS 212 confirms the management data described above, and inputs / outputs data via an input / output port in which “busy” is not set in the busy flag. Specifically, data is input / output via the input / output port under the control of the device driver 214. When “busy” is set in the busy flag, the OS 212 checks the busy flag again after a predetermined time (retry period) has elapsed, and if the busy flag is “not busy”, the data is input / output. I do.

  The device driver 214 controls the input / output ports 30A and 30B included in the I / O card 10 based on an instruction from the OS 212, and enables data input / output to / from an external device.

  Next, processing executed when an error occurs in the I / O card 10 in the information processing apparatus 100 described above will be described. FIG. 4 is a sequence diagram illustrating an example of processing executed by the information processing apparatus 100 when an error occurs in the I / O card 10.

  First, when the FPGA 40 detects a port error, it notifies the I / O library 213 of error detection (A). Here, it is assumed that an error is detected in port 1.

  The I / O library 213 sets the state of the port 1 to “busy state”. Specifically, the I / O library 213 sets “busy” to the busy flag of the management data 1 for managing the port 1 (B). Thus, even when the OS 212 receives an input / output request from the application 211, the OS 212 does not select the port 1 as a port for performing input / output processing. That is, by setting “busy” in the busy flag, the OS 212 that is the host program is notified that the port 1 is in a busy state in which input / output processing cannot be performed. In addition, since the OS 212 does not execute input / output processing using the port 1 in which an error has occurred, the occurrence of an input / output error is prevented.

  Next, the I / O library 213 acquires error information from the I / O card 10 via the device driver 214 (C). Specifically, the I / O library 213 instructs the device driver 214 to acquire error information. The device driver 214 checks the soft error determination register 50 and acquires error information indicating whether or not a soft error has occurred. The device driver 214 transmits error information to the I / O library 213.

  If the detected error is a soft error in the configuration RAM 401, the I / O library 213 stores the management data 2 for managing the port 2 after the input / output processing of the port 2 in which no error has been detected is completed. “Busy” is set in the busy flag (D). As a result, even if the OS 212 receives an input / output request from the application 211, the OS 212 does not select the port 2 as a port for performing input / output processing. Thereby, it is possible to prevent an input / output error from occurring in the port 2 during reconfiguration of the FPGA 40 described later.

  Next, the I / O library 213 instructs the FPGA 40 to perform reconfiguration (resetting circuit arrangement data) via the device driver 214 (E). Specifically, the I / O library 213 requests the device driver 214 to reconfigure the FPGA 40. In response to the request from the I / O library 213, the device driver 214 instructs the FPGA 40 to perform reconfiguration.

  When the reconfiguration of the FPGA 40 is completed, the I / O library 213 restarts the ports 1 and 2 via the device driver 214 and cancels the busy state of each port. Specifically, the I / O library 213 requests the device driver 214 to perform microcode reload or selective reset for each port. In response to a request from the I / O library 213, the device driver 214 performs microcode reload or selective reset for each port. Also, the I / O library 213 changes the busy flag of the management data from “busy” to “non-busy”. As a result, the OS 212 can perform input / output processing using port 1 or port 2.

  Next, an example of functions provided in the control device 20 for realizing the processing shown in the sequence diagram will be described with reference to the functional block diagram of FIG. Each function is implemented as a software mechanism of the I / O library 213 and the device driver 214.

  The control device 20 includes management data 221, a determination unit 222, a setting unit 223, an instruction unit 224, and a restart unit 225.

  The determination unit 222 acquires error information from the soft error determination register 50 of the I / O card 10 and determines whether or not the detected error is a soft error of the configuration RAM 401. The determination unit 222 outputs the determination result to the setting unit 223.

  When an error is detected in either of the input / output ports 30A and 30B from the FPGA 40, the setting unit 223 sets “busy” in the busy flag of the management data for managing the port in which the error has occurred. In addition, the setting unit 223 receives the determination result from the determination unit 222. If the detected error is a soft error in the configuration RAM 401, the setting unit 223 sets “busy” in the busy flag of the management data for managing the port in which no error has occurred. Set. In addition, the setting unit 223 notifies the instruction unit 224 that “busy” is set in the busy flag of the management data for managing the port in which no error has occurred.

  The instruction unit 224 receives the notification from the setting unit 223 and instructs the FPGA 40 to perform reconfiguration. The FPGA 40 receives an instruction from the instruction unit 224 and executes reconfiguration.

  When the reconfiguration of the FPGA 40 is completed, the instruction unit 224 notifies the restart unit 225 to that effect.

  When the reconfiguration of the FPGA 40 is completed, the restart unit 225 cancels the busy state of each port, and restarts the input / output ports 30A and 30B. Specifically, upon receiving a reconfiguration end notification from the FPGA 40, the restart unit 225 changes the busy flag of the management data from “busy” to “non-busy”, and restarts the input / output ports 30A and 30B. Perform startup.

  Next, an example of processing executed by the control device 20 will be described. FIG. 6 is a flowchart illustrating an example of processing executed by the control device 20.

  The setting unit 223 determines whether the FPGA 40 has detected an error in the input / output port 30A or 30B (step S11).

  When the determination in step S11 is NO, the setting unit 223 continues the process in step S11. When the determination in step S11 is YES, the setting unit 223 sets “busy” in the busy flag of the management data for managing the port in which the error is detected (step S12).

  Next, the determination unit 222 acquires error information (step S13). Based on the acquired error information, the determination unit 222 determines whether an error that has occurred in the input / output port 30A or 30B is a soft error in the configuration RAM 401 (step S14).

  If the determination in step S14 is NO, an input / output error process for recovering the input / output error is executed by an error processing unit (not shown in FIG. 5) (step S20).

  When the determination in step S14 is YES, the setting unit 223 determines whether another port in which no error has been detected is performing input / output processing (step S15). When the other port is executing the input / output process (step S15 / YES), the setting unit 223 repeats the process of step S15 until the other port completes the input / output process.

  When the other port is not executing input / output processing (step S15 / NO), the setting unit 223 sets “busy” to the busy flag of the management data for managing the other port (step S16).

  Next, the instruction unit 224 instructs the FPGA 40 to perform reconfiguration (step S17). The restart unit 225 determines whether or not the reconfiguration of the FPGA 40 has been completed (step S18).

  When the reconfiguration of the FPGA 40 is not completed (step S18 / NO), the restarting unit 225 continues the process of step S18. When the reconfiguration of the FPGA 40 is completed (step S18 / YES), the restarting unit 225 releases the port again and releases the “busy” state of the management data (step S19), and ends the process.

  As is apparent from the above description, according to the above-described embodiment, the setting unit 223, for example, if the error that occurred in the port 1 is a soft error in the configuration RAM 401, Is completed, set port 2 to the “busy” state. Then, the instruction unit 224 instructs the FPGA 40 to perform reconfiguration after the port 2 is set to the “busy” state. Thereby, it is possible to prevent the input / output process of the port 2 from being interrupted by the FPGA 40 starting reconfiguration while the port 2 is executing the input / output process. As a result, the occurrence of an input / output error due to the start of reconfiguration is prevented, so that the availability of the I / O card 10 can be prevented from decreasing. Further, since the port 2 can complete the input / output process being executed, the availability of the I / O card 10 is increased. Further, since the port 2 is in the “busy” state while the FPGA 40 is performing reconfiguration, input / output processing using the port 2 can be prevented. As a result, it is possible to prevent an input / output error from occurring while the FPGA 40 is performing reconfiguration. Further, the setting unit 223 does not place the port 2 in the “busy” state when the error occurring in the port 1 is not a soft error in the configuration RAM 401. As a result, in the case of an error that does not require reconfiguration of the FPGA 40, the input / output processing at the port 2 can be continued, so that the availability of the I / O card 10 is increased.

  In addition, the setting unit 223 sets a port in which an error is detected to a busy state. For example, the setting unit 223 sets the port 1 to the busy state when an error is detected on the port 1. As a result, the input / output process using the port where the error is detected can be prevented, and the occurrence of the input / output error can be prevented.

  When the reconfiguration of the FPGA 40 is completed, the restart unit 225 releases the “busy” state and restarts the input / output port. As a result, since the input / output process using the I / O card 10 can be executed again, the period during which the FPGA 40 is executing reconfiguration is the period during which the input / output process using the I / O card 10 cannot be performed. It becomes. In other words, since the I / O card 10 cannot be used, the influence on the OS 212 which is the higher-level program of the device driver 214 and the I / O library 213 is the period during which the FPGA 40 is executing reconfiguration. The availability of the O card 10 increases.

  The embodiment of the present invention has been described in detail above. However, the present invention is not limited to the specific embodiment, and various modifications and changes can be made within the scope of the gist of the present invention described in the claims. Is possible.

  In the embodiment described above, the information processing apparatus 100 includes one I / O card, but the information processing apparatus 100 may include a plurality of I / O cards. For example, as illustrated in FIG. 7, the information processing apparatus 100 includes I / O cards 10A to 10C, and the control apparatus 20 includes device drivers 214A to 214C that control the I / O cards 10A to 10C, respectively. Also good.

  Further, the number of input / output ports provided in the I / O card is not limited to two. For example, three input / output ports may be provided like the I / O card 10B of FIG. Further, as shown in FIG. 7, the control device 20 described above has I / O cards 10A and 10B that control a plurality of ports with a single FPGA, and an I / O that controls a single port with a single FPGA. It can also be used in an environment where cards 10C are mixed. Thereby, the availability of each I / O card can be increased even in information processing apparatuses having different configurations.

  In addition, the function which said control apparatus 20 has is realizable with the computer provided with CPU, ROM, RAM, etc. In that case, a program describing the processing contents of the functions that the control device 20 should have is provided. By executing the program on a computer, the above processing functions are realized on the computer. The program describing the processing contents can be recorded on a computer-readable recording medium.

  When the program is distributed, for example, it is sold in the form of a portable recording medium such as a DVD (Digital Versatile Disc) or a CD-ROM (Compact Disc Read Only Memory) on which the program is recorded. It is also possible to store the program in a storage device of a server computer and transfer the program from the server computer to another computer via a network.

  The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. Further, each time the program is transferred from the server computer, the computer can sequentially execute processing according to the received program.

10 ... I / O card 20 ... control devices 30A, 30B ... input / output port 40 ... FPGA
222: determination unit 223 ... setting unit 224 ... instruction unit 225 ... restarting unit

Claims (7)

In an input / output processing device comprising a plurality of input / output ports and a single programmable logic circuit for controlling the plurality of input / output ports, an error is detected from any one of the plurality of input / output ports. A determination unit for determining whether or not the detected error is a soft error in a circuit arrangement data memory included in the programmable logic circuit,
When the detected error is a soft error in the circuit arrangement data memory, a setting unit that sets the state of the other input / output port in which the error is not detected to a busy state;
An instruction unit that instructs the programmable logic circuit to reset circuit arrangement data after the setting unit sets the busy state;
A control device comprising:   The setting unit sets the state of the other input / output port to a busy state after the input / output processing is completed when the other input / output port is executing the input / output processing. The control device according to claim 1.   The setting unit sets a state of the input / output port in which the error is detected to a busy state when an error detection is detected from any one of the plurality of input / output ports. The control device according to claim 1 or 2.   The programmable logic circuit includes a restarting unit that cancels a busy state of the input / output port in which the error is detected and the other input / output port and restarts after the resetting of the circuit arrangement data. The control device according to any one of claims 1 to 3. An input / output processing device comprising a plurality of input / output ports and a single programmable logic circuit for controlling the plurality of input / output ports;
A control device according to any one of claims 1 to 4,
An information processing apparatus comprising: In an input / output processing device comprising a plurality of input / output ports and a single programmable logic circuit for controlling the plurality of input / output ports, an error is detected from any one of the plurality of input / output ports. A determination step of determining whether or not the detected error is a soft error in a circuit arrangement data memory included in the programmable logic circuit,
When the detected error is a soft error of the circuit arrangement data memory, a setting step for setting the state of the other input / output port where the error is not detected to a busy state;
After completing the setting of the busy state in the setting step, an instruction step for instructing the programmable logic circuit to reset the circuit arrangement data;
A control program for causing a computer to execute. In an input / output processing device comprising a plurality of input / output ports and a single programmable logic circuit for controlling the plurality of input / output ports, an error is detected from any one of the plurality of input / output ports. A determination step of determining whether or not the detected error is a soft error in a circuit arrangement data memory included in the programmable logic circuit,
When the detected error is a soft error of the circuit arrangement data memory, a setting step for setting the state of the other input / output port where the error is not detected to a busy state;
After completing the setting of the busy state in the setting step, an instruction step for instructing the programmable logic circuit to reset the circuit arrangement data;
A control method characterized by comprising:

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