JP2010079356A - Programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To handle a plurality of different types of input/output signals wuth number larger than the input/output number of an input/output circuit respectively without any increase in size of a programmable controller (PLC) nor increase in cost. <P>SOLUTION: In the PLC, the circuit constitution is configured so that a plurality of different types of input signals are inputted into the identical input point 10a of the input circuit 10, an FPGA 14 is arranged between the input circuit 10 and a CPU 16, and to the FPGA 14, the different types of input signals are inputted by time division from the input circuit 10, while in the FPGA 14, the different types of input signals given from the identical input point 10a of the input circuit 10 are processed by time division to be outputted to the CPU 16. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a programmable controller (PLC) that automatically controls various devices.

  The PLC is installed in a production facility, executes a sequence program, and performs sequence control of control devices such as various machines and devices in the production facility connected to the PLC. That is, the PLC inputs an input signal related to ON / OFF of an input device such as a switch or a sensor corresponding to a state to be controlled, executes a logical operation in accordance with a sequence program written in a ladder language, and the like. According to the obtained calculation result, the control target is controlled by outputting an output signal related to ON / OFF to an output device such as a relay, a valve, or an actuator.

  The PLC includes a CPU, a memory, an input circuit, and an output circuit for the above control. The CPU reads the input signal from the input circuit, executes a program, and performs a monitoring process during one scan time of about several tens of ms. And outputting an output signal from the output circuit.

  In the above, the PLC has a plurality of input circuits, and each input circuit has an input point (input pin). Since the above input signal is input to the input point of this input circuit and a PLC circuit including a CPU or the like is configured to process the input signal, other input signals such as a counter signal, an interrupt signal, etc. It cannot be entered and processed. On the other hand, increasing the number of input points so that other input signals such as counter signals and interrupt signals can also be input to the CPU increases the scale of the input circuit, leading to an increase in PLC size and cost. is there.

Patent documents related to the present invention will be described below.
JP 09-026807 A1

  The problem to be solved by the present invention is to increase the scale of the input circuit and output circuit, that is, without increasing the number of input points and output points, the number of input points and output points exceeds the number of input points and output points. It is also possible to handle different types of input signals and output signals.

  The PLC according to the present invention is a programmable controller comprising an input circuit for inputting an input signal of an input device and a CPU for processing the input signal in accordance with the sequence program, wherein the input circuit has a plurality of different types at the same input point. Input signals of different types from the input circuit are input to the FPGA interposed between the input circuit and the CPU by time division. In the FPGA, the above-described input signal is input to the FPGA. The circuit configuration is configured so that different types of input signals given from the same input point of the input circuit are processed in a time-sharing manner and output to the CPU.

  According to the present invention, a plurality of different types of input signals are time-divisionally input to the same input point of the input circuit, and the plurality of time-division input signals are input to the FPGA in a circuit configuration corresponding to each input signal. Since it is configured by division, the CPU can input the plurality of input signals from the FPGA, and the scale of the input circuit can be maintained as it is even if the types of input signals are increased. Increase in size and cost can be avoided.

  In the present invention, a preferred aspect further includes an output circuit that outputs an output signal to an output device, and the CPU outputs a plurality of output signals of different types to the FPGA according to a sequence program, while the FPGA is connected to the CPU. The circuit configuration is configured to output the output signal input from the output circuit to the same output point of the output circuit by time division.

  In this aspect, not only in the input circuit but also in the output circuit, the scale of the output circuit can be maintained as it is even if the number of types of output signals is increased, and the increase in the size and cost of the PLC is avoided. can do.

  According to the present invention, it is possible to handle a plurality of input and output signals having different types exceeding the number of input points and the number of output points of each of the input circuit and the output circuit without causing an increase in the size and cost of the PLC.

  Hereinafter, a PLC according to an embodiment of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a configuration of a PLC according to the embodiment, and FIG. 2 shows a time division configuration of an FPGA. First, in FIG. 1, 10 is an input circuit, 12 is an output circuit, 14 is an FPGA, 16 is a CPU, 18 is a program / work memory, 20 is a configuration memory, and 22 is a bus. The input circuit 10 has 16 input points 10a as an example. The output circuit 12 has 16 output points 12a as an example. These input circuit 10 and output circuit 12 are mounted on an I / O board 24 (not shown).

  Input signals of different types such as a sensor signal, a counter signal, and an interrupt signal are input to the input point 10a of the input circuit 10 in a time division manner. Each input signal requires the number of input points 10a for input.

  From the output point 12a of the output circuit 12, output signals of different types such as relay signals, valve signals, and actuator signals are output in a time-sharing manner. Each output signal requires the number of output points 12a for output.

  Therefore, a plurality of input signals cannot be simultaneously input to the input point 10a, and a plurality of output signals cannot be simultaneously output from the output point 12a. These input signals are time-division input to the input point 10a, and these output signals are time-division output to the output point 12a.

  The FPGA 14 is an SRAM type field programmable gate array. The FPGA 14 is a basic cell composed of LUTs (look-up tables) and flip-flops arranged vertically and horizontally, and the internal hardware logic can be changed by rewriting the LUT. Such an FPGA 14 can be configured into the block shown in FIG. 1 by freely configuring the connection between the internal logic block and the logic block by reading the circuit block information describing the logic block. .

  That is, the FPGA 14 is configured by the input / output circuits 14a and 14b and the logic circuit 14c between the input / output circuits 14a and 14b. As shown in FIG. 2, the logic circuit 14c has a sensor signal processing circuit 14c1 when a sensor signal is input, a counter signal processing circuit 14c2 when a counter signal is input, and a signal when an interrupt signal is input. The interrupt signal processing circuit 14c3 is time-shared configured.

  In the PLC according to the embodiment, the CPU 16 performs input processing of the various input signals and output processing of the various output signals according to a sequence program.

  The program / work memory 18 collectively shows various memories such as ROM and RAM used for program storage, data storage, and the like. The system / work memory 18 stores PLC system programs, sequence programs, and other programs. This memory can be used for

  The configuration memory 20 is composed of a flash memory or the like, and stores configuration data of the FPGA 14. The configuration data is data of a circuit configuration in which the FPGA 14 should be configured in a time division manner into the sensor signal processing circuit 14c1, the counter signal processing circuit 14c2, and the interrupt signal processing circuit 14c3. The FPGA 14 reads the data of the circuit configuration stored in the configuration memory 20 and is configured to the configuration of each circuit.

  In the above configuration, as shown in FIG. 2, the sensor signal is input to the input point 10a of the input circuit 10 at time tn, the counter signal is input to the input point 10a of the input circuit 10 at time tn + 1, and the interrupt signal is At tn + 2, the input point 10a of the input circuit 10 is input in a time division manner. In the FPGA 14, the sensor signal processing circuit 14 c 1 is configured at a time tn when the sensor signal is input. With this configuration, the sensor signal is input from the FPGA 14 to the CPU 16.

  Thereby, the CPU 16 can execute the sequence program. At time tn + 1 when the counter signal is input, the counter signal processing circuit 14c2 is configured. With this configuration, the counter signal is input from the FPGA 14 to the CPU 16. Thereby, the CPU 16 can execute the sequence program. At time tn + 2 when the interrupt signal is input, the interrupt signal processing circuit 14c3 is configured. With this configuration, the interrupt signal is input from the FPGA 14 to the CPU 16. Thereby, the CPU 16 can execute the sequence program.

  Further, output signals such as a relay signal, a valve signal, and an actuator signal from the CPU 16 are input to the FPGA 14 in a time division manner. In the FPGA 14, the relay signal processing circuit, the valve signal processing circuit, and the actuator signal processing circuit are respectively provided in a time division manner. With this configuration, a relay signal, a valve signal, and an actuator signal are output from the output point 12a of the output circuit 12 at different times.

  In the embodiment described above, a plurality of different types of input signals are time-divisionally input to the same input point 10a of the input circuit 10, and the plurality of time-division input signals correspond to the respective input signals in the FPGA 14. Since the circuit configuration is configured in a time-sharing manner, the CPU 16 can input the plurality of input signals in a time-sharing manner, and the scale of the input circuit 10 is maintained as it is even if the types of input signals increase. It is possible to avoid an increase in PLC size and cost. The same applies to the output circuit 12.

FIG. 1 is a diagram showing a configuration of a PLC according to an embodiment of the present invention. FIG. 2 is a diagram showing a time division configuration of the FPGA.

Explanation of symbols

10 input circuit 12 output circuit 14 FPGA
16 CPU

Claims (2)

In a programmable controller comprising an input circuit for inputting an input signal of an input device, and a CPU for processing the input signal according to the sequence program,
In the input circuit, a plurality of different types of input signals are input to the same input point in a time-sharing manner. On the other hand, an FPGA is interposed between the input circuit and the CPU. In the FPGA, the circuit configuration is configured so that different types of input signals given from the same input point of the input circuit are processed in a time division manner and output to the CPU. Programmable controller characterized by being configured to be installed. In addition, an output circuit that outputs the output signal to the output device
While the CPU outputs a plurality of different output signals to the FPGA according to the sequence program, the FPGA has a circuit configuration that outputs the output signal input from the CPU to the same output point of the output circuit in a time-sharing manner. The programmable controller according to claim 1, wherein the programmable controller is configured.

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