JP2003229760A - Device controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate ensuring the reliability of a device controller in of a large scale device and modifying/adding circuits in a mounting board. <P>SOLUTION: A device controller board 21 mounts a plurality of small-scale FPGAs 2111, 2112, 2113, each being functionally divided into a PCI bus control, a main memory control and a local bus control, respectively, so that logic data stored in configuration ROMs 2114, 2115, 2116 are loaded in the FPGA, when a power switch is set on. Each FPGA has a diagnosing circuit for diagnosing whether the loading has been exactly made. Circuits in the board can be changed or added easily by changing the logic data. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device controller for controlling a large-scale device as a whole, and more particularly to a device controller suitable for frequently changing internal circuits such as upgrades and parts revision.

[0002]

2. Description of the Related Art Manufacturing used in the field of semiconductor manufacturing
For large-scale devices such as inspection / evaluation devices and automatic analyzers used in the medical field, a method of configuring an in-device control system using a plurality of substrates having specific functions is well known. This is because if the function of the device is to be realized on one board, the board becomes too large and the processing becomes complicated. Therefore, by distributing the functions to a plurality of boards, maintenance and version upgrade of the device itself can be facilitated. ing.

This concept is general and standardized in the industry. Standards for configuring the board, for example, VME bus (Versa Module Europe: asynchronous bus of IEEE1014 standard), compact PCI bus, and the like are stored in the motherboard as a common bus. A backplane storage type system, which is a rack mounting form in which a plurality of slots connected in parallel to the common bus are provided and a board is inserted into each slot, is widely applied to an in-device control system.

In the control system in the apparatus using the board conforming to the standard such as VME bus, it is composed of a master module which is a board for managing the entire apparatus and a plurality of slave modules which are boards for realizing each function. To be done. VME
Since the master module manages the configuration and control of the bus and the like, the master module also grasps the function and configuration of the entire device. The master module is equipped with an MPU and controls the entire apparatus by an incorporated program, and is therefore called an apparatus controller or an embedded controller.

FIG. 10 shows a conventional example of a device controller. The device controller board 21 is supplied with operating power by connecting the connectors 2132 and 2133 of the VME bus to the backplane 20. The board 21 has a built-in MPU 2100 and operates according to a program incorporated in the main memory 2120. The front panel of the device controller board 21 has an Ethern
Communication I / F connectors such as et, USB, RS-232C, and DeviceNet are arranged. In order to control the dedicated chip of the communication I / F, the MPU 2100 and the dedicated chip are connected by the PCI bus 2102 and the local bus 2103.

In this way, the inside of the device is networked to reduce the number of I / O boards accommodated in the backplane,
A system for reducing the number of substrates to be stored has been applied.

On the other hand, FPGA (Fi
A technique using eld_Programmable_Gate_Array) is known. In Japanese Patent Laid-Open No. 2000-34652, since the FPGA can easily add / change the internal logic circuit,
It is described that emulation using an FPGA is performed before manufacturing I to correct a logic defect during development. Also, when emulating a large-scale LSI, emulation is performed using a plurality of FPGAs.

[0008]

As described above, the device controller controls the entire device and improves the processing capacity of the device and the operating rate of the device.
Higher performance and higher reliability are required.

Therefore, it is necessary to incorporate a circuit for realizing the RAS function such as an error correction function of the main memory to improve reliability. Furthermore, since the I / F of the PCI bus and local bus is also built in, in the controller board,
All circuits could not be placed in one substrate unless a circuit for system control was manufactured by a large-scale LSI (ASIC).

When it is realized by a plurality of boards, there are problems such as a large number of circuit signals shared by the boards and a large number of connection signals between the boards, which makes it difficult to realize it by a plurality of boards. For this reason, it is indispensable to incorporate a large-scale system control LSI in the controller board, but there are the following problems when the system control LSI is manufactured by ASIC. (1) It is not possible to deal with the abolition of main parts such as memory and the addition of new I / F. In addition, the system control LSI will have to be rebuilt every 3 to 5 years, including countermeasures such as MPU_I / F change accompanying the performance improvement of the MPU. Therefore, it is difficult to upgrade the LSI unless it is mass-produced.
Cannot recover the development cost of. (2) When a logic error in the internal circuit is discovered after development, a large amount of cost and time are required for remanufacturing, and therefore there is a large risk associated with LSI development.

In view of the above-mentioned problems of the prior art, an object of the present invention is to provide a plurality of Fs whose circuits can be easily added or modified.
By configuring a system control LSI using PGA, it is possible to reduce the development cost and provide a device controller that is easily remanufactured.

[0012]

The present invention, which achieves the above object, provides an apparatus controller, which is connected to a plurality of field devices of a large-scale apparatus by transmission lines and has a microprocessor to control the entire apparatus. A plurality of gate arrays (FPGA) of a method of configuring an internal logic circuit are mounted on a controller board, and the internal logic circuit is divided for each function and distributed and stored in the plurality of gate arrays. And

The divided functions of the internal logic circuit include, for example, a main memory memory control unit, a PCI bus control unit, and a local bus control unit.

Further, the internal logic circuit of the gate array is provided with a circuit for outputting a completion signal indicating that the configuration is completed, and means for monitoring whether or not the configuration of the gate array is completed within a specified time. When the configuration of the gate array is not completed within the specified time, the configuration is performed again.

Further, a circuit is provided for connecting the gate arrays with a plurality of signal lines and for performing mutual check between the gate arrays by using the signal lines after completion of the configuration of the gate arrays. .

In the above invention, the configuration data obtained by dividing the internal logic circuit for each function is the ROM connected to each gate array, or the ROM connected to one gate array and the shared memory shared with the MPU. It is stored in. Further, the configuration of the plurality of gate arrays is configured to be performed in parallel.

Further, according to the present invention, in a device controller which is connected to a plurality of field devices of a large-scale device by transmission lines and has a microprocessor to control the entire device, an internal logic circuit is provided in a device controller board. One main gate array and at least one sub-gate array of a configuration method are mounted, and the main gate array is divided into mains and means for loading the configuration data stored in the ROM into the main gate array. Means for loading at least one configuration data stored in a shared memory shared by the microprocessor and divided into sub-arrays into the sub-gate array, and dividing the internal logic circuit according to function to each gate array Characterized by storing in To.

In the mounted state, the shared memory is configured such that the data area of the sub configuration data can be read / written by the microprocessor.

Further, in the above invention, when a plurality of definable signal lines are connected between the gate arrays and the internal logic circuit divided for each function exceeds the capacity of one gate array, the excess amount is exceeded. Is stored in a specific area of another gate array, the signal line is defined, and the internal logic circuit can be stored across one gate array.

According to the present invention, it is possible to improve the maintainability by dividing the function of the system control LSI and mounting it on each gate array. Further, by dividing into a plurality of gate arrays, it is possible to use an inexpensive chip that can be mounted on a small logic scale.

Further, since the gate arrays are configured in parallel, the overall configuration time can be shortened and the device controller startup time can be shortened. This enables large capacity FPGA
It is possible to make up for the drawbacks of the above, and the drawbacks of being expensive and lengthening the configuration time.

The control circuit monitors the configuration state of each gate array, and when the configuration is not completed within a certain time, or when the configuration is mutually checked between the gate arrays, a configuration error is detected. If so, the configuration is performed again, so that the reliability of the gate array can be improved.

According to another aspect of the present invention, only one gate array uses the ROM for storing the configuration data. After the gate array is started up, the configuration of another gate array is executed by using the other configuration data in the shared memory (nonvolatile memory) storing the software of the MPU via the gate array. . As a result, the configuration of each gate array is performed in order, so that it is possible to avoid a temporary increase in the power consumption of the entire substrate when the power is turned on.

If the MPU cannot operate until the configuration of all gate arrays is completed,
The equipment controller startup time becomes longer. Therefore,
The gate array that starts up first manages the completion of the entire configuration, and the MPU monitors the state of the entire configuration and executes the diagnosis regarding the completed gate array. As a result, it is possible to provide a highly reliable device controller that uses a gate array and has a short startup time of the entire device controller.

Further, in the above invention, since the configuration data of the gate array can be stored in the shared memory accessible by the MPU, even after the controller board is mounted in the device, the logic circuit of the user can be stored in the gate array. It is possible to add / change to.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIGS. 7-9 show a schematic structure of a large-scale apparatus to which the present invention is applied and an arrangement of each device in the apparatus. The large-scale apparatus here is represented by a manufacturing apparatus and an inspection apparatus used in the field of semiconductor manufacturing, an analysis apparatus and an automation apparatus used in the field of physics and chemistry. The apparatus has a large number of I / Os, and transport control for performing processing such as manufacturing, inspection, and analysis, and control of sensors / actuators are performed.

FIG. 7 shows an example of the structure of a large scale device. A large number of field devices such as motors, valves, and sensors are distributed and arranged in the apparatus. The I / O module in the device controller 2 and the field device 1 are connected by a wire 5 ', and the device controller board 21 of the device controller 2 controls the field device 1 via the I / O module. Operator's console 3
Is connected to the device controller 2 and is operated by the operator.
The operation such as a start command for performing processing such as inspection and analysis is performed, and the progress status of each processing is displayed.

FIG. 8 shows another example of a large-scale apparatus. The apparatus controller board 21 in the apparatus controller 2 and a large number of field devices 1 are connected only by the in-apparatus network 5 to reduce wiring. .

The field device 1 sequentially performs bidirectional communication with the device controller 2 via a transmission line 5 as a digital signal and performs processing such as transmission of a detected physical quantity and reception of a control value. Each part is controlled.

A connection terminal 6 for connecting the in-apparatus network 5 and an external auxiliary device such as a personal computer.
Is also provided. Although illustration is omitted, one or a plurality of I / Os are connected to the field device 1 to perform I / O control and communication processing. For this reason, the device controller 2 has a configuration capable of being downsized and having a single function.

FIG. 9 is a block diagram of the inside of the rack of the in-machine control system using the VME bus. It comprises a VME bus compatible backplane 20, a device controller board 21, and a slave module. Slave module is RS-
An extended communication module 22 such as 232C, an I / O module 23 that performs a pulse motor control process, an I / O module 24 that performs a sensor / actuator control process, and the like.

The number of the device controller board 21 that can be installed in the rack is one, and the installation slot is designated. A plurality of I / O module boards 22-24, which are slave module boards, can be mounted according to the scale of the device, and an expansion slot is provided in the rack in consideration of future function expansion. ing. The operating power of these boards is supplied through a power supply line of + 5V or the like extending in the backplane 20.

The boards mounted inside the rack are connected via the VME bus mounted on the backplane 20 in the rack. Also, various I / O modules are V
The I / O control processing is performed according to the instruction from the device controller 21 connected via the ME bus. For this reason,
The field device is configured to be controlled by the MPU of the device controller board 21 via the I / O module.

FIG. 1 shows the internal structure of the device controller board. As described above, the device controller board 21
Connect the VMEbus connectors 2132 and 2133 to the backplane 20.
The operating power is supplied from the backplane 20 by connecting to the. High-performance MPU2100
Built in, and normally operates according to a program installed in the main memory 2120.

The front panel of the device controller board 21 is provided with an Ethern for connecting with a field device or the like.
Connectors for communication I / F such as et, USB, RS-232C, and DeviceNet are arranged. The Ethernet is connected to the console 3 and the host system, the USB is connected to an auxiliary storage device such as F / D, and the RS-232C is connected to a bar code reader and peripheral devices. Further, DeviceNet is connected to the field device 1 for use as an in-apparatus network.

The communication I / F is configured to communicate with an external device from a communication-dedicated controller via a communication-specific MAU (Medium_Attachment_Unit), and each controller chip is compatible with a PCI bus or a local bus. ing. Therefore, inside the device controller board 21, in addition to the MPU bus 2101 composed of the address bus, data bus, and control line of the MPU 2100, a PCI bus 2102 is provided.
And the local bus 2103 is laid out.

Further, since the backplane 20 is connected to the VME bus, the VME-PCI bus bridge 2130 is connected to the PCI bus 210.
It is configured to be connected to 2. When it is necessary to improve the processing performance of the VMEbus, VME-PCI bus bridge 21
The configuration in which 30 is directly connected to the MPU bus 2101 may be changed.

The main memory 2120 is a plurality of SDRAMs.
It is composed of (Synchronous_DRAM) and is used as a program for the MPU 2100 to execute and its work area. A data area for error correction of data that is read from and written to the main memory is also secured.

The non-volatile memory 2180 stores programs such as an apparatus control program, an apparatus controller board 21 diagnostic / maintenance program, and an initial loading program. It also stores and stores error information and maintenance information of the device controller board 21 and board-specific information such as the IP address of Ethernet. It is configured as a shared memory and uses FROM or FRAM, or battery-backed SRAM. ing.

The RTC 2190 is a clock having a calendar function, and the MPU 2100 reads out the information from the local bus 2103 and sets the RTC 2190.

The system control LSIs 2111, 2112, 2113 are
Small-scale, inexpensive FPGA (Field Pr
ogrammable Gate Array), and is divided by function. Each system control LSI is an SRAM type FPGA, and loads the logical data stored in the configuration ROMs 2114, 2115, and 2116 into the SRAM in the FPGA when the power is turned on.

FIG. 2 shows the detailed construction of the device controller by the system control LSI. Each system control LSI 211
Each of 1, 2112, and 2123 is composed of an FPGA.
ROMs 2114, 2115, 2116 installed externally when the power is turned on
The logical data stored in the configuration circuit
The logic circuit in the FPGA is loaded via 2201, 2202, 2203.

In this embodiment, three FPGAs constitute each system control LSI. The system control LSI 2111 has a PCI bus control unit 2204, the system control LSI 2112 has a main storage memory control unit 2205, and the system control LSI 2113 has a local bus control unit 2106, which are connected to the outside.

Each FPGA has a self-diagnosis circuit 22 for diagnosing whether the loading into the logic circuit has been performed correctly.
07, 2208, 2209 and mutual diagnostic circuits 2210, 2211, 2212 are incorporated. Configuration circuits 2201, 2202,
The configuration completion signal from 2203 and the preparation completion signals from the self-diagnosis circuit and the mutual diagnosis circuit are input to the control signal generation circuits 2213, 2214, 2215. And each F
A signal indicating whether or not the configuration has been normally made is output from the PGA to the control circuit 2104.

Self-diagnostic circuits 2207, 2208, 2209 are FPG
It has means for applying a pseudo input to the internal logic circuit in A and determining whether or not the internal logic is normally loaded by its output signal. Mutual diagnostic circuit 2210, 2211, 2212 is F
The PGA has means for judging whether the internal logic is normally loaded or not, based on the signal output to the outside.

The control circuit 2104 has a built-in timer,
A configuration error is output to the MPU2100 when the configuration is not completed within a certain period of time or when a configuration error signal is output from the FPGA. In this case, although not shown in the figure, the MPU 2100 transmits the corresponding FP via the control circuit 2104.
The operation of resetting the GA is performed, and the operation of configuring the FPGA again is performed.

In this embodiment, the three FPGAs simultaneously perform the configuration, but if temporary increase in power consumption poses a problem, they may be performed in order.

According to this embodiment, it is possible to manufacture an apparatus controller board which has an inexpensive circuit configuration and whose circuit can be easily added and changed. From this, there is also an effect that it becomes easy to cope with the revision and abolition of the parts in the device controller board 21 and to deal with the upgrade.

Further, in this embodiment, a plurality of small scale FPs are used.
Since the GAs simultaneously perform the configuration, the total configuration time can be shortened, and the start-up time of the entire device controller board 21 can be shortened as compared with the case where one large-scale FPGA is used.

In the present embodiment, the control circuit 2104 monitors the FPGA configuration time, and if the configuration is not completed within the specified time, the FP is restarted.
The control circuit 2104 is provided with a sequence for implementing the GA configuration. This ensures high reliability of the configuration, data transfer between FPGA and configuration ROM, and subsequent F
It is also possible to check the effect of noise error when writing to SRAM in PGA.

In this embodiment, each FPGA has a built-in logic circuit that outputs a signal indicating that the configuration is completed to the control circuit 2104. Note that the configuration retry sequence can be performed by the MPU 2100 instead of the control circuit 2104.

Further, in this embodiment, the FPGAs are connected by a plurality of signal lines, and after the configuration is completed, the FPGAs are
Each FPGA has a built-in sequence to perform mutual check with the signal of the logic circuit actually used. If an abnormality is found from the mutual check results, the configuration is performed again to further improve the reliability. As a result, it is possible to provide a system control LSI capable of ensuring high reliability of the FPGA configuration.

Next, the operation of this embodiment will be described. After the power is turned on, the device controller configures each FPGA. At this time, the self-diagnosis program built in the nonvolatile memory 2180 is monitored while being executed by the control circuit 2104. If there is no abnormality, the initial loading program is executed, and the device control program stored in the nonvolatile memory 2180 is loaded into the main memory 2120 and executed. The control program of the device is not stored in non-volatile memory, but Ethernet or US
It is also possible to load a program stored externally via B etc.

FIG. 3 is a process flow chart for monitoring the configuration operation of the FPGA. First, upon starting the configuration, each FPGA starts its own timer count (S101), monitors the configuration of the FPGA (S102), and determines whether all configuration completion signals have been input (S103). If there is no input, monitoring is continued until the timer count ends (S014). If the timer count has ended, an error is displayed, the relevant FPGA is reset (S105), and the configuration is performed again.

When a configuration completion signal is input from all FPGAs, FPGA mutual check is started (S106), the mutual check result is judged (s107), and if there is no error, a completion notice is issued (s108), Finish the configuration. If there is an error, the process starts over from step S105.

In this embodiment, each FPGA may be connected by a plurality of definable signal lines. According to this
When the capacity of the logic circuit that can be mounted on one FPGA is exceeded, another FPGA can be partially replaced, which is advantageous in that a small-scale and inexpensive FPGA can be adopted.

Next, another embodiment relating to the apparatus controller of the present invention will be described.

FIG. 4 is a block diagram of an apparatus controller according to another embodiment. In this example, the configuration is the same as that of FIG. 1 except the configuration related to the configuration of the system control LSI.

In FIG. 4, the configuration of the system control LSI 2113 is a configuration ROM.
This is a form in which the logical data of 2116 is loaded into the FPGA.
The system control LSIs 2111, 2112 are non-volatile memory 2180.
The logical data stored together with the above-mentioned program and information data is transmitted via the system control LSI 2113. The nonvolatile memory 2180 classifies and secures the logical data of the system control LSIs 2111 and 2112 for each memory address. As a result, the system control LSIs 2111, 2112
The configuration ROM of can be omitted.

Further, the MPU 2100 can access the non-volatile memory 2180 via the bus 2101. Therefore, the system control LSI 2111 stored in the nonvolatile memory 2180,
The logical data of 2112 can be changed in a board mounted state via a communication I / F such as Ethernet.

FIG. 5 shows the detailed structure of the system control LSI in the apparatus controller of FIG. System control LSI 2113 is the main FPGA, and system control L
SI2111 and 2112 are sub-FPGAs. Main FP
As in the case of FIG. 1, the GA performs configuration by loading the logical data stored in the ROM 2116. The sub-FPGA transfers the logic data of the FPGA stored in a specific area of the non-volatile memory 2180 to the data transfer circuit 22 of the main FPGA via the local bus 2130.
Loaded via 16.

A plurality of signal lines that can be arbitrarily defined are connected between the FPGAs. When the logic inside the FPGA becomes large and cannot fit in one FPGA, the logic for the excess capacity is loaded to the other FPGA connected by the signal line to define the signal line,
Functional division beyond the framework of FPGA is possible. It should be noted that each FPGA is provided with additional areas 2217 and 2218 for user logic circuits that can be used beyond the frame of the FPGA.

FIG. 6 shows a processing flow of the configuration operation of the device controller according to this embodiment.

When the configuration starts, the main FP
Release the reset of GA and start the timer count (S201). After that, the configuration of the main FPGA is monitored (S202) and repeated until the completion signal is input. If the timer count is over, main F
Displays the PGA configuration error (S2
05), repeat from S201 again.

When the configuration completion signal is input in S203, the configuration of the sub-FPGA is started (S206), and the same operation is performed as in the case of the main FPGA. When the configuration completion signals of all the other FPGAs are obtained in S208, F is the same as in the case of FIG.
The PGA mutual check sequence is started (S210), and if there is no error, a completion notice is output (S212).

According to this, since the FPGA configurations are controlled in sequence, it is possible to avoid a temporary increase in power consumption during configuration.

[0067]

According to the present invention, since the system control LSI of the device controller is composed of a plurality of FPGAs and has the function of checking the soundness of the divided internal logic, a high reliability of the device controller is ensured. There is an effect that can be done. Also, equipment controller upgrades, circuit changes,
This has the effect of making corrections easy.

Further, in the present invention, since the user logic circuit can be added in the FPGA, there is an effect that it can be customized by communication from the outside depending on the use of the device controller.

[Brief description of drawings]

FIG. 1 is a block diagram of an apparatus controller according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing details of a system control LSI according to the first embodiment.

FIG. 3 is a flowchart showing an FPGA configuration operation according to the first embodiment.

FIG. 4 is a block diagram of an apparatus controller according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing details of a system control LSI according to a second embodiment.

FIG. 6 is a flowchart showing an FPGA configuration operation according to the second embodiment.

FIG. 7 is a schematic structural diagram of a large-scale device to which the present invention is applied.

FIG. 8 is a schematic structural diagram of another large-scale device to which the present invention is applied.

FIG. 9 is a configuration diagram of a device controller inside a rack.

FIG. 10 is a block diagram of a conventional device controller.

[Explanation of symbols]

1 ... Field device, 2 ... Device controller, 3 ...
Operator's console, 5 ... Device network,
6 ... External connector, 20 ... Backplane, 21 ...
Device controller board, 2100 ... MPU, 2104 ... Control circuit, 2111 to 2113 ... System control LSI (FPGA), 21
14 to 2116 ... Configuration ROM, 2120 ... Main memory, 2180 ... Non-volatile memory, 2201 to 2203 ... Configuration circuit, 2204 ... RCI bus control circuit, 2205 ...
Main memory control circuit, 2206 ... Local bus control circuit, 2207 ~
2209 ... Self-diagnosis circuit, 2210-2212 ... Mutual diagnosis circuit, 2213
~ 2215 ... Control signal generation circuit, 2216 ... Data transfer circuit.

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Yuji Sugaya             882 Ichige, Ichima, Hitachinaka City, Ibaraki Prefecture             Ceremony company Hitachi High Technologies Design and manufacturing             Headquarters Naka Operations (72) Inventor Yoshiro Gunji             882 Ichige, Ichima, Hitachinaka City, Ibaraki Prefecture             Ceremony company Hitachi High Technologies Design and manufacturing             Headquarters Naka Operations (72) Inventor Takashi Seino             882 Ichige, Ichima, Hitachinaka City, Ibaraki Prefecture             Ceremony company Hitachi High Technologies Design and manufacturing             Headquarters Naka Operations F-term (reference) 5B076 EB02                 5H220 BB17 CC09 CX01 CX10 EE03                       EE07 EE10 FF01 HH04 JJ02                       JJ06 JJ16 JJ18 JJ29                 5J042 BA01 CA00 CA20 DA00 DA06

Claims (9)

[Claims] 1. A device controller for connecting a plurality of field devices of a large-scale device with a transmission line, and mounting a microprocessor to control the entire device, wherein an internal logic circuit is configured on a device controller board. An apparatus controller comprising a plurality of gate arrays, wherein the internal logic circuit is divided for each function and distributed and stored in the plurality of gate arrays. 2. The device controller according to claim 1, wherein the divided functions of the internal logic circuit include a control unit of a main memory, a control unit of a PCI bus, and a local bus control unit. 3. The circuit according to claim 1, which outputs a completion signal indicating that the configuration is completed to the internal logic circuit of the gate array,
A means for monitoring whether or not the configuration of the gate array is completed within a specified time is provided, and if the configuration of the gate array is not completed within the specified time, the configuration is performed again. Characterizing device controller. 4. The gate array according to claim 1, 2 or 3, wherein the gate arrays are connected by a plurality of signal lines, and after the configuration of the gate array is completed,
An apparatus controller comprising a circuit for performing mutual check between gate arrays using the signal line. 5. The apparatus controller according to claim 1, 2, 3, or 4, wherein the plurality of gate arrays are configured to be executed in parallel. 6. The configuration data according to claim 1, wherein the configuration data obtained by dividing the internal logic circuit for each function is ROM connected to each gate array or ROM connected to one gate array. The M
An apparatus controller characterized by being stored in a shared memory shared with a PU. 7. A device controller for connecting a plurality of field devices of a large-scale device with a transmission line and controlling a whole device by mounting a microprocessor, wherein an internal logic circuit is configured in a device controller board. One main gate array and at least one sub-gate array are mounted, and the main gate array is divided into main ROMs.
Means for loading the configuration data stored in the main gate array into the main gate array, and means for loading into the sub gate array at least one configuration data stored in a shared memory which is divided for the sub and shared with the microprocessor. And the internal logic circuit is divided for each function and stored in each gate array. 8. The device controller according to claim 7, wherein the shared memory is configured such that a data area of the sub configuration data can be read / written by the microprocessor in a mounted state. 9. The method according to claim 1, wherein a plurality of definable signal lines are connected between the gate arrays, and the internal logic circuit divided for each function exceeds the capacity of one gate array. An apparatus controller characterized in that the excess is stored in a specific area of another gate array, the signal line is defined, and the internal logic circuit can be stored across one gate array.