JP2012004584A - Circuit manufacturing method, annealing control method, and information recording medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent dopant from undesirably diffusing while relaxing stress in a silicon wafer, when spike-annealing the silicon wafer doped with the dopant.SOLUTION: The silicon wafer heated up to an annealing temperature is cooled at a high cooling rate initially and at a low cooling rate lastly. Since the cooling rate slows down in the middle of the cooling, stress in the silicon wafer is relaxed, and since the cooling rate is high to the halfway, thermal energy sufficient to cut a bond between the dopant and the silicon wafer does not act on the dopant in a lowered solid solubility, thereby the dopant does not undesirably diffuse because the bond between the dopant and the silicon wafer is not cut.

Description

  The present invention relates to a circuit manufacturing method and apparatus that activates impurities implanted into a silicon substrate by annealing, an annealing control method and apparatus that controls the operation of the circuit manufacturing apparatus, and a computer that controls the operation of the circuit manufacturing apparatus. The present invention relates to an information storage medium in which a program for executing the processing operation is stored as software.

  In recent years, MOS transistors used in logic circuits or the like suppress the occurrence of hot carriers and break by adding a lightly doped LDD (Lightly Doped Drain-Source) region inside a normal source / drain region. The decrease in down voltage was also prevented.

  However, in the current MOS transistor, the power supply voltage is also lowered, so the importance of the above object is lowered, and the impurity concentration in the LDD region is increased to reduce the resistance. This is called an extension region and is formed at a concentration lower than that of a normal source / drain region but higher than that of a conventional LDD region.

  A conventional example of the MOS transistor 10 having such a structure will be described below with reference to FIG. First, in a p-channel MOS transistor 10 illustrated as a conventional example, a gate insulating film 12 having a predetermined pattern and a p-type gate electrode 13 are sequentially stacked on the surface of an n-type region of a silicon substrate 11. Side walls 14 are formed on both sides of the gate insulating film 12 and the gate electrode 13.

  A pair of p-type source / drain regions 15 are formed on the surface layer of the silicon substrate 11 outside these sidewalls 14, and p-type source / drain regions 15 are formed on the surface layer of the silicon substrate 11 inside these source / drain regions 15. A pair of extension regions 16 of the mold are formed through one channel region 17.

  In the MOS transistor 10 having the above-described structure, since the extension region 16 is located inside the source / drain region 15, as in the conventional LDD structure, the generation of hot carriers and the decrease in breakdown voltage are prevented. And yet has a lower resistance than conventional LDD structures.

  In the above-described MOS transistor 10, for example, the gate insulating film 12 is formed of a thermal oxide film of the silicon substrate 11, and the source / drain region 15, the extension region 16, and the gate electrode 13 function as a p-channel. Is implanted with a p-type impurity such as boron.

  Here, a transistor manufacturing method for manufacturing such a MOS transistor 10 will be briefly described below. First, the surface of the silicon substrate 11 is heat-treated to form a thermal oxide film over the entire area, and the gate electrode 13 is formed in a predetermined pattern on the surface of the thermal oxide film.

  The thermal oxide film is removed from the surface of the silicon substrate 11 not masked by the gate electrode 13 by dry etching of the thermal oxide film using the gate electrode 13 as a mask, and as shown in FIG. A gate insulating film 12 is formed by a thermal oxide film remaining below the gate insulating film 12.

  Next, as shown in FIG. 6B, p-type impurities are lightly doped in the position of the extension region 16 on the surface layer of the silicon substrate 11 using the gate electrode 13 as a mask, and as shown in FIG. Sidewalls 14 are formed on both sides of the gate insulating film 12 and the gate electrode 13 on the surface of the silicon substrate 11 into which the impurities are ion-implanted.

  Next, as shown in FIG. 4D, p-type impurities are deeply doped at the positions of the source / drain regions 15 on the surface layer of the silicon substrate 11 using these sidewalls 14 as a mask, and thus the silicon substrate 11 The source / drain region 15 and the extension region 16 are formed by activating the impurities ion-implanted in the annealing process, and the p-channel MOS transistor 10 is completed as shown in FIG.

  As described above, the RTA (Rapid Thermal Anneal) method is generally employed as an annealing process for the silicon substrate 11 for forming the source / drain regions 15 and the extension regions 16 as described above. As shown in FIG. 8, in this RTA method, the silicon substrate 11 placed in an atmosphere of nitrogen or argon is heated up to an annealing temperature of about 1000 (° C.) at the maximum speed of the apparatus, and then the maximum speed to room temperature. Decrease the temperature.

  As described above, in the RTA method, the temperature rise and the temperature fall are executed at the maximum speed, and the spike annealing directly shifts from the temperature rise to the temperature drop. Therefore, unnecessary diffusion of impurities can be prevented, and the bonding with the silicon substrate 11 can be prevented. It is possible to form the extension region 16 having a shallow depth and an appropriate concentration.

  As shown in FIG. 9, the method for manufacturing the MOS transistor 10 having the above-described structure is as follows. First, a p-type impurity is deeply inserted into the source / drain region 15 of the silicon substrate 11 using the sidewall 14 as a mask. After doping and annealing, the sidewall 14 is removed, the gate electrode 13 is used as a mask, p-type impurities are lightly doped at the position of the extension region 16 of the silicon substrate 11, and the sidewall 14 is formed again and then annealed. There is also a method of executing the process again.

  In this case, since the first annealing process for activating the source / drain region 15 is not an RTA method but a normal long-time annealing process, defects due to ion implantation are recovered well. Nevertheless, since the second annealing process for activating the extension region 16 is performed by the RTA method, the junction of the extension region 16 can also be made shallow and have a low resistance.

  As described above, when the impurities in the extension region 16 are activated in the silicon substrate 11, the junction of the extension region 16 can be made shallow and low resistance by annealing the silicon substrate 11 by the RTA method. However, in the annealing process in which the temperature increase and the temperature decrease are performed at the maximum speed as described above, the stress acting on each part of the silicon substrate 11 and the like is excessive, and defects such as breakage and peeling may occur in each part. .

  In order to solve such a problem, as shown in FIG. 10, it is possible to lower the temperature drop. However, as shown in FIG. 5A, when the temperature of the silicon substrate 11 raised to the annealing temperature is lowered, the solid solubility of the ion-implanted impurity is also lowered. As described above, when the temperature lowering is slow, sufficient thermal energy acts on the silicon substrate 11 and the impurities.

  For this reason, if the temperature is lowered at a low speed, sufficient thermal energy acts on the impurities whose solid solubility has been lowered to break the bond between the silicon substrate 11 and the bond between the impurities and the silicon substrate 11 is broken. become. In this case, since the impurities in the extension region 16 are diffused unnecessarily, the depth of the junction with the silicon substrate 11 is increased and the resistance is also increased.

  For example, when the p-type extension region 16 of the p-channel MOS transistor 10 is formed as described above, the ion implantation acceleration voltage is currently reduced to about “0.5 (kV)”. The depth of is also as shallow as "40 (nm)". In this way, in the extension region 16 where the junction depth is extremely shallow, if the temperature drop is slow as described above, the junction depth changes significantly.

  The above-described problem also occurs in an n-channel MOS transistor (not shown) in which the extension region 16 is n-type, and a cover film (such as a silicon oxide film) is formed on the surface of the silicon substrate 11 to be annealed. It occurs in the same way whether or not (not shown) is present.

  The present invention has been made in view of the above-described problems. A circuit capable of reducing the junction between the source / drain region and the silicon substrate and reducing the resistance while reducing the stress caused by the temperature drop of the silicon substrate or the like. Manufacturing method and apparatus, annealing control method and apparatus for controlling operation of circuit manufacturing apparatus in this way, information storage medium in which a program for a computer for controlling operation of circuit manufacturing apparatus is stored as software The aim is to provide at least one.

  In the first, second, sixth, seventh and twelfth to fourteenth aspects of the invention, the temperature of the silicon substrate doped with impurities is raised to a predetermined annealing temperature, and the silicon substrate heated to this annealing temperature is first The temperature drops at a variable speed that is high and slow at the end. Accordingly, the temperature lowering rate of the silicon substrate is lowered from the middle so that the stress is relieved, and since the temperature lowering rate of the silicon substrate is high to the middle, sufficient heat is generated to break the bond between the silicon substrate and the impurities whose solid solubility is lowered. Energy does not work. For this reason, the bond between the impurity and the silicon substrate is not broken, and the impurity doped in the silicon substrate does not diffuse unnecessarily.

  According to the third and eighth aspects of the present invention, the silicon substrate is lowered from the annealing arrival temperature at a speed at which thermal energy for cutting the bond with the silicon substrate does not act on the impurities whose solid solubility is lowered due to the temperature drop. Therefore, even if the temperature of the silicon substrate raised to the annealing temperature decreases and the solid solubility of the doped impurity decreases, sufficient thermal energy acts on the impurity to break the bond with the silicon substrate. Therefore, the bond between the impurity and the silicon substrate is not broken.

  In the fourth and ninth aspects of the invention, after the temperature of the doped silicon substrate is raised to an annealing temperature of about 1000 (° C.), the temperature lowering rate is changed from high to low at about 900 (° C.). Switch. Therefore, even when the temperature of the silicon substrate raised to the annealing temperature of about 1000 (° C.) decreases and the solid solubility of the doped boron decreases, it is sufficient for cutting the bond between the boron and the silicon substrate. Thermal energy does not act, and the bond between boron and the silicon substrate is not broken.

  In the fifth and tenth aspects of the present invention, the temperature of the silicon substrate is first lowered at a high speed of 50 (° C./sec) or more and lowered at a low speed of 25 (° C./sec) or less from the middle. Therefore, the rate of temperature drop of the silicon substrate is sufficiently slow from the middle to relieve stress and the rate of temperature drop of the silicon substrate is sufficiently fast to the middle, so that boron doped in the silicon substrate is diffused unnecessarily. do not do.

  In the invention described in claim 11, the wafer temperature lowering means first cools the silicon substrate at the maximum speed. Accordingly, since the temperature drop rate of the silicon substrate becomes sufficiently high halfway, boron doped in the silicon substrate is not reliably diffused unnecessarily.

  It should be noted that the various means referred to in the present invention need only be formed so as to realize the function, for example, dedicated hardware for generating a predetermined function, a computer provided with a predetermined function by a program, a program Predetermined functions implemented in the computer, combinations thereof, etc. are allowed.

  Further, the maximum rate of temperature decrease in the invention described in claim 11 means the maximum rate of temperature decrease possible for the wafer temperature decreasing means. For example, in the case of a gas supply device in which the wafer temperature decreasing means supplies an annealing gas. The annealing gas supply rate is allowed to be maximized.

  In addition, the information storage medium referred to in the present invention may be hardware in which a program for causing a computer to execute various processes is stored in advance as software. For example, the information storage medium is fixed to an apparatus including a computer. ROM (Read Only Memory), HDD (Hard Disc Drive), CD (Compact Disc) -ROM, FD (Flexible Disc), and the like that are detachably loaded in an apparatus including a computer are allowed.

  The computer according to the present invention may be any device that can read a program composed of software and execute a corresponding processing operation. For example, a CPU (Central Processing Unit) is mainly used as a ROM or RAM (Random Access). A device to which various devices such as Memory) and I / F (Interface) are connected as necessary is allowed. It should be noted that having the computer execute various operations corresponding to software in the present invention allows the computer to control the operation of various devices.

  In the first, second, sixth, seventh and twelfth to fourteenth aspects of the invention, the temperature of the silicon substrate doped with impurities is raised to a predetermined annealing temperature, and the silicon substrate heated to this annealing temperature is first By lowering the temperature at a high speed and finally at a low speed, the temperature of the silicon substrate is lowered from the middle, so the stress of each part such as the silicon substrate and the layer film is alleviated to break or peel off. Since the rate of temperature drop of the silicon substrate is high halfway, unnecessary diffusion of impurities doped in the silicon substrate can be prevented, and the junction of the impurities with the silicon substrate is kept shallow and the resistance is reduced. Can be prevented.

  According to the third and eighth aspects of the present invention, the silicon substrate is lowered from the annealing arrival temperature at a speed at which the thermal energy for cutting the bond with the silicon substrate does not act on the impurity whose solid solubility is lowered due to the temperature drop. Since the bond between the impurity and the silicon substrate is not broken, unnecessary diffusion of the impurity doped in the silicon substrate can be prevented.

  In the fourth and ninth aspects of the invention, after the temperature of the doped silicon substrate is raised to an annealing temperature of about 1000 (° C.), the temperature lowering rate is changed from high to low at about 900 (° C.). By switching, unnecessary diffusion of boron can be prevented while relieving stress on the silicon substrate or the like with a simple operation.

  In the inventions according to claims 5 and 10, the temperature of the silicon substrate is lowered by first lowering the temperature of the silicon substrate at a high speed of 50 (° C./sec) or more and lowering the temperature at a low speed of 25 (° C./sec) or less from the middle. Since the speed of the substrate is sufficiently low from the middle, the stress of each part of the silicon substrate and layer film can be relieved well, and the rate of temperature drop of the silicon substrate is sufficiently high halfway, so unnecessary diffusion of boron Can be prevented well.

  In the invention described in claim 11, since the wafer temperature lowering means lowers the silicon substrate at the maximum speed at first, the temperature lowering speed of the silicon substrate becomes sufficiently high halfway. Unnecessary diffusion can be reliably prevented.

It is a characteristic view which shows the temperature change by the circuit manufacturing method of one Embodiment of this invention. It is a typical vertical front view which shows the whole structure of a circuit manufacturing apparatus. It is a block diagram which shows an annealing control apparatus. It is a flowchart which shows the circuit manufacturing method by a circuit manufacturing apparatus. (A) is a characteristic diagram showing the relationship between the solid solubility of the impurity and the temperature, and (b) is a characteristic diagram showing the relationship between the energy for cutting the bond between the silicon substrate and the impurity and the temperature. It is a typical vertical front view which shows the internal structure of a MOS transistor. It is process drawing which shows an example of the method of manufacturing a MOS transistor. It is a characteristic view which shows an example of the temperature change by the conventional circuit manufacturing method. It is process drawing which shows the other example of the method of manufacturing a MOS transistor. It is a characteristic view which shows the other example of the temperature change by the conventional circuit manufacturing method.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In all the drawings, the same reference numerals are given to the same components, and the description will be omitted as appropriate.

  An embodiment of the present invention will be described below with reference to FIGS. However, the same portions as those of the conventional example described above with respect to the present embodiment are denoted by the same names, and detailed description thereof is omitted. The circuit manufacturing apparatus 20 of the present embodiment includes an annealing apparatus main body 21 that is a main body and an annealing control apparatus 22 that is also an annealing control means, and these are connected to each other by a connection connector 23.

  The annealing apparatus main body 21 includes a holding table 201 that is a wafer holding means, and this holding table 201 is disposed inside a processing chamber 202 that is a heat insulating and airtight means. The holding table 201 holds the silicon substrate 11 in a replaceable manner, and the processing chamber 202 hermetically seals and thermally insulates the silicon substrate 11 held by the holding table 201 from the outside.

  Also in this silicon substrate 11, boron is ion-implanted as an impurity that becomes the p-type extension region 16 of the p-channel MOS transistor 10, and this boron has an acceleration voltage of “0.5 (kV)” and “40 (nm). ) "Ion implantation to depth".

  In the processing chamber 202, a pair of lamp units 203 corresponding to wafer temperature raising means are individually arranged above and below, and a gas unit 204 corresponding to wafer temperature lowering means is piped. The lamp unit 203 raises the temperature of the silicon substrate 11 held by the holding table 201 by illumination, and the gas unit 204 supplies an annealing gas made of nitrogen or argon to the position of the silicon substrate 11 held by the holding table 201. .

  The annealing control device 22 includes a so-called computer system, and includes a CPU 101 as hardware serving as a main body of the computer as shown in FIG. In the CPU 101, a ROM 103, a RAM 104, an HDD 105, and an FD 106 are interchangeably loaded via a bus line 102, a CD drive 109 in which a CD-ROM 108 is interchangeably loaded, a keyboard 110, and a mouse 111. , A display 112, a communication I / F 113, and the like are connected, and a connection connector 23 is connected to the communication I / F 113, and the lamp unit 203 of the annealing apparatus main body 21 is connected to the connection connector 23. A gas unit 204 is connected.

  In the circuit manufacturing apparatus 20 according to the present embodiment, hardware such as the ROM 103, the RAM 104, the HDD 105, the replaceable FD 106, the replaceable CD-ROM 108, and the like corresponds to an information storage medium, and at least one of them is the annealing control apparatus 22. Control programs and various data necessary for various operations are stored as software.

  For example, a control program that causes the CPU 101 to execute various processing operations is stored in advance in the FD 106 or the CD-ROM 108. Such software is installed in the HDD 105 in advance, and is copied to the RAM 104 and read by the CPU 101 when the annealing control device 22 is activated.

  As described above, when the CPU 101 reads an appropriate program and executes various corresponding processing operations, the annealing control device 22 of the present embodiment performs the operations of the lamp unit 203 and the gas unit 204 of the annealing device body 21. Integrated control.

  That is, when the temperature of the silicon substrate 11 is raised to a predetermined annealing temperature, the annealing control device 22 of this embodiment turns on the lamp unit 203 while supplying the annealing gas to the gas unit 204 at a low speed, and the silicon substrate 11 is turned on. 11 is lowered from the annealing temperature to room temperature, the lamp unit 203 is extinguished and the annealing gas is supplied to the gas unit 204 at high speed.

  However, when the temperature of the silicon substrate 11 is lowered by the gas supply of the gas unit 204 in this way, the annealing control device 22 acts on the impurities whose solid solubility is lowered due to the temperature drop by the thermal energy for cutting the bond with the silicon substrate 11. Change the rate of temperature drop so that it does not.

  More specifically, when the impurity ion-implanted into the silicon substrate 11 is boron, the annealing control device 22 turns on the lamp unit 203 while supplying the annealing gas to the gas unit 204 at a predetermined low speed when the temperature rises. The silicon substrate 11 is heated to an annealing temperature of 1000 (° C.).

  When the temperature of the silicon substrate 11 is increased to 1000 (° C.), the annealing control device 22 immediately shifts to a temperature lowering operation, turns off the lamp unit 203 and maximizes the gas supply of the gas unit 204. The silicon substrate 11 is cooled to 900 (° C.) at a high speed of 50 (° C./sec) or higher, and the gas supply by the gas unit 204 is adjusted when the temperature of the silicon substrate 11 reaches 900 (° C.). For example, the temperature is lowered to 25 (° C./sec) or lower.

  The control function of the annealing control device 22 as described above is realized by using various types of hardware as necessary. The main function corresponds to the software stored in the information storage medium such as the RAM 104, and the hardware of the computer. This is realized by the function of the CPU 101 as hardware.

  Such software, for example, raises the temperature of the silicon substrate 11 to the lamp unit 203 at a maximum speed to a predetermined annealing temperature, and then causes the gas unit 204 to lower the temperature at a variable speed that is initially high speed and low speed. Are stored in an information storage medium such as the RAM 104 as a control program for causing the CPU 101 or the like to execute processing operations.

  In the configuration as described above, the circuit manufacturing apparatus 20 of the present embodiment also performs an annealing process in order to activate the impurities ion-implanted into the silicon substrate 11. In that case, as shown in FIG. 2, the silicon substrate 11 into which impurities are ion-implanted is held on a holding table 201 inside the processing chamber 202, and the annealing control device 22 causes the lamp unit 203 and the gas unit 204 of the annealing device main body 21 to be held. And control the operation.

  Then, as shown in FIG. 1 and FIG. 4, the annealing control device 22 raises the temperature of the silicon substrate 11 to the predetermined annealing temperature by the lamp unit 203 at a maximum speed (step S1). Then, the temperature drop starts immediately (step S2).

  For this reason, the silicon substrate 11 is annealed as spike annealing by the RTA method. For example, when the ion-implanted impurity is boron, the silicon substrate 11 is heated to an annealing temperature of 1000 (° C.) by the lamp unit 203 and immediately thereafter, the temperature is decreased by the gas unit 204.

  However, in the circuit manufacturing method using the circuit manufacturing apparatus 20 according to the present embodiment, the gas supply by the gas unit 204 is first fully opened and the silicon substrate 11 is cooled at a high speed of 50 (° C./sec) or more (step) S3) When the temperature of the silicon substrate 11 reaches 900 (° C.) (step S4), the gas supply by the gas unit 204 is adjusted, and the temperature is lowered to 25 (° C./sec) or less (step S5).

  In the circuit manufacturing method using the circuit manufacturing apparatus 20 according to the present embodiment, the temperature decreasing rate of the silicon substrate 11 is lowered from the middle as described above, so that the stress is alleviated to prevent breakage or peeling of each part. Can do. Nevertheless, since the temperature lowering speed of the silicon substrate 11 is high halfway, the thermal energy sufficient for cutting the bond with the silicon substrate 11 does not act on the impurity whose solid solubility is lowered.

  For this reason, the bond between the impurity and the silicon substrate 11 is not broken, and the impurity ion-implanted into the silicon substrate 11 does not diffuse unnecessarily, so that the junction of the impurity with the silicon substrate 11 is kept shallow and the resistance is reduced. Can be prevented.

  Here, the mechanism of temperature drop of the circuit manufacturing method by the circuit manufacturing apparatus 20 of the present embodiment will be briefly described below. As shown in FIG. 5A, when the temperature of the silicon substrate 11 that has been raised to the annealing temperature decreases, the solid solubility of the ion-implanted impurity also decreases, so that the bond between the impurity and the silicon substrate 11 is reduced. It becomes easy to be cut.

  However, sufficient thermal energy is required to break the bond between the impurity and the silicon substrate 11, and this thermal energy inevitably increases as the temperature of the silicon substrate 11 increases as shown in FIG. growing. That is, the bond between the impurity and the silicon substrate 11 is easily cut at a lower temperature from the viewpoint of solid solubility, and is easily cut at a higher temperature from the viewpoint of thermal energy.

  When the present inventor actually investigated, when boron was ion-implanted to the depth of “40 (nm)” with the acceleration voltage of “0.5 (kV)” in the silicon substrate 11 as described above, the silicon substrate 11 The necessary time for breaking the bond between boron and boron is about 0.5 (min) at 900 (° C), about 5.0 (min) at 800 (° C), and about 60 (min) at 700 (° C). there were.

  Therefore, when the time for lowering the temperature of the silicon substrate 11 from 1000 (° C.) to 900 (° C.) is 0.5 (min) or more, the bond between the silicon substrate 11 and boron is broken, Even if the time for cooling to 800 (° C.) is 5.0 (min) or longer or the time for cooling to 700 (° C.) is 60 (min) or longer, the bond between the silicon substrate 11 and boron is broken. .

  In other words, if the time for lowering the temperature of the silicon substrate 11 from 1000 (° C.) to 900 (° C.) is sufficiently shorter than 0.5 (min), the bond between the silicon substrate 11 and boron is prevented from being broken. Similarly, the time for lowering the temperature to 800/700 (° C.) should be sufficiently shorter than 5.0 / 60 (min).

  When attention is paid to the relationship between this temperature and time, the allowable time increases rapidly as the temperature decreases, so that the temperature drop of the silicon substrate 11 raised to the annealing temperature is high at high temperatures. It is necessary, but at low temperatures it can be slow.

  Therefore, if the rate of change in the temperature decrease rate is made as low as possible within the range in which thermal energy for cutting the bond with the silicon substrate 11 does not act on the impurities whose solid solubility has decreased due to the temperature decrease, the silicon substrate 11 Impurities that are ion-implanted into the substrate are not diffused unnecessarily, and stress on the silicon substrate 11 or the like can be minimized. However, when the temperature of the silicon substrate 11 is lowered from a high temperature of 1000 (° C.) to room temperature, it is actually difficult to accurately change the speed steplessly corresponding to the temperature.

  Therefore, in the circuit manufacturing method using the circuit manufacturing apparatus 20 according to the present embodiment, when the impurity is boron, first, the gas supply by the gas unit 204 is fully opened, the temperature drop is set to a maximum speed of 50 (° C./sec) or more, and the silicon substrate When the temperature of 11 is lowered to 900 (° C.), the temperature is lowered to a low speed of 25 (° C./sec) or less. With this, the rate of change in the temperature drop rate can be set to a proper state by a simple operation, so that the stress on the silicon substrate 11 and the like can be reduced while the junction with the impurity silicon substrate 11 is shallow and has low resistance. Can do.

  In addition, this invention is not limited to the said form, A various deformation | transformation is accept | permitted in the range which does not deviate from the summary. For example, in the above embodiment, it is assumed that the temperature drop rate is switched by detecting that the temperature of the silicon substrate 11 has decreased from 1000 (° C.) to 900 (° C.), but the temperature drop rate switching is controlled based on time. It is also possible. In addition, although the example in which the supply rate of the annealing gas by the gas unit 204 is adjusted when the temperature decrease rate is changed to a low speed is exemplified, it is possible to make the lamp unit 203 weakly lit.

  Furthermore, in the above embodiment, the same annealing gas is supplied when the temperature of the silicon substrate 11 is raised and lowered. However, the annealing gas can be switched between when the temperature is raised and when the temperature is lowered. For example, when the temperature of the silicon substrate 11 is raised, if a first annealing gas that does not react with the silicon substrate 11 such as argon is supplied, an unnecessary reaction such as nitriding can be prevented from occurring in the silicon substrate 11 that is raised in temperature. it can.

  On the other hand, when the temperature of the silicon substrate 11 is lowered, if the second annealing gas having a high thermal conductivity such as nitrogen is supplied, the temperature of the silicon substrate 11 can be lowered quickly. Unnecessary diffusion can be prevented.

  In the above embodiment, the p-type regions 15 and 16 of the p-channel MOS transistor 10 are activated by annealing, but the annealing of the present invention activates the n-type region of the n-channel MOS transistor. The p-type region and the n-type region of a CMOS (Complementary MOS) transistor can be activated at the same time, and any silicon substrate into which impurities are ion-implanted can be used for various circuits. .

  Further, in the above embodiment, it is assumed that a cover film (not shown) such as a silicon oxide film is not present on the surface of the silicon substrate 11 to be annealed. However, this may be present, and oxygen is present in the atmosphere of the annealing process. May exist.

  In the above embodiment, the CPU 101 operates according to a control program stored as software in the RAM 104 or the like, and various means are logically realized as various functions of the annealing control device 22. However, each of these various means can be formed as unique hardware, and a part can be stored in the RAM 104 or the like as software and a part can be formed as hardware.

  In the above embodiment, it is assumed that software installed in advance in the HDD 105 from the CD-ROM 108 or the like is copied to the RAM 104 when the annealing control device 22 is started, and the CPU 101 reads the software stored in the RAM 104 in this way. Such software can be used by the CPU 101 while being stored in the HDD 105, or can be fixedly stored in the ROM 103 in advance.

  Furthermore, it is possible to store software in the FD 106 or CD-ROM 108, which is an information storage medium that can be handled alone, and install the software from the FD 106 or the like into the HDD 105 or RAM 104. However, such installation is executed. Alternatively, the CPU 101 can directly read the software from the FD 106 or the like and execute the processing operation.

  That is, when various means of the annealing control device 22 of the present invention are realized by software, the software only needs to be in a state where the CPU 101 can read and execute a corresponding operation. In addition, the control program for realizing the various means as described above can be formed by a combination of a plurality of software. In this case, the information storage medium as a single product has an annealing control device 22 of the present invention. It is sufficient to store only the minimum necessary software for realizing the above.

  For example, in the case where application software is provided to an annealing control device 22 in which an existing operating system is installed using an information storage medium such as a CD-ROM 108, software for realizing various means of the annealing control device 22 of the present invention is as follows. Since it is realized by a combination of application software and an operating system, the software depending on the operating system can be omitted from the application software on the information storage medium.

  Further, the method of supplying the software described in the information storage medium to the CPU 101 in this way is not limited to loading the information storage medium directly into the annealing control device 22. For example, it is possible to store the above-described software in an information storage medium of a host computer, connect the host computer to a terminal computer via a communication network, and supply the software from the host computer to the terminal computer by data communication. is there.

  In the above case, it is possible for the terminal computer to execute a stand-alone processing operation with the software downloaded to its own information storage medium, but it is possible to perform real-time data communication with the host computer without downloading the software. It is also possible to execute processing operations. In this case, the entire system in which the host computer and the terminal computer are connected by a communication network corresponds to the annealing control device 22 of the present invention.

DESCRIPTION OF SYMBOLS 11 Silicon substrate 20 Circuit manufacturing apparatus 21 The annealing apparatus main body 22 which is the main body of a circuit manufacturing apparatus 22 Annealing control apparatus 101 which is also an annealing control means CPU which is the main body of a computer
103 ROM as an information storage medium
104 RAM as an information storage medium
105 HDD as an information storage medium
106 FD, an information storage medium
108 CD-ROM as information storage medium
201 Holding table 203 as wafer holding means Lamp unit 204 corresponding to wafer heating means Gas unit corresponding to wafer cooling means

Claims (14)

  A circuit manufacturing method for activating an impurity doped in a silicon substrate by annealing, wherein the silicon substrate is heated to a predetermined annealing temperature, and the silicon substrate heated to the annealing temperature is initially fast Finally, a circuit manufacturing method that lowers the temperature at a variable speed, which is a low speed.   A method for manufacturing a circuit, comprising: activating impurities doped in a silicon substrate by annealing to form a pair of lightly doped shallow regions inside a deeply doped source / drain region of a MOS (Metal Oxide Semiconductor) transistor; The temperature of the silicon substrate is raised to a predetermined annealing temperature, and the temperature of the silicon substrate, which has been raised to the annealing temperature, is lowered at a variable speed, which is high speed first and low speed at the end. Circuit manufacturing method to be formed.   The speed at which the temperature of the silicon substrate is lowered from the annealing temperature is set to a speed at which thermal energy for cutting the bond with the silicon substrate does not act on the impurities whose solid solubility has decreased due to a temperature decrease. Circuit manufacturing method.   2. When the impurity doped in the silicon substrate is boron, the temperature of the silicon substrate is raised to an annealing temperature of about 1000 (° C.) and then the temperature lowering rate is switched from high speed to low speed at about 900 (° C.). The circuit manufacturing method as described in any one of thru | or 3.   The circuit manufacturing method according to claim 4, wherein the temperature of the silicon substrate is first lowered at a high speed of 50 (° C./sec) or more and lowered at a low speed of 25 (° C./sec) or less from the middle.   A circuit manufacturing apparatus for activating an impurity doped in a silicon substrate by annealing, a wafer holding means for holding the silicon substrate in a replaceable manner, and raising the temperature of the silicon substrate held by the wafer holding means Wafer temperature raising means, wafer temperature lowering means for lowering the silicon substrate held by the wafer holding means, and the wafer temperature lowering means after raising the silicon substrate to a predetermined annealing temperature by the wafer temperature raising means And an annealing control means for lowering the temperature at a variable speed that is initially high speed and finally low speed.   A circuit manufacturing apparatus that activates impurities doped in a silicon substrate by annealing to form a pair of lightly doped shallow regions inside a deeply doped source / drain region of a MOS transistor, wherein the silicon substrate is replaceable A wafer holding means for holding the wafer, a wafer temperature raising means for raising the temperature of the silicon substrate held by the wafer holding means, a wafer temperature lowering means for lowering the temperature of the silicon substrate held by the wafer holding means, and the silicon An annealing control means for causing the wafer temperature raising means to raise the temperature of the substrate to a predetermined annealing arrival temperature, and then causing the wafer temperature lowering means to lower the temperature at a variable speed that is initially high speed and finally low speed. Manufacturing equipment.   The annealing control means has a rate at which the temperature of the silicon substrate is lowered from the annealing arrival temperature to the wafer temperature lowering means, and thermal energy that breaks the bond with the silicon substrate does not act on the impurities whose solid solubility has been lowered due to the temperature drop. The circuit manufacturing apparatus according to claim 6, wherein the circuit manufacturing apparatus is a speed.   When the impurity doped into the silicon substrate is boron, the annealing control means raises the temperature of the silicon substrate to an annealing temperature of about 1000 (° C.) by the wafer temperature raising means, and then the wafer temperature lowering means The circuit manufacturing apparatus according to any one of claims 6 to 8, wherein the temperature lowering rate is switched from a high speed to a low speed at about 900 (° C).   10. The annealing control unit according to claim 9, wherein the annealing control unit lowers the temperature of the silicon substrate at a high speed of 50 (° C./sec) or more at first and then lowers the temperature at a low speed of 25 (° C./sec) or less from the middle. Circuit manufacturing equipment.   11. The circuit manufacturing apparatus according to claim 6, wherein the annealing control unit lowers the temperature of the silicon substrate to the wafer cooling unit at a maximum speed at first.   An annealing control method for controlling an operation of a circuit manufacturing apparatus for activating an impurity by an annealing process in which a silicon substrate doped with impurities is heated by a wafer temperature raising means and then lowered by a wafer temperature lowering means. An annealing control method in which the temperature of the substrate is raised to a predetermined annealing temperature by the wafer temperature raising means, and then the temperature is lowered at a variable speed, which is initially high speed and finally low speed.   An annealing control device for controlling an operation of a circuit manufacturing apparatus that activates the impurity by annealing treatment in which a silicon substrate doped with impurities is heated by a wafer temperature raising means and then lowered by a wafer temperature lowering means. An annealing control device that raises the temperature of a substrate to a predetermined annealing temperature by the wafer temperature raising means and then lowers the temperature at a variable speed that is initially high speed and finally low speed.   Stores computer-readable software that controls the operation of the circuit manufacturing apparatus that activates the impurity by annealing that raises the temperature of the silicon substrate doped with impurities by the wafer temperature raising means and then lowers the temperature by the wafer temperature lowering means. The temperature of the silicon substrate is raised to a predetermined annealing arrival temperature by the wafer temperature raising means, and then the temperature of the wafer is lowered at a variable speed that is initially high speed and low speed. An information storage medium storing a program for causing the computer to execute the above.

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