JP2011530246A - Adaptive vise current generation for switched capacitor circuits. - Google Patents

Abstract

  Techniques for adaptively generating a bias current for a switched capacitor circuit are disclosed. A switched capacitor circuit is an ADC that charges and discharges at least one capacitor at a sampling rate, digitizes an analog signal at the sampling rate, and provides a digital signal. The switching capacitor circuit supports multiple modes associated with different sampling rates. The bias circuit provides a bandwidth proportional to the sampling rate for the OTA in the switched capacitor circuit and tracks selected changes in the switching capacitor due to IC process and temperature variations. A bias current proportional to the sampling rate is generated for the switching capacitor circuit. The settling time of a switching capacitor circuit uses multiple modes to track the full range of variations in IC process and temperature.

Description

  The present disclosure relates generally to electronics, and more particularly to techniques for adaptive vise current generation for switched capacitor circuits.

  A switched capacitor circuit is a circuit for transferring charge between different sampling circuits to achieve a desired signal processing function. Switched capacitor circuits can perform signal processing functions accurately based on two things, the ratio of capacitor size (instead of absolute capacitor size) and sampling rate, which can often be obtained with high accuracy. it can. Switched capacitor circuits are used to implement various circuit blocks such as sigma-delta analog-to-digital converters (ΣΔ ADCs), sigma-delta digital-to-analog converters (ΣΔ DACs), filters, decimators, etc. Widely used.

  Switched capacitor circuits include active circuits, such as an operational transconductance amplifier (OTA) that helps to transfer charge between sampling circuits. Active circuits can be biased with excessive current to provide satisfactory performance under worst-case conditions. This in turn results in the active circuit being almost always biased, which would be undesirable.

  Techniques for adaptive vise current generation for switched capacitor circuits to reduce power consumption and achieve desired performance are described herein. In one design, the device includes a switched capacitor and a bias circuit. The switched capacitor includes (i) at least one switching capacitor that charges and discharges at a sampling rate, and (ii) an amplifier such as an operational transconductance amplifier (OTA) having a bandwidth proportional to the bias current. The bias circuit (i) obtains a bandwidth proportional to the sampling rate for the amplifier and (ii) changes in the switched capacitor due to variations in integrated circuit (IC) process and temperature. To track, generate a bias current for the switched capacitor circuit.

  In one design, the switched capacitor circuit comprises a ΣΔ ADC that digitizes an analog signal at a sampling rate and provides digital samples. The ΣΔ ADC may support multiple modes associated with different sampling rates. One mode may be selected from among supported modes. The bias circuit then generates a bias current that should be proportional to the sampling rate for the selected mode. The settling time of the switched capacitor circuit can be tracked using the multimode and across IC processes and temperature variations. In other designs, the switched capacitor circuit may include filters, decimators, and some other circuits.

  In one design, the bias circuit includes a switched capacitor load, a driver circuit, and a current mirror. In one design, the switched capacitor load is (i) a first capacitor that discharges based on a first control signal and charges based on a second control signal; (ii) the second capacitor A second capacitor that discharges based on the control signal and charges based on the first control signal; and (iii) filters a charging current for the first and second capacitors A third capacitor. The bias current may be proportional to the first and second capacitors, which may track the switching capacitor in the switched capacitor via IC process and temperature variations. The driver circuit provides the charging current to the first and second capacitors in the switching capacitor load. The current mirror receives the charging current and provides the bias current.

  The disclosure of various aspects and features is described in detail below.

FIG. 1 shows a block diagram of a wireless communication device. FIG. 2 shows a block diagram of a second order ΣΔ ADC. FIG. 3 shows a schematic diagram of the integrator in the ΣΔ ADC. FIG. 4 shows a schematic diagram of the OTA. FIG. 5 shows a schematic diagram of the bias circuit. FIG. 6 shows a block diagram of a circuit for generating a control signal for the bias circuit. FIG. 7 shows a timing diagram of the control signal. FIG. 8 shows a process for adaptively generating a bias current for a switched capacitor circuit.

  The technique described here can be used for switched capacitor circuits used in various circuit blocks such as ΣΔ ADC, ΣΔ DAC, filters, and decimaters. The technology can also be used for a variety of applications such as wireless communications, computing, networking, consumer electronics and the like. The technology can also be used in various devices such as wireless communication devices, cellular phones, personal digital assistants (PDAs), handheld devices, wireless modems, laptop computers, cordless phones, and the like. For clarity, the use of the technique in wireless communications, which is also possible with a cellular phone or some other device, is described below.

  FIG. 1 shows a block diagram of a design of a wireless communication device 100. For simplicity, only the receiver portion is shown in FIG. Similarly, FIG. 1 shows only one receive chain portion for one antenna. In general, a wireless device may include any number of receive chains for any number of antennas, any number of frequency bands, and any number of radio technologies.

  Antenna 110 receives radio frequency (RF) modulated signals transmitted by the base station and provides received RF signals. A low noise amplifier (LNA) 112 amplifies the received RF signal and provides an amplified RF signal. Filter 114 filters the amplified RF signal to pass signal components in the critical frequency band and remove out-of-band noise and unwanted signals. Downconverter 116 frequency downconverts the filtered RF signal using a local oscillator (LO) signal and provides a downconverted signal. The frequency of the LO signal is selected so that the desired signal in the selected frequency channel is downconverted to the verse band or near baseband.

An amplifier (AMP) 118 amplifies the downconverted signal and provides a signal having a desired signal level. The low pass filter 120 filters the signal from the amplifier 118 to pass the desired signal in the selected frequency channel and remove noise and unwanted signals that may be generated by the downconversion process.

  The ΣΔ ADC 130 digitizes the analog signal from the low-pass filter 120 based on the sampling clock SCLK. The ΣΔ ADC 130 offers certain advantages such as better linearity, improved quantization noise characteristics, and easier implementation on other types of ADCs. The ΣΔ ADC 130 performs analog-to-digital conversion of the analog signal by continuously obtaining a 1-bit approximate value of the change in the amplitude of the analog signal at a sampling rate many times larger than the desired signal band. The digital sample contains the desired signal and quantization noise. The ΣΔ ADC 130 may be designed so that quantization noise is driven out of band (or noise shaped) so that it is more easily filtered.

  The bias circuit 140 generates a bias current for the ΣΔ ADC 130 as will be described below. The ΣΔ ADC 130 and the bias circuit 140 can be implemented on an analog IC, RFIC (RFIC), mixed signal IC, application specific integrated circuit (ASIC), or the like.

  Data processor 150 may include various units for processing digital samples from ΣΔ ADC 130. For example, the data processor 150 may include one or more digital signal processors (DSPs), reduced instruction set computer (RISC) processors, central processing units (CPUs), and the like. The controller / processor 160 can control the operation of the wireless device 100. As shown in FIG. 1, the controller / processor 160 can generate a sampling clock for the ΣΔ ADC 130 and a control signal for the bias circuit. The sampling clock and control signal may also be generated by some other unit within the wireless device 100. Memory 162 may include program code and data for wireless device 100.

  FIG. 1 shows a receiver design implemented using a direct conversion architecture, also referred to as a zero IF (ZIF) architecture. In the direct conversion architecture, the RF signal is frequency down-converted directly from RF to baseband in one stage. The receiver may also frequency downconvert the RF signal in multiple stages, for example, from one stage to RF to intermediate frequency (IF) and then to another stage to IF to baseband. It may be implemented using a superheterodyne architecture. Superheterodyne and direct conversion architectures may use different circuit blocks and / or have different requirements.

  FIG. 1 shows a specific receiver design using a ΣΔ ADC. The receiver can also include different and / or additional circuit blocks not shown. For example, the ΣΔ ADC 130 can be replaced with a regulator ADC, and the low-pass filter 120 can be replaced with a switched capacitor filter. In general, a receiver can include any number of switched capacitor filters for any number of circuit blocks. For simplicity, much of the following description assumes that the ΣΔ ADC 130 is the only switched capacitor circuit in the wireless device 100.

  The wireless device 100 may support one or more wireless technologies such as wireless communication, terrestrial broadcasting, satellite communication, and so on. For example, the wireless device 100 can support one or more of the following wireless technologies.

• Global System for Mobile Communications (GSM®), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE) and / or an organization named “3rd Generation Partnership Project” (3GPP ),
• CDMA2000 1X (or simply 1X), CDMA2000 1xEV-DO (or simply 1xEV-DO), Ultra Mobile Broadband (UMB) and / or “3rd Generation Partnership Project 2” (3GPP2) engine (2GPP) Other wireless technology, from
IEEE 802.11 (Wi-Fi), IEEE 802.16 (WiMAX), IEEE 802.20 and / or other radio technologies from IEEE,
・ Digital Video Broadcasting for Handhelds (DVB-H), Integrated Services Digital Broadcasting for Terrestrial Television Broadcasting (ISDB-T)
• United States Global Positioning System (GPS), European Galileo, Russian GLONASS, or Global Navigation Satellite System (GNSS).

  The wireless device 100 may support multiple modes of operation for one or more wireless technologies. Each mode can be a specific signal bandwidth in a specific wireless technology. LTE and UMB support variable signal bandwidth, and multimode can be defined as different possible signal bandwidths in LTE and UMB. The ΣΔ ADC 130 and other switched capacitor circuits in the wireless device 100 can be designed to handle all modes supported by the wireless device 100.

  The ΣΔ ADC 130 can be implemented in a variety of designs such as a single loop ΣΔ ADC, MASH ΣΔ ADC. The ΣΔ ADC 130 can also be implemented in any order, such as a primary order, a secondary order, or a higher order. In general, higher orders can provide higher performance at the expense of circuit complexity.

  FIG. 2 shows a block diagram of a second order ΣΔ ADC 130, which is one design of ΣΔ ADC 130 of FIG. The ΣΔ ADC 130 includes two sections 210 a and 210 b coupled in series to a quantizer 230 and a 1-bit DAC 232.

Within section 210a, adder 212a subtracts the quantized signal output from DAC 232 from the analog signal. The output of summer 212a is integrated by integrator 220a and amplified by amplifier 222a with a gain of K ₁ to obtain the output of section 210a. Within section 210b, adder 212b subtracts the quantized signal from the output of section 210a. The output of summer 212b is integrated by integrator 220b and amplified by amplifier 222b with a gain of K ₂ to obtain the output of section 210b. The quantizer 230 compares the output of section 210b against a reference voltage and provides 1-bit digital samples based on the comparison result. The DAC 232 changes the digital samples to analog and provides a quantized signal.

  Integrators 220a and 220b can be implemented in various switched capacitor circuit designs such as single sampling switched capacitor circuits, correlated double sampling (CDS) circuits, auto-zeroing (AZ) circuits, chopper stabilization (CS) circuits, etc. Can be implemented. Switched capacitor circuits use one or more amplifiers, capacitors and switches, all of which are easily assembled with complementary metal oxide semiconductors (CMOS).

  FIG. 3 shows a schematic diagram of an integrator 220x design in which a single sampling switched capacitor circuit is used. The integrator 220x can be used for each of the integrators 220a and 220b in FIG. Within integrator 220x, switch 312 has one end that receives input signal Vin and the other end coupled to node X. Capacitor 316 is coupled between node X and node Y. Capacitor 318 is coupled between node Y and circuit ground. Switch 320 is coupled between node Y and the inverting input of an operational transconductance amplifier (OTA) 330. The non-inverting input of OTA 330 is coupled to circuit ground. Capacitor 322 is coupled between the inverting input and output of OTA 330. Switch 324 has one end coupled to the output of OTA 330 and the other end providing output signal Vout. Switches 312 and 318 are controlled by a C1 control signal, and switches 314, 320 and 324 are controlled by a C2 control signal. OTA 330 accepts a bias current of Ibias.

  During the first phase, switches 312 and 318 are closed by a logic high on the C1 signal, switches 314, 320 and 324 are opened by a logic low on the C2 signal, and the capacitor 316 is charged by the input signal Vin. During the second phase, switches 314, 320 and 324 are closed by a logic high on the C2 signal, switches 312 and 318 are opened by a logic low on the C1 signal, and the charge on capacitor 316 is charged to capacitor 322. Transferred, which fluctuates the output signal Vout. In each sampling clock cycle, capacitor 316 is charged by the input signal and then transfers the charge to capacitor 322.

  As shown in FIG. 2, the integrator is a fundamental element of the ΣΔ ADC, as is the case with other types of switched capacitor circuits. Different ΣΔ ADC designs can include different numbers of integrators and / or different integrator configurations. As shown in FIG. 3, the integrator can be implemented with an OTA, a switching capacitor and a switch. OTA moves charge between switching capacitors, for example, from capacitor 316 in FIG. 3 to capacitor 322. The charge transfer rate and accuracy depend on the amount of bias current provided to the OTA and the size of the capacitor. If the charge transfer rate is not fast enough, the charge on the capacitor will not be transferred completely within one clock cycle, and the performance of the ΣΔ ADC may be degraded.

  As noted above, the wireless device 100 can support multiple modes for multiple wireless technologies. Different modes can be associated with different signal bandwidths. For example, the wireless device 100 can support two modes for GSM® and WCDMA. While the signal bandwidth of WCDMA is 1.92 megahertz (MHz), the signal bandwidth of GSM (registered trademark) may be 100 kilohertz (KHz).

  The speed requirement of the ΣΔ ADC 130 may be different in different modes. In general, for a signal bandwidth that gradually increases, the ΣΔ ADC 130 is required to have a gradually increasing speed. To support multiple modes, the ΣΔ ADC 130 can be designed with programmable speed. A relatively complex programmable bias circuit can be used to generate a programmable bias current for the ΣΔ ADC 130 for different modes. However, for each mode, the speed of the ΣΔ ADC 130 can vary significantly due to IC process and temperature variations. To counter this, the bias current can be generated with a sufficiently large margin to ensure that the speed of the ΣΔ ADC 130 meets system requirements even under worst-case conditions. In most cases, excessive bias current can be used for the ΣΔ ADC 130 because the worst case condition is rarely encountered. The power consumption and die area of the ΣΔ ADC 130 may not be optimized.

  In one aspect, the switched capacitor circuit may be designed and operated to have a performance that varies based on the sampling rate. This can be accomplished using a bias circuit that generates (i) OTA with a loop gain bandwidth proportional to the bias current and (ii) a bias current that will be proportional to the sampling rate and capacitance. This makes it possible to change the speed of the switched capacitor circuit for different modes by changing the bias current. This also ensures that the speed and resulting performance of the switched capacitor circuit is sufficient across IC process and temperature variations.

FIG. 4 shows a schematic diagram of an OTA 400 design having a loop gain bandwidth proportional to the bias current. The OTA 400 can be used as the OTA 330 in FIG. Within OTA 400, current source 410 is coupled between node Z and circuit ground and provides a _bias current of I _bias . N-channel metal oxide semiconductor (NMOS) transistors 412 and 422 have sources coupled to node Z and gates coupled to the non-inverting input (V _inp ) and inverting input (V _inn ) of OTA 400, respectively. (Gates). NMOS transistors 414 and 424 have gates receiving bias voltage V _b3 , sources coupled to the drains of NMOS transistors 412 and 422, respectively, and an inverting output (V _outn ) and a non-inverting output ( Voutp) has drains coupled respectively. P-channel MOS (PMOS) transistors 416 and 426 have gates receiving bias voltage V _b2 and drains coupled to the drains of NMOS transistors 414 and 424, respectively. PMOS transistors 418 and 428 have sources coupled to power supply voltage V _DD , gates receiving bias voltage V _b1 , and drains coupled to the sources of PMOS transistors 416 and 426, respectively. ).

In general, a MOS transistor can be operated in one of three regions: a saturated or strong inversion region, a linear region, and a weak inversion region. In one design, NMOS transistors 412 and 422 are operated in a weak inversion region where transconductance g _m is proportional to bias current, ie, g _m = K · I _bias , where K is a scaling factor. Can. And the loop gain bandwidth of OTA400 is
BW = g _m / C = K · I _bias / C Formula (1)
Where C is the integrator capacitor (eg, capacitor 322 of FIG. 3) and BW is the OTA 400 loop gain bandwidth.

As shown in equation (1), by operating NMOS transistors 412 and 422 in the weak inversion region, the loop gain bandwidth of OTA 400 can be varied by changing the bias I _bias . NMOS transistors 412 and 422 are

By selecting a sufficiently large size of the NMOS transistor (transistors) so that it can be operated in the weak inversion region, where V _gs is a gate-source voltage and V _th is a threshold value. Voltage.

In one design, the I- _bias current of the switched capacitor circuit can be adaptively generated to track changes in capacitor size due to variations in IC process and temperature. Sampling capacitors for switched capacitor circuits can vary with IC process and temperature, and the amount of bias current required for a given speed is therefore with IC process and temperature. Can change. The bias current can be generated in proportion to the size of the sampling capacitor in the switched capacitor circuit. This may ensure that the speed and resulting performance of the switched capacitor circuit is sufficient across IC process and temperature variations.

  In one design, the bias current of the switched capacitor circuit can be adaptively generated based on the mode of operation selected. Switched capacitor circuits can be operated at different sampling rates in different modes. The sampling rate for each mode can be selected (eg, proportionally) based on the signal bandwidth for that mode. In one design, the bias current is proportional to the sampling rate or frequency. This can ensure that the switched capacitor circuit has sufficient speed for each mode.

  FIG. 5 shows a schematic diagram of a design of bias circuit 140 of FIG. The bias circuit 140 can adaptively generate a bias current for the switched capacitor circuit (eg, ΣΔ ADC 130) based on the selected mode and to track variations in IC process and temperature. . In the design shown in FIG. 5, the bias circuit 140 includes a driver circuit 510, a switched capacitor load 520 and a current mirror 540.

Within driver circuit 510, operational amplifier (op amp) 512 has a non-inverting input receiving bias voltage V _bias and an inverting input coupled to node C. NMOS transistor 514 has a source coupled to node C, a gate coupled to the output of operational amplifier 512, and a drain coupled to node D. Capacitor 516 is coupled between the output of operational amplifier 512 and circuit ground. Capacitor 518 is coupled between the gate and source of NMOS transistor 514.

  Switched capacitor load 520 is coupled between node C and circuit ground. Within switched capacitor load 520, switch 522 and capacitor 526 are coupled in parallel, and the combination is coupled between node A and circuit ground. Switch 524 is coupled between node A and node C. Switch 532 is coupled between node B and node C. Switch 534 and capacitor 536 are coupled in parallel, and the combination is coupled between node B and circuit ground. Capacitor 528 is coupled between node C and circuit ground. Switches 522 and 532 are controlled by the S1 control signal, and switches 524 and 534 are controlled by the S2 control signal.

  Capacitors 526 and 536 can be implemented with the same type of capacitors used in switched capacitor circuits. Various types of capacitors such as metal capacitors and MOS capacitors can be used. By implementing with the same type of capacitors 526 and 536 as the capacitors in the switched capacitor circuit, the bias current generated by the bias circuit 140 more accurately tracks capacitor size changes due to IC process and temperature variations. can do.

Current mirror 540 is coupled between node D and power supply voltage V _DD . Within current mirror 540, PMOS transistors 542 and 544 have sources coupled to the supply voltage, and gates coupled together and coupled to node D. The drain of PMOS transistor 542 is also coupled to node D, and the drain of PMOS transistor 544 provides a bias current I _bias . Capacitor 546 is coupled between the power supply voltage and the gates of PMOS transistors 542 and 544.

The bias voltage V _bias can be generated using a band gap voltage reference and can be substantially constant across variations in IC process and temperature. The bias voltage V _bias can be generated using another voltage reference and can have any suitable value. The operational amplifier 512 and the NMOS transistor 514 operate as a feedback circuit that provides a voltage of V _{bias to} the node C. Capacitor 516 compensates the feedback loop to be stable. Capacitor 518 reduces current spikes when NMOS transistor 514 is charging capacitor 526 or 536.

Switched capacitor load 520 implements an equivalent resistance by averaging charge transfer across capacitors 526 and 536 for one clock cycle. The average charge current I _charge provided by NMOS transistor 514 depends on the equivalent resistance and the V _bias voltage at node C.

  FIG. 6 shows a block diagram of a design of circuit 600 for generating S1 and S2 control signals for bias circuit 140. The circuit 600 may be part of the controller / processor 160 of FIG. 1 or part of some other unit within the wireless device 100.

  Within circuit 600, clock generator 610 accepts a selected mode for wireless device 100 and generates a sampling clock SCLK based on the selected mode. The frequency or rate of the sampling clock can be determined based on signal bandwidth and / or another factor associated with the selected mode. Control signal generator 620 receives the sampling clock and generates S1 and S2 control signals for the switches in switched capacitor load 520.

FIG. 7 shows a timing diagram of the S1 and S2 control signals. The top of FIG. 7 shows the sampling clock, which has a frequency of f _sampling determined by the selected mode. The S1 signal is a logic high during the first phase φ1 when the sampling clock is a logic high. Conversely, the S2 signal is logic low during the second phase φ2 when the sampling clock is logic high. The S1 and S2 signals are non-overlapping and have a frequency of f _sampling . Each control signal has a duty cycle of less than 50%.

  Referring back to FIG. 5, capacitors 526 and 536 are charged and discharged periodically at the sampling rate via switches 522, 524, 532 and 534. During the first phase φ1, switches 522 and 532 are closed by a logic high on the S1 signal, and switches 524 and 534 are opened by a logic low on the S2 signal. Capacitor 526 is discharged via switch 522 and capacitor 536 is charged by NMOS transistor 514 via switch 532.

  During the second phase φ2, switches 522 and 532 are opened by a logic low on the S1 signal, and switches 524 and 534 are closed by a logic high on the S2 signal. Capacitor 526 is charged by NMOS transistor 514 via switch 524 and capacitor 536 is discharged via switch 534.

Capacitors 526 and 536 are therefore charged on alternate sampling clock phases by NMOS transistor 514, and each capacitor is charged and discharged on a complementary clock phase. The average charging current provided by NMOS transistor 514 is:
I _charge = f _sampling · (C ₁ + C ₂ ) · V _bias , equation (2)
Where C ₁ is the capacitance of capacitor 526 and C ₂ is the capacitance of capacitor 536. Capacitors 526 and 536 can be the same size such that C ₁ = C _{2 As} shown in equation (2), the average charging current is determined by bias voltage V _bias , sampling rate f _sampling , and Determined by the capacitances C ₁ and C _{2 of} capacitors 526 and 536 and are proportional to each other. For higher sampling rates, capacitors 526 and 536 are charged and discharged more frequently and the charging current is therefore proportional to the sampling rate. For larger capacitors 526 and 536, more current is used to charge these capacitors to match the bias voltage in each sampling clock cycle, and the charging current is therefore proportional to the size of the capacitor. .

Capacitor 528 smoothes and filters the charging current and has a capacitance C ₃ , which is greater than the total capacitance of capacitors 526 and 536, ie C ₃ > (C ₁ + C ₂ ). Can do. Capacitor 528 functions as a large current reservoir that smoothes spikes in the charging current whenever switches 524 and 532 are closed. Capacitor 528 and the equivalent resistance derived from charging and discharging capacitors 526 and 536 periodically introduces an extra pole in the feedback loop, and the stability of this loop uses capacitor 516. Secured.

The current mirror 540 generates a bias current I _bias so as to mirror the average charging current I _charge . In one design, PMOS transistors 542 and 544 have the same size, and the bias current is approximately equal to the charging current. In another design, PMOS transistors 542 and 544 have different sizes, and the bias current depends on the ratio of PMOS transistors 542 and 544 in size. For example, PMOS transistor 544 can be a factor of M greater than PMOS transistor 542, and the bias current will then be M times greater than the charge current. This design can reduce the power consumption of the bias circuit 140. Capacitor 546 prevents the gate voltages of PMOS transistors 542 and 544 from fluctuating and thus provides additional filtering.

As shown in equation (2), the design shown in FIG. 5 allows the bias current I _bias to be generated adaptively based on the selected mode. The bias current is proportional to the sampling rate, which can be determined based on the selected mode. For modes where higher speeds and higher sampling rates are applied, a larger bias current is generated by the bias circuit 140 for the ΣΔ ADC.

The design of FIG. 5 also allows the bias current to track changes in the sampling capacitor in the integrator for the ΣΔ ADC due to variations in IC process and temperature. The bias current is proportional to the capacitances C ₁ and C ₂ of capacitors 526 and 536, which can vary over the IC process and temperature in the same way as the sampling capacitors. For example, if the sampling capacitor in the ΣΔ ADC becomes larger due to IC process and temperature variations (eg, hot temperature and / or slow IC process), capacitors 526 and 536 will grow by about the same percentage. And, the bias circuit 140 produces a proportionally larger bias current, which allows multiple OTAs in the ΣΔ ADC to move the charge faster.

  FIG. 8 shows a process 800 for adaptively generating bias current for a switched capacitor circuit (eg, ΣΔ ADC). A mode may be selected from among a plurality of modes associated with different sampling rates (block 812). The switched capacitor circuit may be operated at a sampling rate that may vary depending on the selected mode (block 814). The switched capacitor circuit can have a loop gain bandwidth that is proportional to the bias current. In one design, the switched capacitor circuit comprises a ΣΔ ADC that digitizes an analog signal at a sampling rate and provides digital samples.

  Bias current for the switched capacitor circuit to obtain a selected loop gain bandwidth and track variations in at least one switching capacitor in the switched capacitor circuit due to variations in IC process and temperature Can be generated (proportional) based on the sampling rate for the switched capacitor circuit (block 816). The bias current is generated using (i) at least one capacitor that tracks at least one switching capacitor in the switched capacitor circuit through variations in IC process and temperature and / or (ii) a bandgap or some other reference voltage. Can be generated based on a bias voltage that can be generated.

  In one design of block 816, a first capacitor (eg, capacitor 526) can be discharged based on a first control signal and charged based on a second control signal. A second capacitor (eg, capacitor 536) can be discharged based on the second control signal and charged based on the first control signal. The charging current for the first capacitor and the charging current for the second capacitor can be filtered (eg, using capacitor 528, capacitor 546, etc.) to obtain an average charging current. A bias current can then be generated based on the average charging current (eg, of the current mirror). The bias current can also be generated adaptively in proportion to the sampling rate and / or in other ways of tracking variations in IC process and temperature.

Computer simulations were performed to measure the settling time of multiple OTAs in the ΣΔ ADC 130 over the IC process and temperature. Settling time is the amount of time it takes for the OTA to transfer charge between capacitors with a certain accuracy. Computer simulations show that (i) multiple OTA settling times with adaptively generated bias current based on the design shown in FIG. 5, and (ii) V _bias voltage across a fixed resistance. The settling times of a plurality of OTAs generated by applying Computer simulations show that settling time with adaptively generated bias current has less spread across the variation in IC process and temperature than settling time with conventionally generated bias current showed that.

  The adaptively generated bias current can ensure sufficient speed for worst-case conditions without the need for a large margin for the bias current. Can reduce power consumption and improve the performance of ΣΔ ADCs and other switched capacitor circuits. The performance of ΣΔ ADCs and other switched capacitor circuits can also be varied within tighter ranges across the IC process and temperature, with the use of adaptively generated bias currents, which improves yield Can do. The technique is particularly beneficial when a large number of modes are supported. For example, it is 10 modes of UMB with different sampling rates. The technique can easily generate different bias currents for all modes in order to achieve lower power consumption and good ADC performance.

  The techniques and bias circuits described herein can be implemented on ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, and the like. The bias circuit can also be assembled using various IC process technologies such as CMOS, NMOS, PMOS, bipolar junction transistor (bJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs).

  An apparatus that implements the techniques described herein may be a stand-alone device or part of a larger device. A device is (i) a single IC, (ii) a set of one or more ICs, wherein the one or more ICs can include a memory IC for storing data and / or instructions A pair, (iii) an RFIC such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC such as a mobile station modem (MSM), (v) a module that can be incorporated into other devices. , (Vi) receiver, cellular phone, wireless device, handset or mobile unit, (vii) others.

  In one or more exemplary designs, the functions described can be implemented by hardware, software, firmware, or any combination thereof. If implemented in software, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that enables transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a computer. By way of example, and not limitation, such computer readable media may be in the form of RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage device, or instructions or data structures Any other medium that can be used to carry or store the desired program code and that can be accessed by a computer can be provided. In addition, any connection is appropriately termed with a computer readable medium. For example, the software can use a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology such as infrared, wireless, and microwave, from a website, server, or other remote source When transmitted, coaxial technologies, fiber optic cables, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the media definition. Discs and discs used herein are compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), floppy discs. (Registered trademark) disk and Blu-ray disk (disc), the disk normally reproduces data magnetically, and the disk optically reproduces data with a laser. Combinations of the above should also be included within the scope of computer-readable media.

  The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the above disclosure will be readily apparent to those skilled in the art, and other modifications may be made to the general principles defined herein without departing from the spirit or scope of the disclosure. May be applied. Accordingly, this disclosure is not intended to be limited to the embodiments and designs set forth herein, but is the broadest possible, consistent with the principles and novel features defined by the appended claims. Intended to match the range.

Claims (29)

The device should include:
A switched capacitor circuit comprising at least one switching capacitor and an amplifier, the switching capacitor circuit acting to charge and discharge the at least one switching capacitor at a sampling rate, the amplifier having a bandwidth proportional to the bias current; And a bias circuit coupled to the switching capacitor circuit and operative to generate the bias current for the switching capacitor circuit, the bias current having a bandwidth proportional to the sampling rate of the amplifier. Tracking changes in the at least one switching capacitor due to variations in integrated circuit (IC) process and temperature. .   The bias circuit is operative to generate the bias current based on at least one capacitor tracking the at least one switching capacitor in the switching capacitor circuit that has undergone variations in IC process and temperature. Equipment.   The apparatus of claim 1, wherein the sampling rate for the switched capacitor circuit is variable, and wherein the biasing circuit serves to generate the bias current in proportion to the sampling rate.   The apparatus of claim 2, wherein the bias circuit is further operative to generate the bias current based on a bias voltage.   The amplifier comprises an operational transconductance amplifier (OTA) having at least one metal oxide semiconductor (MOS) transistor that provides signal gain and operates in a weak inversion region. Equipment.   The apparatus of claim 1, wherein the switched capacitor circuit comprises a sigma-delta analog-to-digital converter (ΣΔ ADC) that digitizes an analog signal at the sampling rate and provides digital samples.   The sampling rate is determined based on a mode selected from a plurality of modes associated with different sampling rates, and wherein the bias circuit is connected to the ΣΔ ADC. The apparatus of claim 6, wherein said apparatus is operative to generate said bias current in proportion to said sampling rate.   7. The apparatus of claim 6, wherein the settling time of the switched capacitor circuit uses the plurality of modes and tracks a wide range of variations in IC process and temperature.   The apparatus of claim 1, wherein the switched capacitor circuit comprises a filter or a decimater.   The bias circuit includes a switched capacitor load that operates to draw an average charging current and includes a first capacitor coupled to first and second switches, the first switch being a first switch. Discharging the first capacitor based on a control signal of 1, the second switch charging the first capacitor based on a second control signal, and the average charging current of the first capacitor The apparatus of claim 1 determined based on a charging current for a capacitor.   The switched capacitor load further includes a second capacitor coupled to a third and a fourth switch, the third switch discharging the second capacitor based on the second control signal. The fourth switch charges the second capacitor based on the first control signal, and the average charging current is further based on a charging current for the second capacitor. The apparatus of claim 10 to be determined.   The switched capacitor load further comprises a third capacitor coupled to the second and third switches and operative to filter the charging current for the first and second capacitors. Item 11. The device according to Item 11.   11. The apparatus of claim 10, wherein the bias circuit further comprises a driver circuit coupled to the switched capacitor load and operative to receive a bias voltage and provide the average charging current. The driver circuit is
A transistor that serves to provide the average charge current; and
14. The apparatus of claim 13, comprising an operational amplifier coupled to the transistor and receiving the bias voltage and driving the transistor.   The driver circuit further comprises a capacitor coupled between the gate and source of the transistor and operative to filter a spike in the charging current for the first capacitor. Equipment.   The apparatus of claim 15, wherein the bias circuit further comprises a current mirror that receives the average charge current and serves to provide the bias current. The current mirror is
First and second transistors having sources coupled together and gates coupled together, said first transistor serving to provide said average charging current, and said first transistor Two transistors serve to provide the bias current, and are coupled between the gate and the source of the first and second transistors and provide filtering for the bias current. 17. The apparatus of claim 16, comprising a capacitor acting on.   The apparatus of claim 1, wherein the apparatus is an integrated circuit. The method comprises the following:
Operating a switched capacitor circuit at a sampling rate, the switched capacitor circuit having a bandwidth proportional to a bias current; and obtaining a bandwidth proportional to the sampling rate, and integrated circuit (IC) process and temperature Generating a bias current for the switched capacitor circuit to track changes in at least one switching capacitor in the switched capacitor circuit due to variations in.   The switched capacitor circuit comprises a sigma-delta analog-to-digital converter (ΣΔ ADC), and wherein the switched capacitor circuit is operated at the sampling rate to obtain the digital samples. 20. The method of claim 19, comprising digitizing the analog signal using an ADC. Selecting a mode from among multiple modes associated with different sampling rates; and generating a bias current proportional to the sampling rate for the selected modes 20. The method of claim 19, further comprising:   20. The generating of the bias current comprises generating based on at least one capacitor tracking the at least one switching capacitor in the switching capacitor circuit that has undergone variations in IC process and temperature. the method of. Generating the bias current comprises:
Discharging the first capacitor based on the first control signal;
Charging the first capacitor based on a second control signal; and
20. The method of claim 19, comprising generating the bias current based on a charging current for the first capacitor. Generating the bias current comprises:
Discharging the second capacitor based on the second control signal;
Charging the second capacitor based on a first control signal; and
24. The method of claim 23, further comprising generating the bias current based on a charging current for the second capacitor. Generating the bias current comprises:
25. further comprising filtering the charging current for the first and second capacitors to obtain an average charging current; and generating the bias current based on the average charging current. the method of. The device should include:
Means for operating a switched capacitor circuit at a sampling rate, the switched capacitor circuit having a bandwidth proportional to a bias current; and obtaining a bandwidth proportional to the sampling rate; and an integrated circuit (IC) process And means for generating a bias current for the switched capacitor circuit to track a change in at least one switching capacitor in the switched capacitor circuit due to variations in temperature.   The switched capacitor circuit comprises a sigma-delta analog-to-digital converter (ΣΔ ADC), wherein the means for operating the switched capacitor circuit at the sampling rate is configured to acquire the digital samples. 27. The apparatus of claim 26, comprising means for digitizing the analog signal using the [Sigma] [Delta] ADC. Means for selecting a mode among a plurality of modes associated with different sampling rates; and generating a bias current proportional to the sampling rate for the selected modes 27. The apparatus of claim 26, further comprising means for:   The means for generating the bias current comprises means for generating based on at least one capacitor tracking the at least one switching capacitor in the switching capacitor circuit through variations in IC process and temperature. 27. The apparatus of claim 26.

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