JP2011525781A5 - - Google Patents

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Publication number
JP2011525781A5
JP2011525781A5 JP2011516496A JP2011516496A JP2011525781A5 JP 2011525781 A5 JP2011525781 A5 JP 2011525781A5 JP 2011516496 A JP2011516496 A JP 2011516496A JP 2011516496 A JP2011516496 A JP 2011516496A JP 2011525781 A5 JP2011525781 A5 JP 2011525781A5
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power level
transmission circuit
verification process
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uplink
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JP2011516496A
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JP2011525781A (ja
JP5449344B2 (ja
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Priority claimed from US12/144,977 external-priority patent/US8626238B2/en
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JP2011516496A 2008-06-24 2009-06-22 Ｔｄｄシステムにおける切り換え方法及び装置 Expired - Fee Related JP5449344B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US12/144,977 2008-06-24
US12/144,977 US8626238B2 (en) 2008-06-24 2008-06-24 Method and apparatus for switching in a TDD system
PCT/US2009/048150 WO2010008797A2 (en) 2008-06-24 2009-06-22 Method and apparatus for switching in a tdd system

Publications (3)

Publication Number Publication Date
JP2011525781A JP2011525781A (ja) 2011-09-22
JP2011525781A5 true JP2011525781A5 (enExample) 2012-07-26
JP5449344B2 JP5449344B2 (ja) 2014-03-19

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JP2011516496A Expired - Fee Related JP5449344B2 (ja) 2008-06-24 2009-06-22 Ｔｄｄシステムにおける切り換え方法及び装置

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US (1) US8626238B2 (enExample)
EP (2) EP3313004B1 (enExample)
JP (1) JP5449344B2 (enExample)
CN (1) CN102160302B (enExample)
CA (1) CA2728100A1 (enExample)
WO (1) WO2010008797A2 (enExample)

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