JP2011253880A - Electronic component mounting board and method of manufacturing the same - Google Patents

Electronic component mounting board and method of manufacturing the same Download PDF

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Publication number
JP2011253880A
JP2011253880A JP2010125697A JP2010125697A JP2011253880A JP 2011253880 A JP2011253880 A JP 2011253880A JP 2010125697 A JP2010125697 A JP 2010125697A JP 2010125697 A JP2010125697 A JP 2010125697A JP 2011253880 A JP2011253880 A JP 2011253880A
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electrode
substrate
electronic component
mounting
opening
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Japanese (ja)
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Satoshi Kitada
智史 北田
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Fujikura Ltd
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Fujikura Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73215Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To ensure conduction reliably while reducing a mounting area in wire bonding packaging.SOLUTION: An aperture 17 is formed through a wiring board 10 at a predetermined position thereof, and a chip body 22 of a semiconductor chip 20 is mounted toward the wiring board 10 side so that a chip electrode 21 faces the aperture 17. An insulating substrate 12 at a position continuous to the aperture 17 of the wiring board 10 is removed to become an electrode expose part 18, and a substrate electrode 11a where a wiring layer 11 is exposed is formed. The chip electrode 21 and the substrate electrode 11a are connected in the aperture 17 and the electrode expose part 18 by being bonding with a wire 19.

Description

この発明は、半導体チップなどの電子部品の実装基板及びその製造方法に関し、特にワイヤボンディング実装での実装面積の縮小や実装高さの減少を図りつつ確実に導通を確保することができる電子部品の実装基板及びその製造方法に関する。   The present invention relates to a mounting substrate for an electronic component such as a semiconductor chip and a method for manufacturing the same, and more particularly to an electronic component capable of reliably ensuring conduction while reducing a mounting area and a mounting height in wire bonding mounting. The present invention relates to a mounting substrate and a manufacturing method thereof.

半導体チップなどの電子部品を基板上に実装する方法として、下記特許文献1に開示されたようなワイヤボンディング実装が知られている。このワイヤボンディング実装は、例えば図9に示すように、ベース材101上に基板側の配線や電極102が形成された基板100上の実装箇所に、チップ本体202にチップ側の電極201が形成された半導体チップ200を電極201が基板100と反対側を向くようにしてボンディングシート103を介して搭載する。   As a method for mounting an electronic component such as a semiconductor chip on a substrate, wire bonding mounting as disclosed in Patent Document 1 below is known. In this wire bonding mounting, for example, as shown in FIG. 9, the chip-side electrode 201 is formed on the chip body 202 at the mounting position on the substrate 100 where the substrate-side wiring and the electrode 102 are formed on the base material 101. The semiconductor chip 200 is mounted via the bonding sheet 103 so that the electrode 201 faces the side opposite to the substrate 100.

そして、基板100の電極102と半導体チップ200の電極201とを金属製のワイヤ109によりボンディングして接続し、基板100の実装箇所全体を封止樹脂106により封止して実装が完了する。   Then, the electrode 102 of the substrate 100 and the electrode 201 of the semiconductor chip 200 are connected by bonding with a metal wire 109, and the entire mounting portion of the substrate 100 is sealed with the sealing resin 106, thereby completing the mounting.

特開平5−102337号公報Japanese Patent Laid-Open No. 5-102337

しかしながら、上述した従来技術のワイヤボンディング実装では、半導体チップ200の電極201が基板100と反対側を向くように搭載され、更にこの電極201からワイヤ109を延ばしてループ部分を形成した上で電極102と接続する必要がある。このため、電極102を半導体チップ200からある程度離れた位置に形成する必要があると共に、半導体チップ200の実装高さをある程度確保する必要があり、実装に要する面積を縮小したり高さを抑えたりは困難であるという問題があった。   However, in the above-described conventional wire bonding mounting, the electrode 201 of the semiconductor chip 200 is mounted so as to face the side opposite to the substrate 100, and the wire 109 is further extended from the electrode 201 to form a loop portion, and then the electrode 102. Need to connect with. For this reason, it is necessary to form the electrode 102 at a certain distance from the semiconductor chip 200, and it is necessary to secure the mounting height of the semiconductor chip 200 to some extent, thereby reducing the area required for mounting or suppressing the height. Had the problem of being difficult.

また、ワイヤ109を電極201から延ばす際に、図9に示すエッジ不良箇所Zのように、ループ部分の形成不良でワイヤ109が半導体チップ200のチップ本体202のエッジ部分に接触した状態でボンディングされてしまうことがある。このような場合で、チップ本体202が絶縁性の低い材料からなるときは、導通不良が発生したりショートしたりしてしまうおそれがある。   Further, when the wire 109 is extended from the electrode 201, bonding is performed in a state in which the wire 109 is in contact with the edge portion of the chip body 202 of the semiconductor chip 200 due to poor formation of the loop portion as in the defective edge portion Z shown in FIG. May end up. In such a case, when the chip body 202 is made of a material having low insulation, there is a risk that a conduction failure may occur or a short circuit may occur.

この発明は、上述した従来技術による問題点を解消するため、実装面積の縮小や実装高さの減少を図りつつ確実に導通を確保することができる電子部品の実装基板及びその製造方法を提供することを目的とする。   The present invention provides a mounting board for an electronic component and a method for manufacturing the same capable of reliably ensuring conduction while reducing the mounting area and the mounting height in order to solve the above-described problems caused by the prior art. For the purpose.

上述した課題を解決し、目的を達成するため、本発明に係る電子部品の実装基板は、開口部を有する基板と、この基板上に形成された配線層とを備え、電子部品の電極が前記開口部に臨むように前記基板に実装され、前記電子部品の電極と前記基板の配線層とが前記開口部を通じてワイヤボンディングにより接続されていることを特徴とする。   In order to solve the above-described problems and achieve the object, an electronic component mounting substrate according to the present invention includes a substrate having an opening and a wiring layer formed on the substrate, and the electrode of the electronic component is the above-described electrode. It is mounted on the substrate so as to face the opening, and the electrode of the electronic component and the wiring layer of the substrate are connected by wire bonding through the opening.

本発明に係る電子部品の実装基板によれば、基板の開口部に電極が臨むように電子部品を実装し、この開口部を通じて電子部品の電極と基板の配線層とをワイヤボンディングにより接続するので、ワイヤを開口部内に埋め込むような状態で接続することができ、電子部品の実装面積の縮小や実装高さの減少を図ることができる。また、構造的にワイヤが電子部品のエッジ部分に接触することがないので、電子部品の電極と基板の配線層との電気的導通を確実に確保することができる。   According to the electronic component mounting substrate of the present invention, the electronic component is mounted so that the electrode faces the opening of the substrate, and the electrode of the electronic component and the wiring layer of the substrate are connected by wire bonding through the opening. In addition, the wires can be connected in a state of being embedded in the opening, so that the mounting area of the electronic component can be reduced and the mounting height can be reduced. Further, since the wire does not structurally come into contact with the edge portion of the electronic component, it is possible to ensure electrical continuity between the electrode of the electronic component and the wiring layer of the substrate.

本発明の一態様に係る電子部品の実装基板において、例えば前記電子部品の電極と前記配線層の前記ワイヤボンディングにより接続される面は同じ方向を向いている。これにより、ワイヤの長さが最短に近くなるような状態で電極と配線層とを接続することができるので、実装面積の縮小や実装高さの減少を図ることができる。   In the electronic component mounting substrate according to one aspect of the present invention, for example, the surfaces of the electronic component electrodes and the wiring layer connected by the wire bonding are in the same direction. As a result, the electrode and the wiring layer can be connected in a state where the length of the wire is close to the shortest, so that the mounting area can be reduced and the mounting height can be reduced.

本発明の一態様に係る電子部品の実装基板において、前記開口部は、樹脂により封止されている。   In the electronic component mounting substrate according to one embodiment of the present invention, the opening is sealed with resin.

また、前記配線層は、例えば前記基板の前記電子部品の搭載側に設けられていたり、搭載側と反対側に設けられていたりする。しかし、前記配線層の接続される面は前記電子部品の電極と同じ方向を向くことになる。   In addition, the wiring layer is provided, for example, on the mounting side of the electronic component of the substrate or on the side opposite to the mounting side. However, the surface to which the wiring layer is connected faces the same direction as the electrode of the electronic component.

更に、前記電極は、前記基板における前記電子部品が搭載されている搭載領域外の前記配線層に接続されていたり、搭載領域内の前記配線層に接続されていたりする。   Further, the electrode may be connected to the wiring layer outside the mounting area on which the electronic component is mounted on the substrate, or may be connected to the wiring layer inside the mounting area.

本発明に係る電子部品の実装基板の製造方法は、配線層を有する基板の所定箇所に貫通する開口部を形成する工程と、前記開口部の周縁部にて前記配線層を露出させる工程と、電子部品をその電極が前記開口部に臨むように前記基板に実装する工程と、前記電子部品の電極と前記露出した配線層とを前記開口部を通じてワイヤボンディングにより接続する工程とを備えたことを特徴とする。   The electronic component mounting substrate manufacturing method according to the present invention includes a step of forming an opening penetrating a predetermined portion of a substrate having a wiring layer, a step of exposing the wiring layer at a peripheral portion of the opening, Mounting the electronic component on the substrate such that the electrode faces the opening, and connecting the electrode of the electronic component and the exposed wiring layer by wire bonding through the opening. Features.

本発明に係る電子部品の実装基板の製造方法によれば、基板に開口部を形成すると共にその周縁部で配線層を露出させ、開口部に電極が臨むように電子部品を実装して、この開口部を通じて電子部品の電極と基板の配線層とをワイヤボンディングにより接続するので、ワイヤを開口部内に埋め込むような状態で接続することができ、電子部品の実装面積の縮小や実装高さの減少を図ることができる。また、構造的にワイヤが電子部品のエッジ部分に接触することがないので、電子部品の電極と基板の配線層との電気的導通を確実に確保することができる。   According to the method for manufacturing an electronic component mounting substrate according to the present invention, the opening is formed in the substrate, the wiring layer is exposed at the peripheral portion, and the electronic component is mounted so that the electrode faces the opening. Since the electrode of the electronic component and the wiring layer of the substrate are connected through the opening by wire bonding, the wire can be connected in a state of being embedded in the opening, reducing the mounting area of the electronic component and reducing the mounting height. Can be achieved. Further, since the wire does not structurally come into contact with the edge portion of the electronic component, it is possible to ensure electrical continuity between the electrode of the electronic component and the wiring layer of the substrate.

本発明の一態様に係る電子部品の実装基板の製造方法において、例えば前記電子部品は、前記電極が前記露出した配線層の前記ワイヤボンディングにより接続される面と同じ方向を向くように前記基板に実装される。これにより、ワイヤの長さが最短に近くなるような状態で電極と配線層とを接続することができるので、実装面積の縮小や実装高さの減少を図ることができる。   In the method for manufacturing a mounting substrate for an electronic component according to an aspect of the present invention, for example, the electronic component is placed on the substrate such that the electrode faces the same direction as a surface to which the exposed wiring layer is connected by the wire bonding. Implemented. As a result, the electrode and the wiring layer can be connected in a state where the length of the wire is close to the shortest, so that the mounting area can be reduced and the mounting height can be reduced.

本発明の一態様に係る電子部品の実装基板の製造方法において、前記開口部を樹脂により封止する工程を更に備えても良い。   In the method for manufacturing an electronic component mounting substrate according to an aspect of the present invention, the method may further include a step of sealing the opening with a resin.

本発明によれば、実装面積の縮小や実装高さの減少を図りつつ確実に導通を確保することができる。   According to the present invention, it is possible to reliably ensure conduction while reducing the mounting area and the mounting height.

本発明の第1の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。It is sectional drawing which shows the mounting structure of the mounting substrate of the electronic component which concerns on the 1st Embodiment of this invention. 図1のA矢視図である。It is A arrow directional view of FIG. 同電子部品の実装基板の実装例を示す平面図である。It is a top view which shows the example of mounting of the mounting board | substrate of the same electronic component. 同電子部品の実装基板の実装例を示す平面図である。It is a top view which shows the example of mounting of the mounting board | substrate of the same electronic component. 同電子部品の実装基板の実装例を示す平面図である。It is a top view which shows the example of mounting of the mounting board | substrate of the same electronic component. 同電子部品の実装基板の実装例を示す平面図である。It is a top view which shows the example of mounting of the mounting board | substrate of the same electronic component. 本発明の第1の実施形態に係る電子部品の実装基板の製造方法による実装工程を示すフローチャートである。It is a flowchart which shows the mounting process by the manufacturing method of the mounting substrate of the electronic component which concerns on the 1st Embodiment of this invention. 同電子部品の実装基板の製造方法による実装工程を説明するための工程図である。It is process drawing for demonstrating the mounting process by the manufacturing method of the mounting substrate of the same electronic component. 本発明の第2の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。It is sectional drawing which shows the mounting structure of the mounting substrate of the electronic component which concerns on the 2nd Embodiment of this invention. 本発明の第3の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。It is sectional drawing which shows the mounting structure of the mounting substrate of the electronic component which concerns on the 3rd Embodiment of this invention. 本発明の第4の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。It is sectional drawing which shows the mounting structure of the mounting substrate of the electronic component which concerns on the 4th Embodiment of this invention. 従来のワイヤボンディング実装を説明するための図である。It is a figure for demonstrating the conventional wire bonding mounting.

以下に、添付の図面を参照して、この発明に係る電子部品の実装基板及びその製造方法の実施の形態を詳細に説明する。   Exemplary embodiments of an electronic component mounting board and a method of manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings.

[第1の実施形態]
図1は、本発明の第1の実施形態に係る電子部品の実装基板の実装構造を示す断面図、図2は図1のA矢視図である。本発明の第1の実施形態に係る電子部品の実装基板は、図1及び図2に示すように、例えば配線基板10上に電子部品としての半導体チップ20を実装する場合に適用される。
[First Embodiment]
FIG. 1 is a cross-sectional view showing a mounting structure of a mounting board for an electronic component according to a first embodiment of the present invention, and FIG. 2 is a view taken along arrow A in FIG. The electronic component mounting substrate according to the first embodiment of the present invention is applied, for example, when a semiconductor chip 20 as an electronic component is mounted on a wiring substrate 10 as shown in FIGS.

配線基板10は、例えばフレキシブルプリント基板(FPC)、リジッド基板等により構成される。この配線基板10は、例えばポリエチレンテレフタレート(PET)、ポリエチレンナフタレート(PEN)、ポリイミド(PI)、ポリアミド(PA)、エポキシ樹脂(例えば、ガラスエポキシ樹脂)、或いは液晶ポリマー(LCP)などの絶縁樹脂系材料からなる絶縁基材12と、この絶縁基材12の片面上に形成された銅(Cu)等の金属材料からなる配線層11と、これら絶縁基材12及び配線層11の上にエポキシ系或いはアクリル系の合成樹脂系材料からなる接着剤14を介して貼り付けられた保護部材としてのカバーレイ13とを備える。なお、カバーレイ13は、絶縁基材12と同様の合成樹脂系材料からなる。   The wiring board 10 is composed of, for example, a flexible printed board (FPC), a rigid board, or the like. The wiring substrate 10 is made of, for example, an insulating resin such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyimide (PI), polyamide (PA), epoxy resin (for example, glass epoxy resin), or liquid crystal polymer (LCP). An insulating base material 12 made of a base material, a wiring layer 11 made of a metal material such as copper (Cu) formed on one side of the insulating base material 12, and an epoxy on the insulating base material 12 and the wiring layer 11 And a coverlay 13 as a protective member attached via an adhesive 14 made of a synthetic or acrylic synthetic resin material. The coverlay 13 is made of a synthetic resin material similar to the insulating base material 12.

なお、上記カバーレイ13と接着剤14との組み合わせで構成される保護部材の他に、図示は省略するが、配線基板10においては、例えば感光性或いは熱硬化性の絶縁樹脂系材料からなるソルダレジストを保護部材として用いるようにしても良い。感光性のソルダレジストを形成する場合は、例えばスクリーン印刷によりソルダレジストを構成する絶縁樹脂系材料を絶縁基材12及び配線層11上に塗布した後、通常のフォトリソグラフィ技術により必要箇所にソルダレジストを形成すれば良い。   In addition to the protective member constituted by the combination of the cover lay 13 and the adhesive 14, although not shown in the drawings, in the wiring board 10, for example, a solder made of a photosensitive or thermosetting insulating resin material. A resist may be used as a protective member. In the case of forming a photosensitive solder resist, for example, after applying an insulating resin material constituting the solder resist on the insulating base material 12 and the wiring layer 11 by screen printing, the solder resist is applied to a necessary portion by a normal photolithography technique. Should be formed.

また、熱硬化性のソルダレジストを形成する場合は、例えばスクリーン印刷により絶縁基材12及び配線層11上の必要箇所のみにソルダレジストを構成する絶縁樹脂系材料を塗布した後、熱により硬化させてソルダレジストを形成すれば良い。このように、ソルダレジストによっても、配線基板10に保護部材を設けることができる。なお、ソルダレジストを構成する絶縁樹脂系材料としては、上記絶縁基材12と同様のものを用いることができる。   Further, when forming a thermosetting solder resist, for example, by applying an insulating resin material constituting the solder resist only to necessary portions on the insulating base material 12 and the wiring layer 11 by screen printing, the resin is cured by heat. A solder resist may be formed. As described above, the protective member can be provided on the wiring board 10 also by the solder resist. As the insulating resin material constituting the solder resist, the same material as the insulating base material 12 can be used.

半導体チップ20は、各種集積回路やパッケージ、メモリ等であり、チップ本体22と、このチップ本体22の配線基板10への実装面22a側に形成されたチップ電極21とを備える。この半導体チップ20は、配線基板10側にチップ電極21を向けた状態で、例えば絶縁基材12のみが露出するように形成された実装箇所上にボンディングシート15を介して搭載されている。   The semiconductor chip 20 is various integrated circuits, packages, memories, and the like, and includes a chip main body 22 and a chip electrode 21 formed on the mounting surface 22a side of the chip main body 22 on the wiring substrate 10. The semiconductor chip 20 is mounted via a bonding sheet 15 on a mounting portion formed so that only the insulating base material 12 is exposed, for example, with the chip electrode 21 facing the wiring substrate 10 side.

配線基板10の所定箇所には、例えば金型による打ち抜き加工やドリルによる孔あけ加工によって、基板厚方向に貫通する開口部17が形成されている。所定箇所は、例えば上記実装箇所において半導体チップ20のチップ電極21と対向する領域を含む箇所のことを指し、この開口部17内にチップ電極21が臨むように半導体チップ20が搭載される。   An opening 17 penetrating in the thickness direction of the substrate is formed at a predetermined position of the wiring substrate 10 by, for example, punching with a mold or drilling with a drill. The predetermined location refers to a location including a region facing the chip electrode 21 of the semiconductor chip 20 at the mounting location, for example, and the semiconductor chip 20 is mounted so that the chip electrode 21 faces the opening 17.

また、配線基板10の半導体チップ20の実装側と反対側においては、絶縁基材12が炭酸ガスレーザやUV−YAGレーザなどを用いたレーザ加工によって除去されて、開口部17と連続する電極露出部18が形成され、この電極露出部18においては、本例では絶縁基材12が除去されることにより配線層11の一面がチップ電極21の電極面と同じ方向を向くように露出することで、配線基板10の基板電極11aが形成されている。   Further, on the side opposite to the mounting side of the semiconductor chip 20 of the wiring substrate 10, the insulating base 12 is removed by laser processing using a carbon dioxide gas laser, a UV-YAG laser, or the like, and an electrode exposed portion continuous with the opening 17. In this electrode exposed portion 18, in this example, the insulating base material 12 is removed so that one surface of the wiring layer 11 is exposed to face the same direction as the electrode surface of the chip electrode 21. A substrate electrode 11a of the wiring substrate 10 is formed.

そして、この基板電極11aとチップ電極21とは、開口部17及び電極露出部18内において金(Au)や銅などの金属材料からなるワイヤ19を、ワイヤ19の長さが最短に近くなるようにボンディングすることにより、開口部17を通じて電気的に接続されている。なお、基板電極11aの表面には、ワイヤ19と同様の金などの金属材料でメッキが施されていることが好ましい。   The substrate electrode 11a and the chip electrode 21 are formed so that the wire 19 made of a metal material such as gold (Au) or copper is placed in the opening 17 and the electrode exposed portion 18 so that the length of the wire 19 is close to the shortest. By being bonded to each other, they are electrically connected through the opening 17. The surface of the substrate electrode 11a is preferably plated with a metal material such as gold similar to the wire 19.

更に、開口部17及び電極露出部18内には、これらチップ電極21、基板電極11a及びワイヤ19を覆うように熱硬化性樹脂又は紫外線硬化性樹脂からなる封止樹脂16が充填され、配線基板10と半導体チップ20とが封止されている。このように封止樹脂16で開口部17及び電極露出部18を封止することにより、半導体チップ20の実装面積の縮小や実装高さの減少を図ることができる。   Further, the opening 17 and the electrode exposed portion 18 are filled with a sealing resin 16 made of a thermosetting resin or an ultraviolet curable resin so as to cover the chip electrode 21, the substrate electrode 11 a, and the wire 19. 10 and the semiconductor chip 20 are sealed. By sealing the opening 17 and the electrode exposed portion 18 with the sealing resin 16 in this way, it is possible to reduce the mounting area of the semiconductor chip 20 and the mounting height.

なお、半導体チップ20は、具体的には次のように実装され、配線基板10に支持される。図3A〜図3Dは、配線基板10への半導体チップ20の実装例を示す平面図である。例えば図3Aに示すように、矩形状に形成され角部を除く一対の対向する2辺側にそれぞれチップ電極21が形成された半導体チップ20を、これらチップ電極21が臨むように実装箇所の周縁部に一対形成された開口部17と、この開口部17と連続する電極露出部18により基板電極11aの電極面がチップ電極21の電極面と同じ方向を向くように露出した配線基板10に実装する。   The semiconductor chip 20 is specifically mounted as follows and supported by the wiring board 10. 3A to 3D are plan views showing examples of mounting the semiconductor chip 20 on the wiring board 10. For example, as shown in FIG. 3A, a semiconductor chip 20 formed in a rectangular shape and having chip electrodes 21 formed on a pair of opposing two sides excluding corners is mounted on the periphery of the mounting portion so that these chip electrodes 21 face each other. Mounted on the wiring substrate 10 exposed so that the electrode surface of the substrate electrode 11a faces in the same direction as the electrode surface of the chip electrode 21 by the opening 17 formed in a pair in the part and the electrode exposed part 18 continuous with the opening 17 To do.

この場合、角部を含む他の一対の対向する2辺側にて、半導体チップ20の実装箇所は配線基板10の絶縁基材12(図示せず)と連続しているため、開口部17及び電極露出部18を設けたとしても半導体チップ20は配線基板10上に確実に支持された状態で搭載される。   In this case, since the mounting location of the semiconductor chip 20 is continuous with the insulating base material 12 (not shown) of the wiring substrate 10 on the other two opposite sides of the pair including the corners, the openings 17 and Even if the electrode exposed portion 18 is provided, the semiconductor chip 20 is mounted on the wiring substrate 10 while being securely supported.

また、図3Bに示すように、角部を除く二対の対向する2辺側にそれぞれチップ電極21が形成された半導体チップ20を、これらチップ電極21が臨むように実装箇所の周縁部に二対形成された開口部17と、この開口部17と連続する電極露出部18により基板電極11aの電極面がチップ電極21の電極面と同じ方向を向くように露出した配線基板10に実装する。   Further, as shown in FIG. 3B, two pairs of semiconductor chips 20 each having chip electrodes 21 formed on two opposite sides excluding corners are arranged on the periphery of the mounting portion so that these chip electrodes 21 face each other. The substrate is mounted on the wiring substrate 10 that is exposed so that the electrode surface of the substrate electrode 11 a faces the same direction as the electrode surface of the chip electrode 21 by the paired opening 17 and the electrode exposed portion 18 that is continuous with the opening 17.

この場合、二対の対向する2辺を除く4つの角部にて、半導体チップ20の実装箇所は配線基板10の絶縁基材12と連続しているため、開口部17及び電極露出部18を設けたとしても半導体チップ20は配線基板10上に十分支持された状態で搭載される。なお、開口部17及び電極露出部18を封止樹脂16で封止すれば、この封止樹脂16も半導体チップ20の支持メンバ(部材)として機能するため、強度的には何ら問題はない。   In this case, the mounting portion of the semiconductor chip 20 is continuous with the insulating base material 12 of the wiring board 10 at the four corners excluding two pairs of two opposite sides, so that the opening 17 and the electrode exposed portion 18 are formed. Even if it is provided, the semiconductor chip 20 is mounted on the wiring substrate 10 in a sufficiently supported state. If the opening 17 and the electrode exposed portion 18 are sealed with the sealing resin 16, the sealing resin 16 also functions as a support member (member) of the semiconductor chip 20, so that there is no problem in strength.

更に、図3Cに示すように、二対の対向する2辺の中間部及び角部を除く部分にそれぞれチップ電極21が形成された半導体チップ20を、これらチップ電極21が臨むように上記中間部に対応する箇所を除く実装箇所の角部を含む対角線上に対向するくの字状の連続する2辺からなる二組の周縁部に形成された開口部17と、この開口部17と連続する電極露出部18により基板電極11aの電極面がチップ電極21の電極面と同じ方向を向くように露出した配線基板10に実装する。   Further, as shown in FIG. 3C, the semiconductor chip 20 in which the chip electrodes 21 are respectively formed on the portions excluding the intermediate portion and the corner portion of the two pairs of two opposing sides, the intermediate portion is arranged so that the chip electrodes 21 face each other. The openings 17 are formed in two sets of peripheral edges composed of two continuous sides of a dogleg shape opposite to each other on the diagonal including the corners of the mounting portions except for the portions corresponding to. The electrode exposed portion 18 is mounted on the wiring substrate 10 exposed so that the electrode surface of the substrate electrode 11 a faces the same direction as the electrode surface of the chip electrode 21.

この場合、二対の対向する2辺の中間部にて、半導体チップ20の実装箇所は配線基板10の絶縁基材12と連続しているため、実装箇所の周縁部の大部分に開口部17及び電極露出部18を設けた状態であっても、半導体チップ20は配線基板10上に十分支持された状態で搭載される。なお、この場合も、開口部17及び電極露出部18を封止樹脂16で封止すれば強度的な問題は発生しない。   In this case, since the mounting location of the semiconductor chip 20 is continuous with the insulating base material 12 of the wiring board 10 at the intermediate portion between two pairs of two sides facing each other, the opening 17 is provided in most of the peripheral portion of the mounting location. Even in the state where the electrode exposed portion 18 is provided, the semiconductor chip 20 is mounted in a state of being sufficiently supported on the wiring substrate 10. Also in this case, if the opening 17 and the electrode exposed part 18 are sealed with the sealing resin 16, no problem in strength occurs.

また、図3Dに示すように、角部を含む一組の2辺側にそれぞれチップ電極21が形成された半導体チップ20を、これらチップ電極21が臨むように実装箇所の周縁部の角部を含むくの字状の連続する2辺に形成された開口部17と、この開口部17と連続する電極露出部18により基板電極11aの電極面がチップ電極21の電極面と同じ方向を向くように露出した配線基板10に実装する。   Further, as shown in FIG. 3D, the semiconductor chip 20 having the chip electrodes 21 formed on the two sides of the set including the corners is arranged at the corners of the peripheral portion of the mounting portion so that the chip electrodes 21 face each other. The electrode surface of the substrate electrode 11a is directed in the same direction as the electrode surface of the chip electrode 21 by the opening 17 formed on the two continuous sides of the cross-shaped and the electrode exposed portion 18 continuous with the opening 17. It mounts on the wiring board 10 exposed to (1).

この場合、角部を含む他の一組の2辺側にて、半導体チップ20の実装箇所は配線基板10の絶縁基材12と連続しているため、開口部17及び電極露出部18を設けたとしても半導体チップ20は配線基板10上に十分支持された状態で搭載されると共に、開口部17及び電極露出部18を封止樹脂16で封止すれば同様に強度的な問題は発生しない。なお、半導体チップ20の支持メンバとして配線基板10以外の部材で代用できる場合は、それで半導体チップ20を支持するようにしても良い。   In this case, since the mounting location of the semiconductor chip 20 is continuous with the insulating base material 12 of the wiring board 10 on the other two sides of the other set including the corner, the opening 17 and the electrode exposed portion 18 are provided. Even if the semiconductor chip 20 is mounted in a sufficiently supported state on the wiring substrate 10 and the opening 17 and the electrode exposed portion 18 are sealed with the sealing resin 16, the problem of strength does not occur. . If a member other than the wiring board 10 can be used as a support member of the semiconductor chip 20, the semiconductor chip 20 may be supported by that.

このような実装構造を実現する第1の実施形態に係る電子部品の実装基板によれば、半導体チップ20は配線層11と絶縁基材12を基準とした場合の同一面側に実装され、チップ電極21は半導体チップ20の搭載領域外にチップ電極21の電極面と同じ方向を向くように電極面が形成された基板電極11aに接続される。このため、配線基板10の基板電極11aを半導体チップ20と隣接する位置に形成して開口部17及び電極露出部18を介してチップ電極21とワイヤ19によりワイヤの長さが最短に近くなるように接続することができるので、従来のワイヤボンディング実装よりも半導体チップ20の実装面積の縮小や実装高さの減少を図ることができる。   According to the electronic component mounting substrate according to the first embodiment that realizes such a mounting structure, the semiconductor chip 20 is mounted on the same surface when the wiring layer 11 and the insulating base 12 are used as a reference. The electrode 21 is connected to the substrate electrode 11 a having an electrode surface formed so as to face the same direction as the electrode surface of the chip electrode 21 outside the mounting region of the semiconductor chip 20. Therefore, the substrate electrode 11a of the wiring substrate 10 is formed at a position adjacent to the semiconductor chip 20 so that the length of the wire is made shortest by the chip electrode 21 and the wire 19 through the opening 17 and the electrode exposed portion 18. Therefore, the mounting area of the semiconductor chip 20 and the mounting height can be reduced as compared with the conventional wire bonding mounting.

また、図1に示すように、その構造上ワイヤ19のループ部分が半導体チップ20のエッジ部分に接触することはなく、仮にループ部分が接触したとしてもその接触箇所は基板電極11aのエッジ部分であるため、基板電極11aとチップ電極21とを確実に接続し導通を確保することが可能となる。   Further, as shown in FIG. 1, the loop portion of the wire 19 is not in contact with the edge portion of the semiconductor chip 20 due to its structure, and even if the loop portion contacts, the contact portion is the edge portion of the substrate electrode 11a. Therefore, it is possible to reliably connect the substrate electrode 11a and the chip electrode 21 to ensure conduction.

更に、図示は省略するが、チップ電極21と基板電極11aとを開口部17及び電極露出部18を介してワイヤ19により接続することができるため、配線基板10における半導体チップ20の実装箇所近傍の表裏面いずれにおいても他の電子部品を配置することができるので、実装スペースを縮小化して配線基板10を用いた部品の小型化を図ることが可能となる。   Furthermore, although illustration is omitted, since the chip electrode 21 and the substrate electrode 11a can be connected by the wire 19 through the opening 17 and the electrode exposed portion 18, the vicinity of the mounting location of the semiconductor chip 20 on the wiring substrate 10 is possible. Since other electronic components can be arranged on both the front and back surfaces, the mounting space can be reduced and the components using the wiring board 10 can be downsized.

ここで、本発明の第1の実施形態に係る電子部品の実装基板の製造方法による実装工程について、図4のフローチャートを参照しながら、図5を参照して説明する。まず、図5(a)に示すように、別途加工工程により半導体チップ20の実装箇所を除く絶縁基材12上に配線層11が形成され、更に接着剤14を介してカバーレイ13が形成された配線基板10を用意して準備する(ステップS100)。   Here, the mounting process by the manufacturing method of the mounting board of the electronic component according to the first embodiment of the present invention will be described with reference to FIG. 5 while referring to the flowchart of FIG. First, as shown in FIG. 5A, the wiring layer 11 is formed on the insulating base 12 excluding the mounting location of the semiconductor chip 20 by a separate processing step, and the cover lay 13 is further formed via the adhesive 14. The prepared wiring board 10 is prepared (step S100).

そして、図5(b)に示すように、所定箇所に上述したような打ち抜き加工又は孔あけ加工を施して配線基板10を貫通する開口部17を形成する(ステップS102)。更に、図5(c)に示すように、半導体チップ20の搭載側と反対側の開口部17と連続する箇所の絶縁基材12を上述したようなレーザ加工によって除去して電極露出部18を形成し、配線層11を露出させた基板電極11aをその電極面が実装されるチップ電極21の電極面と同じ方向を向くように形成する(ステップS104)。なお、これらステップS102とステップS104の順序は入れ替わっても良い。   Then, as shown in FIG. 5B, the opening 17 penetrating the wiring board 10 is formed by performing the punching process or the drilling process as described above at a predetermined location (step S102). Further, as shown in FIG. 5 (c), the insulating base material 12 in a portion continuous with the opening 17 on the side opposite to the mounting side of the semiconductor chip 20 is removed by the laser processing as described above to remove the electrode exposed portion 18. Then, the substrate electrode 11a with the wiring layer 11 exposed is formed so as to face the same direction as the electrode surface of the chip electrode 21 on which the electrode surface is mounted (step S104). Note that the order of step S102 and step S104 may be interchanged.

基板電極11aを形成したら、図5(d)に示すように、半導体チップ20のチップ電極21が配線基板10側を向き且つ開口部17に臨むように、半導体チップ20のチップ本体22をボンディングシート15を介して配線基板10の実装箇所にダイボンディングにより搭載する(ステップS106)。   After the substrate electrode 11a is formed, the chip body 22 of the semiconductor chip 20 is bonded to the bonding sheet so that the chip electrode 21 of the semiconductor chip 20 faces the wiring substrate 10 and faces the opening 17 as shown in FIG. 15 is mounted on the mounting location of the wiring board 10 via die bonding (step S106).

そして、図5(e)に示すように、開口部17内のチップ電極21と電極露出部18により形成された基板電極11aとを開口部17内でワイヤ19によりボンディングして接続し(ステップS108)、最後に、開口部17及び電極露出部18を満たすように封止樹脂16を充填して配線基板10と半導体チップ20とを樹脂封止し(ステップS110)、本フローチャートによる一連の実装工程が終了する。これにより、図1に示したように、基板電極11aとチップ電極21とが開口部17及び電極露出部18内でワイヤ19により接続された上で半導体チップ20が配線基板10上に実装される。   Then, as shown in FIG. 5E, the chip electrode 21 in the opening 17 and the substrate electrode 11a formed by the electrode exposed portion 18 are bonded and connected by the wire 19 in the opening 17 (step S108). Finally, the sealing resin 16 is filled so as to fill the opening 17 and the electrode exposed portion 18, and the wiring substrate 10 and the semiconductor chip 20 are resin-sealed (step S110), and a series of mounting steps according to this flowchart. Ends. As a result, as shown in FIG. 1, the semiconductor chip 20 is mounted on the wiring substrate 10 after the substrate electrode 11 a and the chip electrode 21 are connected by the wire 19 in the opening 17 and the electrode exposed portion 18. .

[第2の実施形態]
図6は、本発明の第2の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。なお、以降において、既に説明した部分と重複する箇所には同一の符号を附して説明を割愛し、本発明に特に関連しない部分については明記しないことがあるとする。
[Second Embodiment]
FIG. 6 is a cross-sectional view showing the mounting structure of the electronic component mounting board according to the second embodiment of the present invention. In the following description, the same reference numerals are assigned to portions that overlap with the portions that have already been described, and description thereof is omitted, and portions that are not particularly relevant to the present invention may not be specified.

第2の実施形態は、半導体チップ20が配線層11と絶縁基材12を基準とした場合の同一面側に実装されているが、電極露出部18及び基板電極11aの電極面が半導体チップ20の実装箇所の搭載領域内にチップ電極21の電極面と同じ方向を向くように形成されている点が、先の第1の実施形態と相違している。従って、半導体チップ20のチップ本体22は、配線層11を含めた絶縁基材12上にボンディングシート15を介して搭載されている。このように半導体チップ20を配線基板10上に実装しても、第1の実施形態と同様の作用効果を有することができる。   In the second embodiment, the semiconductor chip 20 is mounted on the same surface when the wiring layer 11 and the insulating base 12 are used as a reference. However, the electrode surfaces of the electrode exposed portion 18 and the substrate electrode 11a are the semiconductor chip 20. This is different from the previous first embodiment in that it is formed in the mounting region of the mounting location so as to face the same direction as the electrode surface of the chip electrode 21. Accordingly, the chip body 22 of the semiconductor chip 20 is mounted on the insulating base 12 including the wiring layer 11 via the bonding sheet 15. Even if the semiconductor chip 20 is mounted on the wiring substrate 10 in this manner, the same effects as those of the first embodiment can be obtained.

[第3の実施形態]
図7は、本発明の第3の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。第3の実施形態は、半導体チップ20が配線層11と反対面側(絶縁基材12の裏面側)に実装されており、電極露出部18及び基板電極11aの電極面が配線基板10の表面側にチップ電極21の電極面と同じ方向を向くように形成されると共に、半導体チップ20の実装箇所の搭載領域外に形成されている点が、先の実施形態と相違している。
[Third Embodiment]
FIG. 7 is a cross-sectional view showing the mounting structure of the electronic component mounting board according to the third embodiment of the present invention. In the third embodiment, the semiconductor chip 20 is mounted on the side opposite to the wiring layer 11 (the back side of the insulating base 12), and the electrode exposed portion 18 and the electrode surface of the substrate electrode 11 a are the surface of the wiring substrate 10. It differs from the previous embodiment in that it is formed on the side so as to face the same direction as the electrode surface of the chip electrode 21 and is formed outside the mounting area of the mounting location of the semiconductor chip 20.

すなわち、半導体チップ20のチップ本体22は、チップ電極21が開口部17に臨むようにボンディングシート15を介して絶縁基材12の裏面上に搭載され、電極露出部18は、接着剤14を介して貼り付けられるカバーレイ13を予め加工しておくことにより形成される。このように半導体チップ20を配線基板上に実装しても、実装面積を縮小して確実に導通を図ることができると共に、カバーレイ13を除去して電極露出部18を形成し基板電極11aを形成する工程を省くことができるので、実装工程をより簡略化することが可能となる。   That is, the chip body 22 of the semiconductor chip 20 is mounted on the back surface of the insulating base 12 via the bonding sheet 15 so that the chip electrode 21 faces the opening 17, and the electrode exposed portion 18 is interposed via the adhesive 14. It is formed by processing the coverlay 13 to be attached in advance. Even if the semiconductor chip 20 is mounted on the wiring board in this way, the mounting area can be reduced to ensure conduction, and the cover lay 13 is removed to form the electrode exposed portion 18 to form the substrate electrode 11a. Since the forming process can be omitted, the mounting process can be further simplified.

[第4の実施形態]
図8は、本発明の第4の実施形態に係る電子部品の実装基板の実装構造を示す断面図である。第4の実施形態は、半導体チップ20が配線層11と反対面側に実装されているが、電極露出部18及び基板電極11aの電極面が配線基板10の表面側にチップ電極21の電極面と同じ方向を向くように形成されると共に、半導体チップ20の実装箇所の搭載領域内に形成されている点が、第3の実施形態と相違している。その他の構成、作用効果等は第3の実施形態と同様である。
[Fourth Embodiment]
FIG. 8: is sectional drawing which shows the mounting structure of the mounting substrate of the electronic component which concerns on the 4th Embodiment of this invention. In the fourth embodiment, the semiconductor chip 20 is mounted on the surface opposite to the wiring layer 11, but the electrode exposed portion 18 and the electrode surface of the substrate electrode 11 a are on the surface side of the wiring substrate 10 and the electrode surface of the chip electrode 21. Is different from the third embodiment in that the semiconductor chip 20 is formed in the mounting region of the mounting portion. Other configurations, operational effects, and the like are the same as those of the third embodiment.

なお、上述した第1の実施形態に係る実装構造と第2の実施形態に係る実装構造とを組み合わせたり、第3の実施形態に係る実装構造と第4の実施形態に係る実装構造とを組み合わせたりして配線基板10に半導体チップ20を実装するようにしても良い。このようにすれば、半導体チップ20の実装態様の自由度を更に広げることができる。   The mounting structure according to the first embodiment described above and the mounting structure according to the second embodiment are combined, or the mounting structure according to the third embodiment and the mounting structure according to the fourth embodiment are combined. Alternatively, the semiconductor chip 20 may be mounted on the wiring board 10. In this way, the degree of freedom of the mounting mode of the semiconductor chip 20 can be further expanded.

10 配線基板
11 配線
12 絶縁基板
13 カバーレイ
14 接着剤
15 ボンディングシート
16 封止樹脂
17 貫通孔
18 開口部
20 半導体チップ
21 チップ電極
22 チップ本体
DESCRIPTION OF SYMBOLS 10 Wiring board 11 Wiring 12 Insulating board 13 Coverlay 14 Adhesive 15 Bonding sheet 16 Sealing resin 17 Through-hole 18 Opening part 20 Semiconductor chip 21 Chip electrode 22 Chip body

Claims (10)

開口部を有する基板と、この基板上に形成された配線層とを備え、
電子部品の電極が前記開口部に臨むように前記基板に実装され、
前記電子部品の電極と前記基板の配線層とが前記開口部を通じてワイヤボンディングにより接続されている
ことを特徴とする電子部品の実装基板。
A substrate having an opening and a wiring layer formed on the substrate,
Mounted on the substrate so that the electrode of the electronic component faces the opening,
The electronic component mounting substrate, wherein the electrode of the electronic component and the wiring layer of the substrate are connected through the opening through wire bonding.
前記電子部品の電極と前記配線層の前記ワイヤボンディングにより接続される面は同じ方向を向いていることを特徴とする請求項1記載の電子部品の実装基板。   2. The electronic component mounting substrate according to claim 1, wherein the electrodes of the electronic component and the surface of the wiring layer connected by the wire bonding face in the same direction. 前記開口部は、樹脂により封止されていることを特徴とする請求項1又は2記載の電子部品の実装基板。   3. The electronic component mounting board according to claim 1, wherein the opening is sealed with a resin. 前記配線層は、前記基板の前記電子部品の搭載側に設けられていることを特徴とする請求項1〜3のいずれか1項記載の電子部品の実装基板。   The electronic component mounting substrate according to claim 1, wherein the wiring layer is provided on a side of the substrate on which the electronic component is mounted. 前記配線層は、前記基板の前記電子部品の搭載側と反対側に設けられていることを特徴とする請求項1〜3のいずれか1項記載の電子部品の実装基板。   4. The electronic component mounting board according to claim 1, wherein the wiring layer is provided on a side of the substrate opposite to the electronic component mounting side. 5. 前記電極は、前記基板における前記電子部品が搭載されている搭載領域外の前記配線層に接続されていることを特徴とする請求項1〜5のいずれか1項記載の電子部品の実装基板。   The electronic component mounting substrate according to claim 1, wherein the electrode is connected to the wiring layer outside the mounting area on which the electronic component is mounted on the substrate. 前記電極は、前記基板における前記電子部品が搭載されている搭載領域内の前記配線層に接続されていることを特徴とする請求項1〜5のいずれか1項記載の電子部品の実装基板。   6. The electronic component mounting substrate according to claim 1, wherein the electrode is connected to the wiring layer in a mounting region on the substrate where the electronic component is mounted. 配線層を有する基板の所定箇所に貫通する開口部を形成する工程と、
前記開口部の周縁部にて前記配線層を露出させる工程と、
電子部品をその電極が前記開口部に臨むように前記基板に実装する工程と、
前記電子部品の電極と前記露出した配線層とを前記開口部を通じてワイヤボンディングにより接続する工程と
を備えたことを特徴とする電子部品の実装基板の製造方法。
Forming an opening penetrating a predetermined portion of the substrate having a wiring layer;
Exposing the wiring layer at the periphery of the opening;
Mounting the electronic component on the substrate such that the electrode faces the opening;
And a step of connecting the electrode of the electronic component and the exposed wiring layer by wire bonding through the opening.
前記電子部品は、前記電極が前記露出した配線層の前記ワイヤボンディングにより接続される面と同じ方向を向くように前記基板に実装されることを特徴とする請求項8記載の電子部品の実装基板の製造方法。   9. The electronic component mounting substrate according to claim 8, wherein the electronic component is mounted on the substrate such that the electrode faces the same direction as a surface of the exposed wiring layer connected by the wire bonding. Manufacturing method. 前記開口部を樹脂により封止する工程を更に備えた
ことを特徴とする請求項8又は9記載の電子部品の実装基板の製造方法。
The method for manufacturing a mounting substrate for an electronic component according to claim 8 or 9, further comprising a step of sealing the opening with a resin.
JP2010125697A 2010-06-01 2010-06-01 Electronic component mounting board and method of manufacturing the same Pending JP2011253880A (en)

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