JP2011222843A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that a complex process such as re-pasting a remaining wafer to a dicing tape after a peripheral ring is cut off using a rotary blade and the like from the rear side of the wafer, relating to a process technology in which, at the time point when a device formation process on a wafer surface is completed while reduction in film thickness of the wafer is being performed, shifting is made to a wafer rear-surface step and a dicing step while a ring-like thick wall portion is formed at the peripheral part of the rear surface of wafer.SOLUTION: In a wafer periphery ring process, after the inner portion of the rear surface of a wafer is made to be a target thickness which is required for a device, shifting is made to a dicing step or the like. During the process, the rear surface of the wafer where a wafer peripheral ring or the like is formed is pasted to a dicing tape in such manner as follows its shape, the wafer peripheral ring is cut/separated from the front surface side of the wafer, and then, under that state, a wafer remaining on the dicing tape is subjected to a dicing process to be separated into respective chips.

Description

  The present invention relates to a technique effective when applied to a wafer dicing peripheral technique in a method of manufacturing a semiconductor device (or semiconductor integrated circuit device).

  In Japanese Patent Laid-Open No. 2003-332271 (Patent Document 1) or US Patent Publication No. 2003-215985 (Patent Document 2) corresponding thereto, the peripheral portion is formed by thinning only the back surface inner region of the wafer. An example of a peripheral ring-shaped wafer dicing method for preventing warpage of the wafer is disclosed by leaving the substrate as thick as a ring-shaped frame portion. The method shown there first, after pasting the dicing tape along the back surface of the wafer, with the stage inserted into the recess on the back surface of the wafer to support it, Dicing with a dicing blade is performed, and then the ring-shaped frame portion is removed.

  In Japanese Patent Laid-Open No. 2008-294287 (Patent Document 3) or US Patent Publication No. 2008-293221 (Patent Document 4) corresponding thereto, a peripheral portion is formed by thinning only an inner region on the back surface of a wafer. An example of a peripheral ring-shaped wafer dicing method for preventing warpage of the wafer is disclosed by leaving the substrate as thick as a ring-shaped frame portion. First, with the protective tape attached to the front surface of the wafer, the ring-shaped frame portion is removed from the back surface of the wafer with a blade, and then the dicing tape is attached to the back surface of the wafer. Remove. Finally, dicing is performed with a dicing blade from the front side of the wafer.

JP 2003-332271 A US Patent Publication No. 2003-215985 JP 2008-294287 A US Patent Publication No. 2008-293221

  As the wafer thinning progresses, when the device formation process on the wafer surface is almost completed, a ring-shaped thick part is left around the back surface of the wafer, and the inside of the wafer back surface is required for the device. A process technique (referred to as a “wafer peripheral ring process”) has been developed in which the final thickness or a thickness close thereto is transferred to a wafer back surface process or a dicing process.

  In this wafer peripheral ring process, as disclosed in the cited document, dicing is performed while leaving the peripheral ring (preceding dicing method), or the peripheral ring is formed by a rotating blade or the like from the back side of the wafer. There has been proposed a complicated process (removal and replacement method of a leading ring) such as replacing the remaining wafer with dicing tape again after cutting and separating. However, in the preceding dicing method, since there is a thick peripheral ring in the periphery, it is difficult to execute dicing itself, and in the preceding ring removal & replacement method, the process is complicated.

  The present invention has been made to solve these problems.

  An object of the present invention is to provide a manufacturing process of a highly reliable semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, one invention of the present application relates to a wafer peripheral ring process in which the inside of the wafer back surface is made to have a final thickness required for the device or a thickness close thereto, and then transferred to the wafer back surface process or the dicing process. By cutting the wafer peripheral ring from the front surface side of the wafer with the ring (annular region) and the back surface of the wafer in which the circular recess region is formed, attached to the dicing tape so as to follow the shape After the wafer peripheral ring is separated from the internal area of the wafer and the dicing tape, the wafer remaining on the dicing tape in that state is diced to separate individual chips.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, in the wafer peripheral ring process in which the interior of the back surface of the wafer is made to have a final thickness required for the device or a thickness close thereto, and then transferred to the wafer back surface process or the dicing process, the wafer peripheral ring (annular region) and The wafer peripheral area and dicing are cut by cutting the wafer peripheral ring from the front side of the wafer with the back surface of the wafer on which the circular recess area is formed attached to the dicing tape so as to follow the shape. After the wafer peripheral ring is separated from the tape, the wafer remaining on the dicing tape in that state is separated into individual chips by dicing, so that the thin film wafer can be diced by a simple process. it can.

It is a wafer top view for demonstrating the wafer processing process (at the time of completion of a wafer surface device formation process) in the manufacturing method of the semiconductor device of one embodiment of this application. 1 is a schematic cross-sectional view of a wafer corresponding to the X′-X cross section of FIG. 1 (in the present application, the thickness direction of the wafer is exaggerated for convenience of illustration. Also, the bevel portion of the wafer is complicated in illustration. Therefore, the vertical side is substituted.) It is a wafer bottom view for demonstrating the wafer processing process (at the time of surface protection tape affixing) in the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 4 is a schematic wafer cross-sectional view corresponding to the X-X ′ cross section of FIG. 3. It is a wafer schematic cross section for demonstrating the wafer processing process (preliminary back grinding process) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer bottom view for demonstrating the wafer processing process (circular recess area | region formation process) in the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 7 is a schematic wafer cross-sectional view corresponding to the X-X ′ cross section of FIG. 6. It is a wafer schematic cross section for demonstrating the wafer processing process (stress relief process) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer schematic cross section for demonstrating the wafer processing process (protective tape peeling process) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer schematic cross section for demonstrating the wafer processing process (back surface metal electrode formation process) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer schematic cross section for demonstrating the wafer processing process (at the time of the dicing tape sticking process start in a vacuum vessel) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer schematic cross section for demonstrating the wafer processing process (the time of completion of the dicing tape sticking process in a vacuum vessel) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer schematic cross section for demonstrating the wafer processing process (ring-cut process start time) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer top view for demonstrating the wafer processing process (at the time of completion of a ring cut process) in the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 15 is a schematic cross-sectional view of a wafer corresponding to the X′-X cross section of FIG. 14. It is a wafer schematic cross section for demonstrating the wafer processing process (annular area | region removal process) in the manufacturing method of the semiconductor device of one embodiment of this application. It is a wafer top view for demonstrating the wafer processing process (during the dicing process) in the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 18 is a schematic cross-sectional view of a wafer corresponding to the X′-X cross-section of FIG. 17 (note that the vertical distance is exaggerated and drawn as in FIG. 2). It is a wafer top view for demonstrating the wafer processing process (dicing process completion time) in the manufacturing method of the semiconductor device of one embodiment of this application. FIG. 20 is a schematic cross-sectional view of a wafer corresponding to the X′-X cross section of FIG. 19.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A semiconductor device manufacturing method including the following steps:
(A) forming a plurality of semiconductor chip regions on the first main surface side of the wafer;
(B) After the step (a), a step of attaching a protective tape to the first main surface of the wafer;
(C) An annular region having a first thickness is formed in a peripheral portion on the second main surface side of the wafer in a state where the protective tape is attached to the first main surface of the wafer. Forming a circular recess region having a second thickness smaller than the first thickness in an inner region of the second main surface;
(D) a step of removing the protective tape after the step (c);
(E) a step of forming a metal film on the second main surface of the wafer after the step (d);
(F) After the step (e), a step of attaching a dicing tape to the second main surface of the wafer so as to follow the shape;
(G) separating the annular region from the inner region and the dicing tape in a state where the dicing tape is attached to the second main surface of the wafer;
(H) After the step (g), the dicing process is performed on the wafer in a state where the dicing tape is attached to the second main surface of the wafer. A process of separating the chip area into individual semiconductor chips.

  2. In the method of manufacturing a semiconductor device according to the item 1, the peripheral portion of the dicing tape is fixed to a dicing frame in the step (h).

  3. In the method of manufacturing a semiconductor device according to the item 1, the peripheral portion of the dicing tape is fixed to a dicing frame in the steps (f) to (h).

  4). 4. In the method for manufacturing a semiconductor device according to any one of items 1 to 3, the step (f) is performed in a vacuum container.

  5. 5. In the method for manufacturing a semiconductor device according to any one of 1 to 4, the step (c) is executed by partially grinding the second main surface of the wafer.

  6). 6. In the method for manufacturing a semiconductor device according to any one of 1 to 5, in the step (g), the annular region is separated from the inner region by a rotating blade.

  7). 7. In the method for manufacturing a semiconductor device according to any one of 1 to 6, the dicing process in the step (h) is performed by a rotating blade.

  8). In the method for manufacturing a semiconductor device according to any one of 1 to 7, the step (e) is performed by sputtering film formation.

9. The method for manufacturing a semiconductor device according to any one of 1 to 8 further includes the following steps:
(I) A step of performing stress relief treatment on the second main surface of the wafer after the step (c) and before the step (d).

  10. In the method for manufacturing a semiconductor device according to the item 9, the stress relief process is a wet etching process.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Furthermore, in the present application, the term “semiconductor device” mainly refers to a single device such as various transistors (active elements), and mainly a resistor, a capacitor, etc. on a semiconductor chip or the like (for example, a single crystal silicon substrate). It is a collection. In addition, even if it is called a single unit, there are actually a plurality of small elements integrated. Here, as a typical example of various transistors, a MISFET (Metal Insulator Semiconductor Transistor which can be a MISFET represented by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a transistor, an IGB transistor which can be an IGBT transistor, an IBB transistor, an IGB transistor, an IBB transistor, an IGB transistor, an IGB transistor, an IB transistor, an IGB transistor, an IGBT, and an IGBT. . Also, “MOS” does not limit the insulating film to oxide.

  2. Similarly, in the description of the embodiment and the like, the material, composition, etc. may be referred to as “X consisting of A”, etc., except when clearly stated otherwise and clearly from the context, except for A It does not exclude what makes an element one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say.

  3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

  4). In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  5. “Wafer” usually refers to a single crystal silicon wafer on which a semiconductor device (same as a semiconductor integrated circuit device and an electronic device) is formed, but an insulating substrate such as an epitaxial wafer, an SOI substrate, an LCD glass substrate, and the like. Needless to say, a composite wafer such as a semiconductor layer is also included.

  6). In the present application, the “power semiconductor device” refers to, for example, a power MOSFET, IGBT, LDMOSFET (Laterally Diffused MOSFET), a power diode, and the like, and an integrated circuit having at least one of these. The same applies to “power MOS semiconductor device”, “IGBT semiconductor device”, “LDMOS semiconductor device”, and the like.

  7). In the present application, “dicing” or “dicing process” includes not only a rotating blade but also a laser or the like. Further, “in the case of using a laser or the like” includes a process in which an altered layer is formed by a laser, a process using grooving by a laser, and a process of combining these with a rotating blade.

[Details of the embodiment]
The embodiment will be further described in detail. In the drawings, the same or similar parts are denoted by the same or similar symbols or reference numerals, and description thereof will not be repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, it may be hatched to clearly indicate that it is not a void.

1. Description of the wafer processing process in the method of manufacturing a semiconductor device according to an embodiment of the present application (mainly FIGS. 1 to 20)
Here, in order to explain mainly the handling of a thin film wafer, specifically, a wafer process assuming a power MOSFET having a relatively low withstand voltage will be described as an example. Needless to say, it can be applied. Needless to say, the following processes can be applied not only to power MOSFETs but also to power semiconductor devices such as IGBTs, bipolar power transistors, power diodes and the like.

  FIG. 1 is a wafer top view for explaining a wafer processing process (at the time of completion of a wafer surface device forming step) in a method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 2 is a schematic wafer cross-sectional view corresponding to the X′-X cross section of FIG. 1. FIG. 3 is a wafer bottom view for explaining the wafer processing process (at the time of attaching the surface protection tape) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 4 is a schematic wafer cross-sectional view corresponding to the X-X ′ cross section of FIG. 3. FIG. 5 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (preliminary backgrinding step) in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 6 is a wafer bottom view for explaining a wafer processing process (circular recess region forming step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 7 is a schematic wafer cross-sectional view corresponding to the X-X ′ cross section of FIG. 6. FIG. 8 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (stress relief process) in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 9 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (protective tape peeling step) in the method of manufacturing a semiconductor device according to one embodiment of the present application. FIG. 10 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (back surface metal electrode forming step) in the method of manufacturing a semiconductor device according to one embodiment of the present application. FIG. 11 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (at the start of a dicing tape attaching process in a vacuum vessel) in the method for manufacturing a semiconductor device according to an embodiment of the present application. FIG. 12 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (at the time of completion of a dicing tape attaching process in a vacuum vessel) in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 13 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (at the start of the ring-cut process) in the method for manufacturing a semiconductor device according to one embodiment of the present application. FIG. 14 is a wafer top view for explaining a wafer processing process (when the ring-cut process is completed) in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 15 is a schematic cross-sectional view of a wafer corresponding to the X′-X cross section of FIG. 14. FIG. 16 is a schematic cross-sectional view of a wafer for explaining a wafer processing process (annular region removing step) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 17 is a wafer top view for explaining the wafer processing process (during the dicing process) in the method of manufacturing a semiconductor device according to the embodiment of the present application. FIG. 18 is a schematic wafer cross-sectional view corresponding to the X′-X cross section of FIG. 17. FIG. 19 is a wafer top view for explaining a wafer processing process (when the dicing process is completed) in the semiconductor device manufacturing method according to the embodiment of the present application. FIG. 20 is a schematic wafer cross-sectional view corresponding to the X′-X cross section of FIG. 19. Based on these, the wafer processing process in the method of manufacturing a semiconductor device according to an embodiment of the present application will be described.

  Here, a 200-phi N− type epitaxial wafer 1 (N + type single crystal silicon wafer formed with an N− type silicon epitaxial layer) is used as a raw material wafer (the wafer thickness is about 500 to 900 micrometers, for example). As an example, the wafer diameter may be 300 phi, 450 phi, or others. If necessary, it may be a P-type epitaxial wafer, a semiconductor wafer other than silicon, or a substrate. Note that the thickness of the wafer (initial wafer thickness) is arbitrary, but for the convenience of explanation, for example, it is about 725 micrometers.

  FIG. 1 shows a wafer 1 in which the wafer surface process is almost completed. As shown in FIG. 1, the wafer 1 has a substantially circular shape with a notch 3, and a plurality of chip regions 2 are formed in the inner region of the front main surface 1a (first main surface). .

  Next, FIG. 2 shows a cross section taken along line X'-X in FIG. As shown in FIG. 2, at this stage, nothing is formed on the back side main surface 1 b (second main surface) of the wafer 1 (except for an impurity region not shown), but the front side main surface of the wafer 1 is not formed. On the surface 1a (first main surface), for example, semiconductor element main parts 4 such as a source region, a gate electrode, and a source electrode are provided corresponding to each semiconductor chip region 2 (semiconductor chip).

  Next, the surface protection tape attaching process will be described. The wafer 1 with the surface protective tape 5 (surface protective adhesive sheet) attached is shown in FIG. 3 (broken line is the semiconductor chip region 2 on the front main surface 1a) and FIG. 4 (in the XX ′ cross section in FIG. 3). Is). As shown in FIG. 3, nothing is basically formed as in FIG. On the other hand, as shown in FIG. 4, a single-sided adhesive tape 5 (surface protective tape) is attached to the front main surface 1a of the wafer 1 so as to cover almost the entire surface thereof.

  Next, it moves to a preliminary back grinding process. In this step, as shown in FIG. 5, a grinding blade 52, a grinding blade holding plate 53, etc., with the surface protective tape 5 (surface protective adhesive sheet) adhered to the front main surface 1a of the wafer 1. By rotating and translating the wheel 51 relatively in a pressurized state, the back surface 1b of the wafer 1 (usually, the wafer is also rotating) is uniformly back-grounded on the entire surface ("the entire surface back-grinding process"). And the wafer thickness is reduced to a grinding target thickness of 6. The target grinding thickness 6 can also be changed as necessary, but here, for example, it is about 650 micrometers. That is, in this example, the shaving amount is about 75 micrometers. This step is not necessary depending on the initial wafer thickness.

  Next, the process proceeds to a wafer inner region thinning process (referred to as “wafer partial thinning process” or “partial backgrinding process”). As shown in FIGS. 6 and 7, the wafer inner region 8 (substantially circular region including almost all semiconductor chip regions 2) leaving an annular region 7 (wafer peripheral region) around the back surface 1b of the wafer 1. A partial backgrinding process is performed by relatively rotating and translating a grinding wheel 51 similar to the above from the back surface of the wafer 1 in a pressurized state (usually, the wafer is also rotated as usual). Apply. As a result, the wafer inner region 8 is changed to the circular recess region 8 and the thick annular region 7 is left in the peripheral portion of the wafer 1. The thickness of the circular recess region 8 (the wafer inner region) at the time when the partial back grinding process is completed is arbitrary, but here, for example, about 50 micrometers (this is the second thickness). The range is 20 to 200 micrometers). Therefore, the amount of cutting here is about 600 micrometers. In addition, the thickness (first thickness) of the annular region 7 at the time when the partial back grinding process is completed is about 650 micrometers in this example, and the width thereof is relatively arbitrary. For example, it is about 2.5 millimeters excluding the width of the bevel portion (as a suitable range, for example, in the case of 200 phi, about 1.5 to 7 millimeters can be exemplified).

  Next, a stress relief process is performed on the back surface 1b of the wafer 1 in order to remove the altered layer formed on the back surface 1b of the wafer 1 mainly by a partial backgrinding process. In this stress relief process, for example, as shown in FIG. 8, the front side main surface 1a of the wafer 1 to which the surface protective tape 5 is attached is rotated while being attracted to the spin table 54, and in this state, the wafer 1 is rotated. This is carried out by supplying a chemical liquid 56 (silicon etching liquid) from the nozzle 55 or the like to the back main surface 1b of this, that is, the surface of the circular recess region 8. The stress relief treatment is not limited to wet etching, and may be other methods such as dry polishing and CMP (Chemical Mechanical Polishing). Examples of the silicon etching solution include a mixed acid of hydrofluoric acid and nitric acid. Examples of the etching amount during the wet etching include about 0.5 to 3 micrometers, preferably about 1 to 2 micrometers.

  Next, as shown in FIG. 9, the surface protective tape 5 (surface protective adhesive sheet) is peeled (removed) from the front main surface 1 a of the wafer 1. This is because the subsequent backside treatment involves heat treatment at about several hundred degrees Celsius or higher.

  Next, as shown in FIG. 10, the film forming process of the back surface metal electrode 9 (for example, a titanium film / nickel film / gold film can be exemplified from a layer close to the wafer) is performed by sputtering film forming or the like. Executed. In this sputtering film formation, the partially thinned wafer 1 is accommodated in, for example, a heat-resistant ring-shaped susceptor 57 (for example, quartz, heat-resistant metal, other heat-resistant ceramics, etc.). If it is processed in the state, it is easy to handle. At this time, since the wafer 1 has the thick annular region 7, the shape thereof can be maintained. If attention is paid to the wafer stage of the sputtering film forming apparatus, the processing can be performed without using such a susceptor. However, the device structure may be complicated. Further, a heat-resistant reinforcing plate may be attached to the back surface 1b of the wafer 1, but in this case, the process becomes complicated and the reinforcing plate material is expensive.

  After the back surface metal electrode film forming step (before the dicing step), a wafer probe test is performed as necessary. If necessary, the wafer probe test may be executed between the entire back grinding process and the wafer partial thinning process. However, the measurement accuracy is higher in the latter part of the film forming step of the back metal electrode because the back metal electrode can be used for measurement.

  Next, as shown in FIG. 11, the dicing tape 63 (in this case, the peripheral portion of the dicing tape is, for example, adhesively fixed in advance to a substantially annular dicing frame 62 in the vacuum container 59. The rear surface 1b of the wafer 1 may be attached to the substrate 1). In this case, the dicing tape 63 (one-sided adhesive tape) needs to be adhered (adhered) according to its shape so as not to form a substantially gap with the back surface 1b of the wafer 1. Therefore, as a first stage, as shown in FIG. 11, a wafer stage having a surface formed of, for example, a fluorocarbon resin so as not to damage or contaminate the wafer surface is provided. Note that the protective tape may be re-applied to the surface 1a of the wafer 1, but in this case, the process is complicated), and the wafer 1 is held downward, and the dicing frame 62 attached thereon is provided. With the dicing tape 63 placed, it is housed in a vacuum container 59 sealed with an O-ring 60 and evacuated from the vacuum exhaust hole 61 to be in a vacuum state. An example of the dicing tape 63 is a UV curable tape having a thickness of about 90 micrometers. Moreover, as the dicing frame 62, for example, a stainless steel product having a thickness of about 1.2 millimeters and an inner diameter (diameter of an internal circular opening) of about 250 millimeters can be exemplified.

  Next, as shown in FIG. 12, when the atmosphere is released, only the space surrounded by the circular recess region 8, the annular region 7, and the dicing tape 63 remains in a vacuum, so that the dicing tape 63 expands, Following the shape of the back surface of the wafer 1, it comes into close contact (the step between the circular recess region 8 and the annular region 7 is only about 0.6 mm in this case).

  When the attachment of the dicing tape 63 to the back surface of the wafer 1 is completed, the wafer or other composite composed of the wafer 1, the dicing tape 63, the dicing frame 62, etc. is taken out from the vacuum vessel 59, and the next ring cutting step (annular region) Move to cutting step.

  As shown in FIG. 13, for example, in a state where a composite such as a wafer is set on a wafer back surface holding table 65 (vacuum suction table), an annular region 7 is formed by a rotating blade 64 from the front main surface 1 a side of the wafer 1. And cut along the circumferential boundary of the circular recess region 8.

  That is, as shown in FIGS. 14 and 15, a circular separation groove 10 is formed by cutting along a circumferential boundary between the annular region 7 and the circular recess region 8. As a result, the annular region 7 and the circular recess region 8 are physically separated.

  Next, as shown in FIG. 16, the annular region 7 is separated from the composite such as a wafer by separating the annular region 7 from the dicing tape 63. As a result, only the circular recess region 8 (the wafer inner region), the dicing tape 63 and the dicing frame 62 remain in the composite body such as a wafer. Thereafter, the circular recess region 8 (the wafer inner region) becomes the wafer 1 substantially.

  Next, as shown in FIGS. 17 and 18, the back surface 1 b of the wafer 1 is attached to the dicing tape 63 (the wafer 1 is held by the dicing frame 62 via the dicing tape 63), for example. First, dicing processing is performed by the rotating blade 64 in the Y direction, and the dicing groove 11 is formed. Here, in the stage of FIG. 16, some slack remains in the dicing tape 63, but during dicing, the dicing frame 62 is slightly pushed down, so that the slack is eliminated. Usually, as the dicing method, a full cut method having a cutting depth reaching a part of the dicing tape 63 including the adhesive layer is performed. However, other semi-full cut methods or half cut methods may be used as required. However, the full cut method is most advantageous in terms of less chipping and ease of pickup.

  Next, as shown in FIGS. 19 and 20, with the back surface 1b of the wafer 1 attached to the dicing tape 63 (the wafer 1 is held by the dicing frame 62 via the dicing tape 63), X The dicing process is performed by the rotating blade 64 in the direction, and the X direction dicing groove 11 is further formed.

  As a result, the plurality of semiconductor chip regions are separated into individual semiconductor chips.

2. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

  For example, in the above-described embodiment, the power semiconductor device has been mainly described as an example. However, the present invention is not limited thereto, and a general semiconductor integrated circuit device (without a back surface metal electrode) It is needless to say that the present invention can be applied almost similarly.

  Further, in the above-described embodiment, specific description has been made by taking mainly rotating blade dicing as an example of dicing, but the present invention is not limited thereto, and is similarly applied to dicing using a laser. Needless to say, you can.

1 Wafer 1a First main surface (front side main surface) of wafer
1b Second main surface of wafer (back side main surface)
2 Semiconductor chip area (semiconductor chip)
3 Notch 4 Main part of semiconductor element 5 Surface protective tape (surface protective adhesive sheet)
6 Target grinding thickness 7 Wafer peripheral area (annular area)
8 Wafer internal area (circular recess area)
9 Back side metal electrode 10 Circular separation groove 11 Dicing groove 51 Grinding wheel 52 Grinding blade 53 Grinding blade holding plate 54 Spin table 55 Chemical solution nozzle 56 Etching solution 57 Ring-shaped susceptor 58 Wafer surface protection stage 59 Vacuum vessel 60 O-ring 61 Vacuum exhaust Hole 62 Dicing frame 63 Dicing tape 64 Rotating blade 65 Wafer back surface holding table 66 Dicing table

Claims (10)

A semiconductor device manufacturing method including the following steps:
(A) forming a plurality of semiconductor chip regions on the first main surface side of the wafer;
(B) After the step (a), a step of attaching a protective tape to the first main surface of the wafer;
(C) An annular region having a first thickness is formed in a peripheral portion on the second main surface side of the wafer in a state where the protective tape is attached to the first main surface of the wafer. Forming a circular recess region having a second thickness smaller than the first thickness in an inner region of the second main surface;
(D) a step of removing the protective tape after the step (c);
(E) a step of forming a metal film on the second main surface of the wafer after the step (d);
(F) After the step (e), a step of attaching a dicing tape to the second main surface of the wafer so as to follow the shape;
(G) separating the annular region from the inner region and the dicing tape in a state where the dicing tape is attached to the second main surface of the wafer;
(H) After the step (g), the dicing process is performed on the wafer in a state where the dicing tape is attached to the second main surface of the wafer. A process of separating the chip area into individual semiconductor chips.     In the method of manufacturing a semiconductor device according to the item 1, the peripheral portion of the dicing tape is fixed to a dicing frame in the step (h).     In the method of manufacturing a semiconductor device according to the item 1, the peripheral portion of the dicing tape is fixed to a dicing frame in the steps (f) to (h).     In the method for manufacturing a semiconductor device according to the item 3, the step (f) is performed in a vacuum vessel.     In the method of manufacturing a semiconductor device according to the item 4, the step (c) is performed by partially grinding the second main surface of the wafer.     In the method of manufacturing a semiconductor device according to the item 5, in the step (g), the annular region is separated from the inner region by a rotating blade.     In the method of manufacturing a semiconductor device according to item 6, the dicing process in the step (h) is executed by a rotating blade.     In the method for manufacturing a semiconductor device according to the item 7, the step (e) is performed by sputtering film formation. The method for manufacturing a semiconductor device according to the item 8, further includes the following steps:
(I) A step of performing stress relief treatment on the second main surface of the wafer after the step (c) and before the step (d).     In the method for manufacturing a semiconductor device according to the item 9, the stress relief process is a wet etching process.

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