JP2011216606A - Method of manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a thin film transistor in which a gate electrode and a source drain electrode are formed with high alignment precision and the source-drain electrode is patterned with high precision without performing a lift-off step.SOLUTION: On a translucent substrate, a light-shielding gate electrode, a translucent insulating layer, an oxide semiconductor layer and a translucent conductive layer are formed in order. Then, a reversal type resist film or negative type resist film is provided on the conductive layer, and image reversal processing is performed when the reversal type resist film is provided after exposure is performed from the substrate side, or the exposure is performed from the substrate side when the negative type resist film is provided. Then, the resist film is developed to form a resist pattern, having an opening at a position corresponding to the gate electrode, on the conductive layer. The conductive layer is etched through the opening of the resist pattern to divide the conductive layer, thereby forming a source electrode and a drain electrode.

Description

  The present invention relates to a method for manufacturing a thin film transistor.

When manufacturing an electronic device such as an organic electroluminescence (organic EL) display device, a liquid crystal display device, an X-ray imaging device, etc., a thin film transistor (TFT) and a capacitor are manufactured on a support substrate, and then, according to the electronic device to be manufactured. Electrodes and functional layers are formed.
For example, when a bottom-gate thin film transistor is manufactured, a gate electrode, an insulating layer (gate insulating film), a silicon semiconductor layer (active layer), and a source / drain electrode are sequentially formed and patterned on a glass substrate.
On the other hand, attempts have been made to use a lightweight and flexible resin substrate instead of a glass substrate in order to further reduce the thickness, weight, and breakage resistance of electronic devices.
However, the manufacture of a thin film transistor using the above-described silicon semiconductor layer as an active layer requires a relatively high temperature heat treatment step and is generally difficult to form directly on a resin substrate having low heat resistance.

  An oxide semiconductor film has been proposed as a semiconductor material replacing the silicon thin film constituting the active layer. For example, an In—Ga—Zn—O-based amorphous oxide can be formed at a low temperature, and has attracted attention as a material that can be formed on a resin substrate at room temperature. Since a thin film transistor using an In—Ga—Zn—O-based amorphous oxide as an active layer has higher mobility than a thin film transistor using amorphous silicon as an active layer, a thin film transistor for a flexible electronic device As being considered.

However, the resin substrate has a problem that the alignment accuracy is liable to be reduced due to a change in dimensions due to heat and a solvent in the manufacturing process of the thin film transistor.
Therefore, as a method of manufacturing a thin film transistor having an oxide semiconductor layer using a resin substrate, for example, using a gate electrode as a mask, partially irradiating the oxide semiconductor layer with ultraviolet light reduces the sheet resistance value. Has proposed a method of forming a source region and a drain region electrically connected to the source / drain electrodes in a self-aligned manner (see Patent Document 1).

  Further, a gate electrode, an oxide semiconductor layer, and a gate insulating layer are sequentially formed on a resin substrate, a positive resist is applied on the gate insulating layer, exposure is performed from the substrate side using the gate electrode as a mask, development, A method of forming a source / drain electrode in a self-aligned manner by forming a metal film to be a drain electrode and then removing the resist film by a lift-off process has been proposed (see Patent Document 2).

JP 2009-111125 A JP 2006-165527 A

  The present invention provides a method of manufacturing a thin film transistor that can form a gate electrode and a source / drain electrode with high alignment accuracy and can pattern the source / drain electrode with high accuracy without performing a lift-off process. With the goal.

In order to achieve the above object, the following present invention is provided.
<1> A step of forming a light-shielding gate electrode on a part of a light-transmitting substrate, a step of forming a light-transmitting insulating layer on the substrate and the gate electrode, and the insulating layer Forming a part of the oxide semiconductor layer so as to straddle the gate electrode via the insulating layer, and a part of the oxide semiconductor layer so as to straddle the gate electrode via the oxide semiconductor layer A step of forming a light-transmissive conductive layer; and an inversion-type resist film or a negative-type resist film is provided on the conductive layer, and when the inversion-type resist film is provided, after exposure from the substrate side In the case where an image reversal process is performed and the negative resist film is provided, exposure is performed from the substrate side, and then the resist film is developed, so that the resist film is developed at a position corresponding to the gate electrode. Resist pattern with openings A method of manufacturing a thin film transistor, comprising: forming a source electrode and a drain electrode by dividing the conductive layer by etching the conductive layer through the opening of the resist pattern.
<2> The method for producing a thin film transistor according to <1>, wherein the entire surface is exposed from the resist film side as the image inversion processing.
<3> Used when etching the conductive layer in the step of forming the source electrode and the drain electrode between the step of forming the conductive layer on the oxide semiconductor layer and the step of forming the resist pattern. The manufacturing method of the thin-film transistor as described in <1> or <2> including the process of forming the protective layer which protects the said oxide semiconductor layer from the etching liquid to perform.
<4> The method for producing a thin film transistor according to any one of <1> to <3>, wherein a resin substrate is used as the substrate.

  According to the present invention, there is provided a thin film transistor manufacturing method capable of forming a gate electrode and a source / drain electrode with high alignment accuracy and patterning the source / drain electrode with high accuracy without performing a lift-off process. Is done.

1 schematically shows an example (first half) of a process of manufacturing a thin film transistor according to the present invention. 1 schematically shows an example (second half) of a method of manufacturing a thin film transistor according to the present invention. It is the schematic which shows the cross-sectional shape of the opening part of the resist pattern formed by this invention.

Hereinafter, the present invention will be specifically described with reference to the accompanying drawings.
The method of manufacturing a thin film transistor according to the present invention includes a step of forming a light-shielding gate electrode on a part of a light-transmitting substrate, and a step of forming a light-transmitting insulating layer on the substrate and the gate electrode. And forming a part of the oxide semiconductor layer on the insulating layer so as to straddle the gate electrode through the insulating layer, and the oxide semiconductor layer on the oxide semiconductor layer through the oxide semiconductor layer. When forming a light-transmitting conductive layer that overlaps across the gate electrode, and providing an inverted resist film or negative resist film on the conductive layer, and providing the inverted resist film, After exposure from the substrate side, image reversal processing is performed, and when the negative resist film is provided, exposure is performed from the substrate side, and then the resist film is developed to form the resist film on the conductive layer. The position corresponding to the gate electrode And forming a source electrode and a drain electrode by dividing the conductive layer by etching the conductive layer through the opening of the resist pattern. .

  1 and 2 schematically show an example of steps of a method for manufacturing a thin film transistor according to the present invention. In the following description, in the step of forming a resist pattern, a case where an inversion type resist film is provided will be mainly described. However, a negative resist may be used.

<Formation of gate electrode>
A light-blocking gate electrode 12 is formed on a part of the light-transmitting substrate 10 (FIG. 1A).

-Light transmissive substrate-
First, as the substrate (support) 10 on which the thin film transistor 100 is formed, at least the surface on which the thin film transistor 100 is formed has an insulating property in addition to light transmittance, and further, dimensional stability, solvent resistance, workability, It is preferable to use one having heat resistance.

As the substrate 10 satisfying the above conditions, an inorganic material such as glass or zirconia stabilized yttrium oxide (YSZ) is suitable. In addition, in order to reduce the elution ion from glass, it is preferable to use an alkali free glass. When soda lime glass is used, it is preferable to use an inorganic insulating film such as a SiO ₂ , SiON, or SiN film or a barrier coating such as a multilayer film thereof.

Further, a resin substrate made of an organic material may be used. For example, polyesters such as polyethylene terephthalate, polybutylene terephthalate, polyethylene naphthalate (PEN), polystyrene, polycarbonate, polyethersulfone, polyarylate, allyl diglycol carbonate, polyimide, polycycloolefin, norbornene resin, poly (chlorotrifluoroethylene) ) And other organic materials such as synthetic resins.
Although the resin substrate made of an organic material is easily deformed by heat, a solvent, or the like, in the present invention, an oxide semiconductor layer that can be formed at a low temperature by a sputtering method or the like is formed as an active layer, and the source / drain electrodes 18A. , 18B are formed in a self-aligning manner, high alignment accuracy can be achieved even if the substrate is somewhat expanded or contracted during the manufacturing process.
In the case of using a resin substrate, an inorganic layer such as SiO ₂ , SiN, or SiON or a multilayer structure of an organic thin film or an inorganic thin film is formed as a barrier layer on at least one surface in order to suppress permeation of oxygen and moisture. It is preferable.

The shape, structure, size, thickness and the like of the substrate 10 are not particularly limited and may be appropriately selected according to the purpose. In general, the shape of the substrate 10 is preferably a plate shape from the viewpoints of handleability, ease of forming a thin film transistor, and the like. The structure of the substrate 10 may be a single layer structure or a laminated structure.
Moreover, the board | substrate 10 may be comprised by the single member and may be comprised by two or more members.

-Gate electrode-
The gate electrode 12 formed on the substrate 10 controls a current between the source / drain electrodes 18A and 18B through the oxide semiconductor layer 16 by application of a voltage.
The gate electrode 12 is formed so as not to transmit light used for exposure from the substrate side in the step of forming the resist pattern 22. The material constituting the gate electrode 12 depends on the thickness, but for example, a metal such as Cu, Al, Mo, Cr, Ta, Ti, Au, or Ag, an alloy such as Al—Nd, APC, or tin oxide Preferred examples include metal oxide conductive films such as zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof. Of these materials, when exposed from the substrate side by the back exposure method, a laminated structure of materials that are opaque to the exposure light is configured so that the light used for exposure does not pass through the gate electrode. In some cases.
For example, a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, or an ion plating method, a chemical method such as a CVD or a plasma CVD method, etc. The film is formed according to a method appropriately selected in consideration of suitability, the material of the substrate 10 and the like.

After film formation, patterning is performed into a predetermined shape by photolithography. At this time, the gate electrode 12 and the gate wiring are simultaneously patterned.
The thickness of the gate electrode 12 is, for example, 10 nm or more from the viewpoint of preventing the exposure light from the substrate side from being transmitted in the step of forming the resist pattern 22 and reducing the resistance of the gate wiring and preventing the delay of the control signal of the thin film transistor. From the viewpoint of preventing breakage by reducing the level difference of each layer formed on the gate electrode 12, the thickness is set to 1000 nm or less.

<Formation of insulating layer>
After the gate electrode 12 is formed over the substrate 10, a light-transmitting insulating layer (gate insulating layer) 14 is formed over the substrate 10 and the gate electrode 12 (FIG. 1B).
The gate insulating layer 14 is formed so as to transmit exposure light from the substrate side in the step of forming the resist pattern 22. Material of the gate insulating layer 14, depending on its thickness, for example _{SiO 2, SiN x, SiON,} Al 2 O 3, Y 2 O 3, Ta 2 O 5, an insulating material such as HfO ₂ and the like, they It is good also as an insulating layer containing 2 or more types of these compounds. Alternatively, a polymer insulator such as polyimide may be used.
For example, suitability for materials used from wet methods such as printing methods, coating methods, physical methods such as vacuum deposition methods, sputtering methods, ion plating methods, chemical methods such as CVD and plasma CVD methods, etc. Is formed on the gate electrode 12 and the substrate 10 in accordance with a method selected appropriately, and is patterned into a predetermined shape by a photolithography method and a shadow mask method as necessary.

  The thickness of the gate insulating layer 14 needs to have a thickness for suppressing leakage current and improving the voltage resistance. On the other hand, if the thickness of the gate insulating layer 14 is too large, the light transmittance is lowered and the driving voltage is increased. I will. Although depending on the material of the gate insulating layer 14, from the viewpoint of light transmission, time required for film formation and voltage resistance, the thickness of the gate insulating layer 14 is, for example, 50 nm or more and 1000 nm or less for an inorganic insulator. In the case of a polymer insulator, the thickness is set to several nm or more and 5 μm or less in consideration of the self-assembled film.

<Formation of oxide semiconductor layer>
After the insulating layer 14 is formed, an oxide semiconductor layer 16 is formed on a part of the insulating layer 14 so as to overlap the gate electrode 12 with the insulating layer 14 interposed therebetween.
The oxide semiconductor layer 16 is light transmissive and transmits exposure light from the substrate side in the step of forming the resist pattern 22. The material forming the oxide semiconductor layer 16 is preferably an amorphous oxide semiconductor. Since an amorphous oxide semiconductor can be formed at a low temperature, it can be formed over a flexible resin substrate such as plastic.
An amorphous oxide semiconductor containing at least one of In, Ga, Zn, and Sn is preferable, and an amorphous oxide semiconductor containing In or Zn is more preferable. As an amorphous oxide semiconductor that can be formed at a low temperature, an oxide containing In, an oxide containing In and Zn, and an oxide containing In, Ga, and Zn can be given. As the composition, an oxide containing any one of In, Ga, or Zn, or two or all three types is preferable. These are n-type semiconductors whose carriers are electrons. Note that a p-type oxide semiconductor such as ZnO.Rh ₂ O ₃ , CuGaO ₂ , or SrCu ₂ O ₂ may be used for the active layer 16, or an oxide semiconductor disclosed in Japanese Patent Application Laid-Open No. 2006-165529. May be used.

An oxide containing an In, Ga, and Zn oxide is preferable, and an amorphous oxide semiconductor is preferable, and an oxide having a composition close to that of InGaZnO ₄ (referred to as “IGZO” as appropriate) is more preferable. When it is formed at a low temperature, it becomes a compound containing In, Ga, and Zn in an amorphous state, and the composition ratio does not become an integer composition like a crystal but has various arbitrary values. As a feature of the amorphous oxide semiconductor having this composition, the electron mobility tends to increase as the electrical conductivity increases. In order to control the electrical conductivity, it can be controlled by the oxygen partial pressure during film formation.
The thickness of the oxide semiconductor layer 16 is such that exposure light from the substrate side is transmitted in the step of forming the resist pattern 22 and that the drain current sufficiently flows and the time required for film formation is not excessively long. From the viewpoint, for example, the thickness is 5 nm or more and 150 nm or less.
In addition, the electrical conductivity of the oxide semiconductor layer 16 is preferably 10 ⁻¹¹ Scm ⁻¹ or more and less than 10 ⁻⁷ Scm ⁻¹ in order to function as an active layer.

  In the case of forming an IGZO layer, for example, as the oxide semiconductor layer 16, the oxide semiconductor layer 16 is formed using a vapor phase deposition method using a polycrystalline sintered body of an oxide semiconductor containing In, Ga, and Zn in a target composition as a target. . Among the vapor phase film forming methods, the sputtering method and the pulse laser deposition method (PLD method) are more preferable, and the sputtering method is particularly preferable from the viewpoint of mass productivity. The oxide semiconductor layer 16 is processed into a desired region by a photolithography technique and an etching technique.

<Formation of protective layer>
After the oxide semiconductor layer 16 is formed, the conductive layer 18 is formed, but before that, a protective layer (not shown) may be formed over the oxide semiconductor layer 16. This protective layer protects the oxide semiconductor layer 16 from an etching solution used when the conductive layer 18 is etched. The protective layer preferably has an etching rate as slow as possible with respect to an etching solution for etching the conductive layer 18. Specific examples of the material constituting the protective layer include gallium oxide, TiO, SiO ₂ , and Si ₃ N ₄ . When a protective layer is introduced, a resist is applied before the conductive layer 18 is formed, and then back exposure is performed from the substrate side, and then a step of removing the protective layer other than on the gate electrode 12 is performed. Thereby, the conductive layer 18 and the semiconductor layer 16 are directly connected. However, this step may not be required depending on the thickness of the protective layer itself and the resistance value.

<Formation of conductive layer>
A light-transmitting conductive layer 18 is formed over the oxide semiconductor layer 16 so as to straddle the gate electrode 12 with the oxide semiconductor layer 16 interposed therebetween (FIG. 1C).
This conductive layer 18 will later constitute source / drain electrodes 18A, 18B. The conductive layer 18 is formed with a light-transmitting material and thickness so as to transmit exposure light from the substrate side in the step of forming the resist pattern 22 after forming a desired wiring pattern by a photolithography process and an etching process. To do. Specific materials include metals such as Cu, Al, Mo, Cr, Ta, Ti, Au, and Ag, alloys such as Al-Nd and APC, tin oxide, zinc oxide, indium oxide, and indium tin oxide (ITO). And metal oxide conductive films such as zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or a mixture and laminated film thereof. ITO and IZO are particularly preferable from the viewpoint of light transmittance, but the metal layer may be thinned and laminated with a metal oxide conductive film.
Although the thickness of the conductive layer 18 varies depending on the material, it is set to, for example, 10 nm to 1000 nm in consideration of film forming property, conductivity (reduction in resistance), etc. in addition to light transmission.

The film forming method is not particularly limited, and can be selected from a printing method, a wet method such as a coating method, a physical method such as a vacuum deposition method, a sputtering method, and an ion plating method, and a chemical method such as CVD and plasma CVD method. The film may be formed according to a method selected in consideration of suitability for the material.
For example, when an ITO layer is formed, it can be formed according to a direct current or high frequency sputtering method, a vacuum deposition method, an ion plating method, or the like. When an organic conductive compound is selected, it is performed according to a wet film formation method. be able to.

<Formation of resist pattern>
An inversion-type resist film 20 is provided on the conductive layer 18, and after exposure from the substrate side, an image inversion process is performed. Next, by developing the resist film 20, a resist pattern 22 having an opening 24 at a position corresponding to the gate electrode 12 is formed on the conductive layer 18.

-Reversal resist-
An inversion type resist (referred to as “inversion resist” as appropriate) is applied onto the conductive layer 18 by, for example, spin coating to form the resist film 20.
As the reversal resist, a resist capable of obtaining a positive image or a negative image (positive / negative reversal) depending on the presence or absence of a specific treatment after exposure is used. Specific treatment after exposure varies depending on the type of resist, but includes heating, exposure with light of other wavelengths, atmosphere, treatment with a developer, and the like. From the viewpoint of further improving the resolution of the resist pattern 22 obtained after development, a reverse resist capable of obtaining a positive image or a negative image depending on the exposure method (irradiation wavelength) is particularly preferable. Examples of commercially available reverse resist include AZ5214E (manufactured by AZ Electronic Materials Co., Ltd.).

-exposure-
After the resist film 20 is formed over the conductive layer 18, exposure is performed from the substrate side (FIG. 1D). As the exposure light source, for example, a high-pressure mercury lamp, deep-UV, or the like can be used depending on the type of resist. It is preferable to use a high-pressure mercury lamp as a light source from the viewpoint of simplicity of the exposure operation.
When exposed from the substrate side, the substrate 10, the insulating layer 14, the oxide semiconductor layer 16, and the conductive layer 18 transmit light, but the gate electrode 12 does not transmit light and functions as a mask. As a result, a positive image is formed on the resist film 20 so that the exposed portion can be removed by development processing.

Next, the entire surface is exposed from the resist film side (FIG. 2A). As the exposure light source, for example, AZ5214E can be used although it depends on the reverse resist to be used. It is preferable to use a high-pressure mercury lamp as a light source from the viewpoint of easy exposure operation.
When the entire surface is exposed from the resist film side, the positive / negative is reversed, and a negative image is formed on the resist film 20.

-developing-
The resist film 20 exposed from the substrate side and the resist film side as described above is developed with a resist developer. Thereby, a resist pattern 22 having an opening 24 at a position corresponding to the gate electrode 12 is formed on the conductive layer 18 (FIG. 2B).
If positive / negative reversal is performed using a reversal resist in this way, no special processing is required in the development and peeling processes, and as shown in FIG. 2B, the resist pattern 22 has a width on the conductive layer side as the gate electrode. An opening 24 having a cross-sectional shape inclined so as to be narrower than the width of 12 is formed.
In the case of using a negative resist, a negative resist film is provided on the conductive layer 18, and after exposure from the substrate side, the resist film 20 is developed to correspond to the gate electrode 12 on the conductive layer 18. A resist pattern having an opening at a position can be formed.

<Formation of source / drain electrodes>
After the resist pattern 22 is formed, the conductive layer 18 is etched through the opening 24 of the resist pattern 22, thereby dividing the conductive layer 18 to form the source electrode 18A and the drain electrode 18B (FIG. 2C). ).
The etchant may be selected according to the material constituting the conductive layer 18. For example, in the case of an ITO layer, etching may be performed using oxalic acid. The conductive layer 18 is divided by etching to form source / drain electrodes 18A and 18B. Note that if a protective layer is provided at a position corresponding to the opening 24 of the resist pattern 22 on the oxide semiconductor layer 16, the oxide semiconductor layer 16 functions as an etching stopper. In this case, etching of the oxide semiconductor layer 16 after the conductive layer 18 is etched can be suppressed.

  Here, the conductive layer 18 exposed from the opening 24 of the resist pattern 22 is etched. As shown in FIG. 3, the width of the opening 24 on the conductive layer 18 side is narrower than the width of the gate electrode 12. Thus, the region to be etched is at least narrower than the width of the gate electrode 12. Therefore, the source / drain electrodes 18A and 18B overlap the gate electrode 12 via the insulating layer 14 and the oxide semiconductor layer 16, and the source / drain is passed through the oxide semiconductor layer 16 by applying a voltage to the gate electrode 12. Switching between the electrodes 18A and 18B can be performed.

  Further, since the source / drain electrodes 18A and 18B are formed by photolithography and etching, there is a problem in the case of forming the source / drain electrodes by a lift-off method using a general positive resist, that is, residual by a lift-off process. Problems such as a reduction in yield due to adhesion of resist and exfoliated material, and a low tact process derived from the lift-off process can be solved.

  Through the above steps, the thin film transistor 100 is manufactured. According to the method of the present invention, since the source / drain electrodes 18A, 18B are formed in a self-aligned manner, the alignment accuracy is high, and the source / drain electrodes 18A, 18B are patterned by photolithography and etching instead of lift-off. Therefore, the source / drain electrodes 18A and 18B having high patterning accuracy can be formed.

<Subsequent steps>
After patterning the conductive layer 18 into the source / drain electrodes 18A and 18B, the resist pattern 22 is removed as required (FIG. 2D).
Furthermore, pixel electrodes, other functional layers, and the like are formed according to the electronic device to be manufactured. For example, in the case of manufacturing an organic EL display device, an interlayer insulating film (planarization layer), an organic EL element, and the like are sequentially formed and then sealed. Alternatively, when manufacturing a radiation imaging apparatus, an interlayer insulating film (planarization layer), a charge collection electrode, a photoelectric conversion layer (charge generation layer, charge transport layer), a bias electrode, a phosphor layer, and the like may be sequentially stacked. .

  Hereinafter, examples will be described, but the present invention is not limited thereto.

<Example 1>
On a resin substrate (material: PEN) provided with a barrier layer (material: organic film / inorganic film laminated structure, thickness: 2 μm) on one side, a Mo film (40 nm) is formed by sputtering, and by photolithography and etching. A gate electrode and a gate wiring were formed.
Next, a SiO ₂ film (thickness: 200 nm) was formed as a gate insulating layer by sputtering.
After forming an IGZO film (thickness: 50 nm) on the gate insulating layer, the IGZO film was patterned by photolithography and etching to form an active layer across the gate electrode through the gate insulating layer.

Next, an ITO layer (thickness: 100 nm) was formed on the active layer and the gate insulating layer by a sputtering method. Thereafter, a desired wiring pattern was formed by photolithography.
Next, an inverted resist film was formed on the ITO layer by spin coating using AZ5214E (manufactured by AZ Electronic Materials Co., Ltd.).
After pre-baking (90 ° C., 15 minutes), exposure from the substrate side (g-line, wavelength: 436 nm, exposure time: 6 seconds), reverse baking (90 ° C., 15 minutes), entire exposure from the resist film side (g Line, wavelength: 436 nm, exposure time: 20 seconds). Next, development (AZ-300MIF developer 120 seconds), pure water rinsing, and post-baking (120 ° C., 30 minutes) were performed. Thereby, a resist pattern having an opening at a position corresponding to the Mo layer (gate electrode and gate wiring) was formed.

Next, the ITO layer was etched using oxalic acid. The ITO layer was divided at positions corresponding to the openings of the resist pattern by etching while paying attention to selectivity with the active layer, and source / drain electrodes were formed. Thereby, a thin film transistor was formed.
When a protective layer such as SiO ₂ , SiN, or GaO is formed on the active layer, the protective layer remains only on the active layer corresponding to the position of the gate electrode / wiring before forming the S / D conductive layer. In some cases, back exposure is performed using the gate electrode / wiring layer as a mask, and the protective layer is left only at a desired position on the active layer to act as an etching stopper.

<Comparative Example 1>
As in Example 1, a gate electrode (gate wiring), a gate insulating layer, and an active layer (IGZO) were sequentially formed on the substrate.
Next, using TSMR8900 (manufactured by Tokyo Ohka Kogyo Co., Ltd.) as a lift-off resist, a resist film is formed on the gate insulating layer and the active layer, and after the exposure from the substrate side, the entire exposure from the resist film side is not performed. Developed. As a result, a resist pattern was formed on the gate electrode and the gate wiring.
Next, an ITO layer (thickness: 100 nm) was formed by a sputtering method. Thereafter, lift-off was performed, and the source / drain electrodes were patterned.

-Evaluation-
The thin film transistors manufactured in Example 1 and Comparative Example 1 were evaluated as follows. In Example 1, 10 elements (TFTs) were assigned Id vs.. Vg characteristics were measured to obtain approximately the same characteristics, but in Comparative Example 1, 3 out of 10 did not operate. As a result of examination, in the case of Comparative Example 1, the lift-off was incomplete, and there were portions where the source / drain electrodes could not be formed. As a result of investigating the cause, the cross-sectional shape in the thickness direction of the resist remaining on the gate by the self-alignment method needs to be an inverted trapezoidal shape, that is, a shape where the upper side is larger than the lower side, in order to ensure lift-off In Comparative Example 1, since the resist cross-sectional shape is a trapezoidal shape in which the upper side is smaller than the lower side, the lift-off is not completely performed, and the S / D wiring remains connected, and the yield of the lift-off is increased. I found it bad. There was also a problem that the lifted-off resist adhered to the glass substrate and could not be removed well.

As mentioned above, although this invention was demonstrated, this invention is not limited to the said embodiment and Example. For example, the use of a substrate including a thin film transistor manufactured by the method according to the present invention is not limited to the manufacture of an organic EL display device or a radiation imaging device, and other electronic devices driven by thin film transistors such as a liquid crystal display device and electronic paper. You may apply to manufacture of.
Moreover, when manufacturing a radiation imaging device, you may apply not only to the indirect type | mold provided with the fluorescent substance layer and the organic photoelectric converting layer but to the direct conversion type | mold manufacturing provided with the fluorescent substance layer.

DESCRIPTION OF SYMBOLS 10 Substrate 12 Gate electrode 14 Insulating layer 16 Oxide semiconductor layer 18A Source electrode 18B Drain electrode 18 Conductive layer 20 Resist film 22 Resist pattern 24 Opening 100 Thin film transistor

Claims (4)

Forming a light-shielding gate electrode on a part of a light-transmitting substrate;
Forming a light-transmissive insulating layer on the substrate and the gate electrode;
Forming an oxide semiconductor layer overlapping a part of the insulating layer so as to straddle the gate electrode through the insulating layer;
Forming a light-transmitting conductive layer on the oxide semiconductor layer so as to overlap the gate electrode through the oxide semiconductor layer;
When an inversion type resist film or a negative type resist film is provided on the conductive layer, and the inversion type resist film is provided, the negative resist is subjected to image inversion processing after exposure from the substrate side. Forming a resist pattern having an opening at a position corresponding to the gate electrode on the conductive layer by exposing from the substrate side when the film is provided, and then developing the resist film;
Etching the conductive layer through the opening of the resist pattern to divide the conductive layer to form a source electrode and a drain electrode;
A method of manufacturing a thin film transistor including:   The method for manufacturing a thin film transistor according to claim 1, wherein the entire surface is exposed from the resist film side as the image inversion process.   Etching solution used when etching the conductive layer in the step of forming the source electrode and the drain electrode between the step of forming the conductive layer on the oxide semiconductor layer and the step of forming the resist pattern The manufacturing method of the thin-film transistor of Claim 1 or Claim 2 including the process of forming the protective layer which protects the said oxide semiconductor layer from.   The method for manufacturing a thin film transistor according to claim 1, wherein a resin substrate is used as the substrate.

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