JPH0661257A - Thin film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To restrain parasitic capacity generated between a gate electrode, and a source electrode and a drain electrode. CONSTITUTION:A gate electrode 2 is formed on a glass substrate 1 and an SiNx-based insulation layer 3, an a-Si: H-based channel layer 4 and an n-type impurity doped layer 5 are formed thereon. A transparent electrode layer 6 and a negative type resist layer 7 are formed, back exposure is carried out from a lower surface side of the glass substrate 1 and shadow of the gate electrode 2 is formed in a resist layer. A non-exposure part 7b is removed by developing the resist layer, the transparent electrode layer 6 is etched using an exposure part 7a as a mask and a source electrode and a drain electrode are formed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method of a thin film transistor, and more particularly to a manufacturing method capable of suppressing generation of parasitic capacitance.

[0002]

2. Description of the Related Art Thin film transistors have high utility value especially in the field of liquid crystal displays, and the demand for thin film transistors is expected to increase in the future. A thin film transistor is usually a device in which a gate electrode is formed on a glass substrate, and a source electrode and a drain electrode and a channel layer made of an intrinsic semiconductor are formed on the gate electrode with an insulating layer interposed therebetween. The channel layer is a region formed between the source electrode and the drain electrode, and by controlling the voltage applied to the gate electrode, the channel layer can be brought into a conductive state or a non-conductive state, It is possible to operate as a switching element in which the source electrode and the drain electrode are turned on / off.

When such a thin film transistor is applied to a liquid crystal display, each transistor is arranged vertically and horizontally in a matrix so that one transistor corresponds to one pixel. Then, for example, by extending the gate electrode in the horizontal direction of this matrix, extending the drain electrode in the vertical direction of this matrix, and connecting the source electrode to the display electrode corresponding to each pixel, by combining the gate electrode and the drain electrode, It becomes possible to control the potential of the display electrode corresponding to an arbitrary pixel.

[0004]

The gate electrode, the source electrode, and the drain electrode forming the thin film transistor are naturally made of a conductive material (usually a metal). Moreover, the structure is such that the source electrode and the drain electrode are formed with the insulating layer interposed between the gate electrode and the gate electrode. Therefore, the gate electrode is
A capacitive element using the electrode, the source electrode, and the drain electrode as the second electrode is formed, which causes parasitic capacitance on the circuit. Such parasitic capacitance has the effect of deforming the waveform of the gate pulse applied to the gate electrode, and behaves unfavorably in the operation of the thin film transistor.

In order to suppress the influence of such parasitic capacitance, normally, another capacitance element called a storage capacitance is intentionally formed. However, when such a storage capacitor is provided, the structure becomes complicated, and another adverse effect that the aperture ratio of the display electrode is reduced occurs.

Therefore, an object of the present invention is to provide a method of manufacturing a thin film transistor capable of suppressing the parasitic capacitance generated between the gate electrode and the source and drain electrodes.

[0007]

[Means for Solving the Problems] (1) A first invention of the present application is a thin film transistor in which a source electrode, a drain electrode, and a gate electrode are formed on a substrate, when a pattern of each electrode is projected on the upper surface of the substrate. In addition, there is no overlap between the projected pattern of the source electrode and the projected pattern of the gate electrode and between the projected pattern of the drain electrode and the projected pattern of the gate electrode.

(2) A second invention of the present application is, in a method of manufacturing a thin film transistor, irradiating light from a substrate side when patterning a source electrode and a drain electrode,
The exposure is performed using the gate electrode as a mask.

(3) A third invention of the present application is a method of manufacturing a thin film transistor, wherein a step of forming an opaque gate electrode on an upper surface of a transparent substrate, and a transparent semiconductor layer on the step of forming an opaque gate electrode. A step of sequentially forming a channel layer and a transparent impurity-doped layer, a transparent electrode layer is formed thereon, a resist layer is formed on the transparent electrode layer, and light is irradiated from the lower surface side of the substrate, Using the gate electrode as a mask, exposing the resist layer, developing the resist layer, removing the unexposed portion, using the exposed portion of the resist layer as a mask, etching the transparent electrode layer,
The step of forming the facing portion of the source electrode and the drain electrode and the step of patterning the transparent electrode layer to form a portion other than the facing portion of the source electrode and the drain electrode are performed.

(4) A fourth invention of the present application is the method of manufacturing a thin film transistor according to the second invention, wherein the step of forming an auxiliary wiring layer for electrically connecting the drain electrodes of the plurality of thin film transistors is performed. This is done further.

(5) A fifth invention of the present application is a method of manufacturing a thin film transistor, wherein when patterning a gate electrode, light is irradiated from a substrate side to perform exposure using a source electrode and a drain electrode as a mask. It is the one.

(6) A sixth aspect of the invention of the present application is the step of forming an opaque source electrode and a drain electrode on the upper surface of a transparent substrate in a method of manufacturing a thin film transistor, and a transparent insulating layer formed on the opaque source electrode and drain electrode. The step of forming a transparent semiconductor channel layer, the step of forming a transparent electrode layer on this, the step of forming a resist layer on this transparent electrode layer, and the step of irradiating light from the lower surface side of the substrate to the source electrode and drain. Using the electrode as a mask, exposing the resist layer, developing the resist layer and removing the non-exposed portion, and using the exposed portion of the resist layer as a mask, the transparent electrode layer is etched to remove both sides of the gate electrode. The step of forming a portion and the step of patterning the transparent electrode layer to form a portion other than both side portions of the gate electrode are performed.

[0013]

[Operation] The cause of parasitic capacitance is that the source electrode and the drain electrode partially cover the gate electrode. This is because the patterning of the gate electrode and the patterning of the source electrode and the drain electrode are performed by photolithography using completely different masks. The point of the method according to the present invention is that in a so-called bottom gate type thin film transistor, patterning of the source electrode and the drain electrode is performed by photolithography using the already formed gate electrode itself as a mask. In the thin film transistor, the gate electrode is patterned by photolithography using the already formed source electrode and drain electrode as a mask. Since each electrode itself serves as a mask, so-called self-alignment is performed, and the source electrode and drain electrode are not covered by the gate electrode. As described above, in order to enable photolithography using the electrode itself as a mask, a transparent electrode layer is used as an electrode layer to be a mask electrode, and back exposure is performed by irradiating light from the substrate side.

[0014]

The present invention will be described below based on illustrated embodiments. FIG. 1 is a top view showing a state in which a plurality of thin film transistors are arranged in a matrix when the thin film transistors are used in a general liquid crystal display. The portion shown by the solid line in the drawing is the gate electrode G. The gate electrode G is composed of a main portion which extends in the horizontal direction of the drawing and corresponds to the scanning line of the display, and a gate portion which extends downward from the main portion and acts as a gate for each transistor element. There is. On the other hand, the portion shown by the broken line in the drawing is the drain electrode D, and this drain electrode D extends in the vertical direction of the drawing and functions as the data line of the display. In this way, a large number of squares are formed by the plurality of gate electrodes G arranged in the horizontal direction and the plurality of drain electrodes D arranged in the vertical direction, and the display electrodes E (indicated by a chain double-dashed line in the figure) are formed in each square. Shown) are formed. Each source electrode S (shown by a chain line in the figure) is formed so as to make electrical contact with each display electrode E, and the active layer A is provided between each source electrode S and the drain electrode D. (Indicated by a dotted line in the figure) are formed. The gate portion of the gate electrode G overlaps with each active layer A.
Depending on the voltage applied to the channel layer in the active layer A
N / OFF control is possible.

In the above structure, one set of thin film transistors is composed of a source electrode S, a drain electrode D, an active layer A formed between them, and a gate electrode G for controlling the active layer A. Will be. FIG. 1 shows a state in which four sets of thin film transistors are formed, but in reality, a large number of transistors are formed on a two-dimensional plane, and a display having each display electrode E as one pixel is formed. It By applying a predetermined voltage to the gate electrode G corresponding to one specific scanning line, the channel layers of the thin film transistors arranged in a row in the figure can be turned on, and the drain electrodes D as data lines can be applied. The given signal value can be written in the display electrode E. In other words, by selectively applying a voltage to the plurality of gate electrodes G arranged in the horizontal direction of the drawing and the plurality of drain electrodes D arranged in the vertical direction of the drawing, two-dimensional A desired charge can be stored in a desired electrode among the large number of display electrodes E arranged on the plane.

FIG. 2 shows a part of a cross section corresponding to the section line XX 'in FIG. Gate electrode 2 on glass substrate 1
(Corresponding to the gate electrode G in FIG. 1) is formed, and the channel layer 4 (corresponding to the active layer A in FIG. 1) is formed on the insulating layer 3 in between. Further, the drain electrode 6D (corresponding to the drain electrode D in FIG. 1) is interposed via the drain side impurity doped layer 5D, and the source electrode 6S (corresponding to the source electrode S in FIG. 1) is interposed via the source side impurity doped layer 5S. Each is formed. The drain side impurity doped layer 5D and the source side impurity doped layer 5S are intermediate layers for ensuring ohmic contact with the channel layer 4.

The reason why the parasitic capacitance is generated in the thin film transistor having such a structure will be described with reference to FIG. FIG. 3 shows the sectional view of FIG. 2 in a different way. Here, the gate electrode 2 and the drain electrode 6 are shown.
It can be understood that parasitic capacitance is generated by focusing on the spatial positional relationship between D and the source electrode 6S. That is, the gate electrode 2 and the drain electrode 6D overlap in the section Δ1 in the figure, and the gate electrode 2 and the source electrode 6S overlap in the section Δ2 in the figure. Therefore, the portions indicated by thick lines of the respective electrodes form the counter electrodes at the top and bottom, and the capacitive element is formed. As described above, such a parasitic capacitance has a function of deforming the waveform of the gate pulse applied to the gate electrode 2 and behaves unfavorably in the operation of the thin film transistor. In the present invention, the drain electrode 6D and the source electrode 6S are patterned using the gate electrode 2 as a mask,
It is intended to provide a manufacturing method for making the lengths of the overlapping sections Δ1 and Δ2 zero. Therefore, transparent electrodes are used for the drain electrode 6D and the source electrode 6S, and back exposure is performed from the substrate side. Hereinafter, each step of this manufacturing method will be described in order for a cross section corresponding to the cutting plane XX 'in FIG.

First, as shown in FIG. 4, the gate electrode 2 is formed on the glass substrate 1. This gate electrode 2 corresponds to the gate electrode G of FIG. 1, and has the pattern shown in FIG. 1 in plan view. Such patterns are
It can be formed by a general photolithography process.
Subsequently, as shown in FIG. 5, an insulating layer 3, a channel layer 4, and an impurity-doped layer 5 are sequentially formed thereon. The planar patterns of the channel layer 4 and the impurity-doped layer 5 are shown in FIG.
The pattern corresponding to the active layer A in FIG. Such a pattern can also be formed by a general photolithography process. In this embodiment, Cr is used as the material of the gate electrode 2 and SiNx is used as the material of the insulating layer 3.
Hydrogen-doped amorphous silicon (a-Si: H) is used as the material of the channel layer 4, and as the material of the impurity-doped layer 5, the material of the channel layer 4 is further doped with n ⁺ -type impurities. Material (n ⁺ a-
Si: H) is used. These materials are general materials used in conventional general thin film transistors, and the steps up to FIG. 5 are exactly the same as the conventional manufacturing steps.

Subsequently, as shown in FIG. 6, a transparent electrode layer 6 and a resist layer 7 are formed thereon. Here, the transparent electrode layer 6 includes a source electrode 6S and a drain electrode 6D.
One of the features of the present invention is that it is an electrode layer that is a base for forming the film, and that it is made of a transparent conductive material. Conventionally, the source electrode and the drain electrode were generally formed by using an opaque metal such as Cr or Al. However, in the present invention, because the back exposure process is performed later,
It must be made of a transparent conductive material. In this embodiment, the material of the transparent electrode layer 6 is ITO (In
dium Tin Oxide) is used. In addition, the resist layer 7
Is a negative resist for patterning the transparent electrode layer 6.

The point of the present invention is to pattern the transparent electrode layer 6 using the gate electrode 2 as a mask to form the source electrode 6S and the drain electrode 6D. Therefore, as shown in FIG. 7, light is radiated from the lower surface side of the glass substrate 1 to perform so-called back exposure (in the conventional manufacturing process, all the exposure for patterning is performed from the upper surface side of the glass substrate 1). ). Here, the gate electrode 2 made of Cr is opaque, but since the other layers are all transparent, only the shadow of the gate electrode 2 is projected on the resist layer 7, and the exposed portion 7a that is not hidden by the shadow is formed. , The non-exposed portion 7b hidden in the shadow is formed. If a negative resist is used, by developing the resist layer 7, it is possible to leave only the exposed portion 7a and remove the non-exposed portion 7b. By performing the etching process using the remaining exposed portion 7a as a mask, the patterning of the source electrode 6S and the drain electrode 6D is completed as shown in FIG. Subsequently, when the impurity-doped layer 5 is etched using both of these electrodes as a mask, as shown in FIG. 9, the source-side impurity-doped layer 5S and the drain-side impurity-doped layer 5D are formed.
Can be formed.

Through the above steps, the manufacture of the main part of the thin film transistor is completed. Structurally, an element having the same structure as that of the conventional structure shown in FIG. 2 is formed. However, in the conventional structure element, as shown in FIG.
Gate electrode 2, source electrode 6S and drain electrode 6
Although overlapping sections Δ1 and Δ2 are generated between the element and D, parasitic capacitance is generated, but in the device manufactured by the process of the present invention, as shown in FIG.
As shown by the alternate long and short dash line, the ends of the gate electrode 2 and the ends of the source electrode 6S and the drain electrode 6D are aligned, and the overlapping section is zero. As described above, by using the gate electrode 2 as a mask to pattern the source electrode 6S and the drain electrode 6D, it is possible to make the parasitic capacitance almost zero.

Although the process of the present invention has been described above with respect to the cross section corresponding to the section line XX 'in FIG. 1, the above process description is not complete considering the planar structure. In practice, two extra steps are required. The first extra step is the source electrode 6S and the drain electrode 6D.
Is a step of completing the patterning of. In the above description based on the cross-sectional view, the source electrode 6S as shown in FIG. 8 is formed by etching after the back exposure shown in FIG.
Although it is shown that the drain electrode 6D and the drain electrode 6D are formed, in reality, only part of the source electrode 6S and the drain electrode 6D are formed at this point.
This can be understood by considering the planar pattern formed by the back exposure shown in FIG. That is, the planar pattern of the gate electrode 2 is shown in FIG.
Is a pattern as shown by the solid line. Therefore, in the step shown in FIG. 7, by performing back exposure using the gate electrode 2 as a mask, the resist layer 7
The pattern transferred onto is the pattern itself shown by the solid line in FIG. 1 as the gate electrode G. Figure 10
A part of this pattern (a region corresponding to one thin film transistor) is shown in FIG. The hatched portion is the exposed portion 7a, and the white portion is the non-exposed portion 7b. It can be seen that the cross section corresponding to the section line XX 'has the state shown in FIG. Therefore, when etching is performed using a resist having such a plane pattern, the transparent electrode layer 6 is exposed to the hatched exposed portion 7a.
All areas corresponding to will remain. Figure 8
The source electrode 6S and the drain electrode 6D shown in FIG. 11 actually correspond to a part of the hatched portion of FIG. 10, and the hatched portion of FIG. 10 has not yet been patterned into a correct shape for each electrode. . In other words, the back exposure in FIG. 7 can be said to be a step for forming the facing portions 6SS and 6DD (see FIGS. 8 and 10) of the source electrode 6S and the drain electrode 6D. Therefore, after the state shown in FIG.
It is necessary to perform the patterning process for forming the source electrode 6S and the drain electrode 6D again. This is the first extra step.

Specifically, a photolithography process using a mask as shown in FIG. 11 may be performed. Here, the gate region Ag indicated by a broken line indicates a planar region in which the gate electrode 2 is formed, and the hatched portion is the source region As and the drain region A.
d and defines the source region As and the drain region A
The transparent electrode layer 6 may be etched a second time so that only the region corresponding to d remains. At this time, as shown in FIG. 8, the source electrode 6S and the drain electrode 6D purposely formed by the first etching.
The facing portions 6SS and 6DD of 1 need to be in a state where they are not affected by the second etching. Therefore, as shown in FIG. 11, the boundary between the source region As and the drain region Ad needs to be designed to have some margins Δ3 and Δ4 with respect to the boundary between the gate regions Ag. If the margins Δ3 and Δ4 are set to be larger than the error generated during mask alignment, the facing portion 6
SS and 6DD are not affected by the second etching.

After all, in the process of the present invention, the transparent electrode layer 6 is patterned (etched) twice. In the first patterning, the hatched area in FIG. 10 remains, and in the second patterning, the hatched area in FIG. 11 remains. Therefore, by patterning twice, only the portion shown by hatching in FIG. 12 remains finally. That is, the source electrode 6S and the drain electrode 6
D is formed, and the opposing portions 6SS and 6DD of both are aligned with the boundary portion of the gate region Ag. The cross-sectional view shown in FIG. 8 actually corresponds to the state after such second patterning.

By the way, as clearly shown in FIG. 12, since the gate electrode 2 is used as a mask for patterning (first patterning), the drain electrode is divided into the drain electrodes 6D and 6D 'in the divided region Z. It has been divided into. As shown by the broken line in the plan view of FIG. 1, the drain electrode D originally has to extend in the vertical direction of the drawing and form a common electrode for a plurality of elements arranged in a line. However, when the process according to the present invention is carried out, the drain electrode D is divided at the intersection of the gate electrode G and the drain electrode D in the plan view of FIG. Second required for the present invention
Extra step (if the drain electrode is not used as wiring, this second extra step is not always necessary)
Is a step of forming an auxiliary wiring layer for electrically connecting the drain electrode D thus divided.

FIG. 13 shows a cross section corresponding to the section line YY 'in FIG. The drain electrodes 6D and 6D 'formed on the insulating layer 3 are divided in the dividing region Z. This is because patterning was performed using the gate electrode 2 as a mask. Therefore, an auxiliary wiring layer 8 (for example, a metal material such as Cr or Al is used) as shown by hatching in FIG. 14 is formed in such a divided portion, and both are electrically connected. By doing so, an element having the same function as that of the conventional thin film transistor group shown in FIG. 1 can be realized.

Generally, the transparent electrode material is Cr or A.
Since the electric resistance is higher than that of a metal material such as l, if the entire drain electrode D used as a common wiring for a plurality of elements is made of only this transparent electrode material, the electric resistance of the wiring becomes high. There are cases. In such a case, a layer made of a material having a high electric conductivity such as Cr or Al may be further formed on a part of the upper surface of the drain electrode D made of a transparent electrode material.

Further, if the source electrode 6S and the drain electrode 6D are made of a transparent electrode material, there is a disadvantage that it is difficult to maintain ohmic contact with the source-side impurity-doped layer 5S and the drain-side impurity-doped layer 5D. is there. In such a case, the structure may be such that a thin Cr layer or the like is sandwiched between the two. Specifically, the thin Cr layer may be formed on the impurity-doped layer 5, and the transparent electrode layer 6 may be formed on the thin Cr layer. If the thickness of the Cr layer is set to about 0.05 μm, this Cr layer becomes a substantially transparent layer and does not become an obstacle when performing back exposure.

The above manufacturing process is one in which the present invention is applied to a thin film transistor having a sectional structure shown in FIG. 9 which is a so-called bottom gate stagger structure. In addition to this, the present invention can be applied to a thin film transistor having a cross-sectional structure as shown in FIG. 15 which is a so-called top gate type stagger structure. In the thin film transistor shown in FIG. 15, the source electrode 6S and the gate electrode 6D are formed on the upper surface of the glass substrate 1, and the channel layer 4 and the gate electrode 2 are formed on the source electrode 6S and the gate electrode 6D with the insulating layer 3 interposed therebetween. . When manufacturing a thin film transistor having such a top gate type structure, the gate electrode 2 may be patterned using the source electrode 6S and the drain electrode 6D as a mask, contrary to the above-described embodiment. That is, as shown in FIG. 16, light is irradiated from the lower surface side of the substrate 1 with the amorphous silicon layer 4 ′, the transparent electrode layer 2 ′, and the negative resist layer 7 formed on the insulating layer 3. , Back exposure is performed. By developing the resist layer 7, only the exposed portion 7a can be left and the non-exposed portion 7b can be removed. Thus, the remaining exposed portion 7
By performing the etching process using a as a mask, both sides of the gate electrode 2 as shown in FIG. 15 can be formed. After that, the transparent electrode layer 2 ′ may be patterned again to form a portion other than both sides of the gate electrode 2.

The present invention has been described above based on the illustrated embodiment, but the present invention is not limited to this embodiment and can be implemented in various modes other than this. In particular, the specific material of each layer shown in the above-mentioned examples is given as one example, and the present invention is not limited to these materials.

[0031]

As described above, in the method of manufacturing a thin film transistor according to the present invention, when patterning the source electrode and the drain electrode (or the gate electrode), these electrodes are made of a transparent material, and light is emitted from the substrate side. Since irradiation is performed and exposure is performed using the gate electrode (or the source electrode and the drain electrode) as a mask, the source electrode and the drain electrode are not covered by the gate electrode, and parasitic between the electrodes is generated. The capacity can be suppressed.

[Brief description of drawings]

FIG. 1 is a top view showing a state in which a plurality of thin film transistors are arranged in a matrix when the thin film transistors are used in a general liquid crystal display.

FIG. 2 is a cross-sectional view of a cutting portion corresponding to cutting line XX ′ in FIG.

FIG. 3 is a diagram for explaining generation of parasitic capacitance in the cross-sectional view shown in FIG.

FIG. 4 is a cross-sectional view showing a manufacturing process of a general thin film transistor in which a gate electrode 2 is formed on a glass substrate 1.

5 is a cross-sectional view showing a manufacturing process of a general thin film transistor in which an insulating layer 3, a channel layer 4, and an impurity doped layer 5 are further formed on the state shown in FIG.

6 is a cross-sectional view showing a step of forming a transparent electrode layer 6 and a resist layer 7 peculiar to the manufacturing method of the present invention on the state shown in FIG.

7 is a cross-sectional view showing a step of performing back exposure using the gate electrode 2 as a mask in the state shown in FIG.

8 is a cross-sectional view showing a state where the transparent electrode layer 6 is etched after the back exposure shown in FIG.

9 is a diagram illustrating an impurity-doped layer 5 after the etching shown in FIG.
It is sectional drawing which shows the state which was etched with respect to.

10 is a plan view showing a pattern used for a first patterning performed to obtain the structure shown in FIG.

FIG. 11 is a plan view showing a pattern used for a second patterning performed to obtain the structure shown in FIG.

12 is a plan view showing a pattern obtained by overlapping the pattern shown in FIG. 10 and the pattern shown in FIG.

13 is a cross-sectional view of a cutting portion corresponding to cutting line YY 'in FIG.

14 is a cross-sectional view showing a state in which an auxiliary wiring layer 8 for connecting the divided regions Z shown in FIG. 13 is formed.

FIG. 15 is a sectional view showing a sectional structure of a general top-gate thin film transistor.

16 is a cross-sectional view showing a step of applying the present invention to the structure of the thin film transistor having the structure shown in FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Glass substrate 2 ... Gate electrode 2 '... Transparent electrode layer 3 ... Insulation layer 4 ... Channel layer 4' ... Amorphous silicon layer 5 ... Impurity doped layer 5D ... Drain side impurity doped layer 5S ... Source side impurity doped layer 6 ... Transparent Electrode layers 6D, 6D '... Drain electrode 6DD ... Opposing part 6S ... Source electrode 6SS ... Opposing part 7 ... Resist layer 7a ... Exposed part 7b ... Non-exposed part 8 ... Auxiliary wiring layer A ... Active layer Ag ... Gate region As ... Source Region Ad ... Drain region C ... Channel region D ... Drain electrode (data line) G ... Gate electrode (scan line) S ... Source electrode Δ1, Δ2 ... Overlapping section Δ3, Δ4 ... Margin portion

Claims (6)

[Claims] 1. A thin film transistor having a source electrode, a drain electrode and a gate electrode formed on a substrate,
Between the projection pattern of the source electrode and the projection pattern of the gate electrode, and between the projection pattern of the drain electrode and the projection pattern of the gate electrode when the patterns of the electrodes are projected on the upper surface of the substrate. A thin film transistor, characterized in that it is configured so that no overlap occurs. 2. A method for manufacturing a thin film transistor, which comprises irradiating light from a substrate side and performing exposure using a gate electrode as a mask when patterning a source electrode and a drain electrode. 3. A step of forming an opaque gate electrode on the upper surface of a transparent substrate, and a step of sequentially forming a transparent semiconductor channel layer and a transparent impurity-doped layer on the transparent gate electrode via a transparent insulating layer. Forming a transparent electrode layer on the transparent electrode layer, and forming a resist layer on the transparent electrode layer; and irradiating light from the lower surface side of the substrate, exposing the resist layer using the gate electrode as a mask. And developing the resist layer to remove the non-exposed portion, and using the exposed portion of the resist layer as a mask, the transparent electrode layer is etched to form a facing portion of the source electrode and the drain electrode. A step of patterning the transparent electrode layer to form a portion of the source electrode and the drain electrode other than the facing portion, Production method. 4. The method of manufacturing a thin film transistor according to claim 3, further comprising the step of forming an auxiliary wiring layer for electrically connecting the drain electrodes of the plurality of thin film transistors. 5. When patterning the gate electrode,
A method of manufacturing a thin film transistor, which comprises irradiating light from a substrate side and performing exposure using a source electrode and a drain electrode as a mask. 6. A step of forming an opaque source electrode and a drain electrode on an upper surface of a transparent substrate, a step of forming a transparent semiconductor channel layer on the transparent substrate via a transparent insulating layer, and a step of forming a transparent semiconductor channel layer thereon. Forming a transparent electrode layer and forming a resist layer on the transparent electrode layer; and irradiating light from the lower surface side of the substrate, exposing the resist layer using the source electrode and the drain electrode as a mask. A step of developing the resist layer and removing an unexposed portion, a step of etching the transparent electrode layer using the exposed portion of the resist layer as a mask to form both sides of the gate electrode, Patterning the transparent electrode layer to form a portion other than the both side portions of the gate electrode, and a method of manufacturing a thin film transistor.