JP2011210983A - Copper foil for printed wiring board which forms circuit with superior electrical transmission characteristic, and layered body using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a copper foil for a printed wiring board that has an excellent etching property during circuit pattern formation, is suitable to fine pitch fabrication, and has excellent electrical transmission characteristics, and to provide a layered body using the same.SOLUTION: The copper foil for the printed wiring board includes: a copper foil base material, at least one of surfaces of which has a surface roughness Ra of ≤0.1 μm; and a coating layer which covers at least a part of the surface of the copper foil base material and is composed of one or more kinds among Pt, Au and Pd.

Description

  The present invention relates to a copper foil for a printed wiring board and a laminate using the same, and more particularly to a copper foil for a flexible printed wiring board and a laminate using the same.

  Printed wiring boards have made great progress over the last half century and are now used in almost all electronic devices. In recent years, with the increasing needs for miniaturization and higher performance of electronic devices, higher density mounting of components and higher frequency of signals have progressed, and conductor patterns have become finer (fine pitch) and higher frequency than printed circuit boards. Response is required.

  A printed wiring board is made by bonding an insulating substrate to a copper foil, or depositing a Ni alloy or the like on the insulating substrate and then forming a copper layer by electroplating to form a laminate, and then etching the conductor on the copper foil or copper layer surface. In general, it is manufactured through a process of forming a pattern. Therefore, good etching properties are required for the copper foil or copper layer for printed wiring boards.

  If the copper foil is not subjected to surface treatment on the non-adhesive surface with the resin, the copper portion of the copper foil circuit after etching is etched away from the surface of the copper foil, that is, toward the resin layer. (Sagging). Normally, the angle on the side of the circuit is “sagging”, and when a large “sagging” occurs, the copper circuit may be short-circuited near the resin substrate, resulting in a defective product with poor electrical transmission characteristics. Here, FIG. 3 shows an enlarged photograph of the circuit surface showing an example in which “sagging” occurs when the copper circuit is formed and the copper circuit is short-circuited in the vicinity of the resin substrate.

  Such “sag” is necessary to improve the electrical transmission characteristics as much as possible, but in order to prevent such poor etching, the etching time is extended to increase the etching, It is possible to reduce this “sag”. However, in this case, if there is a portion that has already reached the predetermined width dimension, it will be further etched, so that the circuit width of the copper foil portion will be reduced accordingly, and the circuit design will be a uniform target. The line width (circuit width) cannot be obtained, and heat is generated particularly in that portion (thinned portion), and in some cases, there is a problem of disconnection. As the fine patterning of electronic circuits further progresses, the problem due to such etching failure still appears more strongly and still becomes a big problem in circuit formation.

  As a method for improving these, Patent Document 1 discloses a surface treatment in which a metal or alloy layer having an etching rate slower than that of copper is formed on a copper foil on the etching surface side. In this case, the metal or alloy includes Ni, Co, and alloys thereof. In circuit design, the etching solution penetrates from the resist coating side, that is, from the surface of the copper foil, so if there is a metal or alloy layer with a slow etching rate directly under the resist, the etching of the copper foil portion in the vicinity is suppressed. Since the etching of the copper foil portion of the metal film progresses, the “sag” is reduced, and a circuit with a more uniform width can be formed. This makes it possible to form a sharper circuit compared to the prior art, and a great progress has been made. It can be said that there was.

  Further, in Patent Document 2, a Cu thin film having a thickness of 1000 to 10,000 mm is formed, and an Ni thin film having an etching rate slower than that of copper having a thickness of 10 to 300 mm is formed on the Cu thin film.

JP 2002-176242 A JP 2000-269619 A

  In recent years, further miniaturization and higher density of circuits have progressed, and there is a demand for circuits having side surfaces that are more steeply inclined. However, the technique described in Patent Document 1 cannot cope with these.

  Moreover, it is necessary to remove the surface treatment layer described in Patent Document 1 by soft etching, and furthermore, the non-adhesive surface-treated copper foil with the resin is a process of processing into a laminate, and the application of the resin High temperature treatment is applied. This causes oxidation of the surface treatment layer, and as a result, the etching property of the copper foil deteriorates.

  As for the former, it is necessary to reduce the thickness of the surface treatment layer as much as possible in order to shorten the etching removal time as much as possible, and to remove it cleanly. In the latter case, in order to receive heat, The underlying copper layer is oxidized (discolored, so it is commonly called “yake”), due to poor resist coatability (uniformity, adhesion), excessive etching of interfacial oxide during etching, etc. There is a problem that defects such as etching property in pattern etching, short circuit, and controllability of the width of the circuit pattern occur, so that improvement is required or replacement with other materials is required.

  Then, this invention makes it a subject to provide the copper foil for printed wiring boards with favorable etching property at the time of circuit pattern formation, suitable for fine pitch formation, and favorable electrical transmission characteristics, and a laminated body using the same.

  As a result of intensive studies, the present inventors have made a coating layer composed of at least one of Pt, Au, and Pd on the non-adhesion surface side of the copper foil resin whose surface roughness is prescribed to a predetermined value or less. It was found that a circuit having an inclination angle of 80 ° or more on the side surface of the circuit can be formed. As a result, it is possible to form a circuit with good electrical transmission characteristics that can sufficiently cope with the recent miniaturization and high density of circuits.

  The present invention completed on the basis of the above knowledge, in one aspect, at least one surface roughness Ra covers 0.1 μm or less of the copper foil base, and at least part of the surface of the copper foil base, and , Pt, Au, and a copper foil for printed wiring board provided with a coating layer composed of at least one of Pd.

  In one embodiment of the copper foil for printed wiring boards according to the present invention, the surface roughness Ra of the copper foil is 0.07 μm or less.

  In another embodiment of the copper foil for printed wiring boards according to the present invention, the surface roughness Ra of the copper foil is 0.03 μm or less.

In still another embodiment of the copper foil for printed wiring board according to the present invention, the coating layer has an adhesion amount of Au of 1000 μm / dm ² or less, Pt of 1050 μm / dm ² or less, and Pd of 600 μm / dm ² or less. Exists.

In still another embodiment of the copper foil for printed wiring boards according to the present invention, Au of the coating layer is 20 to 400 μm / dm ² , Pt is 20 to 400 μm / dm ² , and Pd is 20 to 250 μm / dm ² . Present in the amount of adhesion.

In still another embodiment of the copper foil for printed wiring boards according to the present invention, Au of the coating layer is 50 to 300 μm / dm ² , Pt is 50 to 300 μm / dm ² , and Pd is 30 to 180 μm / dm ² . Present in the amount of adhesion.

  In another embodiment of the copper foil for printed wiring boards according to the present invention, the printed wiring board is a flexible printed wiring board.

  In another aspect of the present invention, there is provided a laminate of the copper foil and the resin substrate according to the present invention.

  According to still another aspect of the present invention, there is provided a laminate of a copper layer and a resin substrate, wherein at least one surface roughness Ra of the copper layer is 0.1 μm or less, and at least a part of the surface of the copper layer is formed. It is a laminate provided with a coating layer according to the present invention that is coated with one or more of Au, Pd, and Pt.

  In one embodiment of the laminate according to the present invention, a circuit is formed on a copper foil or a copper layer, the width of the circuit surface is W1 (μm), the width of the circuit bottom is W2 (μm), the copper foil or copper The layer thickness is b (μm), the circuit pitch width is X (μm), the etching factor E.I. F. Is b / {(W2-W1) / 2}, and W2 / X ≧ 0.2, E.E. F. ≧ 1.5, and the standard deviation of W1 and W2 is 0.8 or less.

  In another embodiment of the laminate according to the present invention, when W2 / X ≧ 0.2, E.E. F. ≧ 2.5.

  In another embodiment of the laminate according to the present invention, the resin substrate is a polyimide substrate.

  In yet another aspect, the present invention is a printed wiring board made of the laminate according to the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the copper foil for printed wiring boards with favorable etching property at the time of circuit pattern formation, suitable for fine pitch formation, and favorable electrical transmission characteristic, and a laminated body using the same can be provided.

It is the outline | summary of the calculation method of the etching factor (EF) using the surface photograph of a part of circuit pattern, the schematic diagram of the cross section of the width direction of the circuit pattern in the said part, and this schematic diagram. 40 is a photograph showing a circuit formed according to Example 29 and a cross section thereof. It is an enlarged photograph of the circuit surface which shows the example which produced "sagging" at the time of copper circuit formation, and the copper circuit short-circuited in the resin substrate vicinity.

(Copper foil base material)
Although there is no restriction | limiting in particular in the form of the copper foil base material which can be used for this invention, Typically, it can use with the form of rolled copper foil or electrolytic copper foil. In general, the electrolytic copper foil is produced by electrolytic deposition of copper from a copper sulfate plating bath onto a drum of titanium or stainless steel, and the rolled copper foil is produced by repeating plastic working and heat treatment with a rolling roll. Rolled copper foil is often used for applications that require flexibility.
In addition to high-purity copper such as tough pitch copper and oxygen-free copper, which are usually used as conductor patterns for printed wiring boards, for example, Sn-containing copper, Ag-containing copper, Cr, Zr or Mg are added as the copper foil base material. It is also possible to use a copper alloy such as a copper alloy, a Corson copper alloy to which Ni, Si and the like are added. In addition, when the term “copper foil” is used alone in this specification, a copper alloy foil is also included.

  There is no restriction | limiting in particular also about the thickness of the copper foil base material which can be used for this invention, What is necessary is just to adjust to the thickness suitable for printed wiring boards suitably. For example, it can be set to about 5 to 100 μm. However, for the purpose of forming a fine pattern, it is 30 μm or less, preferably 20 μm or less, and typically about 5 to 20 μm.

  The copper foil substrate used in the present invention has a surface roughness Ra of 0.1 μm or less on at least the surface of the copper foil substrate opposite to the bonding surface with the insulating substrate (circuit formation scheduled surface side). For this reason, fine pitch and high frequency electrical characteristics are improved. The surface roughness Ra is preferably 0.07 μm or less, and more preferably 0.03 μm or less.

(1) Structure of coating layer The coating layer is formed in at least one part of the above-mentioned surface of a copper foil base material. The coating layer is composed of at least one of Pt, Au, and Pd.
In addition, on the adhesive surface side of the copper foil base material with the insulating substrate, for the purpose of improving the adhesiveness with the insulating substrate, for example, another coating layer composed of an intermediate layer and a surface layer laminated in order from the copper foil base material surface May be formed. In this case, the intermediate layer preferably contains at least one of Ni, Mo, Ti, Zn, Co, V, Sn, Mn, Nb, Ta, and Cr, for example. The intermediate layer may be composed of a single metal, for example, preferably composed of any one of Ni, Mo, Ti, Zn, Co, Nb, and Ta. The intermediate layer may be made of an alloy, for example, preferably made of an alloy of at least any two of Ni, Zn, V, Sn, Mn, Cr and Cu.

(2) Identification of coating layer The coating layer can be identified by the presence of each detected peak by performing argon sputtering from the surface layer with a surface analyzer such as XPS or AES and performing chemical analysis in the depth direction.

(3) When the coating weight coating layer is composed of Au is a deposition amount of Au is 1000 .mu.m / dm ² or less, more preferably from 20~400μg / dm ^2, in 50~300μg / dm ² Even more preferably. When the coating layer is made of Pd, the adhesion amount of Pd is 600 μg / dm ² or less, more preferably ²⁰ to 250 μg / dm ² , and even more preferably 30 to 180 μg / dm ^2. preferable. If the coating layer is composed of Pt is the amount of adhesion of Pt 1050μg / dm ² or less, more preferably from 20~400μg / dm ^2, further that a 50~300μg / dm ² from preferable. When the Au adhesion amount of the coating layer is less than 10 μg / dm ² , the Pd adhesion amount of the coating layer is less than 10 μg / dm ² , and the Pt adhesion amount of the coating layer is less than 10 μg / dm ² , the effect is obtained. not enough. On the other hand, the amount of adhered 1000 [mu] g / dm ² of the Au coating layer, the coating layer of the adhesion amount 600 [mu] g / dm ² of Pd, and, when the amount of deposition of Pt of the coating layer exceeds 1050μg / dm ^2, respectively initial etch resistant Adversely affect.

(Manufacturing method of copper foil)
The copper foil for printed wiring boards according to the present invention can be formed by sputtering after the surface roughness Ra is 0.1 μm or less by the surface treatment of the copper foil base material. That is, at least a part of the surface of the copper foil base material is coated with the coating layer by a sputtering method. Specifically, a coating layer made of at least one of Pt, Au, and Pd having an etching rate lower than that of copper is formed on the etching surface side of the copper foil by a sputtering method. The coating layer is not limited to the sputtering method, and may be formed by, for example, a wet plating method such as electroplating or electroless plating.

(Printed wiring board manufacturing method)
A printed wiring board (PWB) can be manufactured according to a conventional method using the copper foil according to the present invention. Below, the example of the manufacturing method of a printed wiring board is shown.

  First, a laminated body is manufactured by bonding a copper foil and an insulating substrate. The insulating substrate on which the copper foil is laminated is not particularly limited as long as it has characteristics applicable to a printed wiring board. For example, paper base phenolic resin, paper base epoxy resin, synthetic fiber for rigid PWB Use cloth base epoxy resin, glass cloth / paper composite base epoxy resin, glass cloth / glass non-woven composite base epoxy resin, glass cloth base epoxy resin, etc., use polyester film, polyimide film, etc. for FPC I can do things.

  In the case of the rigid PWB, a prepreg is prepared by impregnating a base material such as a glass cloth with a resin and curing the resin to a semi-cured state. It can be carried out by superposing a copper foil on the prepreg from the opposite surface of the coating layer and heating and pressing.

  In the case of a flexible printed wiring board (FPC), a polyimide film or a polyester film and a copper foil can be bonded using an epoxy or acrylic adhesive (three-layer structure). In addition, as a method without using an adhesive (two-layer structure), a polyimide varnish (polyamic acid varnish), which is a polyimide precursor, is applied to a copper foil and heated to form an imidization or on a polyimide film. There is a laminating method in which a thermoplastic polyimide is applied to the substrate, a copper foil is overlaid thereon, and heated and pressed. In the casting method, it is also effective to apply an anchor coating material such as thermoplastic polyimide in advance before applying the polyimide varnish.

  The laminate according to the present invention can be used for various printed wiring boards (PWB) and is not particularly limited. For example, from the viewpoint of the number of layers of the conductor pattern, the single-sided PWB, double-sided PWB, and multilayer PWB ( It is applicable to rigid PWB, flexible PWB (FPC), and rigid flex PWB from the viewpoint of the type of insulating substrate material. Further, the laminate according to the present invention is not limited to the above-described copper-clad laminate obtained by attaching a copper foil to a resin, and is a metalizing material in which a copper layer is formed on the resin by sputtering or plating. Also good.

A resist is applied to the surface of the coating layer formed on the copper foil of the laminate produced as described above, the pattern is exposed with a mask, and the resist pattern formed by development is immersed in an etching solution. At this time, the coating layer composed of at least one of Pt, Au, and Pd that suppresses etching is located near the resist portion on the copper foil, and the etching of the copper foil on the resist side Etching of the copper circuit pattern proceeds substantially vertically by etching of the copper in a portion away from the coating layer at a speed faster than the speed at which the vicinity is etched. Thus, unnecessary portions of copper can be removed, and then the etching resist can be peeled and removed to expose the circuit pattern.
With respect to the etching solution used for forming the circuit pattern on the laminate, the etching rate of the coating layer is sufficiently smaller than that of copper, so that the etching factor is improved. As the etching solution, a cupric chloride aqueous solution, a ferric chloride aqueous solution, or the like can be used. In addition, a base layer may be provided between the copper foil base material and the coating layer from the viewpoint of heat discoloration resistance as long as the initial etching property is not adversely affected. As the underlayer, nickel, nickel alloy, cobalt, silver, and manganese are preferable. Either a dry method or a wet method may be used as a method for providing the base layer.

(Circuit shape on the copper foil surface of the printed wiring board)
As described above, the circuit on the copper foil surface of the printed wiring board formed by etching from the coating layer side is not usually formed with two long side surfaces perpendicular to the insulating substrate. From the surface of the foil downward, that is, toward the resin layer, it is formed so as to spread toward the end (generation of sagging). Thus, the two long side surfaces each have an inclination angle θ with respect to the surface of the insulating substrate. It is important to reduce the circuit pitch as much as possible for miniaturization (fine pitch) of the circuit pattern that is currently required. However, if this inclination angle θ is small, the sagging increases accordingly, The pitch becomes wider. In addition, the width W1 (μm) of the circuit surface and the width W2 (μm) of the circuit bottom are usually not completely constant in each circuit and circuit. If such variations in W1 and W2 are large, the circuit quality may be adversely affected. Therefore, in the circuit on the copper foil surface of the printed wiring board formed by etching from the coating layer side, the two long side surfaces each have an inclination angle θ of 65 to 90 ° with respect to the insulating substrate surface. desirable. Further, the thickness of the copper foil or copper layer is b (μm), the pitch width of the circuit is X (μm), the etching factor E.I. F. Is b / {(W2-W1) / 2}, and W2 / X ≧ 0.2, E.E. F. It is desirable that the standard deviation of W1 and W2 is 0.8 or less, and when W2 / X ≧ 0.2, E.E. F. It is desirable that ≧ 2.5.

  EXAMPLES Examples of the present invention will be described below, but these are provided for better understanding of the present invention and are not intended to limit the present invention.

(Example 1: Examples 1-32)
(Formation of coating layer on copper foil)
As the copper foil base materials of Examples 1 to 32, various copper foils or copper layers having the thickness and surface roughness shown in Table 1 (Nikko Metal C1100 for rolled copper foil, Nikko Metal for metalizing CCL) Macinas [copper layer side Ra 0.01 μm, tie coat layer metal adhesion amount Ni 1780 μg / dm ² , Cr 360 μg / dm ² ] was prepared.

A thin oxide film adhering to the surface of the copper foil was removed by reverse sputtering, and a target of Au, Pt, and Pd was sputtered with the following apparatus and conditions to form a coating layer. The thickness of the coating layer was changed by adjusting the film formation time. The simple substance of the various metals used for sputtering used the thing of purity 3N.
-Equipment: Batch type sputtering equipment (ULVAC, Model MNS-6000)
・ Achieving vacuum: 1.0 × 10 ⁻⁵ Pa
・ Sputtering pressure: 0.2 Pa
・ Reverse sputtering power: 100W
・ Sputtering power: 50W
・ Target: For etching surface Au-50wt% Pd, Pt-50wt% Pd
Au-50wt% Pt
Au, Pt, Pd, Ni, Zn, Co, Cr, Ag, Mn (3N)
Ni-20wt% Cr, Ni-7wt% V, Ni-20wt% Mn
Ni-20wt% Zn, Ni-20wt% Sn
・ Target: Ni, Cr (3N) for adhesive surface
Film formation rate: About 0.2 μm of film was formed for each target for a fixed time, the thickness was measured with a three-dimensional measuring device, and the sputtering rate per unit time was calculated.

The thin oxide film previously attached to the surface opposite to the coating layer was removed from the copper foil provided with the coating layer by reverse sputtering, and a Ni layer and a Cr layer were sequentially formed.
A polyimide film with an adhesive (manufactured by Nikkan Kogyo Co., Ltd., CISV1215) was laminated on the copper foil that had been subjected to the surface treatment by the above procedure by a hot press at a pressure of 7 kgf / cm ² and 160 ° C. for 40 minutes. Some copper foil was laminated | stacked with the polyimide film in the said procedure, after hold | maintaining at 350 degreeC for 2 hours by nitrogen atmosphere.

<Measurement of adhesion amount>
The adhesion amount of Au, Pd, and Pt in the coating layer was measured by atomic absorption spectrometry by dissolving the surface-treated copper foil sample with aqua regia, diluting the solution. To measure the adhesion amount of Ni and Ni-based alloys, a film of 50 mm × 50 mm copper foil surface was dissolved in a mixed solution of HNO ₃ (2 wt%) and HCl (5 wt%), and the metal concentration in the solution Was quantified with an ICP emission spectroscopic analyzer (SFC-3100, manufactured by SII Nanotechnology Co., Ltd.), and the amount of metal (μg / dm ² ) per unit area was calculated.

(Circuit shape by etching)
The etched surface of the copper foil was degreased with acetone and immersed in sulfuric acid (100 g / L) for 30 seconds to remove the surface contamination and the oxide layer. Next, a liquid resist (manufactured by Tokyo Ohka Kogyo Co., Ltd., OFPR-800LB) was dropped onto the etching surface using a spin coater and dried. The resist thickness after drying was adjusted to 1 μm. Thereafter, 10 circuits were printed by an exposure process, and an etching process for removing unnecessary portions of the copper foil was performed under the following conditions.

<Etching conditions>
-Ferric chloride aqueous solution: (37 wt%, Baume degree: 40 °)
・ Liquid temperature: 50 ° C
・ Spray pressure: 0.25 MPa
(50 μm pitch circuit formation)
・ Resist L / S = 33μm / 17μm
-Finished circuit bottom (circuit bottom) width: 25 μm
Etching time: 10 to 130 seconds (30 μm pitch circuit formation)
・ Resist L / S = 25μm / 5μm
-Finished circuit bottom (circuit bottom) width: 15 μm
-Etching time: 30 to 200 seconds-Confirmation of etching end point: Etching was carried out at several levels by changing the time, and it was confirmed that copper did not remain between the circuits with an optical microscope.
After the etching, the resist was peeled off by dipping in a 45 ° C. aqueous NaOH solution (100 g / L) for 1 minute.

<Etching factor measurement conditions>
The etching factor is the distance of the length of sagging from the intersection of the vertical line from the upper surface of the copper foil and the resin substrate, assuming that the circuit is etched vertically when sagging at the end (when sagging occurs) Is a (= (W2-W1) / 2), the ratio of this a to the thickness b of the copper foil: b / a is shown. The larger this value, the greater the inclination angle. This means that no etching residue remains and sagging is reduced. FIG. 1 shows a surface photograph of a part of a circuit pattern, a schematic diagram of a cross section in the width direction of the circuit pattern at the part, and an outline of a method for calculating an etching factor using the schematic diagram. W1 and W2 were measured by SEM observation from above the circuit, and the etching factor (EF = b / a) was calculated. By using this etching factor, it is possible to easily determine whether the etching property is good or bad. Furthermore, the inclination angle θ was calculated by calculating the arc tangent using a and the thickness b of the copper foil measured in the above procedure. These measurement ranges had a circuit length of 600 μm, and adopted W1 and W2 at 12 points, their standard deviations, and average values of etching factors and inclination angles θ as results.

(Example 2: Comparative Examples 33 to 49)
As copper foil base materials of Comparative Examples 33 to 49, various copper foils or copper layers having the thicknesses and surface roughnesses shown in Table 3 were prepared (Nikko Metal C1100 for rolled copper foil and Nikko for electrolytic copper foil. For metal JTC foil and metalizing CCL, Nikko Metal's Macinas [copper layer side Ra 0.01 μm, tie coat layer metal adhesion amount Ni 1780 μg / dm ² , Cr 360 μg / dm ² ]), surface treatment according to the procedure of Example 1 respectively. Etching was performed.
Each measurement result of Examples 1-2 is shown in Tables 1-4.

<Evaluation>
(Examples 1-32)
In Examples 1 to 32, it was possible to form a circuit having a cross section close to a rectangular shape with both a 50 μm pitch and a 30 μm pitch resist pattern with a large etching factor and no variation.
FIG. 2 shows a photograph of a circuit formed according to Example 29 and a cross-sectional photograph thereof.

(Comparative Examples 33-49)
In Comparative Examples 33 and 46, Pt, Pd, and Au were not attached to the surface, and the etching factor was small.
In Comparative Examples 34 to 39, the adhesion amount of Pt, Pd, and Au was large, and the linearity was poor.
In Comparative Examples 40 to 49, the copper foil used had a large surface roughness Ra, resulting in poor linearity.

Claims (13)

  A copper foil base having at least one surface roughness Ra of 0.1 μm or less, and covering at least a part of the surface of the copper foil base, and at least one of Pt, Au, and Pd The copper foil for printed wiring boards provided with the comprised coating layer.   The copper foil for printed wiring board according to claim 1, wherein the surface roughness Ra is 0.07 μm or less.   The copper foil for printed wiring boards according to claim 2, wherein the surface roughness Ra is 0.03 μm or less. The copper foil for printed wiring boards according to any one of claims 1 to 3, wherein Au of the coating layer is present in an amount of 1000 µm / dm ² or less, Pt is 1050 µm / dm ² or less, and Pd is 600 µm / dm ² or less. . The copper foil for printed wiring boards according to claim 4, wherein Au of the coating layer is present in an amount of ²⁰ to 400 μm / dm ² , Pt is 20 to 400 μm / dm ² , and Pd is 20 to 250 μm / dm ² . The copper foil for printed wiring boards according to claim 5, wherein Au of the coating layer is present in an amount of 50 to 300 µm / dm ² , Pt is 50 to 300 µm / dm ² , and Pd is 30 to 180 µm / dm ² .   A printed wiring board is a flexible printed wiring board, Copper foil for printed wiring boards in any one of Claims 1-6.   The laminated body of the copper foil and resin substrate in any one of Claims 1-7. A laminate of a copper layer and a resin substrate,
The surface roughness Ra of at least one of the copper layer is 0.1 μm or less, and at least a part of the surface is covered with at least one of Au, Pt, and Pd. The laminated body provided with the coating layer.   A circuit is formed on the copper foil or copper layer, the width of the circuit surface is W1 (μm), the width of the circuit bottom is W2 (μm), the thickness of the copper foil or copper layer is b (μm), The pitch width is X (μm), the etching factor is E.E. F. Is b / {(W2-W1) / 2}, and W2 / X ≧ 0.2, E.E. F. The laminate according to claim 8 or 9, wherein ≧ 1.5 and the standard deviation of W1 and W2 is 0.8 or less.   E. When W2 / X ≧ 0.2 F. The laminate according to claim 10, wherein ≧ 2.5. The laminate according to any one of claims 8 to 11, wherein the resin substrate is a polyimide substrate.   The printed wiring board which used the laminated body in any one of Claims 8-12 as a material.