JP5746876B2 - Method for forming an electronic circuit - Google Patents

Description

The present invention relates to a method for forming an electronic circuit .

  Printed wiring boards have made great progress over the last half century and are now used in almost all electronic devices. In recent years, with the increasing needs for miniaturization and higher performance of electronic devices, higher density mounting of components and higher frequency of signals have progressed, and conductor patterns have become finer (fine pitch) and higher frequency than printed circuit boards. Response is required.

  A printed wiring board is made by bonding an insulating substrate to a copper foil, or depositing a Ni alloy or the like on the insulating substrate and then forming a copper layer by electroplating to form a copper-clad laminate, and then etching the copper foil or copper layer surface. In general, it is manufactured through a process of forming a conductor pattern. For this reason, the copper foil or copper layer for printed wiring boards is required to have adhesion and etching properties with an insulating substrate.

  The adhesiveness here means that the formed circuit does not peel from the insulating substrate. For this reason, the roughening process which forms an unevenness | corrugation in the adhesion surface side with the resin of copper foil or a copper layer, and processes, such as Ni plating and chromate, are further performed as needed. Alternatively, from the viewpoint of the skin effect and the like, a method of directly performing a chromate treatment or the like on a copper foil without performing a roughening treatment is also known (Patent Document 1).

  Etchability means that no metal derived from the surface treatment remains in the insulating portion between the circuits, and that the circuit tailing is small. If metal remains in the insulating part between the circuits, a short circuit occurs between the circuits. In the etching for forming the circuit, the circuit is etched from the upper surface to the lower side (insulating substrate side), and the cross section of the circuit becomes a trapezoid. If the difference between the upper and lower bases of the trapezoid (hereinafter referred to as “tailing”) is small, the space between circuits can be narrowed, and a high-density wiring board can be obtained. If the skirting is large, the circuit is short-circuited if the space between the circuits is narrowed, so that a high-density mounting substrate cannot be manufactured.

  Etching proceeds in two directions, the thickness direction and the planar direction of the copper foil or copper layer. Since the etching rate in the plate thickness direction is lower than that in the plane direction, the circuit cross section becomes trapezoidal. For this reason, in order to obtain a circuit with a small footing, the thickness of the copper foil or the copper layer may be reduced to shorten the etching time (Patent Document 2).

  In addition to the copper foil or copper layer, the thickness of the photoresist also affects the etching time. Usually, for FPC applications, a dry film resist having a thickness of 3 μm or more is used. If the resist is thick, the etching solution is not sufficiently supplied to the opening, and the etching proceeds in the plane direction rather than the thickness direction of the copper foil or the copper layer, so that a circuit having a sufficient width cannot be formed. Therefore, when forming a thin line circuit, a liquid resist is widely used. Since the thickness of the liquid resist is about 1 μm, the etching solution is more sufficiently supplied to the opening than when a dry film resist is used.

  In addition, there is a method of forming a metal having a slower etching rate than copper or an alloy layer thereof on the etching surface side of the copper foil in order to reduce the bottoming (Patent Documents 3 and 4). These candidate metals are Ni, Co and the like. A layer of several tens of nanometers formed by adhering a large amount of these to the etching surface of the copper foil or copper layer suppresses the lateral etching at the top of the circuit and forms a circuit with a small tail.

  As the circuit pitch of the printed circuit board becomes finer, the circuit interval also becomes smaller, so the circuit tailing must be small. According to Non-Patent Document 1, the circuit width (L, the unit is μm) and the circuit interval (S, the unit is μm) tend to be reduced year by year, and the flexible printed wiring board has L / S = 25 / in 2012. It will reach 25. In order to cope with the fine pitch of the wiring circuit, the thickness of the copper foil must be reduced in order to reduce the bottom of the circuit. However, since the handling at the time of manufacture becomes difficult when the thickness of the copper foil is reduced, it is said that the limit of the wiring pattern that can be handled by the electrolytic copper foil or the rolled copper foil is L / S = 25/25. Even if a metal layer such as Ni or Co is formed on the etched surface of the copper foil, it is expected that it is difficult to cope with such a circuit pattern.

  A method of imparting conductivity by depositing a nickel alloy or the like on a resin film such as polyimide by sputtering and then performing copper plating (metalizing method) is suitable for forming a fine wiring pattern. Since this method can easily change the thickness of the copper layer formed by plating, it is a material suitable for the fine pitch of the wiring circuit. However, since it takes time to form the copper layer, there is a problem that the manufacturing cost is high.

JP 2006-222185 A JP 2000-269619 A JP-A-1994-81172 JP 2002-176242 A

2009 Japan Packaging Technology Roadmap Printed Wiring Board

  In the method of forming a circuit from copper foil (subtractive method), in the conventional thickness, the etching in the planar direction proceeds until the etching in the thickness direction of the copper foil is completed, and the circuit having a cross-sectional shape with a large tailing is only used. Can't get. Since the current concentrates on the upper surface of the circuit with a narrow width, heat is generated and there is a possibility of disconnection in some cases. In addition, it is expected that it will be difficult to mount an IC chip.

  In order to reduce the bottom of the circuit cross section, the thickness of the copper foil may be reduced and the etching time may be shortened. However, the thinner the copper foil, the more difficult it is to handle in the CCL manufacturing process, which adversely affects product yield. Further, when the copper layer is thin as in Patent Document 2, the cross-sectional area of the circuit is reduced, so that there is a possibility that a necessary amount of conductivity cannot be ensured.

  The technique of providing a Ni, Co layer or the like on the etched surface of the copper foil may not be able to cope with the narrow pitch of circuit patterns that are expected to advance in the future. In the prior art, these metals need to be attached in large amounts. Since these metal layers have ferromagnetism, they may adversely affect electronic devices. Therefore, it is necessary to remove these layers by soft etching after circuit formation etching and resist removal, which increases the number of manufacturing steps.

  Further, unlike the case where a dry film resist is thermocompression bonded to the etching surface of the copper foil or the copper layer to obtain physical adhesion, the liquid resist is applied to the etching surface by spin coating or a method equivalent thereto. In general, since a liquid resist is assumed to be in close contact with copper, the compatibility with the surface treatment applied to the etched surface is not always good, and the resist may be easily peeled off. In the case of using a liquid resist, the etching surface is roughened by pretreatment, and physical adhesion is often secured.

  Then, this invention makes it a subject to provide the formation method of the copper foil for printed wiring boards, and the formation method of an electronic circuit which can manufacture the circuit of the cross-sectional shape with small tailing suitable for fine pitch formation with favorable manufacturing efficiency. .

Conventionally, in order to form a fine pitch circuit by a subtractive method, it has been necessary to reduce the thickness of the copper foil. In addition, in order to form a circuit having a cross-sectional shape with a small skirt, it is necessary to deposit a large amount of ferromagnetic Ni or Co on the etched surface of the copper foil to form a layer having a thickness of several tens of nm. On the other hand, as a result of intensive studies, the present inventors have found that when a small amount of noble metal is attached to the etched surface of the copper foil, the bottom of the formed circuit is reduced. As a result, even if the copper foil is not thin, it is possible to form a circuit with a small trailing edge, and thus a high-density mounting substrate can be formed. Furthermore, the adhesion with the liquid resist is ensured by covering the noble metal with a different metal. This makes it possible to omit a pre-processing step that has been conventionally performed, and to stably form a fine wiring pattern.
On the other hand, when there are too many noble metals that originally have corrosion resistance, the initial etching properties of the portions exposed to the resist openings deteriorate, and the linearity of the circuit deteriorates. Therefore, it is necessary to improve the initial etching property by making the amount of noble metal extremely small or by promoting the diffusion of copper from the copper foil base material to the noble metal layer by thermal diffusion or the like. However, the present inventors have found that the adhesiveness to the resist deteriorates when excessive thermal diffusion occurs or when the amount of noble metal is very small. Thermal diffusion always occurs in the CCL manufacturing process, and noble metals are expensive and need to be extremely small for industrialization. Although details are unknown, it is presumed from the analysis result of the surface treatment layer that a structure unfavorable for the adhesion to the resist is formed in a specific case, and this is to promote the resist peeling during the etching.
Therefore, the present inventors control the ratio between the amount of noble metal and copper in the vicinity of the surface layer so that the initial etching property is good, resist peeling is suppressed, and a fine circuit pattern can be formed. It has been found that a copper foil can be obtained.

The present invention completed on the basis of the above knowledge is, in one aspect, a copper foil for a printed wiring board provided with a copper foil substrate and a coating layer covering at least a part of the surface of the copper foil substrate, The coating layer includes at least one of Pt, Pd, and Au, and the coating layer includes Au of 200 to 2000 μg / dm ² , Pt of 200 to 2000 μg / dm ² , and Pd of 120 to 1200 μg. / present at a coverage of dm ^2, when subjected to heat history of the CCL manufacturing process, the depth depth direction obtained from the direction analysis from該被undercover surface by XPS: Pt of (x units nm), Pd, Assuming that the atomic concentration (%) of one or more of Au and Au is f (x) and the atomic concentration of copper is g (x), 0.1 ≦ ∫f (x) dx in the interval [0, 5] / ∫g (x) dx is a copper foil for printed wiring board that satisfies 0.7.

In one embodiment, the copper foil for printed wiring board according to the present invention has an adhesion amount of Pt of 400 to 1050 μg / dm ² or less, an adhesion amount of Pd of 240 to 600 μg / dm ² or less, and an adhesion amount of Au of 400 to 1000 μg. / Dm ² or less.

  In another embodiment of the copper foil for printed wiring board according to the present invention, a rust preventive treatment layer composed of a chromium layer or a chromate layer and / or a silane treatment layer is formed on the outermost layer.

  In yet another embodiment of the copper foil for a printed wiring board according to the present invention, the printed wiring board is a flexible printed wiring board.

  In another aspect, the present invention is a laminate of the copper foil of the present invention and a resin substrate.

  In yet another aspect, the present invention is a laminate including a copper layer and a resin substrate, the laminate including the coating layer of the present invention that covers at least a part of the surface of the copper layer.

  In one embodiment of the laminate according to the present invention, the resin substrate is a polyimide substrate.

  In yet another aspect, the present invention is a printed wiring board made from the laminate of the present invention.

In another aspect of the present invention, a coating layer containing any one or more of Pt, Pd, and Au is formed on at least a part of the surface of the copper foil base material, and the adhesion amount of Pt in the coating layer is 200~2000μg / dm ² or less, the adhesion amount of Pd is 120~1200μg / dm ² or less, so that deposition amount of Au is 200~2000μg / dm ² or less, a dry formed in a continuous line reel-to-reel method Atomic concentration (%) of any one or more of Pt, Pd, and Au in the depth direction (x: unit nm) formed by the film method and obtained from the depth direction analysis from the coated surface by XPS Is f (x) and the atomic concentration of copper is g (x), so that 0.1 ≦ ∫f (x) dx / ∫g (x) dx ≦ 0.7 is satisfied in the interval [0, 5]. Etching after giving thermal history of CCL manufacturing including resist pattern formation A method of forming an electronic circuit forming a circuit by removing unnecessary portions of the copper performs grayed.

  In one embodiment of the method for forming an electronic circuit according to the present invention, the thermal history of CCL manufacture including the process up to the formation of the resist pattern is measured in the depth direction (x : (Nm), when the atomic concentration (%) of at least one of Pt, Pd, and Au is f (x) and the atomic concentration of copper is g (x), 0.15 ≦ ∫f (x) dx / ∫g (x) dx ≦ 0.4 is satisfied.

In another embodiment of the method for forming an electronic circuit according to the present invention, the adhesion amount of Pt is 400 to 1050 μg / dm ² or less, the adhesion amount of Pd is 240 to 600 μg / dm ² or less, and the adhesion amount of Au is 400 to 400 1000 μg / dm ² or less.

  In still another embodiment of the method for forming an electronic circuit according to the present invention, the coating layer is a layer composed of at least one of Pt, Pd, and Au, and one or more metals other than the three types. It is composed of layers consisting of

  In still another embodiment of the method for forming an electronic circuit according to the present invention, the printed wiring board is a flexible printed wiring board.

  In still another embodiment of the method for forming an electronic circuit according to the present invention, a resin substrate is formed on the back surface of the copper foil base material forming the coating layer, and the copper foil base material, the resin substrate, The laminate is composed of

  ADVANTAGE OF THE INVENTION According to this invention, the formation method of the copper foil for printed wiring boards and the electronic circuit which can manufacture the circuit of the cross-sectional shape with small tailing suitable for fine pitch production with favorable manufacturing efficiency can be provided.

It is a photograph which shows the healthy part (part which the resist and copper base material have not peeled). It is a photograph which shows an abnormal part (part from which a resist and a copper base material have partly peeled). It is the outline | summary of the calculation method of the etching factor (EF) using the surface photograph of a part of circuit pattern, the schematic diagram of the cross section of the width direction of the circuit pattern in the said part, and this schematic diagram. It is the density | concentration profile of the depth direction by XPS of the copper foil which concerns on Example 22. FIG.

(Copper foil base material)
Although there is no restriction | limiting in particular in the form of the copper foil base material which can be used for this invention, Typically, it can use with the form of rolled copper foil or electrolytic copper foil. In general, the electrolytic copper foil is produced by electrolytic deposition of copper from a copper sulfate plating bath onto a drum of titanium or stainless steel, and the rolled copper foil is produced by repeating plastic working and heat treatment with a rolling roll. Rolled copper foil is often used for applications that require flexibility.
In addition to high-purity copper such as tough pitch copper and oxygen-free copper, which are usually used as conductor patterns for printed wiring boards, for example, Sn-containing copper, Ag-containing copper, Cr, Zr or Mg are added as the copper foil base material. It is also possible to use a copper alloy such as a copper alloy, a Corson copper alloy to which Ni, Si and the like are added. In addition, when the term “copper foil” is used alone in this specification, a copper alloy foil is also included.

  There is no restriction | limiting in particular also about the thickness of the copper foil base material which can be used for this invention, What is necessary is just to adjust to the thickness suitable for printed wiring boards suitably. For example, it can be set to about 5 to 100 μm. However, for the purpose of forming a fine pattern, it is 30 μm or less, preferably 20 μm or less, and typically about 5 to 20 μm.

  Although the copper foil base material used for this invention is not specifically limited, For example, you may use what does not perform a roughening process. Conventionally, the surface is generally roughened by special plating with irregularities on the order of μm, and the physical anchor effect provides adhesion to the resin. A smooth foil is considered to have good characteristics, and a roughened foil may work in a disadvantageous direction. Moreover, since the roughening process process is abbreviate | omitted if it does not perform a roughening process, there exists an effect of economical efficiency and productivity improvement.

(1) Structure of coating layer The coating layer is formed in at least one part of the surface on the opposite side (circuit formation plan side) of the copper foil base material with the insulating substrate. The coating layer contains at least one of Pt, Pd, and Au. Moreover, the coating layer is composed of a layer made of at least one of Pt, Pd, and Au and a layer made of one or more metals other than the above three, which are sequentially laminated from the surface of the copper foil base material. May be. Examples of the metal other than Pt, Pd, and Au include one or more of Ni, Co, Sn, and Zn. In addition, as a metal other than Pt, Pd, and Au, Ni alloys such as Ni—V, Ni—Sn, Ni—Zn, and Ni—Mn may be used. In this way, when a small amount of noble metal is attached to the etched surface of the copper foil, the bottom of the formed circuit is reduced. As a result, even if the copper foil is not thin, it is possible to form a circuit with a small trailing edge, and thus a high-density mounting substrate can be formed. Further, by covering the noble metal with a dissimilar metal, adhesion with the liquid resist is ensured, whereby a pre-treatment process that has been conventionally performed can be omitted, and a fine wiring pattern can be stably formed.

(2) Identification of coating layer The coating layer can be identified by the presence of each detected peak by performing argon sputtering from the surface layer with a surface analyzer such as XPS or AES and performing chemical analysis in the depth direction.

(3) Amount of adhesion When the coating layer is composed of Pt, the amount of adhesion of Pt is 200 to 2000 μg / dm ² , and more preferably 400 to 1050 μg / dm ² . When the coating layer is composed of Pd, the adhesion amount of Pd is 120 to 1200 μg / dm ² , and more preferably 240 to 600 μg / dm ² . If the coating layer is composed of Au, the adhesion amount of Au is 200~2000μg / dm ^2, and more preferably 400~1000μg / dm ^2. When the coating amount of Pt of the coating layer is less than 200 μg / dm ² , the coating amount of Pd of the coating layer is less than 120 μg / dm ² , and the coating amount of Au of the coating layer is less than 200 μg / dm ² , the effect is obtained. not enough. On the other hand, when the coating amount of Pt in the coating layer is 2000 μg / dm ² , the coating amount of Pd in the coating layer is 1200 μg / dm ² , and the deposition amount of Au in the coating layer exceeds 2000 μg / dm ² , initial etching properties are obtained. Adversely affect.

Further, when the metal layer other than Pt, Pd and Au is one or more single layer or alloy layer of Ni, Co, Sn and Zn, Ni is 1500 μg / dm ² or less, and Co is 1500 μg. / Dm ² or less, Sn is 1200 μg / dm ² or less, and Zn is present in an amount of 1200 μg / dm ² or less. Ni coating amount of the coating layer is 1500 μg / dm ² , Co coating amount of the coating layer is 1500 μg / dm ² , Sn coating amount of the coating layer is 1200 μg / dm ² , Zn coating amount of the coating layer is 1200 μg / dm ^{2 If} it exceeds ² , each will adversely affect the initial etchability.

Ni alloy layer, Ni-V alloy layer deposited amount consists 1500 [mu] g / dm ² or less of Ni and 500 [mu] g / dm ² or less and V, the amount of deposition from 1500 [mu] g / dm ² or less of Ni and 500 [mu] g / dm ² or less of Sn comprising Ni-Sn alloy layer, Ni-Zn alloy layer deposited amount consists 1500 [mu] g / dm ² or less of Ni and 1100μg / dm ² or less of Zn, or the amount of deposition is 1500 [mu] g / dm ² or less of Ni and 500 [mu] g / dm ² The Ni-Mn alloy layer which consists of the following Mn may be sufficient. If the adhesion amount of each metal element exceeds the above range, the initial etching property is adversely affected.

  As described above, by covering the etched surface of the copper foil with a noble metal, side etching is suppressed and a circuit having a cross-sectional shape close to a rectangle can be obtained. On the other hand, when there are too many noble metals that originally have corrosion resistance, the initial etching properties of the portions exposed to the resist openings deteriorate, and the linearity of the circuit deteriorates. Therefore, it is necessary to improve the initial etching property by making the amount of noble metal extremely small or by promoting the diffusion of copper from the copper foil base material to the noble metal layer by thermal diffusion or the like. However, when the amount of excessive heat diffusion or the amount of noble metal is very small, the adhesion with the resist deteriorates. When the state of the surface treatment layer is specific, a structure unfavorable for adhesion to the resist is formed, which is considered to promote the resist peeling during the etching. On the other hand, when the copper foil for printed wiring boards according to the present invention receives a thermal history of CCL production, the depth direction (x: unit nm) obtained from the depth direction analysis from the surface of the coated surface by XPS When the atomic concentration (%) of at least one of Pt, Pd, and Au is f (x) and the atomic concentration of copper is g (x), 0.1 ≦ ∫ in the interval [0, 5] f (x) dx / ∫g (x) dx ≦ 0.7 is satisfied. By controlling the ratio between the amount of noble metal and the amount of copper in the vicinity of the surface layer in this way, the initial etching property is good, resist peeling is suppressed, and a fine circuit pattern can be formed. Further, the ratio of the amount of noble metal in the vicinity of the surface layer to the amount of copper is preferably 0.15 ≦ ∫f (x) dx / ∫g (x) dx ≦ 0.4 in the interval [0, 5]. Here, “thermal history of CCL production” means heating for about 0.5 to 10 hours at 200 to 500 ° C. when CCL production is carried out by a casting method, and 100 to 400 ° C. when carrying out by a laminating method. Shows heating for about 1 to 600 seconds.

  In addition, a base layer may be provided between the copper foil base material and the coating layer from the viewpoint of heat discoloration resistance as long as the initial etching property is not adversely affected. As the underlayer, nickel, nickel alloy, cobalt, silver, and manganese are preferable. The method for providing the underlayer may be either a dry method or a wet method.

  In order to enhance the rust prevention effect, a rust prevention treatment layer composed of a chromium layer or a chromate layer and / or a silane treatment layer can be further formed on the outermost layer on the coating layer. Moreover, in order to suppress the oxidation by heat processing further between the coating layer and copper foil, you may form the base layer which has oxidation resistance.

(Manufacturing method of copper foil)
The copper foil for printed wiring boards according to the present invention can be formed by a dry film forming method, for example, a sputtering method, or further by electroplating. At this time, a continuous conveyance method such as a reel-to-reel method can be used for conveying the copper foil base material. Thereby, at least a part of the surface of the copper foil base material is covered with the coating layer. Specifically, a layer containing any one or more of Pt, Pd, and Au having a lower etching rate than copper is formed on the etching surface side of the copper foil by a sputtering method. Preferably, a layer made of one or more of Pt, Pd, and Au and a layer made of one or more metals other than the above three are formed.

(Printed wiring board manufacturing method)
A printed wiring board (PWB) can be manufactured according to a conventional method using the copper foil according to the present invention. Below, the example of the manufacturing method of a printed wiring board is shown.

  First, a laminated body is manufactured by bonding a copper foil and an insulating substrate. The insulating substrate on which the copper foil is laminated is not particularly limited as long as it has characteristics applicable to a printed wiring board. For example, paper base phenolic resin, paper base epoxy resin, synthetic fiber for rigid PWB Use cloth base epoxy resin, glass cloth / paper composite base epoxy resin, glass cloth / glass non-woven composite base epoxy resin, glass cloth base epoxy resin, etc., use polyester film, polyimide film, etc. for FPC I can do things.

  In the case of the rigid PWB, a prepreg is prepared by impregnating a base material such as a glass cloth with a resin and curing the resin to a semi-cured state. It can be carried out by superposing a copper foil on the prepreg from the opposite surface of the coating layer and heating and pressing.

  In the case of a flexible printed wiring board (FPC), a polyimide film or a polyester film and a copper foil can be bonded using an epoxy or acrylic adhesive (three-layer structure). In addition, as a method without using an adhesive (two-layer structure), a polyimide varnish (polyamic acid varnish), which is a polyimide precursor, is applied to a copper foil and heated to form an imidization or on a polyimide film. There is a laminating method in which a thermoplastic polyimide is applied to the substrate, a copper foil is overlaid thereon, and heated and pressed. In the casting method, it is also effective to apply an anchor coating material such as thermoplastic polyimide in advance before applying the polyimide varnish.

  The laminate according to the present invention can be used for various printed wiring boards (PWB) and is not particularly limited. For example, from the viewpoint of the number of layers of the conductor pattern, the single-sided PWB, double-sided PWB, and multilayer PWB ( It is applicable to rigid PWB, flexible PWB (FPC), and rigid flex PWB from the viewpoint of the type of insulating substrate material. Further, the laminate according to the present invention is not limited to the above-described copper-clad laminate obtained by attaching a copper foil to a resin, and is a metalizing material in which a copper layer is formed on the resin by sputtering or plating. Also good.

  The copper foil of the present invention receives Pt in the depth direction (x: unit nm) obtained from the analysis of the depth direction from the surface of the coated surface by XPS after receiving the thermal history in the production process of CCL using the copper foil. When the atomic concentration (%) of at least one of Pd and Au is f (x) and the atomic concentration of copper is g (x), 0.1 ≦ ∫f (x dx / ｘg (x) dx ≦ 0.7. The thermal history in the CCL manufacturing process is preferably given so as to satisfy 0.15 ≦ ∫f (x) dx / ∫g (x) dx ≦ 0.4 in the interval [0, 5].

A resist is applied to the surface of the coating layer formed on the copper foil of the laminate produced as described above, the pattern is exposed with a mask, and developed to form a resist pattern. At this time, if a layer made of one or more metals other than the three types of Pt, Pd, and Au is formed on the surface of the coating layer of the laminate, the adhesion with the liquid resist is improved, and the coating layer is previously formed. There is no need for surface pretreatment.
Subsequently, the coating layer exposed at the opening of the resist pattern is removed using a reagent. As the reagent, one containing hydrochloric acid, sulfuric acid or nitric acid as a main component is preferably used for reasons such as availability.
Next, the laminate is immersed in an etching solution. At this time, the coating layer containing at least one of Pt, Pd, and Au that suppresses etching is located near the resist portion on the copper foil, and the etching of the copper foil on the resist side Etching of the copper circuit pattern proceeds substantially vertically by etching of the copper in a portion away from the coating layer at a speed faster than the speed at which the vicinity is etched. Thus, unnecessary portions of copper can be removed, and then the etching resist can be peeled and removed to expose the circuit pattern.
With respect to the etching solution used for forming the circuit pattern on the laminate, the etching rate of the coating layer is sufficiently smaller than that of copper, so that the etching factor is improved. As the etching solution, a cupric chloride aqueous solution, a ferric chloride aqueous solution, or the like can be used.
In addition, a heat-resistant layer may be formed in advance on the surface of the copper foil base before forming the coating layer.

(Circuit shape on the copper foil surface of the printed wiring board)
As described above, the circuit on the copper foil surface of the printed wiring board formed by etching from the coating layer side is not usually formed with two long side surfaces perpendicular to the insulating substrate. From the surface of the foil downward, that is, toward the resin layer, it is formed so as to spread toward the end (generation of sagging). Thus, the two long side surfaces each have an inclination angle θ with respect to the surface of the insulating substrate. It is important to reduce the circuit pitch as much as possible for miniaturization (fine pitch) of the circuit pattern that is currently required. However, if this inclination angle θ is small, the sagging increases accordingly, The pitch becomes wider. In addition, the inclination angle θ is usually not completely constant in each circuit and circuit. If the variation in the inclination angle θ is large, the circuit quality may be adversely affected. Accordingly, the circuit on the copper foil surface of the printed wiring board formed by etching from the coating layer side has two long side surfaces each having an inclination angle θ of 65 to 90 ° with respect to the insulating substrate surface, In addition, it is desirable that the standard deviation of tan θ in the same circuit is 1.0 or less. The etching factor is preferably 1.5 or more, and more preferably 2.5 or more when the circuit pitch is 50 μm or less.

  EXAMPLES Examples of the present invention will be described below, but these are provided for better understanding of the present invention and are not intended to limit the present invention.

(Example 1: Examples 1 to 24)
(Formation of coating layer on copper foil)
As a copper foil base material of Examples 1 to 24, a rolled copper foil (Nikko Metal C1100) having a thickness of 8 μm was prepared. The surface roughness (Rz) of the rolled copper foil was 0.5 μm.

The copper foil base material was surface-treated with a roll coater manufactured by Shinko Seiki Co., Ltd. After removing the oxide layer on the copper foil surface by ion gun treatment, a coating layer was formed by sputtering. The thickness of the coating layer was controlled by adjusting the conveyance speed, output, and Ar pressure.
・ Achieving vacuum: 1.0 × 10 ⁻⁵ Pa
Sputtering pressure: Ar 0.2 to 0.4 Pa
・ Sputtering power: 300 to 4000 W
・ Copper foil transport speed: 1-15m / min
Target: Ni, Cr, Au, Pt, Pd (3N)

For the copper foil provided with the coating layer, the oxide film previously adhered to the surface opposite to the coating layer was removed by ion gun treatment, and a Ni layer and a Cr layer were sequentially formed.
On the copper foil subjected to the above-mentioned procedure, a polyimide film with an adhesive (manufactured by Nikkan Kogyo, CISV1215) was laminated in an air atmosphere or an inert atmosphere with a pressure of 7 kgf / cm ² and a heating press at 160 ° C. for 40 minutes. . Since CCL is manufactured by a casting method in addition to laminating, some copper foils are held in a nitrogen atmosphere at 350 ° C. for 2 hours or 5 hours under the assumption that the polyimide is cured, and then the polyimide film is subjected to the above procedure. And laminated. The thermal history that the sample receives when including the later-described resist pattern formation is as follows.
Heat treatment (350 ° C. × n hours (n = 0, 2, 5): in nitrogen)
→ Laminate (160 ° C x 40 min: in air)
→ Resist pattern formation (85 ° C x 30 minutes + 125 ° C x 30 minutes: in air)

<Measurement of adhesion amount>
The adhesion amount of Au, Pd, and Pt in the coating layer was measured by atomic absorption spectrometry by dissolving the surface-treated copper foil sample with aqua regia, diluting the solution.

<Measurement by XPS>
The XPS operating conditions are shown below.
・ Device: XPS measuring device (ULVAC-PHI, Model 5600MC)
・ Achieving vacuum: 3.8 × 10 ⁻⁷ Pa
Excitation source: monochromatic AlKα
・ Output: 210W
・ Detection area: 800μmφ
-Incident angle: 15 degrees, 45 degrees-Extraction angle: 75 degrees, 45 degrees-No neutralization conditions-Sputtering conditions Ion species: Ar ⁺
Acceleration voltage: 3 kV
Sweep area: 3mm x 3mm
Rate: 2.0 nm / min (SiO ₂ conversion)

(Resist pattern formation)
The etched surface of the CCL produced by the above procedure was degreased with acetone and immersed in sulfuric acid (100 g / L) for 30 seconds to remove the surface contamination. Next, a liquid resist (manufactured by Tokyo Ohka Kogyo Co., Ltd., OFPR-800LB) was dropped onto the etching surface using a spin coater and dried (prebaked at 85 ° C., 30 minutes). The resist thickness after drying was adjusted to 1 μm. After that, 10 circuits (30 μm pitch circuit (resist L / S = 25 μm / 5 μm)) are printed through exposure, development, and drying (post-bake 125 ° C., 30 minutes) steps, and unnecessary portions of the copper foil are further printed. The etching process to remove was implemented on condition of the following.

<Etching conditions>
-Ferric chloride aqueous solution: 37 wt% (Baume degree: 40 °)
・ Liquid temperature: 50 ℃
・ Spray pressure: 0.25 MPa
-Finished circuit bottom (bottom) width: around 15μm

<Resistance peel resistance evaluation>
Here, FIGS. 1 and 2 show photographs from the upper part of the circuit where the resist is not stripped with alkali after etching. Among these, FIG. 1 shows a healthy part (a part where the resist and the copper base material are not peeled), and FIG. 2 shows an abnormal part (a part where the resist and the copper base material are partly peeled). If the resist is sufficiently in close contact with the substrate, the metallic luster can be confirmed through the resist as shown in FIG. 1, and the circuit can be confirmed to be a straight line. On the other hand, if the resist and the substrate are peeled off during etching, the metallic luster cannot be confirmed over the resist as in the part surrounded by the dotted line in FIG. The sex is inferior. For this reason, in the resist stripping resistance evaluation in this example, the resist pattern (L / S = 25 μm / 5 μm, 10 pieces) in the resist pattern (L / S = 25 μm, 10 pieces) is ◎, if it is up to 5 places, it is up to 6-15 places A, Δ for 16 to 25 locations, x for 26 or more locations. After the resist stripping resistance evaluation, the resist was stripped by dipping in a 45 ° C. NaOH aqueous solution (100 g / L) for 1 minute.

<Etching factor measurement conditions>
The etching factor is the distance of the length of sagging from the intersection of the vertical line from the upper surface of the copper foil and the resin substrate, assuming that the circuit is etched vertically when sagging at the end (when sagging occurs) Is a ratio of a to the thickness b of the copper foil: b / a, and the larger the value, the larger the inclination angle, and the etching residue does not remain and the sagging is small. It means to become. FIG. 3 shows a surface photograph of a part of the circuit pattern, a schematic diagram of a cross section in the width direction of the circuit pattern at the part, and an outline of an etching factor calculation method using the schematic diagram. This a was measured by SEM observation from above the circuit, and the etching factor (EF = b / a) was calculated. By using this etching factor, it is possible to easily determine whether the etching property is good or bad. Furthermore, the inclination angle θ was calculated by calculating the arc tangent using a and the thickness b of the copper foil measured in the above procedure. The measurement range was a circuit length of 600 μm, and an etching factor of 12 points, its standard deviation, and an average value of the inclination angle θ were adopted as a result.

(Example 2: Comparative Example 1)
Etching samples were prepared in the same procedure as in Example 1 without performing surface treatment on a rolled copper foil (Nikko Metal C1100) having a thickness of 8 μm, and various evaluations were performed.

(Example 3: Comparative Examples 2 to 19)
Etching samples were prepared in the same procedure as in Example 1, and various evaluations were performed.
Each measurement result of Examples 1-2 is shown to Tables 1-2.

<Evaluation>
In each of the examples, the etching factor was large and there was no variation, and a circuit having a cross section close to a rectangular shape could be formed. FIG. 4 shows the concentration profile of the copper foil according to Example 22 in the depth direction by XPS.
In Comparative Example 1, no surface treatment was performed and resist peeling did not occur, but a circuit with a large footing was obtained.
In Comparative Examples 2 to 4, 8 to 10, and 14 to 16, ∫f (x) dx / ∫g (x) dx exceeds 0.7 in the interval [0, 5], and noble metal is near the copper foil surface. However, although resist peeling did not occur, the initial etching property was poor and a circuit could not be formed. In Example 1, the amount of noble metal deposited was the same as in Comparative Examples 2 and 3, but in Example 1 the precious metal concentration in the vicinity of the copper foil surface was lowered by thermal diffusion, so the initial etching property was good. It has become.
In Comparative Examples 5 to 7, 11 to 13, and 17 to 19, the adhesion amount of the noble metal is small, or the ratio of the noble metal amount to the copper amount (∫f (x) dx / ∫g (x) dx) is 0.1. And the resist peeled off.

Claims (6)

When at least a part of the surface of the copper foil base material includes a coating layer containing only one of Pt, Pd, and Au, and the coating layer contains Pt, the amount of Pt deposited on the coating layer is 264 to 961 μg / dm ² or less, when the coating layer contains Pd, the adhesion amount of Pd in the coating layer is 120 to 573 μg / dm ² or less, and when the coating layer contains Au, Au in the coating layer Is formed by a dry film forming method on a continuous line of a reel-to-reel method so that the amount of adhering to 200 to 2000 μg / dm ² or less,
The atomic concentration (%) of Pt, Pd or Au in the depth direction (x: unit nm) obtained from XPS depth direction analysis from the surface of the coated surface is f (x), and the atomic concentration of copper is g ( x), a thermal history of CCL production including resist pattern formation is provided so as to satisfy 0.1 ≦ ∫f (x) dx / ∫g (x) dx ≦ 0.7 in the interval [0, 5]. After
A method of forming an electronic circuit in which an unnecessary portion of copper is removed by etching to form a circuit.   The thermal history of CCL production including the formation of the resist pattern is expressed by the atomic concentration (%) of Pt, Pd, or Au in the depth direction (x: unit nm) obtained from the depth direction analysis from the surface of the coating surface by XPS. ) Is f (x) and the atomic concentration of copper is g (x), 0.15 ≦ ∫f (x) dx / ∫g (x) dx ≦ 0.4 in the interval [0, 5] The method for forming an electronic circuit according to claim 1, wherein the electronic circuit is provided so as to satisfy the condition. When the coating layer contains Pt, the adhesion amount of Pt in the coating layer is 400 to 961 μg / dm ² or less, and when the coating layer contains Pd, the adhesion amount of Pd in the coating layer is 240 to 573 μg / ^{3. The} method of forming an electronic circuit according to claim 1, wherein when the coating layer contains Au, the adhesion amount of Au in the coating layer is 400 to 1000 μg / dm ² or less.   The said coating layer is comprised in the layer which consists of a layer which consists only of 1 type among Pt, Pd, and Au, and a layer which consists of 1 or more types of metals other than said 3 types. Method for forming an electronic circuit.   The method for forming an electronic circuit according to claim 1, wherein the printed wiring board is a flexible printed wiring board.   The resin substrate is formed in the back surface of the copper foil base material which forms the said coating layer, The laminated body is comprised with this copper foil base material and this resin substrate. Method for forming an electronic circuit.