TWI455659B - Printed wiring board with copper foil and the use of its layered body - Google Patents

Description

Copper foil for printed wiring board and laminated body using the same

The present invention relates to a copper foil for a printed wiring board and a laminated board using the same, and more particularly to a copper foil for a flexible printed wiring board and a laminated board using the same.

Printed wiring boards have made great progress in the past half century and have now reached the level of use for almost all electronic devices. With the increase in the demand for miniaturization and high performance of electronic devices in recent years, the high-density mounting of components and the high-frequency of signals are being developed, and the wiring pattern is required to be fine-grained (fine pitch). Fine pitch or high frequency response.

In general, a printed wiring board is manufactured by forming an aluminum-clad laminate on a copper foil or depositing a nickel alloy on an insulating substrate, and then forming a copper layer by electroplating to form a copper-clad laminate, and then etching. A conductor pattern is formed on the copper foil or copper layer. Therefore, good etching properties are required for the copper foil or copper layer for printed wiring boards.

As a technique for improving the etchability, for example, Patent Document 1 discloses an invention of a copper foil with a silver-based coating layer: silver or silver is provided on the bonding surface of the insulating substrate as a constituent material of the copper-clad laminate. A silver-based coating layer composed of a palladium alloy.

[Patent Document 1] Japanese Patent Laid-Open Publication No. 2005-101398

However, in order to form a high-density package substrate with a precision circuit which has been required in recent years, it is not sufficient to simply make the etching property of the copper foil good. which is, The etching property required in recent years means that the metal from the surface treatment does not remain in the insulating portion between the circuits, and the taper of the circuit is small. If the metal remains in the insulating portion between the circuits, a short circuit occurs between the circuits. Further, during the etching of the circuit formation, etching is performed from the upper surface of the circuit downward (on the insulating substrate side) to make the cross section of the circuit trapezoidal. If the difference between the upper and lower bottoms of the trapezoid (hereinafter referred to as "taper") is small, the interval between circuits can be narrowed, and a high-density wiring board can be obtained. If the taper is large, the circuit is short-circuited when the interval between the circuits is reduced, so that it is not possible to manufacture a high-density package substrate.

On the other hand, in the invention disclosed in Patent Document 1, since a coating layer made of a noble metal is formed on the roughened surface of the copper foil, side etching is not suppressed, and it is difficult to form a circuit having a small taper.

Therefore, an object of the present invention is to provide a copper foil for a printed wiring board which is suitable for a fine pitch and which can produce a circuit having a small taper shape, and a laminated board using the same.

As a result of intensive studies, the present inventors have found that when a trace amount of precious metal is attached to the etched surface of the copper foil as a layer, the taper of the formed circuit is reduced, whereby a high-density package substrate can be formed. Such a configuration is based on the idea that the composition of the coating layer made of a noble metal is substantially different from the roughened surface of the copper foil described in Patent Document 1, and the effect is also greatly different.

The present invention, which is completed based on the above findings, is a copper foil for a printed wiring board comprising: a copper foil substrate and a coating layer, the coating layer covering at least a part of the surface of the copper foil substrate, and including One or more of the group consisting of Au, Pt, and Pd; and the adhesion amount of Au in the coating layer is 200 μg/dm ² or less, and the adhesion amount of Pt is 200 μg/dm ² or less, and the adhesion amount of Pd is 120 μg/dm ² or less.

In one embodiment of the copper foil for a printed wiring board of the present invention, the adhesion amount of Au in the coating layer is 30 to 200 μg/dm ² or less, and the adhesion amount of Pt is 30 to 200 μg/dm ² or less, and Pd is The adhesion amount is 25 to 120 μg/dm ² or less.

In another embodiment of the copper foil for a printed wiring board according to the present invention, the coating layer further contains one or more selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn.

In still another embodiment of the copper foil for a printed wiring board according to the present invention, the metal selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn is Ni and Co, and Ni in the coating layer The adhesion amount is 300 μg/dm ² or less, and the adhesion amount of Co is 300 μg/dm ² or less.

In still another embodiment of the copper foil for a printed wiring board according to the present invention, the depth direction (x: unit nm) obtained by analyzing the depth direction from the surface by XPS is selected from the group consisting of Au, Pt, and Pd. The atomic concentration (%) of one or more types is f(x), and the atomic concentration of one or more metals selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn is g(x). When the depth of the first maximum value in f(x) and g(x) in the interval [0, 5] is X, g(X) ≧ f(X) is satisfied.

In another aspect, the invention provides a method for forming an electronic circuit, comprising the steps of: preparing a rolled copper foil or an electrolytic copper foil composed of the copper foil of the invention; and using the coating layer of the copper foil as an etched surface, a step of preparing the laminate of the copper foil and the resin substrate; and dissolving with ferric chloride The liquid or copper chloride aqueous solution etches the above laminated body, and removes a circuit that does not require copper to form copper.

In another aspect, the present invention is a laminate which is a laminate of the copper foil and the resin substrate of the present invention.

In still another aspect, the present invention provides a laminate comprising a laminate of a copper layer and a resin substrate, comprising a coating layer of the present invention covering at least a portion of a surface of the copper layer.

In another aspect, the present invention is a printed wiring board using the laminate of the present invention as a material.

According to the present invention, it is possible to provide a copper foil for a printed wiring board which is suitable for a fine pitch and which can produce a circuit having a cross-sectional shape having a small taper, and a laminated board using the same.

(copper foil substrate)

The form of the copper foil substrate which can be used in the present invention is not particularly limited, and is typically used in the form of a rolled copper foil or an electrolytic copper foil. In general, an electrolytic copper foil is produced by electrically analyzing copper from a copper sulfate plating bath onto a titanium or stainless steel drum, and the rolled copper foil is repeatedly produced by plastic working and heat treatment using a calender roll. Rolled copper foil is often used in applications where flexibility is required.

As the material of the copper foil substrate, in addition to high-purity copper such as refined copper or oxygen-free copper which is usually used as a conductor pattern of a printed wiring board, for example, Sn-doped copper, Ag-doped copper, Cr, Zr or Mg added may be used. A copper alloy such as a Cason copper alloy such as Ni or Si is added to the copper alloy. Furthermore, in this description When the term "copper foil" is used alone in the book, it also contains a copper alloy foil.

The thickness of the copper foil substrate which can be used in the present invention is also not particularly limited as long as it is appropriately adjusted to a thickness suitable for a printed wiring board. For example, it can be set to about 5 to 100 μm. However, in the case of forming a fine pattern, it is 30 μm or less, preferably 20 μm or less, and typically about 5 to 20 μm.

The copper foil substrate used in the present invention is not particularly limited, and for example, those which have not been subjected to roughening treatment can also be used. In the prior art, the surface roughening treatment is performed by attaching a special plating to the surface with a μm-order unevenness, and has an adhesion to the resin due to a physical anchor effect. On the other hand, fine In terms of pitch or high-frequency electrical characteristics, it is considered that the smooth foil is better, and the roughened foil is in a bad direction. In addition, if it is not roughened, the roughening process step is omitted, and the effect of improving economical efficiency and productivity is improved.

(1) Composition of the cover layer

A coating layer is formed on at least a portion of the surface of the copper foil substrate opposite to the bonding surface of the insulating substrate (predetermined to form the circuit surface side). The coating layer contains one or more selected from the group consisting of Au, Pt, and Pd. The metal other than Pt, Pd, and Au may be one or more selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn. If such a precious metal is slightly attached to the etched surface of the copper foil, the taper of the formed circuit becomes small. Thereby, even if the thickness of the copper foil is not thin, a circuit having a small taper can be formed, so that a high-density package substrate can be formed. The thickness of the coating layer is 0.2 to 3 nm, preferably 0.4 to 3 nm. If the thickness of the coating layer is less than 0.2 nm, the side etching effect will be suppressed. It is insufficient and the resist peeling resistance is deteriorated. Even if the thickness of the coating layer exceeds 3 nm, it is difficult to further improve the initial etching property, and therefore it is preferably controlled to be 3 nm or less in terms of cost.

(2) Identification of the coating

The coating layer can be identified by argon sputtering from the surface layer by a surface analysis device such as XPS or AES, and subjected to chemical analysis in the depth direction, and identified by the presence of each detection peak.

(3) Adhesion amount

When the coating layer contains Au, the adhesion amount of Au is 200 μg/dm ² or less, preferably 30 to 200 μg/dm ² , more preferably 80 to 200 μg/dm ² . When the coating layer contains Pt, the adhesion amount of Pt is 200 μg/dm ² or less, preferably 30 to 200 μg/dm ² , more preferably 80 to 200 μg/dm ² . When the coating layer contains Pd, the adhesion amount of Pd is 120 μg/dm ² or less, preferably 25 to 120 μg/dm ² , more preferably 60 to 120 μg/dm ² . Even if the adhesion amount of Au in the coating layer exceeds 200 μg/dm ² , the adhesion amount of Pt in the coating layer exceeds 200 μg/dm ² , and the adhesion amount of Pd in the coating layer exceeds 120 μg/dm ² , and it is difficult to further improve the initial stage. Since the etching property is controlled, the adhesion amount of Au is controlled to 200 μg/dm ² or less, the adhesion amount of Pt is controlled to 200 μg/dm ² or less, and the adhesion amount of Pd is controlled to 120 μg/ Dm ² or less.

And, when one or more kinds selected from the group consisting of covering layer comprises Ni, V, Co, Cr, Sn , and Zn in the composition of the Ni and Co, the Ni deposition amount of the 300 μg / dm ² or less, preferably 80 ~300 μg/dm ² . Further, the adhesion amount of Co is 300 μg/dm ² or less, preferably 80 to 300 μg/dm ² . Even if the adhesion amount of Ni and Co in the coating layer exceeds 300 μg/dm ² , it is difficult to further improve the initial etching property. Therefore, in terms of cost, it is preferable to control the adhesion amount of Ni and Co to 300 μg, respectively. /dm ² or less.

(4) Atomic concentration on the surface of the coating

The coating layer is preferably one or more atomic concentrations (%) selected from the group consisting of Au, Pt, and Pd in the depth direction (x: unit nm) obtained by depth analysis from the surface by XPS. In the case of f(x), the atomic concentration of one or more metals selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn is g(x), and f is obtained in the interval [0, 5]. When the depth of the first maximum value in (x) and g(x) is X, g(X) ≧ f(X) is satisfied. When the amount of the noble metal adhered is small, the noble metal does not exist in a layer form but in an island shape on the copper foil base material, so that the side etching suppressing effect is insufficient. However, since a noble metal is formed as a "precious metal alloy layer" by forming a different layer such as Ni or Co thereon, the side etching suppressing effect can be improved. Further, by covering the noble metal layer with such a different layer such as Ni or Co, peeling of the resist is less likely to occur during etching.

Here, the "first maximum value" means the maximum value that exists first when the surface of the coating layer is viewed in the depth direction.

Further, as long as the initial etching property is not adversely affected, the underlayer may be provided between the copper foil substrate and the coating layer from the viewpoint of heat discoloration resistance. The base layer is preferably nickel, nickel alloy, cobalt, silver or manganese. The method of setting the base layer may be either dry or wet.

In order to enhance the rust-preventing effect, a rust-preventing treatment layer composed of a chromium layer, a chromate layer, and/or a decane-treated layer may be further formed on the outermost layer on the coating layer. Further, in order to suppress oxidation by heat treatment, it is also possible to coat the coating layer. A base layer having oxidation resistance is formed between the copper foil and the copper foil.

(Manufacturing method of copper foil)

The copper foil for a printed wiring board of the present invention can be formed by a sputtering method. That is, at least a part of the surface of the copper foil substrate is coated with a coating layer by sputtering. Specifically, a layer formed of one or more selected from the group consisting of Au, Pt, and Pd having an etching rate lower than that of copper is formed on the etched surface side of the copper foil by a sputtering method. The coating layer is not limited to the sputtering method, and may be formed, for example, by wet plating such as electroplating or electroless plating. In this case, the coating layer may be formed by further adding one or more selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn.

Further, the copper foil for a printed wiring board of the present invention is preferably pretreated as a surface of the copper foil by a known method before the sputtering treatment.

(Manufacturing method of printed wiring board)

A printed wiring board (PWB) using the copper foil of the present invention can be manufactured according to a usual method. An example of a method of manufacturing a printed wiring board is shown below.

First, a copper foil and an insulating substrate are bonded together to produce a laminate. The insulating substrate in which the copper foil is laminated is not particularly limited as long as it has characteristics applicable to the printed wiring board. For example, for rigid PWB, paper substrate phenol resin, paper substrate epoxy resin, synthetic fiber can be used. Cloth substrate epoxy resin, glass cloth-paper composite substrate epoxy resin, glass cloth-glass non-woven composite substrate epoxy resin and glass cloth substrate epoxy resin, etc., for FPC (Flexible Print Circuit, flexible) For the printed circuit, a polyester film, a polyimide film, or the like can be used.

About the method of fitting, when used in the case of rigid PWB, prepare to make glass A prepreg obtained by impregnating a substrate such as a glass cloth with a resin and curing the resin to a semi-hardened state. The copper foil can be bonded by superposing the surface of the copper foil from the opposite side of the coating layer on the prepreg and heating and pressing.

In the case of a flexible printed wiring board (FPC), an epoxy-based or acrylic-based adhesive may be used instead of a polyimide film or a polyester film and a copper foil (three-layer structure). Further, a method in which no adhesive is used (two-layer structure) may be exemplified by a casting method in which a polyimide varnish (polyamic acid varnish) which is a precursor of polyimine is coated on a copper foil. And by imidization by heating, or by laminating, a thermoplastic polyimide is coated on the polyimide film, and the copper foil is laminated thereon and heated and pressurized. In the casting method, it is also effective to apply an anchor coat material such as thermoplastic polyimide under the pre-coating of the polyimide pigment varnish.

The laminate of the present invention can be used for various printed wiring boards (PWB), and is not particularly limited. For example, it can be applied to a single-sided PWB, a double-sided PWB, or a multilayer PWB (three or more layers) from the viewpoint of the number of layers of the conductor pattern. From the viewpoint of the type of the insulating substrate material, it can be applied to a rigid PWB, a flexible PWB (FPC), or a rigid-flexible PWB. Moreover, the laminated body of the present invention is not limited to the copper-clad laminate which is obtained by attaching a copper foil to a resin, and may be a metal spray which is formed by sputtering or plating on a resin. (metallizing) material.

A resist is applied to the surface of the coating layer formed on the copper foil of the laminate produced as described above, and the pattern is exposed and developed by a mask to form a resist pattern.

Then, the reagent is used to remove the exposed portion of the opening of the resist pattern. Cladding. As the reagent, it is preferred to use hydrochloric acid, sulfuric acid or nitric acid as a main component for reasons such as easy availability. Since the precious metal layer is very thin, the copper of the copper foil substrate is moderately diffused during the thermal history of the manufacturing process, and the diffusion of the copper atoms reaching the outermost layer due to the drying step of the atmosphere or the resist is performed by the diffusion. It is oxidized to form copper oxide. In the noble metal/copper alloy layer formed by diffusion, since the copper oxide is easily dissolved in the acid, the noble metal is also removed. Therefore, even a noble metal layer having corrosion resistance can be easily removed from a portion exposed to the opening of the resist pattern.

Then, the layered body is immersed in the etching liquid. At this time, the coating layer containing any one or more of platinum, palladium, and gold which suppress etching is located at a position close to the resist portion on the copper foil, and the etching of the copper foil on the resist side is made closer to the vicinity of the coating layer. The etch is performed at a faster rate to perform copper etching away from the portion of the cladding layer, thereby etching the copper circuit pattern substantially vertically. Thereby, the part that does not need copper can be removed and then peeled off. The resist is removed to expose the circuit pattern.

The etching liquid for forming a circuit pattern on the laminated body has an effect of improving the etching factor because the etching speed of the coating layer is sufficiently smaller than that of copper. As the etching liquid, an aqueous solution of copper chloride or an aqueous solution of ferric chloride or the like can be used.

Further, a heat-resistant layer may be formed in advance on the surface of the copper foil substrate before the formation of the coating layer.

(Circuit shape of copper foil surface of printed wiring board)

In the circuit of the copper foil surface of the printed wiring board formed by etching from the coating layer side as described above, the two side faces of the strip are not formed vertically. The insulating substrate is usually formed from the surface of the copper foil downward, that is, gradually extending toward the resin layer (the occurrence of depression). Thereby, both sides of the elongated strip have an inclination angle θ with respect to the surface of the insulating substrate. In order to achieve the miniaturization (fine pitch) of the circuit pattern required at present, it is important to narrow the distance between the circuits as much as possible, but if the inclination angle θ is small, the corresponding depression will become larger, and the distance between the circuits will be widened. . Further, the inclination angle θ is not always completely fixed in each circuit and circuit. If the unevenness of the inclination angle θ is large, there is a problem that the quality of the circuit is adversely affected. Therefore, it is preferable that the copper foil surface circuit of the printed wiring board formed by etching from the coating layer side has an inclined angle θ of 65 to 90° with respect to the surface of the insulating substrate, and is in the same circuit. The standard deviation of tan θ is 1.0 or less. Further, when the etching factor is 50 μm or less between the circuits, it is preferably 1.5 or more, and more preferably 2.5 or more.

[Examples]

The following examples of the invention are provided to provide a better understanding of the invention and are not intended to limit the invention.

(Example 1: Examples 1 to 7, 9 to 15, 18 to 22, 24, 25, 27 to 29, 31, 32) (formation of the coating layer on the copper foil (etched surface))

A rolled copper foil (C1100 manufactured by Nippon Mining Metal Co., Ltd.) having a surface roughness (Rz) of 0.1 μm and a thickness of 8 μm was prepared as a copper foil substrate.

The surface of the copper foil was pretreated by using a Vaccume WEB Chamber (14 Å wide) manufactured by CHA Corporation, which has an ion beam source. The ion beam source was a linear Ion Source (manufactured by ION TECH INC) of a Kaufmann type ion beam source of 6.0 cm × 40 cm. The source of the ion beam source is the company's MPS-5001, and the maximum output of the ion beam is approximately 3 W/cm ² .

The treatment conditions before the surface treatment were performed using the ion beam were as follows: Output: 1.2 W/cm ²

Argon pressure: 0.2 Pa

Copper foil conveying speed: 10 m/min.

By using the pretreatment to remove a thin oxide film adhering to the surface of the copper foil, and sputtering a target of Au, Pt, Pd, Ni, V, Co, Cr, Sn, Zn or the alloy to form a coating Floor. A single system of various metals for sputtering uses a purity of 3 N. Further, CoCr (Cr: 20% by mass), NiV (V: 7% by mass), NiZn (Zn: 20% by mass), and NiSn (Sn: 20% by mass) were used as specific alloy targets. In the film formation order, any one of Au, Pt, and Pd is formed, and then a layer made of any one of Ni, V, Co, Cr, Sn, and Zn is formed. The amount of adhesion is adjusted by changing the output.

(Formation of surface treatment layer (following surface))

The surface of the copper foil substrate on the opposite side to the surface on which the coating layer was formed was formed into an adhesive layer with a polyimide film using the same sputtering apparatus. After removing the thin oxide film by the pretreatment, a Ni layer (the adhesion amount was 90 μg/dm ² ) was formed, and a Cr layer (the adhesion amount was 70 μg/dm ² ) was formed thereon.

(Measurement of adhesion amount)

The coating amount of Au, Pt, and Pd in the coating layer was measured by dissolving one-half of the copper layer with aqua regia, and diluting the solution to be carried out by atomic absorption spectrometry. Further, a film of a surface of a copper layer of 50 mm × 50 mm was dissolved in a solution in which HNO ₃ (2% by weight) and HCl (5% by weight) were mixed, and an ICP emission spectrometer (SFC manufactured by SII NanoTechnology Co., Ltd.) was used. -3100) The metal concentration in the solution was quantified, and the amount of metal per unit area (μg/dm ² ) was calculated.

(measured by XPS)

The following shows the conditions for implementing XPS in the depth analysis of the coating layer.

. Device: XPS measuring device (ULVAC-PHI, model 5600MC)

. Ultimate vacuum: 3.8×10 ^-7 Pa

. X-ray: monochromatic AlKα or non-monochromatic MgKα, X-ray output is 300 W, detection area is 800 μm , the angle between the sample and the detector is 45°

. Ion beam: ion type is Ar ⁺ , accelerating voltage is 3 kV, scanning area is 3 mm × 3 mm, sputtering rate is 2.0 nm/min (SiO ₂ conversion)

(CCL)

The polyimide film (CISV1215 manufactured by NIKKAN Co., Ltd.) with an adhesive was applied under the conditions of a pressure of 7 kgf/cm ² , 160 ° C, and 40 minutes, followed by formation of the Ni layer and the Cr layer of the copper foil substrate. surface.

(by etching the circuit shape)

On the surface of the copper foil on which the surface treatment layer was formed, 10 21 μm wide circuits (opening width: 9 μm) were printed by a photosensitive resist coating and exposure step, and removal of the copper foil was performed under the following conditions. Part of the etching process.

(etching conditions)

The etching was performed using a spray etching apparatus under the following conditions.

. Liquid composition

Copper chloride (2.0 mol/L) + hydrochloric acid (1.5 mol/L)

. Spray pressure: 0.2 MPa

. Liquid temperature: 50 ° C

(Form a 30 μm pitch circuit)

. Resist L/S=21 μm/9 μm

. Complete the bottom of the circuit: 15 μm

. Confirmation of the end point of etching: etching was performed for several degrees of etching, and it was confirmed by an optical microscope that copper was not left between circuits and was set as an etching time.

After the etching, the resist was peeled off by immersing in an aqueous NaOH solution (100 g/L) at 45 ° C for 1 minute.

(Measurement conditions of etching factor)

In the case of a gradually expanding etching (indentation), it is assumed that the distance between the vertical line from the copper layer and the indentation length of the resin substrate when the circuit is vertically etched is a, the etching factor indicates the a and copper. The ratio b of the thickness b of the layer is b/a. The larger the value is, the larger the inclination angle is, and no etching residue remains, and the depression is small. 1 is a view showing a surface photograph of a portion of a circuit pattern, a cross-sectional view in a width direction of a circuit pattern in the portion, and an outline of an etching factor calculation method using the schematic diagram. This a is measured by SEM observation from above the circuit, and the etching factor (EF = b / a) is calculated. The etchability can be easily determined by using the etching factor. Further, the inclination angle θ is calculated by calculating the arc tangent using a measured by the above procedure and the thickness b of the copper layer. These measurement ranges are within the circuit length of 600 μm, 12 The point etch factor, using the average of its standard deviation and tilt angle θ as a result.

Here, FIGS. 2 and 3 are photographs showing the upper portion of the circuit in which the resist is not peeled off by alkali after the etching. 2 shows a normal portion (a portion where the resist and the copper substrate are not peeled off), and FIG. 3 shows an abnormal portion (a portion where the resist and the copper substrate are partially peeled off). When the resist was sufficiently adhered to the substrate, as shown in Fig. 2, it was confirmed that the metal gloss was over the resist, and it was confirmed that the circuit was a straight line. On the other hand, if the resist and the substrate are peeled off during the etching, it is impossible to confirm that the metallic luster covers the resist as in the portion surrounded by the broken line in FIG. 3, and the straight line of the portion is compared with the normal portion. Poor sex. Therefore, in the resist peeling resistance evaluation of the present embodiment, in the resist pattern (L/S = 21 μm / 9 μm, 10 strips), if the resist is peeled off as shown in FIG. When it is set to ○, it is set to △ when it is 16 to 25, and is set to × when it is 26 or more.

(Example 2: Examples 16, 17, 26, 33 (alloy target))

In the procedure of Example 1, PdNi (Pd is 20% by mass), AuNi (Au is 20% by mass), and PtNi (Pt is 20% by mass) are sputtered on a rolled copper foil (C1100 made of Nippon Minerals) having a thickness of 8 μm. Each alloy layer is formed. The resist pattern was printed on the surface, and the etching property was evaluated.

(Example 3: Examples 8, 23, 30)

After forming a NiV alloy layer by sputtering on a rolled copper foil (C1100 manufactured by Nippon Mining Co., Ltd.) having a thickness of 8 μm, any layer of Au, Pd, or Pt was formed by sputtering. The resist pattern was printed on the surface, and the etching property was evaluated.

(Example 4: Comparative Example 1 (blank material))

Rolled copper foil with a thickness of 8 μm thick in the procedure of Example 1 It is manufactured by C1100) and polyimide film, and the etching property is evaluated.

(Example 5: Reference Examples 2, 7, and 8, Comparative Examples 3 to 6)

The Pd, Au, Pt, NiV, CoCr, NiSn, and NiZn layers were formed by sputtering on a rolled copper foil (C1100 made of Nippon Minerals) having a thickness of 8 μm in the procedure of Example 1. The resist pattern was printed on the surface, and the etching property was evaluated.

The test conditions and measurement results of Examples 1 to 5 are shown in Tables 1 and 2.

Further, the depth analysis using XPS after sputtering in Example 12 is shown in Fig. 4 .

<evaluation>

In Examples 1, 6, 18, 20, and 27, resist peeling occurred during etching, but when the etching factor was measured in the portion where the circuit was formed, it was larger than the value of the blank material (Comparative Example 1).

In Examples 2 to 4, 7, 9 to 14, 19, 21, 22, 24, 28, 29, and 31, the precious metal layer is covered with a layer other than the noble metal and Cu, whereby even a very small amount of precious metal is attached. The resist peeling is not generated in the etching, and a circuit having a small taper can be formed.

In the examples 5, 15, 25, and 32, the adhesion amount of the main component Ni covering the noble metal layer exceeds 300 μg/dm ² , but the examples 4, 12, 24, and 31 are the same as the precious metal adhesion amount. In comparison, it is known that since the taper of the circuit is the same, even if the adhesion amount of Ni exceeds 300 μg/dm ² , the effect is saturated, and the adhesion amount of the main component Ni covering the noble metal layer is 300 μg/in terms of the cost surface. Dm ² or less.

In Examples 8, 23, and 30 in which the noble metal layer was the outermost layer, the etching factor was small as compared with Examples 7, 22, and 29 in which the adhesion amount was the same. From this, it is understood that it is preferable to cover a very small amount of a noble metal layer with a layer of a different metal.

In Examples 16, 17, 26, and 33 in which the alloy target was used, the etching factor was also increased as compared with the blank material (Comparative Example 1).

In Comparative Examples 3 to 6, the etching factor was higher than that of the blank material, but the etching factor was smaller than when there was a combination with the noble metal layer.

When Examples 19, 24, and 31 of the reference examples 2, 7, and 8 were compared with each other, it was found that since the etching factor was the same, the adhesion amount of Au was 200 μg/dm ² or less, and Pt was The adhesion amount is 200 μg/dm ² or less, and the adhesion amount of Pd may be 120 μg/dm ² or less.

A‧‧‧distance

B‧‧‧ Thickness of copper layer

1 is a photograph of a surface of a portion of a circuit pattern, a schematic cross-sectional view in the width direction of a circuit pattern in the portion, and an outline of a method for calculating an etching factor (EF) using the schematic.

Figure 2 is a magnified surface photograph of the entire circuit pattern.

Figure 3 is an enlarged surface photograph of the abnormal portion of the circuit pattern.

Figure 4 is a depth profile using XPS after sputtering of Example 12.

Claims (9)

A copper foil for a printed wiring board comprising: a copper foil base material and a coating layer, the coating layer covering at least a part of a surface of the copper foil base material, and comprising one or more selected from the group consisting of Au, Pt, and Pd; Further, the adhesion amount of Au in the coating layer is 200 μg/dm ² or less, the adhesion amount of Pt is 200 μg/dm ² or less, and the adhesion amount of Pd is 120 μg/dm ² or less; wherein the depth from the surface is measured by XPS The atomic concentration (%) of one or more selected from the group consisting of Au, Pt, and Pd in the depth direction (x: unit nm) obtained by the direction analysis is f(x), and is selected from Ni, V, Co, The atomic concentration of one or more metals in the group consisting of Cr, Sn, and Zn is g(x), and the first maximum value of f(x) and g(x) is obtained in the interval [0, 5]. When the depth is set to X, g(X) ≧ f(X) is satisfied. The copper foil for a printed wiring board according to the first aspect of the invention, wherein the adhesion amount of Au in the coating layer is 30 to 200 μg/dm ² or less, and the adhesion amount of Pt is 30 to 200 μg/dm ² or less, and Pd is The adhesion amount is 25 to 120 μg/dm ² or less. The copper foil for a printed wiring board according to the first aspect of the invention, wherein the coating layer further comprises one or more selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn. The copper foil for a printed wiring board according to claim 3, wherein the metal selected from the group consisting of Ni, V, Co, Cr, Sn, and Zn is Ni and Co; and Ni in the coating layer The adhesion amount is 300 μg/dm ² or less, and the adhesion amount of Co is 300 μg/dm ² or less. A method for forming an electronic circuit, comprising the steps of: preparing a rolled copper foil or an electrolytic copper foil composed of a copper foil according to any one of claims 1 to 4; using the coating layer of the copper foil as an etched surface a step of producing a laminate of the copper foil and the resin substrate; and etching the laminate using an aqueous solution of ferric chloride or copper chloride, and removing a portion of the copper that does not require copper to form a circuit. A laminate which is a laminate of a copper foil and a resin substrate according to any one of claims 1 to 4. A laminate comprising a laminate of a copper layer and a resin substrate, and a coating layer according to any one of claims 1 to 4, which covers at least a part of the surface of the copper layer. A printed wiring board is made of a laminate of the sixth application of the patent application. A printed wiring board is made of a laminate of the seventh application of the patent application.