JP2011203962A - Verification apparatus and verification method for semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the design quality of a semiconductor integrated circuit.SOLUTION: A verification apparatus for the semiconductor integrated circuit verifies the conformity of a circuit connection relation between connection specification information indicative of a connection relation of a circuit constituting the semiconductor integrated circuit and circuit description information describing a constitution of the semiconductor integrated circuit, and includes an assertion production unit for converting the connection specification information into a connection information file described in an assertion language, a comparison unit for comparing conformity between first terminal information and second terminal information depending on the first terminal information obtained by extracting an open terminal from the connection specification information and the second terminal information obtained by extracting information on an open terminal from the circuit description information, and a formal verification unit for performing formal verification depending on the connection information file and the circuit description information, and verifies the connection relation of the circuit constituting the semiconductor integrated circuit from the verification result of the formal verification unit and the comparison result of the comparison unit.

Description

  The present invention relates to a semiconductor integrated circuit verification apparatus and verification method.

  In general, logic circuit verification methods are roughly classified into logic simulation and formal verification. Logic simulation is a method in which an input pattern is applied to a circuit to be verified to simulate an operation, and an output pattern is compared with an expected value to verify the correctness of the circuit.

  On the other hand, formal verification is a method for verifying the correctness of a circuit by mathematically analyzing a design specification and a circuit to be verified. The design specifications are generally described in PSL (Property Specification Language) standardized by IEEE or SVA (System Verilog Assertion) assertion language.

  A semiconductor integrated circuit is composed of functional blocks (hereinafter referred to as macros). The scale of semiconductor integrated circuits is increasing year by year. In a large-scale semiconductor integrated circuit, when a logic simulation is used to verify the connection relationship between macros constituting a large amount of time, it takes a huge amount of test patterns and a long time to simulate them. For this reason, a great amount of verification steps are required.

  On the other hand, in formal verification, since it is not necessary to create a test pattern, a significant reduction in man-hours can be expected. In addition, since it can be mathematically proved, there is no worry of test pattern leakage in the simulation. For this reason, formal verification is more effective than simulation for connection verification between macros, and its use is expanding.

  As a semiconductor integrated circuit verification apparatus for formal verification of the consistency of circuit connection relations with the connection specifications of the circuits constituting the semiconductor integrated circuit and its circuit description, for example, a verification apparatus as disclosed in Patent Document 1 has been proposed. The configuration of the verification apparatus 10 disclosed in Patent Document 1 is shown in FIG.

  As illustrated in FIG. 13, the verification apparatus 10 includes a property generation unit 3, a verification execution unit 5, and a verification result confirmation unit 6.

  The property generation unit 3 reads the connection specification 1 of the circuit to be verified and generates a property 4. The property generation unit 3 sets unique properties for each output signal, and generates the same property or a property obtained by adding polarity information to the same property for the input signal to which the output signal is connected.

  The verification execution means 5 reads the property 4 and the circuit description 2 and compares and verifies whether the properties of the connected output signal and input signal match.

  The verification result confirmation unit 6 displays the verification result in the verification execution unit 5.

Japanese Patent Laid-Open No. 2005-196681

  In the conventional technique such as Patent Document 1, only the one that can be converted from the connection specification to the assertion (property) can be verified. For this reason, it is usually impossible to verify a location where a macro terminal of a semiconductor integrated circuit existing as a connection specification is open (not connected).

  This is open in the assertion languages (for example, PSL, SVA) generally used as the description language of the design specification in the formal verification performed for verifying the coincidence between the design specification of the semiconductor integrated circuit and the circuit description. This is because there is no concept of describing a terminal and it cannot be described.

  Therefore, there is a problem that it cannot be distinguished whether the designer intentionally opened it or opened it as a design mistake.

  One embodiment of the present invention is a semiconductor integrated circuit that verifies the consistency of circuit connection relation between connection specification information indicating a connection relation of circuits constituting the semiconductor integrated circuit and circuit description information describing the configuration of the semiconductor integrated circuit. An assertion generator for converting the connection specification information into a connection information file described in an assertion language, first terminal information obtained by extracting an open terminal from the connection specification information, and the circuit A comparison unit that compares the match between the first terminal information and the second terminal information in accordance with second terminal information obtained by extracting information on terminals that are open from the description information; the connection information file; and A formal verification unit that performs formal verification according to the circuit description information, and configures the semiconductor integrated circuit from the verification result of the formal verification unit and the comparison result of the comparison unit. A verification device for a semiconductor integrated circuit to verify the connection relation of the circuit to be.

  Another aspect of the present invention is a semiconductor integrated circuit that verifies the consistency of circuit connection relation between connection specification information indicating a connection relation of circuits constituting a semiconductor integrated circuit and circuit description information describing the structure of the semiconductor integrated circuit. A method for verifying a circuit, comprising: converting the connection specification information into a connection information file described in an assertion language; extracting first open terminals from the connection specification information; and the circuit description information. The first terminal information and the second terminal information are compared in accordance with the second terminal information obtained by extracting the information of the terminal that is open, and in accordance with the connection information file and the circuit description information. Formal verification is performed, and the connection relation of the circuits constituting the semiconductor integrated circuit is checked from the verification result of the formal verification and the comparison result of the coincidence between the first terminal information and the second terminal information. It is a method of verifying a semiconductor integrated circuit.

  The verification apparatus for a semiconductor integrated circuit according to the present invention includes not only connection specifications limited between the terminals of the circuits constituting the semiconductor integrated circuit but also open (unconnected) locations of the terminals of the circuits constituting the semiconductor integrated circuit. It is possible to verify the coincidence of the circuit connection relationship with the circuit description as the design result by using the connected specification. As a result, in addition to verifying the connection of the circuit constituting the semiconductor integrated circuit, the open terminal of the circuit constituting the semiconductor integrated circuit is distinguished whether the designer intentionally opened it or opened it as a design error. It is possible.

  The present invention makes it possible to improve the design quality of a semiconductor integrated circuit.

1 is a block diagram showing a configuration of a semiconductor integrated circuit verification device according to a first exemplary embodiment; 3 is an example of connection specification information according to the first exemplary embodiment; 1 is an example of a configuration of a semiconductor integrated circuit configured by a circuit description according to a first embodiment; 3 is an example of a Verilog description of a circuit description according to the first exemplary embodiment; It is an example of the assertion file produced | generated by the assertion production | generation part concerning Embodiment 1. FIG. It is an example of the bind file produced | generated by the assertion production | generation part concerning Embodiment 1. FIG. 3 is an example of an open list generated by an open list generation unit according to the first embodiment; 4 is an example of result information generated by a verification result confirmation unit according to the first exemplary embodiment; FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit verification device according to a second exemplary embodiment; 6 is an example of connection specification information according to the second exemplary embodiment; It is an example of the result information which the verification result confirmation part concerning Embodiment 2 generates. It is a block diagram which shows the structure of the verification apparatus of the semiconductor integrated circuit concerning other embodiment. It is a block diagram which shows the structure of the verification apparatus of the conventional semiconductor integrated circuit.

  Embodiment 1 of the Invention

  Hereinafter, a specific first embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the first embodiment, the present invention is applied to a semiconductor integrated circuit verification apparatus. FIG. 1 shows a block configuration of a verification apparatus of the semiconductor integrated circuit 100 according to the first embodiment.

  As shown in FIG. 1, the semiconductor integrated circuit verification apparatus 100 includes an assertion generation unit 103, an open list generation unit 105, an open detection unit 107, a formal verification unit 108, an open comparison unit 109, and a verification result confirmation. Part 110.

  The assertion generation unit 103 converts the connection specification 101 into an assertion 104 that is a connection information file described in an assertion language.

  Here, the connection specification 101 describes connection specifications between macros of the circuit description 102 to be verified. The circuit description 102 is a circuit description to be verified describing the configuration of the semiconductor integrated circuit, and is composed of a plurality of macros and is generally described in Verilog or VHDL.

  The formal verification unit 108 verifies the consistency between the assertion 104, which is a connection information file, and the circuit description 102.

  The open list generation unit 105 extracts open (not connected) terminal information from the connection specification 101 and generates the open list 106.

  The open detection unit 107 extracts terminal information that is open (not connected) from the circuit description 102.

  The open comparison unit 109 compares the open list 106 generated by the open list generation unit 105 with the open terminal information of the circuit description 102 extracted by the open detection unit 107.

  The verification result confirmation unit 110 displays the verification result obtained by the formal verification unit 108 and the open comparison result obtained by the open comparison unit 109 as a comprehensive verification result.

  Next, the operation of the semiconductor integrated circuit verification apparatus 100 will be described. First, an example of the connection specification 101 is shown in FIG. FIGS. 3 and 4 show a configuration example and Verilog description example of the semiconductor integrated circuit S_CHIP based on the circuit description 102, respectively. Since it is obvious to those skilled in the art that the description content of Verilog in FIG. 4 becomes the configuration of the semiconductor integrated circuit S_CHIP in FIG. 3, detailed description regarding the description content in FIG. 4 is omitted.

  The semiconductor integrated circuit is usually composed of a plurality of macros. In the example of FIG. 3, the semiconductor integrated circuit S_CHIP has two macros D_MACRO and C_MACRO. Here, the instance names of the macros D_MACRO and C_MACRO are configured as DINST and CINST, respectively, and are connected as shown in FIG.

  The configuration of the semiconductor integrated circuit S_CHIP in FIG. 3 is defined as a connection specification, which is the connection specification 101 in FIG. In this connection specification 101, connection between macros, connection between a macro and an external terminal, a location clamped by a macro terminal, and a location open (unconnected) by a macro terminal are defined.

  In detail, as shown in Fig. 2, the top module name, from-side instance name, port name, bit range, to-side instance name, port name, and bit range are described. Connections are defined.

  For example, if the macro instance name CINST and the terminal name CLK are connected to the external terminal with the external terminal name CCLK, “CINST” in the From instance-name column and “CLK” in the From port-name column "Exported:" indicating external terminal connection in the To instance-name column, and "CCLK" in the To port-name column.

  Also, if the specification is such that the bus terminal with macro instance name CINST and terminal name DATA_O [31: 0] is connected to the bus terminal with macro instance name DINST and terminal name DATA_I [31: 0], From instance -name field is "CINST", From port-name field is "DATA_O", From msb field is "31", From lsb field is "0", To instance-name field is "DINST", To port-name field is “DATA_I”, “31” in the Tomsb column, and “0” in the Tolsb column.

  In addition, if the macro instance name DINST and the terminal whose terminal name is ACK are open (unconnected), “DINST” in the From instance-name field, “ACK” in the From port-name field, To In the instance-name field, “open:” indicating opening is described.

  An assertion 104 is generated from the connection specification 101 by the assertion generation unit 103. The assertion 104 is composed of an assertion file and a bind file. The assertion is generated in a generally used SVA (System Verilog Assertion) language. Hereinafter, it is assumed that the SVA language is also used in the first embodiment.

  An example of an assertion file generated by the assertion generation unit 103 from the example of the connection specification in FIG. 2 is shown in FIG. 5, and an example of the bind file is shown in FIG. The operation of the assertion generation unit 103 will be described with reference to FIGS. 2, 5, and 6.

As shown in FIG. 5, the assertion of connection verification is created in such a way that each assert statement calls the property block syntax shown below whose property name is connection.

property connection (sig_a, sig_b);
@ (sva_check_clk) (sig_a == sig_b);
endproperty: connection

In the connection specification 101 of FIG. 2, in the specification in which the terminal having the macro instance name CINST and the terminal name CLK is connected to the external terminal having the external terminal name CCLK, the assert statement is generated as follows.

CINST__CLK___CCLK:
assert property (connection (CINST_p_CLK, CCLK));

  Here, for “CINST__CLK___CCLK”, a label is generated so that the instance name, the terminal name, and the external terminal name can be recognized by the assert label. In addition, the connection property block syntax is called by the “assert property (connection (CINST_p_CLK, CCLK))”.

  The band file of FIG. 6 is generated so that “CINST_p_CLK” of connection (CINST_p_CLK, CCLK) is bound to S_CHIP.CINST.CLK indicating the terminal having the macro instance name CINST and the terminal name CLK in the circuit description 102. Similarly, the bind file of FIG. 6 is generated so that “CCLK” of connection (CINST_p_CLK, CCLK) is bound to S_CHIP.CCLK indicating the external terminal having the external terminal name CCLK in the circuit description 102. Thereafter, an assert statement and a bind file are generated from the connection specification 101 of FIG.

  Here, the open list 106 is generated from the connection specification 101 by the open list generation unit 105. An open list 106 generated by the open list generation unit 105 from the connection specification 101 of FIG. 2 is shown in FIG.

  The operation of the open list generation unit 105 will be described with reference to FIGS. In the connection specification of FIG. 2, a line whose To instance-name column is “open:” is extracted, and an open list is generated from the instance name, terminal name, and bit range. When the To instance-name field is “open:”, the From instance-name field is “DINST”, and the From port-name field is “ACK”, “DINST.ACK” is displayed in the open list as shown in FIG. Generated.

  Here, an open terminal is detected by the open detection unit 107 from the circuit description 102. The operation of the open detection unit 107 will be described with reference to FIG. The open detection unit 107 traces whether each terminal of each macro is connected to another macro, to an external terminal, or to be clamped in the circuit description 102 of FIG. But what is not is detected as open. In the case of the circuit description 102 in FIG. 3, ACK and END [7: 1] which are terminals of the macro name D_MACRO and the instance name DINST are detected. And this detection result is produced | generated as open terminal information.

  Here, the formal verification unit 108 verifies the consistency between the assertion 104 and the circuit description 102. The operation of the formal verification unit 108 will be described with reference to FIGS. 5, 6, and 4.

The formal verification unit 108 binds the assertion file description of FIG. 5 and the circuit description 102 (Verilog description) of FIG. 4 in accordance with the bind file of FIG. 6, and then verifies whether the bound target is connected. To do. For example, the description of the assertion file in FIG. 5 as shown below is an assertion that verifies that DINST_p_TCO and CINST_p_INT [9] are connected.
DINST__TCO___CINST__INT__msb9lsb9:
assert property (connection (DINST_p_TCO, CINST_p_INT [9]));

  According to the description of the assertion file, DINST_p_TCO is bound to S_CHIP.DINST.TCO of the Verilog description of FIG. 4 according to the bind file of FIG. Here, “S_CHIP.DINST.TCO” indicates a terminal having a module name S_CHIP, an instance name DINST, and a terminal name TCO in the Verilog description of FIG.

  Also, CINST_p_INT [9] is bound to S_CHIP.CINST.INT [9] of the Verilog description of FIG. 4 according to the bind file of FIG. Here, “S_CHIP.CINST.INT [9]” indicates a terminal having the module name S_CHIP, the instance name CINST, and the terminal name INT [9] in the Verilog description of FIG.

  Whether the module name S_CHIP, instance name DINST, and terminal name TCO of the Verilog description and the terminal of module name S_CHIP, instance name CINST, and terminal name INT [9] are connected by this assertion file description. The formal verification unit 108 performs formal verification. In this formal verification, if the terminals are connected, the assertion is determined to be Pass, or if different connections are made in the Verilog description, it is determined to be Fail. Such formal determination is performed for each description of the assertion file in FIG.

  Here, the open list 106 and the open terminal information detected by the open detection unit 107 are compared by the open comparison unit 109. Based on the comparison result, open comparison result information is generated as to whether they match or whether there is an extra list or a missing list in the open list 106.

  If it is determined by the open comparison result information that they match, it indicates that the circuit description 102 is designed in accordance with the specifications of the open terminal described in the connection specification 101.

  Also, when it is determined by the open comparison result information that there is an extra list in the open list 106, there is a part that is not open in the circuit description 102, unlike the open terminal specification described in the connection specification 101. Is shown. On the other hand, when it is determined by the open comparison result information that there is a list that is not sufficient for the open list 106, this indicates that an open terminal that is not defined in the connection specification 101 exists in the circuit description 102.

  The verification result confirmation unit 110 receives the determination information on the coincidence between the assertion 104 from the formal verification unit 108 and the circuit description 102, and the location where the open comparison unit 109 and the terminal of the macro of the circuit description 102 are open. Read open comparison result information. And it displays on a display apparatus etc. as a comprehensive verification result, or outputs as data to a data output apparatus etc. For example, in the case of the connection specification 101 of FIG. 2 and the circuit description 102 (Verilog description) of FIG. 4, the result shown in FIG. 8 is displayed.

  The operation of the verification result confirmation unit 110 will be described below with reference to FIG. As shown in Fig. 8, "Pass" of "Assertion check result (Summary)" is the number of places where the circuit description is connected according to the connection specification, and "Fail" is the circuit description according to the connection specification. The number of places that are not displayed is displayed.

  Also, as shown in FIG. 8, “Pass” of “Open terminal check result (Summary)” indicates the number of locations where the terminals of the macro in the circuit description are open according to the connection specification. “Fail” indicates the number of locations where the connection specification is open but the circuit description does not open the corresponding macro terminal. “Undef” displays the number of locations that are not defined as open in the connection specification but are open in the circuit description.

  Further, the assertion check result (details) displays the assert label and the results of Pass and Fail. The assert label is the same as that shown in FIG. 5 and is configured as “<instance name> _ << terminal name> __ <instance name> _ << terminal name>”. Then, it can be seen from the above information which connection assertion between terminals has passed or failed.

  Further, in the “open terminal check result (detail)”, the open terminal extracted from the connection specification and the circuit description is displayed with the information of the Pass, Fail, and Undef.

  As described above, the verification apparatus 100 for the semiconductor integrated circuit according to the first embodiment uses the connection specification 101 when the connection verification between macros is performed in the formal verification that does not require the test pattern. The consistency of the circuit connection relationship with the description 102 can be verified.

  This is a formal verification between the assertion 104 generated by the assertion generation unit 103 and the circuit description 102 for the connection specifications between the macro terminals, and the open list generation unit 105 for the open specifications of the macro terminals. This is performed by comparing the open list 106 and the open terminal information generated by the open detection unit 107 from the circuit description 102.

  As a result, in addition to verifying the connection between macros, it is possible to distinguish whether the open terminal of a macro is intentionally open or whether it is open as a design error, which improves the design quality of semiconductor integrated circuits. It becomes possible.

  Embodiment 2 of the Invention

  Hereinafter, a specific second embodiment to which the present invention is applied will be described in detail with reference to the drawings. In the second embodiment, as in the first embodiment, the present invention is applied to a semiconductor integrated circuit verification apparatus. FIG. 9 shows a block configuration of the verification apparatus of the semiconductor integrated circuit 200 according to the first embodiment.

  As shown in FIG. 9, the semiconductor integrated circuit verification apparatus 200 includes an assertion generation unit 103, an open list generation unit 105, an open detection unit 107, a formal verification unit 108, an open comparison unit 109, and a verification result confirmation. Unit 110 and specification coverage comparison unit 211. In addition, the structure which attached | subjected the code | symbol same as FIG. 1 among the codes | symbols shown in FIG. 9 has shown the structure similar to or similar to FIG. The difference from the first embodiment is that a specification coverage comparison unit 211 is further provided. Therefore, in the second embodiment, the different parts will be described with emphasis, and description of other parts similar to those of the first embodiment will be omitted unless particularly necessary.

  The specification coverage comparison unit 211 reads the assertion 104, the open list 106, and the circuit description 102, and verifies that the circuit description 102 has no extra connection other than the defined connection specification.

  The verification result confirmation unit 110 compares the verification result determination information obtained by the formal verification unit 108, the open comparison result information obtained by the open comparison unit 109, and the specification coverage comparison obtained by the specification coverage comparison unit 211. Together with the result information, it is displayed as a comprehensive verification result.

  Next, the operation of the semiconductor integrated circuit verification apparatus 200 will be described. In the description of this operation, only the difference from the first embodiment is performed. Description of other parts similar to those in the first embodiment is omitted.

  The specification completeness comparison unit 211 reads the assertion 104, the open list 106, and the circuit description 102. Then, all external terminals and macro terminals are extracted from the circuit description 102. From the assertion 104, all the external terminals and macro terminals included in the description of the assertion are extracted. The terminal extracted from the assertion 104 plus the terminal of the open list 106 is compared with the terminal extracted from the circuit description 102, and the result is transmitted to the verification result confirmation unit 110.

  The verification result confirmation unit 110 compares the assertion 104 from the formal verification unit 108 with the determination information on the coincidence between the circuit description 102 and the open comparison unit 109 from the comparison between the open list 106 and the part where the macro terminal of the circuit description 102 is open. The result information (open comparison result information) is comparison result information (specification coverage comparison) between the terminal information of the assertion 104 and the terminal information of the circuit description 102 obtained by adding the terminal information of the open list 106 to the terminal information of the assertion 104 from the specification coverage comparison unit 211. Result information) and display it as a comprehensive verification result.

  Here, FIG. 10 shows an example of the connection specification 101 of the second embodiment. In the case of this connection specification 101 and the circuit description 102 (Verilog description) of FIG. 4, the verification result confirmation unit 110 displays the result shown in FIG.

  In the connection specification 101 of FIG. 10, compared to the connection specification 101 of FIG. 2, the terminal having the macro instance name DINST and the terminal name TCO and the terminal having the macro instance name CINST and the terminal name INT [9] Connection is not defined. The connection specification 101 in FIG. 10 and the designed circuit description 102 in FIG. 4 have forgotten to define the part without the above definition in the connection specification 101, or the connection specification 101 in error by the circuit description 102 in FIG. It is possible that you have designed a connection that is not present.

  The operation of the verification result confirmation unit 110 will be described with reference to FIG. The “assertion check result (Summary)”, “open terminal check result (Summary)”, “assertion check result (detail)”, and “open terminal check result (detail)” shown in FIG. 11 are the same as in the first embodiment. Therefore, explanation is omitted.

  As shown in FIG. 11, in the “connection definition omission check result (Summary)”, the terminal information of the circuit description 102 does not coincide with the terminal information of the circuit description 102 than the terminal information of the assertion 104 plus the terminal information of the open list 106. If there is a bad terminal, the number is displayed as “Fail”. In addition, in the “connection definition omission check result (detail)”, when terminal information of the circuit description 102 includes extra terminal information other than the terminal information of the assertion 104 plus the terminal information of the open list 106 Displays the terminal name.

  As described above, the semiconductor integrated circuit verification apparatus 200 according to the second embodiment uses the connection specification 101 when performing connection verification between macros in formal verification that does not require a test pattern, as in the first embodiment. Thus, the consistency of the circuit connection relationship with the circuit description 102 as the design result can be verified.

  This is a formal verification between the assertion 104 generated by the assertion generation unit 103 and the circuit description 102 for the connection specifications between the macro terminals, and the open list generation unit 105 for the open specifications of the macro terminals. This is performed by comparing the open list 106 and the open terminal information generated by the open detection unit 107 from the circuit description 102.

  As a result, in addition to verifying the connection between macros, it is possible to distinguish whether the open terminal of a macro is intentionally open or whether it is open as a design error, which improves the design quality of semiconductor integrated circuits. It becomes possible.

  Furthermore, in the second embodiment, the specification coverage comparison unit 211 can compare the terminal of the assertion 104 with the terminal of the open list 106 and the terminal of the circuit description 102.

  What added the terminal of the open list | wrist 106 to the terminal of the assertion 104 is a terminal including the open location defined by the connection specification 101. FIG. For this reason, the specification coverage comparison unit 211 compares this with the terminal of the circuit description 102, so that it is possible to verify whether the connection specification including the open part can be comprehensively verified.

  In the first embodiment, as the comprehensiveness verification of the connection specification, there is a possibility that the verification that there is no extra connection other than the connection specification in the circuit description or the verification of the leakage of the connection specification is insufficient. It was. However, in the second embodiment, it is possible to accurately verify that there is no extra connection in the circuit description other than the defined connection specification, or to verify the connection specification omission in the circuit description. Therefore, the design quality of the semiconductor integrated circuit can be further improved as compared with the first embodiment.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

  For example, the above-described semiconductor integrated circuit verification device according to the first and second embodiments may be realized by a computer 300 such as a PC as shown in FIG. Hereinafter, an example in which a semiconductor integrated circuit verification apparatus is configured with such a computer 300 will be briefly described. As illustrated in FIG. 12, the computer 300 includes a CPU 301, a main memory 302, an HDD 303, a ROM 304, an input / output device 305, and a bus 306. A bus 306 is connected to the CPU 301, the main memory 302, the HDD 303, the ROM 304, and the input / output device 305, and transmits various types of information.

  Each information of the connection specification 101 and the circuit description 102 described above is stored in the HDD 303 of the computer 300, the database 307 in the network, or the like. Then, the CPU 301 calls a program (hereinafter referred to as a processing program) for realizing verification of the semiconductor integrated circuit stored in the HDD 303 or the ROM 304 and develops it in the main memory 302.

  The assertion generation unit 103, open list generation unit 105, open detection unit 107, formal verification unit 108, open comparison unit 109, verification result confirmation unit 110, and specification coverage comparison unit 211 described above are modularized in this processing program. ing. Note that an operating system that controls the computer 300 may control each module program.

  For example, in the first embodiment, programs that operate as the assertion generation unit 103 and the open list generation unit 105 generate the assertion 104 and the open list 106 from the information of the connection specification 101 stored in the HDD 303 or the like. A program that operates as the open list detection unit 105 generates open terminal information from the circuit description 102 stored in the HDD 303 or the like.

  Then, a program that operates as the formal verification unit 108 generates determination information from the assertion 104 and the connection specification 101. In addition, a program that operates as the open comparison unit 109 generates open comparison result information. Then, a program that operates as the verification result confirmation unit 110 displays it on a display device (not shown) or the like as a comprehensive verification result corresponding to the determination information and the open comparison result information.

  Note that the assertion generation unit 103, the open list generation unit 105, the open detection unit 107, the formal verification unit 108, the open comparison unit 109, the verification result confirmation unit 110, and the specification coverage comparison unit 211 are not programs but dedicated hardware. It may be realized.

100, 200 Semiconductor integrated circuit verification apparatus 101 Connection specification 102 Circuit description 103 Assertion generation unit 104 Assertion 105 Open list generation unit 106 Open list 107 Open detection unit 108 Formal verification unit 109 Open comparison unit 110 Verification result confirmation unit 211 Specification coverage Comparison part

Claims (9)

A verification apparatus for a semiconductor integrated circuit that verifies the consistency of circuit connection relation between connection specification information indicating a connection relation of circuits constituting a semiconductor integrated circuit and circuit description information describing a configuration of the semiconductor integrated circuit,
An assertion generator for converting the connection specification information into a connection information file described in an assertion language;
The first terminal information according to the first terminal information extracted from the connection specification information and the second terminal information extracted from the circuit description information. A comparison unit for comparing the coincidence of the second terminal information;
A formal verification unit that performs formal verification according to the connection information file and the circuit description information;
A verification apparatus for a semiconductor integrated circuit that verifies a connection relation of circuits constituting a semiconductor integrated circuit from a verification result of the formal verification section and a comparison result of the comparison section. An open detection unit, and an open list generation unit;
The open list generation unit extracts terminal information that is open from the connection specification information, and generates the first terminal information.
2. The semiconductor integrated circuit verification device according to claim 1, wherein the open detection unit extracts information on a terminal that is open from the circuit description information and generates the information as the second terminal information. 3. The semiconductor integrated circuit according to claim 1, wherein an open terminal can be verified in a connection relationship of the circuits constituting the semiconductor integrated circuit from a verification result of the formal verification unit and a comparison result of the comparison unit. Verification device. It also has a specification coverage comparison unit,
The specification coverage comparison unit extracts connection relations of circuits constituting the semiconductor integrated circuit from the connection information file, the first terminal information, and the circuit description information, and generates third terminal information. The verification apparatus of the semiconductor integrated circuit of any one of Claims 1-3 which do. From the verification result of the formal verification unit, the comparison result of the comparison unit, and the third terminal information, the terminal that is open in the connection relationship of the circuits constituting the semiconductor integrated circuit, and the connection specification information The semiconductor integrated circuit verification device according to claim 4, wherein the matching error of the circuit description information can be verified. A method for verifying a semiconductor integrated circuit for verifying the coincidence of circuit connection relation between connection specification information indicating a connection relation of circuits constituting a semiconductor integrated circuit and circuit description information describing a configuration of the semiconductor integrated circuit,
Convert the connection specification information into a connection information file described in the assertion language,
The first terminal information according to the first terminal information extracted from the connection specification information and the second terminal information extracted from the circuit description information. Compare the consistency of the second terminal information,
Perform formal verification according to the connection information file and the circuit description information,
A semiconductor integrated circuit verification method for verifying a connection relationship of circuits constituting a semiconductor integrated circuit from a verification result of the formal verification and a comparison result of coincidence between the first terminal information and the second terminal information. The open terminal can be verified in the connection relationship of the circuits constituting the semiconductor integrated circuit from the verification result of the formal verification and the comparison result of the coincidence between the first terminal information and the second terminal information. Item 7. A method for verifying a semiconductor integrated circuit according to Item 6. 8. The third terminal information is generated by extracting a connection relationship of circuits constituting the semiconductor integrated circuit from the connection information file, the first terminal information, and the circuit description information. 2. A method for verifying a semiconductor integrated circuit according to 1. Based on the verification result of the formal verification, the comparison result of the coincidence between the first terminal information and the second terminal information, and the third terminal information, the connection relationship of the circuits constituting the semiconductor integrated circuit is opened. 9. The method for verifying a semiconductor integrated circuit according to claim 8, wherein the terminal and the coincidence error between the connection specification information and the circuit description information can be verified.

Images