JP2011203079A - Clock control circuit, control method of the same, semiconductor device, and clock generation method of the semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock control circuit capable of setting a set value without using an external terminal, and a control method of the clock control circuit.SOLUTION: This clock control circuit includes a clock control block 11 for generating a scan clock of a circuit as an object of a scan test, a block setting storage circuit 13 for setting a set value for the clock control block 11, and a setting storage circuit 12 for scanning that is arranged between the clock control block 11 and block setting storage circuit 13, receives the set value of the block setting storage circuit 13, and sets the set value for the clock control block 11 in the scan test.

Description

  The present invention relates to a clock control circuit that generates a scan clock for a scan test, a control method thereof, a semiconductor device, and a clock generation method thereof, and more particularly, a clock control circuit that requires a predetermined setting during a scan test, a control method thereof, and a semiconductor The present invention relates to an apparatus and a clock generation method thereof.

  Conventionally, a scan path test is known as a method for testing an internal circuit (combination circuit) and the like. In this scan path test, a flip-flop connected to a combinational circuit to be tested is composed of a shift register called a scan chain, a serial input SCAN-IN terminal, a serial output SCAN-OUT terminal, and a test mode input SCAN. A terminal for ENABLE and a terminal for test clock input SCAN-CLOCK are provided, and test data is input to the scan chain via these terminals. The circuit under test is tested by observing data from the scan chain from the SCAN-OUT terminal.

  Patent Document 1 includes a test circuit that supports a plurality of test methods and incorporates a test circuit into one circuit to be tested to enable a test by a plurality of test methods without increasing the number of test terminals. A circuit is disclosed. This test circuit has a register for switching modes, and saves a setting value in the register and switches test settings to realize terminal reduction.

JP 2004-191055 A

  However, although it is effective when it has two test modes of the scan test and the boundary scan test, it cannot be applied to a configuration having neither the scan test mode nor the boundary scan test mode and circuit. is there.

  For example, consider a case where a semiconductor integrated circuit (LSI) has a clock control circuit that generates a scan clock at the time of a scan test and an internal circuit of a circuit under test on which the scan test is performed. The clock control circuit includes a plurality of blocks A to C and a block setting storage circuit that sets a setting value corresponding to each block.

  In such an LSI, at the time of a scan test, the clock control circuit generates a scan clock and supplies the scan clock to the scan chain of the internal circuit. At this time, the clock control circuit divides the clock input from the outside and outputs it to the internal circuit. For this reason, the block A to the block C are configured by, for example, a PLL (Phase Locked Loop), a frequency dividing circuit, a selector, or the like. Then, in accordance with the scan clock to be output, a set value for determining a frequency division ratio or the like is set in each of the blocks A to C. The block setting storage circuit is a circuit for setting the set values in the blocks A to C.

  Here, at the time of the scan test, the block setting storage circuit also needs to be scan-tested. However, when this block setting storage circuit is subjected to a scan test, the block setting storage circuit cannot continue to hold the set value, and therefore, the set value cannot be set in the blocks A to C. Once the set value is set, the block setting storage circuit cannot be scan-tested this time.

  A clock control circuit according to the present invention is a clock control circuit that supplies a clock to a scan chain during a scan test, and stores a clock generation circuit that generates the clock and a setting value that specifies an operation of the clock generation circuit A second storage unit is coupled between the clock generation circuit and the first storage unit, and stores the setting value stored in the first storage unit as a setting value for a scan test. And the clock generation circuit generates the clock based on the setting value for the scan test stored in the second storage unit during a scan test.

  A semiconductor device according to the present invention includes a clock generation circuit and realizes a predetermined function. The semiconductor device includes a scan flip-flop that forms a scan chain, and determines the operation of the clock generation circuit. A first storage unit that stores a set value, and is arranged between the clock generation circuit and the first storage unit, acquires the first set value at a predetermined timing, and stores it as a second set value. A clock signal based on the second set value when the semiconductor device performs a scan test using the scan chain. And when the semiconductor device performs a normal operation for realizing the predetermined function, the previous setting value is generated based on the first setting value or the second setting value. And it generates a clock signal.

  In the present invention, since the second storage unit is provided, it is not necessary to use the setting value of the first storage unit during the scan test. Therefore, the scan test of the first storage unit can be performed at the time of the scan test.

  The control method of the clock control circuit according to the present invention is a control method of the clock control circuit that supplies a clock to the scan chain during a scan test, and in the normal mode, a setting that specifies the operation of the clock generation circuit that generates the clock The set value is received from a first storage unit that stores a value, a clock is generated, and is arranged between the clock generation circuit and the first storage unit and stored in the first storage unit during a scan test. The set value is received from a second storage unit that stores the set value as a set value for a scan test, and a clock is generated.

  A clock generation method for a semiconductor device according to the present invention is a clock generation method for a semiconductor device that has a clock generation circuit and realizes a predetermined function. The clock generation circuit is configured to scan the semiconductor device using the scan chain. When performing a test, the first set value is arranged between the clock generation circuit and a first storage unit configured by a scan flip-flop constituting a scan chain and determining the operation of the clock generation circuit. Is generated at a predetermined timing and stored as a second setting value, a clock signal is generated based on the second setting value of the second storage unit not including the scan flip-flop, and the semiconductor device When performing a normal operation for realizing the function, the clock signal is based on the first set value or the second set value. It is intended to generate a.

  In the present invention, when a scan test is performed, the clock generation circuit is between the clock generation circuit and a first storage unit that is configured by a scan flip-flop that forms a scan chain and determines the operation of the clock generation circuit. In order to generate a clock by receiving the second setting value from the second storage unit that does not include the scan flip-flop that is arranged at the predetermined timing and acquires the first setting value at a predetermined timing and stores it as the second setting value. Can be scan-tested.

  Another clock control circuit according to the present invention is a clock control circuit that supplies a clock to a scan chain during a scan test, the clock generation circuit generating the clock, and

  A first storage unit that stores a setting value that specifies the operation of the clock generation circuit; and a second storage unit that stores a setting value that specifies the operation of the clock generation circuit during a scan test;

  The first storage unit is connected to a scan chain during the scan test, and a scan test is performed.

  ADVANTAGE OF THE INVENTION According to this invention, the clock control circuit which can perform the scan test of the memory | storage part which sets a setting value to a clock generation circuit, its control method, a semiconductor device, and its clock generation method can be provided.

1 is a diagram illustrating a clock control circuit and its peripheral circuits according to a first embodiment of the present invention. 1 is a block diagram showing details of a clock control circuit 10 according to a first exemplary embodiment of the present invention. It is a figure which shows the modification concerning Embodiment 1 of this invention. It is a figure which shows the setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. It is a figure explaining the normal operation | movement of the scan setting preservation | save circuit concerning Embodiment 2 of this invention. Similarly, it is a diagram for explaining a normal operation of the scan setting storage circuit according to the second embodiment of the present invention. Similarly, it is a diagram for explaining a normal operation of the scan setting storage circuit according to the second embodiment of the present invention. It is a figure explaining the scan test operation | movement of the setting storage circuit for a scan concerning Embodiment 2 of this invention. Similarly, it is a diagram for explaining a scan test operation of the scan setting storage circuit according to the second embodiment of the present invention. It is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. Similarly, it is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. Similarly, it is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. Similarly, it is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. Similarly, it is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. Similarly, it is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention. Similarly, it is a figure which shows the other setting storage circuit 12 for a scan concerning Embodiment 2 of this invention.

  Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In this embodiment, the present invention is applied to a scan clock control circuit that generates a scan clock for a scan test.

Embodiment 1 of the present invention.
FIG. 1 is a diagram illustrating a clock control circuit and its peripheral circuits according to the present embodiment. As shown in FIG. 1, the semiconductor integrated circuit includes a clock control circuit 10, a scan test target circuit 20, and a bus 40. The scan test target circuit 20 includes a combinational logic circuit 22 that performs a scan test, and a plurality of flip-flops (FF) 21 that form a scan chain for performing the scan test.

  The clock control circuit 10 includes clock control blocks A11 to C11 as clock generation circuits, scan setting storage circuits A12 to C12 as second storage units, and a block setting storage circuit 13 as first storage units. Have. The clock control blocks A11 to C11 generate a scan clock by, for example, dividing a clock input from the outside. For this reason, the clock control blocks A11 to C11 include, for example, a PLL (Phase Locked Loop), a frequency dividing circuit, or a selector. In these clock control blocks A11 to C11, setting values for setting a frequency division value and the like are set in order to generate a clock having a predetermined frequency or the like when the clock is generated. The scan setting storage circuit A12 is coupled between the clock control blocks A11 to C11 and the block setting storage circuit 13, and stores the setting values stored in the block setting storage circuit 13 as scan test setting values. is there.

  The scan setting storage circuits A12 to C12 (hereinafter referred to as the scan setting storage circuit 12 unless otherwise distinguished) are not connected to the bus 40 and set the setting values from the block setting storage circuit 13. It is configured to be. Since it is not directly connected to the bus 40, that is, it is not necessary to capture data from the bus 40, the scan setting storage circuit 12 does not require a bus interface circuit or the like. Since the setting storage circuit 12 is separated from the bus 40, there is no possibility that the setting value is erroneously rewritten due to noise or the like. Further, as will be described later, the scan setting storage circuit 12 can capture and set the setting value from the block setting storage circuit 13 in the normal mode, so that the setting of the scan setting storage circuit 12 is set during the scan test. There is no need to do it again. The scan setting storage circuit 12 does not constitute a scan chain.

  The block setting storage circuit 13 is a circuit that sets setting values in the clock control blocks A11 to C11 in the normal mode, not in the test mode, and stores setting values that specify the operation of the clock control blocks A11 to C11. The block setting storage circuit 13 receives a setting value from the bus 40, and this is referred to as a clock control block A11 to C11 (hereinafter referred to as a clock control block 11 if it is not necessary to distinguish between them) via a scan setting storage circuit A12. ). In the present embodiment, the block setting storage circuit 13 is described as setting the setting value in the clock control block 11 via the scan setting storage circuit 12. However, the block setting storage circuit 13 passes through the scan setting storage circuit 12. Of course, it may be set without any change. The block setting storage circuit 13 is composed of flip-flops that constitute a scan chain, and during the scan test, a scan test is performed, so that a set value cannot be set in the clock control block 11. For this purpose, the scan setting storage circuit 12 is provided.

  Therefore, the above-described scan chain is connected to the block setting storage circuit 13 of the clock control circuit 10 and constitutes a scan chain together with the FF 21 of the block setting storage circuit 13. That is, in the clock control circuit 10 according to the present embodiment, the block setting storage circuit 13 is a target of the scan test.

  As a result, the block setting storage circuit 13 can perform a scan test during the scan test. In the normal mode, the setting value of the scan setting storage circuit 12 can be used.

  FIG. 2 is a block diagram showing details of the clock control circuit 10 according to the present embodiment. As shown in FIG. 2, the scan setting storage circuit 12 will be described assuming that a 4-bit set value is set in the clock control block 11. The scan setting storage circuit 12 includes four selectors 121, four FFs 122, and four selectors 123 for setting a 4-bit value in the clock control block 11.

  The block setting storage circuit 13 includes four selectors 131 and four FFs 132 for outputting a 4-bit set value.

  In the normal mode, the block setting storage circuit 13 takes in data from the bus 40, selects it with the selector 131, and takes in a value into the FF 132. A set value is set in the clock control block 11 by outputting this to the clock control block 11 via the selector 121 of the scan setting storage circuit 12.

  Further, the setting value for the scan test can be stored in the FF 122 in the normal mode. First, the selection source of the selector 123 is set to 0 side. Next, the setting value set at the time of the scan test is stored in the FF 132. Since the selector 123 is set to 0, the value of the FF 132 is stored in the normal FF 122 without reset.

  Thereafter, during the scan test, the selection source of the selector 123 is set to 1 side so that the setting of the FF 122 is not changed. Then, by setting the selection source of the selector 121 to 1, the setting value is set in the clock control block 11 via the setting port. Thereby, a scan test can be implemented.

  According to the present embodiment, the scan setting storage circuit 12 is inserted between the clock control block 11 and the block setting storage circuit 13 when the scan clock is distributed to the entire chip using a PLL or a frequency divider. By doing so, it is possible to reduce the number of terminals necessary for the test without lowering the normal path failure detection rate while maintaining the freedom of the scan test. Since the block setting storage circuit 13 that is a normal path is a scan test target, it is a circuit that does not lower the failure detection rate of a circuit that is normally used as compared with a conventional circuit. In other words, according to the present embodiment, the test setting is performed before the start of the scan test, and the scan test can be performed while the setting is stored by the scan setting storage circuit 12. Therefore, the degree of freedom of the scan test is maintained. This makes it possible to reduce the number of test terminals.

FIG. 3 is a diagram illustrating a modification according to the embodiment of the present invention. In this modification, the selector 121 is a three-input selector, and a fixed value holding unit 124 is provided at one terminal thereof. As described above, the block setting storage circuit 13 can fetch data from the bus 40, set a value in the FF 122, and set a setting value in the clock control block 11. However, a fixed value holding unit 124 is provided. Thus, a fixed value can be set in the clock control block 11. The fixed value holding unit 124 eliminates the need to take in the setting value from the bus 40 using the block setting storage circuit 13. The scan setting storage circuit 12 may be composed of only the fixed value holding unit 124.

Embodiment 2 of the present invention.
FIG. 4 is a diagram illustrating the scan setting storage circuit 12 according to the second embodiment of the present invention. As shown in FIG. 4, in the present embodiment, the scan setting storage circuit 12 further includes an FF 125 and a selector 126. In addition, logic circuits 127 to 129 are provided to control the selectors 121, 123, and 126. Thereby, the scan setting storage circuit 12 can hold two setting values, and can change the setting values during the scan test. In this example, the number of FFs provided in the scan setting storage circuit 12 is two. However, it is possible to use two or more FFs and hold two or more set values.

  Next, the operation of the scan setting storage circuit 12 according to the present embodiment will be described. FIGS. 5 to 9 are diagrams for explaining the operation of the scan setting storage circuit 12. First, the normal operation, not the scan test, will be described. In the normal operation, as shown in FIG. 5, the test terminal TEST1 = 0 (TEST0 = 0 or 1) is set, and the value of the block setting storage circuit 13 can be set in the clock control block 11. The block setting storage circuit 13 fetches a value from the bus 40 and sets a value from each setting port to the clock control block 11 via the selector 121.

  Next, an operation of storing the scan test setting value in the scan setting storage circuit 12 will be described. The setting values for the scan test can be stored in the FFs 122 and 125 of the scan setting storage circuit 12 during the normal operation. First, as shown in FIG. 6, test terminals TEST0 = 0 and TEST1 = 0 are set. This is a normal operation (setting 1). The selector 126 sets the selection source to 1, and the selector 123 sets the selection source to 0. The value of FF 125 is held as it is, and the value of FF 132 is set in FF 122 via selector 123. During this time, the value of the FF 132 of the block setting storage circuit 13 is set in the clock control block 11 via the selector 121.

  Next, a value is set in the other FF 125. As shown in FIG. 7, TEST0 = 1 and TEST1 = 0. This is normal operation (setting 2). In this case, the value of FF 132 is set to FF 125 via selector 126. In this case, the value of FF 122 is maintained as described above. When it is desired to make the value of the FF 125 different from the value of the FF 122, the FF 132 takes in a different value from the bus 40 and sets it in the FF 125. Note that the value of the FF 132 of the block setting storage circuit 13 continues to be set in the clock control block 11 via the selector 121 during this time. Setting values can be stored in the two FFs 122 and 125 of the scan setting storage circuit 12 in the normal mode.

  Next, the operation during the scan test will be described. As shown in FIG. 8, TEST0 = 0 and TEST1 = 1, the selection source of the selector 121 is 2, the selection source of the selector 123 is 1, and the selection source of the selector 126 is 1. As a result, the value of the FF 122 is set in the clock control block 11 via each setting port.

  Next, as shown in FIG. 9, TEST0 = 1 and TEST1 = 1 are set, the selection source of the selector 121 is 3, the selection source of the selector 123 is 1, and the selection source of the selector 126 is 1. As a result, the value of the FF 125 is set in the clock control block 11 via each setting port.

  As described above, when the scan setting storage circuit 12 has two or more FFs, different values can be set for the clock control block 11 during the scan test.

  Here, if the setting value of the clock control block 11 is not desired to be changed, the value of the FF 122 may be output to the clock control block 11 instead of the value of the FF 132 even in the normal mode. 10 to 16 are other examples showing details of the scan setting storage circuit. As shown in FIG. 10, the scan setting storage circuit 12 according to this example includes two OR circuits 127a and 128a and an inverter 129a, and further has a terminal for inputting a TEST2 signal. Other configurations are the same as those of the scan setting storage circuit 12 shown in FIG.

  First, in the normal operation, as shown in FIG. 11, TEST1 = 0 is set so that the value of the block setting storage circuit 13 reaches the clock control block 11. Next, in normal operation (setting 1), as shown in FIG. 12, TEST0 = 1 and TEST1 = 0. Then, the setting value stored in the block setting storage circuit 13 is stored in the FF 122. On the other hand, the value of FF125 does not change.

  Here, as shown in FIG. 13, the second value is set after changing the terminals in the order of TEST0 = 1, TEST1 = 0 → TEST0 = 0, TEST1 = 0 → TEST0 = 0, TEST1 = 1. To do. This is to prevent glitches from being placed on the setting port of the clock control block 11. When the terminal is changed in the order of TEST0 = 1, TEST1 = 0 → TEST0 = 1, TEST1 = 1 → TEST0 = 0, TEST1 = 1, the selector (4 input MUX) 121 selects 3 for a moment and invalid register for a moment Set the value.

  Next, as shown in FIG. 14, TEST0 = 0 and TEST1 = 1 are set in the normal operation (setting 2). The setting value stored in the FF 122 of the scan setting storage circuit 12 reaches the clock control block 11. The FF 125 stores the value stored in the block setting storage circuit 13. At this time, the value of the FF 122 is not changed.

  Next, as shown in FIG. 15, TEST2 = 1. As a result, the register values of the FF 122 and the FF 125 are not changed (the scan test mode is set). At this time, the value of the FF 122 of the scan setting storage circuit 12 reaches the clock control block 11.

  Also, as shown in FIG. 16, when it is desired to output the value of the FF 125 to the clock control block 11, TEST0 = 1 and TEST1 = 1. Since TEST2 = 1, the values of FF122 and FF125 are not changed.

  It should be noted that the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the present invention.

10 clock control circuit 11 clock control block 12 scan setting storage circuit 13 block setting storage circuit 21, 122, 125, 132 FF
20 Scan Test Target Circuit 22 Combinational Logic Circuit 40 Bus 121, 123, 126, 131 Selector 124 Fixed Value Holding Unit 127, 128, 127a, 128a OR Circuit 129, 129a Inverter Circuit

Claims (11)

A clock control circuit for supplying a clock to the scan chain during a scan test,
A clock generation circuit for generating the clock;
A first storage unit for storing a setting value for designating the operation of the clock generation circuit;
A second storage unit coupled between the clock generation circuit and the first storage unit and storing the set value stored in the first storage unit as a set value for a scan test; ,
The clock generation circuit, wherein the clock generation circuit generates the clock based on the setting value for the scan test stored in the second storage unit during a scan test.   The clock control circuit according to claim 1, wherein the first storage unit is connected to a scan chain and performs a scan test during the scan test. A semiconductor device having a clock generation circuit and realizing a predetermined function,
A first storage unit configured to store a first set value that is configured by a scan flip-flop constituting a scan chain and determines the operation of the clock generation circuit;
A second storage unit that is arranged between the clock generation circuit and the first storage unit and does not include the scan flip-flop that acquires the first set value at a predetermined timing and stores it as a second set value When,
Have
The clock generation circuit generates a clock signal based on the second set value when the semiconductor device performs a scan test using the scan chain, and performs a normal operation in which the semiconductor device realizes the predetermined function. A semiconductor device that generates the clock signal based on the first set value or the second set value when performing.   The second storage unit is coupled to the first storage unit during the normal operation to acquire the first set value as the second set value, and when executing the scan test, the second storage unit The semiconductor device according to claim 3, wherein the semiconductor device is separated from one storage unit and does not acquire a value of the first set value.   The semiconductor device according to claim 4, wherein the clock generation circuit includes a PLL (Phase Locked Loop), a frequency divider, or a selector.   4. The semiconductor device according to claim 3, further comprising a third storage unit that stores a third set value that determines an operation of the clock generation circuit as a fixed value. 5. A control method of a clock control circuit for supplying a clock to a scan chain during a scan test,
In the normal mode, the setting value is received from the first storage unit that stores the setting value that specifies the operation of the clock generation circuit that generates the clock, the clock is generated,
During a scan test, a second storage unit is disposed between the clock generation circuit and the first storage unit, and stores the setting value stored in the first storage unit as a setting value for a scan test. A control method for a clock control circuit, which receives the set value and generates a clock.   8. The method of controlling a clock control circuit according to claim 7, wherein the first storage unit is connected to a scan chain during the scan test and the scan test is executed. A clock generation method for a semiconductor device having a clock generation circuit and realizing a predetermined function,
When the semiconductor device performs a scan test using the scan chain, the clock generation circuit is configured by the clock generation circuit and a scan flip-flop constituting the scan chain, and determines the operation of the clock generation circuit. The second set value of the second storage unit that does not include the scan flip-flop that is arranged between the storage unit and the first set value is acquired at a predetermined timing and stored as the second set value. Based on the clock signal,
A semiconductor device clock generation method for generating the clock signal based on the first set value or the second set value when the semiconductor device performs a normal operation for realizing the predetermined function.   The second storage unit is coupled to the first storage unit during the normal operation to acquire the first set value as the second set value, and when executing the scan test, the second storage unit The method for generating a clock of a semiconductor device according to claim 9, wherein the method is separate from one storage unit and does not acquire the value of the first set value. A clock control circuit for supplying a clock to the scan chain during a scan test,
A clock generation circuit for generating the clock;
A first storage unit for storing a setting value for designating the operation of the clock generation circuit;
A second storage unit that stores a setting value that specifies the operation of the clock generation circuit during a scan test;
The first storage unit is a clock control circuit that is connected to a scan chain and performs a scan test during the scan test.

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