JP2011199222A - Nitride semiconductor epitaxial wafer, method of manufacturing the same, and field effect transistor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a nitride semiconductor epitaxial wafer that has a higher breakdown voltage and reduces or eliminates a current collapse phenomenon, a method of manufacturing the same, and a field effect transistor element.SOLUTION: The nitride semiconductor epitaxial wafer includes a substrate 1, a first nitride semiconductor layer 3 formed on the substrate 1, and a second nitride semiconductor layer 5 formed on the first nitride semiconductor layer 3 and having smaller electron affinity than the first nitride semiconductor layer 3. The first nitride semiconductor layer 3 is doped with iron in a depth direction from a surface thereof with a depth-directional profile represented by an approximation expression of NFe=A×exp(B×C), (NFe: an iron concentration in the nitride semiconductor layer, A: 1E14 to 1E17 [cm], B: 3 to 8 [cm], C: a depth from the surface of the first nitride semiconductor layer), and a silicon doping region 4 formed by doping with silicon to a concentration higher than that of the iron is provided on the surface side of the first nitride semiconductor layer.

Description

  The present invention relates to a nitride semiconductor epitaxial wafer, a method for manufacturing the same, and a field effect transistor element.

Nitride semiconductors composed of indium (In), gallium (Ga), aluminum (Al), nitrogen (N), etc., control the composition ratio of group III elements, so that the wavelength region of most of ultraviolet to visible light Development is progressing as a material for innovative high-efficiency light-emitting devices that can cover the above, and it has been put to practical use.
In addition, since nitride semiconductors have high saturation electron speed and high breakdown voltage, in the future, high efficiency and high output will be achieved in the high-frequency range, compared with conventional electronic devices. In other words, it is expected to be applied as a material for dream devices.

In the structure of a conventional field effect transistor element, generally, if any leak path exists in the structure, when the gate electrode is closed, a leakage current is generated between the electrodes, and the breakdown voltage of the element is significantly reduced. Become.
Leak paths usually tend to occur in layers having a high electron affinity in the device structure.
For this reason, more specifically, for example, impurities mixed in a very small amount as a background in a layer with originally high electron affinity, atomic vacancies contained in the layer, etc. are emitted from conductive carriers. Some or all of the layer may become a leak path.
In a nitride semiconductor epitaxial wafer for a field effect transistor device, a layer made of gallium nitride generally corresponds to a layer having a high electron affinity, and there is a possibility that a leak path will occur in this layer.

In order to suppress the occurrence of a leak path in the gallium nitride layer, a commonly used technique is doping of iron (Fe) to the gallium nitride layer.
Generally, when a compound semiconductor is doped with a transition element, the resistance of the compound semiconductor is increased. This is because the doped transition element forms a deep trap level in the band gap of the compound semiconductor and traps free carriers. For example, in a gallium nitride-based or indium phosphide-based compound semiconductor layer, iron (Fe) is used as a transition element for a dopant for increasing the resistance of the compound semiconductor layer as described above.
In this way, by doping iron into a compound semiconductor layer made of a material having a high electron affinity such as gallium nitride, the occurrence of a leak path is suppressed, and the withstand voltage of an electronic device having a structure including the compound semiconductor layer is reduced. This can be improved (see Patent Document 1 above).

JP 2009-21362 A

However, if the compound semiconductor layer made of gallium nitride having a high electron affinity as described above is doped with iron, the conductivity is lowered.
In particular, in a nitride transistor, carriers running in the channel region are trapped by trapping levels generated by iron mixed in the nitride semiconductor layer, so that the drain current is significantly reduced during high-frequency operation. It has been pointed out that a collapse phenomenon occurs.
That is, when a layer of gallium nitride is doped with a transition element such as iron, the transition element forms a deep trap level in the band gap of the compound semiconductor. For this reason, it is preferable in terms of withstand voltage that the portion not directly contributing to the operation as the transistor element is doped with iron. However, on the other hand, in the operation as a transistor element, in the most important channel region portion, if iron is mixed, the conductivity is lowered.

  As a measure for achieving both high breakdown voltage and reduction or elimination of the current collapse phenomenon, most of the compound semiconductor layer made of gallium nitride having a high electron affinity is doped with iron, while the compound semiconductor layer It is also considered that iron should not be doped at least in the channel region from the surface side of the compound semiconductor layer to a depth of about 0.5 μm or shallower than that.

However, such a measure is actually very difficult to implement.
In order to dope iron into gallium nitride, an organic metal called biscyclopentadienyl iron (Cp ₂ Fe) is used. This biscyclopentadienyl iron has the property of having a strong memory effect. is doing.
For example, to increase the breakdown voltage, even if it is intended that gallium nitride having a high electron affinity is doped with iron only in a region 0.5 μm or deeper from the surface side, due to the memory effect. Thus, the biscyclopentadienyl iron remaining in the pipe for introducing the doping gas gradually flows into the reactor.
For this reason, iron (Fe) is mixed into an unintended region having a depth from the surface side of 0.5 μm or thinner, and that portion, that is, the portion including the channel region, is mixed with iron. Therefore, the resistance increases.

  As described above, in the conventional technique, a nitride semiconductor epitaxial wafer in which a channel region is formed in a semiconductor layer made of a nitride such as gallium nitride, or a field effect transistor element manufactured using the same, There is a problem that it is extremely difficult to achieve both the breakdown voltage and the reduction or elimination of the current collapse phenomenon.

  The present invention has been made in view of such problems, and an object of the present invention is to provide a nitride semiconductor epitaxial wafer, a method of manufacturing the same, and an electric field capable of achieving both high breakdown voltage and reduction or elimination of the current collapse phenomenon. The object is to provide an effect transistor element.

The nitride semiconductor epitaxial wafer of the present invention includes a substrate serving as a base for growing a nitride semiconductor, a first nitride semiconductor layer formed on the substrate, and the first nitride semiconductor layer. A nitride semiconductor epitaxial wafer having a second nitride semiconductor layer having an electron affinity smaller than that of the first nitride semiconductor layer formed thereon, wherein the first nitride semiconductor layer includes: From the surface to the depth direction:
NFe = A × exp (B × C)
here,
NFe: Iron concentration in the first nitride semiconductor layer A: 1E14 (1 × 10 ¹⁴ ) to 1E17 (1 × 10 ¹⁷ ) [cm ⁻³ ]
B: Coefficient in the range of 3 to 8 [μm ⁻¹ ] C: Depth from the surface of the first nitride semiconductor layer [μm]
And a silicon doping region doped with silicon (Si) is provided on the surface side of the first nitride semiconductor layer, with a depth profile represented by The silicon doping region is characterized in that the concentration of silicon (Si) is higher than the concentration of iron (Fe).
The method for manufacturing a nitride semiconductor epitaxial wafer according to the present invention includes a step of forming a nucleation layer on a surface of a substrate, and a first nitride semiconductor layer is formed on the substrate on which the nucleation layer is formed. And a step of forming a second nitride semiconductor layer having an electron affinity smaller than that of the first nitride semiconductor layer on the first nitride semiconductor layer. The method of forming the first nitride semiconductor layer includes: a first step of growing a nitride semiconductor while supplying an iron (Fe) dopant; and a supply of the iron (Fe) dopant. A second step of growing the nitride semiconductor in a stopped state, and a third step of growing the nitride semiconductor while supplying a silicon (Si) dopant during or after the second step. Oh And the silicon concentration is higher than the concentration of iron (Fe) contained as an impurity concentration in a silicon doping region formed by growing a nitride semiconductor while supplying the silicon (Si) dopant. It is a feature.
The field effect transistor device of the present invention uses the above-described nitride semiconductor epitaxial wafer, and is directly above the second nitride semiconductor layer or on the second nitride semiconductor layer in the nitride semiconductor epitaxial wafer. An intermediate layer is provided, and a source electrode, a gate electrode, and a drain electrode are provided on the intermediate layer.

  According to the present invention, it is possible to realize a nitride semiconductor epitaxial wafer, a method for manufacturing the same, and a field effect transistor device that can achieve both high breakdown voltage and reduction or elimination of the current collapse phenomenon.

It is a figure which shows the structure of the principal part of the field effect transistor element produced using the nitride semiconductor epitaxial wafer which concerns on embodiment of this invention. In the field effect transistor device according to the example of the present invention, a curve of an experimental result of investigating a relationship between a coefficient A used in a formula for obtaining a suitable numerical aspect of the iron doping concentration NFe and a leakage current, It is a figure which shows the curve of the experimental result which investigated the relationship between the coefficient A used for the type | formula which calculates | requires the suitable numerical aspect of doping concentration NFe, and electron mobility. In the field effect transistor device according to the example of the present invention, a curve of an experimental result of investigating a relationship between a coefficient B used in an equation for obtaining a suitable numerical aspect of the iron doping concentration NFe and a leakage current, and iron It is a figure which shows the curve of the experimental result which investigated the relationship between the coefficient B used for the formula which calculates | requires the suitable numerical aspect of doping concentration NFe, and electron mobility. The difference between the drain current value during DC driving and the drain current value during RF driving was investigated for the field effect transistor device according to the example of the present invention and the conventional general field effect transistor device. It is a figure which shows a result.

  Hereinafter, a nitride semiconductor epitaxial wafer, a manufacturing method thereof, and a field effect transistor element according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a main part of a field effect transistor element manufactured using a nitride semiconductor epitaxial wafer according to an embodiment of the present invention.
Here, the field effect transistor element according to the embodiment of the present invention is mainly composed of individual semiconductor element chips obtained by performing various processes on the nitride semiconductor epitaxial wafer according to the embodiment of the present invention. It is produced by including it as a component. Therefore, in the description of the present embodiment, in order to avoid the so-called double complexity, the field effect transistor element manufactured using the nitride semiconductor epitaxial wafer according to the embodiment of the present invention is described. By explaining as the center, the explanation about the nitride semiconductor epitaxial wafer is included therein.

  The field effect transistor device includes a substrate 1, a nucleation layer 2, a first nitride semiconductor layer 3, a silicon doping region 4, a second nitride semiconductor layer 5, an intermediate layer 6, a source electrode. 7, a drain electrode 8, and a gate electrode 9 are provided as main parts thereof.

  The substrate 1 is a substrate serving as a base for growing a nitride semiconductor. As this substrate 1, for example, a silicon carbide substrate such as polytype 4H or polytype 6H can be used.

  A nucleation layer 2 is formed on the surface of the substrate 1. The nucleation layer 2 is preferably made of, for example, undoped aluminum nitride.

The first nitride semiconductor layer 3 is formed by using the nucleation layer 2 as a growth nucleus, and using the MOVPE (Metal Organic Chemical Vapor Deposition) apparatus, for example, on the substrate 1 including the nucleation layer 2 to form gallium nitride. It is formed by growing such a nitride semiconductor. The first nitride semiconductor layer 3 is preferably made of gallium nitride as a main material.
In the lower layer portion of the first nitride semiconductor layer 3, that is, at least a predetermined depth region near the interface with the substrate 1, the depth from the surface is C [μm], and the coefficient A is 1E14 to 1E17 [cm]. ⁻³ ] and the coefficient B within the range of 3 to 8 [μm ⁻¹ ], the iron concentration (NFe) is NFe = A × exp (B × C) [cm ^−3. ] Is set.
Further, in an upper layer portion of the first nitride semiconductor layer 3, that is, in a predetermined depth region below the surface of the first nitride semiconductor layer 3 (interface with the second nitride semiconductor layer 5). Is doped with silicon (Si) to form a silicon doped region 4. The silicon concentration (NSi) in the silicon doping region 4 is higher than the iron concentration (NFe) in the silicon doping region 4 (NSi> NFe).

  A second nitride semiconductor layer 5 having an electron affinity smaller than that of the first nitride semiconductor layer 3 is formed on the first nitride semiconductor layer 3. The second nitride semiconductor layer is preferably made of, for example, aluminum gallium nitride as a main material.

The total film thickness of the first nitride semiconductor layer 3 is preferably 1.0 μm or more and 4.0 μm or less.
The thickness of the region doped with iron in the first nitride semiconductor layer 3 is preferably 0.1 μm or more and 0.5 μm or less.
The silicon doping region 4 is preferably formed in a region having a depth from the surface of the first nitride semiconductor layer 3 shallower than 0.5 μm.

  The field effect transistor element according to the embodiment of the present invention, in which the main part is configured as described above, is manufactured as follows.

  First, the substrate 1 is prepared, and the nucleation layer 2 is formed on the surface using, for example, a MOVPE apparatus.

Subsequently, the first nitride semiconductor layer 3 is formed on the substrate 1 including the nucleation layer 2 using, for example, a MOVPE apparatus.
At this time, as a first step, a nitride semiconductor such as gallium nitride is grown using an MOVPE apparatus while supplying an iron dopant.
At this time, various process conditions such as a flow are set so that the iron concentration (NFe) in the growing nitride semiconductor is NFe = A × exp (B × C) [cm ⁻³ ].

  Subsequently, as a second step, a nitride semiconductor is grown in a state where the supply of the iron dopant is stopped using, for example, an MOVPE apparatus.

Subsequently, or in the middle of the second step, as a third step, for example, by using a MOVPE apparatus, a nitride semiconductor is grown while supplying a silicon dopant, so that the portion becomes the silicon doping region 4. .
At this time, the silicon concentration (NSi) in the nitride semiconductor that grows while being doped with silicon (that is, the silicon doping region 4) is the concentration of iron in the nitride semiconductor that grows while being doped with silicon (that is, the silicon doping region 4). Various process conditions such as a flow are set so that the value becomes higher than (NFe) (NSi> NFe).
Subsequently, for example, using an MOVPE apparatus, the electron affinity of the first nitride semiconductor layer 3 (that is, the silicon doping region 4) is smaller than that of the first nitride semiconductor layer 3, for example, aluminum gallium nitride. Then, the second nitride semiconductor layer 5 is formed with the main material.

In this way, the main part of the nitride semiconductor epitaxial wafer according to the embodiment of the present invention is completed.
The growth process of each of these layers is continued using a manufacturing apparatus such as the same MOVPE apparatus. By doing in this way, the production efficiency of the nitride semiconductor epitaxial wafer used for this field effect type transistor element can be made higher.

  Thereafter, a source electrode 7, a drain electrode 8, and a gate electrode 9 are formed at predetermined positions on the surface of the intermediate layer 6 in the above-described nitride semiconductor epitaxial wafer, and subjected to dicing or the like to obtain individual semiconductor element chips. Thus, the main part of the field effect transistor element according to the embodiment of the present invention is completed.

  In the nitride semiconductor epitaxial wafer, the manufacturing method thereof, and the field effect transistor element according to the embodiment of the present invention, the first nitride semiconductor layer 3 positioned immediately below the second nitride semiconductor layer 5 By providing the silicon doping region 4 in a region extending from the vicinity of the surface to a predetermined depth, the first nitride semiconductor layer 3 and the second nitride semiconductor layer 5, the silicon doping region 4 and the like are provided. In a nitride semiconductor epitaxial wafer and a field effect transistor device manufactured using the same, it is possible to achieve both high breakdown voltage and reduction or elimination of the current collapse phenomenon.

That is, in the nitride semiconductor epitaxial wafer, the manufacturing method thereof, and the field effect transistor element according to the embodiment of the present invention, the first nitride semiconductor layer 3 made of a nitride semiconductor such as gallium nitride having a high electron affinity is used. By doping iron (Fe) in most regions, a high breakdown voltage as a transistor element is realized.
Further, a silicon doping region 4 is provided by doping silicon (Si) at a concentration higher than the iron concentration in a region extending from the vicinity of the surface of the first nitride semiconductor layer 3 to a predetermined depth. As a result, the current collapse phenomenon can be reduced or eliminated.

The silicon doping region 4 functions as follows.
Silicon (Si) becomes an n-type impurity in a nitride semiconductor such as gallium nitride and forms a shallow donor level. Electrons emitted from the donor level are trapped in a deep trapping level created by iron. Then, since the trapping level of iron is filled with electrons, no more carriers are trapped in the trapping level of iron. Therefore, carriers traveling in the channel are prevented from being trapped by the trapping level of iron mainly composed of the first nitride semiconductor layer 3. In this manner, the current collapse phenomenon caused by iron doped in the first nitride semiconductor layer 3 in the prior art can be drastically reduced or eliminated.

Here, in order to form the silicon doping region 4, preferably, doping of silicon (Si) into a region having a depth of 0.5 μm from the surface is performed by mono silane (S).
It is preferable to use iH ₄ ). This is because monosilane is a source gas capable of easily controlling the process condition setting, and the doping depth and concentration in the first nitride semiconductor layer 3 can be controlled with extremely high accuracy. Because it is a thing.
In other words, this is coupled with the use of a source gas that is easy to control during silicon (Si) doping such as monosilane, and according to the technique according to the embodiment of the present invention, the first nitride is used. Silicon using silicon that can easily control the concentration of the current collapse caused by doping the first nitride semiconductor layer 3 with iron that is difficult to control the concentration in the semiconductor layer 3 It can also be reduced or eliminated by doping.

As described above, according to the nitride semiconductor epitaxial wafer, the manufacturing method thereof, and the field effect transistor element according to the embodiment of the present invention related to the present embodiment, the first nitride semiconductor layer 3 includes From the surface to the depth direction, an approximate expression: NFe = A × exp (B × C) (where NFe: iron concentration in the first nitride semiconductor layer, A: 1E14 to 1E17 [cm ⁻³ ] range Is doped with iron (Fe) in a depth profile represented by: B: coefficient in the range of 3-8 [μm ⁻¹ ], C: depth from the surface of the first nitride semiconductor layer In addition, since the silicon doping region 4 formed by doping silicon (Si) at a concentration higher than the concentration of iron (Fe) is provided on the surface side of the first nitride semiconductor layer 3, And It is possible to reduce or eliminate the current collapse phenomenon.

  A field effect transistor element having the configuration described in the above embodiment as a main part was manufactured.

As the substrate 1, a silicon carbide substrate of polytype 4H (which may be polytype 6H) was prepared.
Then, a nucleation layer 2 made of undoped aluminum nitride having a film thickness of 150 nm was formed on the surface of the substrate 1 using ammonia gas and TMA (Tri Methyl Aluminum) as raw materials by a MOVPE apparatus. The reaction temperature for forming the aluminum nitride layer was 1200 ° C. corresponding to the most preferable process conditions.

Subsequently, the same MOVPE apparatus is used, and a gallium nitride layer having a total film thickness of 2000 nm is formed on the nucleation layer 2 by using ammonia gas and TMG (Tri Methyl Gallium). To become a physical semiconductor layer 3). The reaction temperature in the formation process was set to 1020 ° C.
During the growth of the gallium nitride layer, when forming a portion corresponding to 400 nm in the vicinity of the interface with the substrate, biscyclopentadienyl iron (Cp ₂ Fe) is simultaneously used as an iron (Fe) raw material. Intentionally, iron doping was performed. Even after the formation of the portion corresponding to 400 nm is completed, iron is automatically doped into the gallium nitride layer formed thereafter by the memory effect, but the concentration of iron NFe is changed to the nitridation formed at that time. For the thickness C [μm] of the gallium layer,
NFe = 2.0E15 × exp (3.5 × C) [cm ⁻³ ]
The flow of intentional doping before that was adjusted.

Subsequently, a gallium nitride layer is grown, but when forming a portion corresponding to a thickness of 100 nm near the surface of the target thickness, that is, of the total thickness of the first nitride semiconductor layer 3. At the same time, monosilane (SiH ₄ ) was used as a silicon (Si) raw material to perform silicon doping, and a portion corresponding to a thickness of 100 nm was defined as a silicon doping region 4. In this case, the silicon doping concentration (NSi) is NSi = 2E16 [cm ^−3.
].

  After the first nitride semiconductor layer 3 is formed in this manner, the same MOVPE apparatus is subsequently used and the first nitride semiconductor layer 3 is formed on the first nitride semiconductor layer 3 using ammonia gas, TMA, and TMG. Then, a second nitride semiconductor layer 5 which is an aluminum gallium nitride supply layer having a thickness of 30 nm was formed.

  Subsequently, while using the same MOVPE apparatus, an intermediate layer 6 made of gallium nitride having a thickness of 8 nm was formed on the second nitride semiconductor layer 5 using ammonia gas and TMG.

Thus, a nitride semiconductor epitaxial wafer according to an example of the present invention was produced.
Thereafter, the source electrode 7, the drain electrode 8, and the gate electrode 9 are formed at predetermined positions on the surface of the intermediate layer 6 by using a general metal film forming process and a photolithography process, and according to the embodiment of the present invention. The main part of the field effect transistor element was completed.

  FIG. 2 is a graph showing the relationship between the coefficient A and the leakage current used in the equation for determining a suitable numerical aspect of the iron doping concentration NFe in the field effect transistor device according to the embodiment of the present invention formed as described above. It is a figure which shows the curve of the experimental result which investigated the relationship, and the curve of the experimental result which investigated the relationship between the coefficient A used for the formula which calculates | requires the suitable numerical aspect of the doping concentration NFe of iron, and an electron mobility.

From the experimental result curve 11 in which the relationship between the coefficient A and the leakage current is examined, if the coefficient A is smaller than 1.0E14, the iron concentration in the vicinity of the surface of the first nitride semiconductor layer 3 is too low, and the leakage path Occurs, the leakage current becomes 1.0E-05 (1.0 × 10 ⁻⁵ ) or more, and the breakdown voltage is deteriorated. From this point, the coefficient A is desirably 1.0E14 or more.
On the other hand, from the curve 12 of the experimental result of investigating the relationship between the coefficient A and the electron mobility, when the coefficient A is larger than 1.0E17, the electron mobility in the channel region is sharply decreased, and the transistor element operates. Characteristics deteriorate.
From such experimental results, it was concluded that the value of the coefficient A is preferably 1.0E14 or more and 1.0E17 or less.

  FIG. 3 shows the relationship between the coefficient B and the leakage current used in the equation for determining a suitable numerical aspect of the iron doping concentration NFe in the field effect transistor device according to the embodiment of the present invention formed as described above. It is a figure which shows the curve of the experimental result which investigated the relationship, and the curve of the experimental result which investigated the relationship between the coefficient B used for the formula which calculates | requires the suitable numerical aspect of the doping concentration NFe of iron, and an electron mobility.

From the experimental result curve 13 for examining the relationship between the coefficient B and the leakage current, if the coefficient B is smaller than 3, the iron concentration in the vicinity of the surface of the first nitride semiconductor layer 3 is too low and a leakage path is generated. However, the leakage current becomes 1.0E-05 or more, and the breakdown voltage is deteriorated. From this point, the coefficient B is desirably 3 or more.
On the other hand, from the curve 14 of the experimental result of investigating the relationship between the coefficient B and the electron mobility, when the coefficient B is greater than 8, the electron mobility in the channel region is lowered, and the operation characteristics as a transistor element are deteriorated. .
From such experimental results, it was concluded that the value of the coefficient B is preferably 3 or more and 8 or less.

FIG. 4 shows the drain current value and the RF driving for DC driving for the field effect transistor device according to the embodiment of the present invention formed as described above and the conventional general field effect transistor device, respectively. It is a figure which shows the result of having investigated the deviation with the drain current value at the time. In general, the greater the difference in drain current value between DC driving and RF driving, the more likely the current collapse occurs.
From the experimental results shown in FIG. 4, in the field effect transistor device according to the example of the present invention, the difference in the drain current value between the DC drive and the RF drive is compared with that in the related art. Thus, it was confirmed that it was remarkably miniaturized. Therefore, it was confirmed that the current collapse can be reduced or eliminated very effectively in the field effect transistor device according to the example of the present invention as compared with the case of the prior art.

The silicon doping concentration (NSi) in the silicon doping region 4 is preferably 1.5E16 [cm ⁻³ ] or more and 1.5E18 [cm ⁻³ ] or less. In particular, with respect to the upper limit, if doping is performed to a concentration exceeding 1.5E18 [cm ⁻³ ], the mobility is likely to decrease. From this point, the upper limit is set to 1.5E18 [cm ⁻³ ]. It is desirable to do.
Moreover, as a suitable numerical aspect of the thickness of the silicon doping region 4, it is desirable that the thickness be 50 nm or more and 500 nm or less. More desirably, it is 80 nm or more and 200 nm or less.

In the above-described embodiment and each example, the case where the silicon doping region 4 is a single layer has been described. However, the present invention is not limited to this. The silicon doping region 4 may be formed by being divided into a plurality of layers.
Further, the concentration of silicon (Si) in the silicon doping region 4 is within the above preferable numerical range depending on the degree of current collapse caused by the doping of iron into the first nitride semiconductor layer 3. Of course, it is possible to appropriately change the setting of the numerical value.

DESCRIPTION OF SYMBOLS 1 Substrate 2 Nucleation layer 3 First nitride semiconductor layer 4 Silicon doping region 5 Second nitride semiconductor layer 6 Intermediate layer 7 Source electrode 8 Drain electrode 9 Gate electrode

Claims (7)

A substrate serving as a base for growing a nitride semiconductor; a first nitride semiconductor layer formed on the substrate; and the first nitride semiconductor layer formed on the first nitride semiconductor layer. A nitride semiconductor epitaxial wafer having a second nitride semiconductor layer having a lower electron affinity than the nitride semiconductor layer,
The first nitride semiconductor layer has the following approximate expression in the depth direction from the surface:
NFe = A × exp (B × C)
here,
NFe: Iron concentration in the first nitride semiconductor layer A: 1E14 to 1E17 [cm ⁻³ ]
B: Coefficient in the range of 3 to 8 [μm ⁻¹ ] C: Depth from the surface of the first nitride semiconductor layer [μm]
Is doped with iron (Fe), with a depth profile represented by
A silicon doping region formed by doping silicon (Si) is provided on the surface side of the first nitride semiconductor layer, and in the silicon doping region, the concentration of silicon (Si) is the concentration of iron (Fe). Nitride semiconductor epitaxial wafer characterized by being higher than that. The nitride semiconductor epitaxial wafer according to claim 1,
The first nitride semiconductor layer is made of gallium nitride as a main material;
The nitride semiconductor epitaxial wafer, wherein the second nitride semiconductor layer is made of aluminum gallium nitride as a main material. The nitride semiconductor epitaxial wafer according to claim 1 or 2,
A nitride semiconductor epitaxial wafer, wherein a nucleation layer made of aluminum nitride is provided between the substrate and the first nitride semiconductor layer. In the nitride semiconductor epitaxial wafer according to any one of claims 1 to 3,
The total thickness of the first nitride semiconductor layer is 1.0 μm or more and 4.0 μm or less,
The thickness of the region doped with iron is 0.1 μm or more and 0.5 μm or less,
The nitride semiconductor epitaxial wafer, wherein the silicon doping region is formed in a region whose depth from the surface of the first nitride semiconductor layer is shallower than 0.5 μm. Forming a nucleation layer on the surface of the substrate;
Forming a first nitride semiconductor layer on the substrate on which the nucleation layer is formed;
Forming a second nitride semiconductor layer having an electron affinity smaller than that of the first nitride semiconductor layer on the first nitride semiconductor layer. There,
The step of forming the first nitride semiconductor layer includes a first step of growing a nitride semiconductor while supplying an iron (Fe) dopant, and a nitride in a state where supply of the iron (Fe) dopant is stopped. A second step of growing a semiconductor, and a third step of growing a nitride semiconductor while supplying a silicon (Si) dopant during or after the second step,
The silicon concentration is higher than the concentration of iron (Fe) contained as an impurity concentration in a silicon doping region formed by growing a nitride semiconductor while supplying the silicon (Si) dopant. A method for manufacturing a nitride semiconductor epitaxial wafer. 5. The nitride semiconductor epitaxial wafer according to claim 1, wherein the nitride semiconductor epitaxial wafer is directly above the second nitride semiconductor layer in the nitride semiconductor epitaxial wafer or the second nitride semiconductor. A field effect transistor element comprising an intermediate layer provided on a layer and a source electrode, a gate electrode, and a drain electrode provided on the intermediate layer. The field effect transistor device according to claim 6, wherein
A field effect transistor element characterized in that a material of at least the second nitride semiconductor layer and the source electrode or the drain electrode in the intermediate layer is gallium nitride as a main material. .

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