JP2014136658A - Group iii nitride semiconductor epitaxial wafer and production method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a group III nitride semiconductor epitaxial wafer capable of suppressing a memory effect of Fe without lowering a throughput, while suppressing an influence of Si contamination by Fe doping, and to provide a production method thereof.SOLUTION: In a group III nitride semiconductor epitaxial wafer including a group III nitride semiconductor substrate 2, and a group III nitride semiconductor layer 3 having at least two layers formed on the group III nitride semiconductor substrate 2, a substrate to which Fe is added is used as the group III nitride semiconductor substrate 2, and in a first group III nitride semiconductor layer 4 formed just above the group III nitride semiconductor substrate 2, Fe is added to the periphery of an interface with the group III nitride semiconductor substrate 2 by diffusion from the group III nitride semiconductor substrate 2, and the Fe concentration is three or more times as high as the Si concentration over the whole area where the Si concentration is 2×10cmor higher.

Description

  The present invention relates to a group III nitride semiconductor epitaxial wafer and a method for manufacturing the same.

  Group III nitride semiconductors, consisting of group III elements indium, gallium, aluminum and group V element nitrogen, control the composition ratio of group III elements to cover most of the UV to visible region. As a material for a typical high-efficiency light-emitting device, development has been promoted and put into practical use.

  Group III nitride semiconductors also have high saturation electron velocities and high breakdown voltage, so they are expected to be used in the future as electronic device materials that achieve orders of magnitude higher efficiency and higher output in the high frequency range. ing.

  There is a field effect transistor as an electronic device using a group III nitride semiconductor. The field effect transistor is formed by stacking a plurality of group III nitride semiconductor layers (group III nitride semiconductor thin films) having different compositions on a semi-insulating crystal substrate. As a semi-insulating substrate crystal (hereinafter referred to as a substrate), a silicon carbide substrate or a group III nitride semiconductor substrate is used.

  By the way, when manufacturing a group III nitride semiconductor epitaxial wafer, a common problem regardless of the type of substrate used is contamination of the substrate surface by Si. Even if a substrate with a very clean surface can be obtained, Si is deposited only by exposing the substrate surface to air, and this deposited Si acts as a donor in the group III nitride semiconductor, and the substrate and III A low resistance layer is formed at the interface of the group nitride semiconductor layer (epitaxial layer), and the breakdown voltage is lowered.

  In order to solve this problem, conventionally, in the initial growth stage of a group III nitride semiconductor layer in direct contact with the substrate, iron (Fe) is doped using ferrocene, and the substrate and the group III nitride semiconductor layer (epitaxial) A countermeasure is taken to increase the resistance in the vicinity of the interface of the layer) (see Patent Documents 1 and 2).

  However, Fe doping using ferrocene has a remarkable memory effect, and thus has a problem that not only the vicinity of the interface between the substrate and the group III nitride semiconductor layer (epitaxial layer) but also the entire device is adversely affected.

  In order to avoid the influence of such a memory effect, Patent Document 1 proposes a method of sufficiently purging the ferrocene line during the growth of the group III nitride semiconductor layer. In this method, in order to prevent the group III nitride semiconductor layer (in this case, the GaN layer) immediately above the substrate from deteriorating during the growth interruption, a sufficient purge was performed after forming a cap layer of AlN or AlGaN mixed crystal. In addition, it was necessary to grow a group III nitride semiconductor layer thereafter.

  That is, as shown in FIG. 4, in the group III nitride semiconductor epitaxial wafer 41 manufactured by the conventional method, after forming the group III nitride semiconductor layer on the substrate 42, the cap layer 44 is formed to purge the ferrocene line. After that, in order to resume the growth of the group III nitride semiconductor layer, the first group III nitride semiconductor layer 43, the cap layer 44, the second group III nitride semiconductor layer 45, and the electron supply layer are formed on the substrate 42. 46 is sequentially laminated.

Japanese Patent No. 5013218 JP 2009-21362 A

  According to the above-described conventional method of purging the ferrocene line, the influence of contamination of the electron supply layer 46 due to Fe can be avoided, but it is necessary to form the cap layer 44 made of an originally unnecessary AlN or AlGaN mixed crystal. In order to perform a sufficient purge of the ferrocene line, it is necessary to interrupt the growth for about 30 minutes during the growth of the group III nitride semiconductor layer, resulting in a problem that the throughput is significantly reduced.

  The present invention has been made in view of the above circumstances, and a group III nitride semiconductor epitaxial wafer capable of suppressing the memory effect of Fe without reducing the throughput while suppressing the influence of Si contamination by Fe doping and its An object is to provide a manufacturing method.

The present invention was devised to achieve the above object, and comprises a group III nitride semiconductor substrate, and at least two group III nitride semiconductor layers formed on the group III nitride semiconductor substrate. A Group III nitride semiconductor epitaxial wafer provided with the Group III nitride semiconductor substrate to which Fe is added as the Group III nitride semiconductor substrate, and the Group III nitride semiconductor formed directly on the Group III nitride semiconductor substrate In the first group III nitride semiconductor layer, Fe is added by diffusion from the group III nitride semiconductor substrate in the vicinity of the interface with the group III nitride semiconductor substrate, and the Si concentration is It is a group III nitride semiconductor epitaxial wafer in which the Fe concentration is three times or more of the Si concentration over the entire region of 2 × 10 ¹⁵ cm ⁻³ or more.

The group III nitride semiconductor substrate may have an Fe concentration of 2 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

The group III nitride semiconductor substrate may have an Fe concentration of 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

The present invention also provides a group III nitride semiconductor epitaxial wafer comprising a group III nitride semiconductor substrate and at least two group III nitride semiconductor layers formed on the group III nitride semiconductor substrate. In the method, the Group III nitride semiconductor substrate is a group III nitride semiconductor substrate formed by adding Fe, and is a Group III nitride semiconductor layer formed immediately above the Group III nitride semiconductor substrate. Fe is added by diffusion from the group III nitride semiconductor substrate near the interface between the nitride semiconductor layer and the group III nitride semiconductor substrate, and the Si concentration of the first group III nitride semiconductor layer is 2 ×. This is a method for manufacturing a group III nitride semiconductor epitaxial wafer in which the Fe concentration is three times or more of the Si concentration over the entire region of 10 ¹⁵ cm ⁻³ or more.

  The growth temperature may be 1000 ° C. or more and 1200 ° C. or less, and the total holding time at the growth temperature may be 1000 seconds or more and 8000 seconds or less.

  ADVANTAGE OF THE INVENTION According to this invention, the group III nitride semiconductor epitaxial wafer which can suppress the memory effect of Fe, without reducing the throughput, and its manufacturing method can be provided, suppressing the influence of Si contamination by Fe doping.

It is sectional drawing which shows the structure of the group III nitride semiconductor epitaxial wafer which concerns on one embodiment of this invention. In this invention, it is a graph which shows the temperature dependence characteristic of the diffusion coefficient in the group III nitride semiconductor of Si and Fe. In the present invention, the time from drying to putting into the glove box of the MOCVD apparatus, and the interface between the group III nitride semiconductor substrate and the first group III nitride semiconductor layer after the growth of the first group III nitride semiconductor layer It is a graph which shows the relationship with Si concentration. It is sectional drawing which shows the structure of the conventional group III nitride semiconductor epitaxial wafer.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional view showing the structure of a group III nitride semiconductor epitaxial wafer according to the present embodiment.

  As shown in FIG. 1, a group III nitride semiconductor epitaxial wafer 1 includes a group III nitride semiconductor substrate 2 and at least two group III nitride semiconductor layers 3 formed on the group III nitride semiconductor substrate 2. It is equipped with.

  In the present embodiment, a gallium nitride (GaN) substrate is used as the group III nitride semiconductor substrate 2.

  In the present embodiment, the group III nitride semiconductor layer 3 includes a first group III nitride semiconductor layer 4 formed immediately above the group III nitride semiconductor substrate 2, and a first group III nitride semiconductor. And an electron supply layer 5 formed on the layer 4. In addition, the structure of the group III nitride semiconductor layer 3 is not limited to this, For example, it is good also as three or more layers. In the present embodiment, the case where the first group III nitride semiconductor layer 4 is made of GaN and the electron supply layer 5 is made of AlGaN will be described.

  As described above, by adding Fe to the vicinity of the interface between the first group III nitride semiconductor layer 4 and the group III nitride semiconductor substrate 2, resistance reduction due to Si contamination is suppressed and semi-insulating properties are maintained. Is possible. However, in Fe doping using ferrocene as in the conventional method, purging is essential to prevent Fe contamination in the electron supply layer, and a reduction in throughput is inevitable.

  The present inventors diligently studied a method of adding Fe instead of Fe doping using ferrocene, and investigated in detail the diffusion coefficient of Fe and the diffusion coefficient of Si in the group III nitride semiconductor. It has been found that the diffusion coefficient of Fe in the inside is larger than the diffusion coefficient of Si in the group III nitride semiconductor.

Based on this knowledge, the present inventors diffuse Fe contained in the group III nitride semiconductor substrate 2 without supplying Fe to be added to the first group III nitride semiconductor layer 4 by a vapor phase raw material. In the first group III nitride semiconductor layer 4, the Fe concentration is set to 3 times or more of the Si concentration over the entire region where the Si concentration is 2 × 10 ¹⁵ cm ⁻³ or more. The present inventors have found that a desired effect, that is, formation of a low resistance layer due to Si contamination can be suppressed, and the present invention has been achieved.

That is, the group III nitride semiconductor epitaxial wafer 1 according to the present embodiment uses a group III nitride semiconductor substrate 2 to which Fe is added, and the first group III nitride semiconductor layer 4 has its III Fe is added by diffusion from group III nitride semiconductor substrate 2 in the vicinity of the interface with group nitride semiconductor substrate 2, and the Fe concentration over the entire region where the Si concentration is 2 × 10 ¹⁵ cm ⁻³ or more. It is more than 3 times the Si concentration.

In the first group III nitride semiconductor layer 4, when the Fe concentration is less than 3 times the Si concentration in the region where the Si concentration is 2 × 10 ¹⁵ cm ⁻³ or more, the breakdown voltage is reduced due to the low resistance by Si. Defects such as lowering occur.

  Here, the concentration and diffusion coefficient of Fe and Si in the group III nitride semiconductor (here, GaN) will be described.

The Si concentration piled up at the interface between the group III nitride semiconductor substrate 2 and the first group III nitride semiconductor layer 4 is the presence or absence of cleaning immediately before introducing the group III nitride semiconductor substrate 2 into the growth apparatus, The total amount of Si varies in the range of 5 × 10 ¹⁷ to 1 × 10 ¹⁹ cm ⁻³ depending on the time from taking out from the container in which the group III nitride semiconductor substrate 2 is stored and introducing it into the growth apparatus. It is generally determined when it is introduced into the growth equipment.

The determined total amount of Si diffuses so-called drive-in into the first group III nitride semiconductor layer 4 and the like during the growth of the group III nitride semiconductor layer 3. At this time, the Si concentration at the position x (cm) away from the interface between the group III nitride semiconductor substrate 2 and the first group III nitride semiconductor layer 4 toward the first group III nitride semiconductor layer 4 is expressed as N _s. (Cm ⁻³ ), the piled-up Si concentration is Q (cm ⁻² ), the diffusion coefficient of Si in the group III nitride semiconductor is D _s (cm ² / s), and the total retention time at the growth temperature is Assuming t (s), the relationship of the equation (1) shown in [Equation 1] is obtained.

Note that the diffusion coefficient D _s in the group III nitride semiconductor of Si varies with temperature. That is, the concentration of Si piled up at the interface between the group III nitride semiconductor substrate 2 and the first group III nitride semiconductor layer 4 increases as the growth temperature increases and as the retention time increases. It decreases and diffuses to a region farther away from the interface. This diffusion occurs both on the group III nitride semiconductor substrate 2 side and on the first group III nitride semiconductor layer 4 side.

Here, when the group III nitride semiconductor substrate 2 containing a sufficiently high concentration of Fe is used, Fe diffuses from the group III nitride semiconductor substrate 2 to the first group III nitride semiconductor layer 4 side. At this time, since the group III nitride semiconductor substrate 2 containing Fe is sufficiently thick, it can be considered that the Fe raw material concentration does not decrease by diffusion. Therefore, the Fe concentration at a position x (cm) away from the interface between the group III nitride semiconductor substrate 2 and the first group III nitride semiconductor layer 4 toward the first group III nitride semiconductor layer 4 is represented by N _f ( cm ⁻³ ), the Fe concentration of the group III nitride semiconductor substrate 2 is N _f0 (cm ⁻³ ), the diffusion coefficient of Fe in the group III nitride semiconductor is D _f (cm ² / s), and the growth temperature is Assuming that the total holding time is t (s), the relationship of Expression (2) shown in [Expression 2] is obtained.

Note that the diffusion coefficient D _f in the group III nitride semiconductor of Fe also varies depending on the temperature, similarly to the diffusion coefficient D _s in the group III nitride semiconductor of Si described above. FIG. 2 shows the temperature dependence characteristics of the diffusion coefficient D _s in the group III nitride semiconductor of Si and the diffusion coefficient D _f in the group III nitride semiconductor of Fe obtained by experiments. As shown in FIG. 2, it can be seen that D _f > D _{s in} the temperature range of at least 800 ° C. and 1200 ° C.

Diffusion coefficients D _s and D _f obtained from equations (1) and (2) and the temperature dependence characteristics of FIG. 2 and the growth temperature are piled up as expected from the substrate management status or the previous pretreatment until the start of growth. Using the Si concentration Q, the group III nitriding is performed so that the Fe concentration becomes three times or more of the Si concentration over the entire region where the Si concentration of the first group III nitride semiconductor layer 4 is 2 × 10 ¹⁵ cm ⁻³ or more. The Fe concentration N _f0 of the physical semiconductor substrate 2 and the total holding time t at the growth temperature are determined.

At this time, the Fe concentration N _f0 of the group III nitride semiconductor substrate 2 may be 2 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less, more preferably 1 × 10 ¹⁹ cm ⁻³ or more. It is good that it is 1 × 10 ²⁰ cm ⁻³ or less.

  The growth temperature is preferably 1000 ° C. or more and 1200 ° C. or less, and the total holding time t at the growth temperature is preferably 1000 seconds or more and 8000 seconds or less. The total holding time t at the growth temperature can be adjusted by holding it for a required time while maintaining the growth temperature after all the group III nitride semiconductor layers 3 have been grown.

Here, for reference, a GaN substrate to which Fe is not added is used as a group III nitride semiconductor substrate, which is immersed in a solution of hydrofluoric acid: nitric acid = 12: 1 for 5 minutes, and is rinsed sufficiently with pure water. After performing N ₂ blow-drying, after growing the GaN having a thickness of 300 nm as the first group III nitride semiconductor layer, the time until it is put into the glove box of the MOCVD (Metal Organic Chemical Vapor Deposition) apparatus FIG. 3 shows the relationship between the Si concentration at the interface between the group III nitride semiconductor substrate and the first group III nitride semiconductor layer. Note that ammonia gas and TMG (Tri Methyl Gallium) were used as raw materials for the first group III nitride semiconductor layer. Further, the Si concentration at the interface was analyzed by SIMS (Secondary Ion Mass Spectrometry).

  As shown in FIG. 3, it can be seen that the Si concentration increases as the standing time until the glove box is put into the glove box after drying is longer. It is desirable that the standing time until it is put into the glove box after drying is as short as possible.

As described above, in the group III nitride semiconductor epitaxial wafer 1 according to the present embodiment, a group III nitride semiconductor substrate 2 to which Fe is added is used, and the group III nitride semiconductor substrate 2 is directly above the group III nitride semiconductor substrate 2. The formed first group III nitride semiconductor layer 4 has Fe added by diffusion from the group III nitride semiconductor substrate 2 in the vicinity of the interface with the group III nitride semiconductor substrate 2, and its Si concentration The Fe concentration is 3 times or more of the Si concentration over the entire region where is 2 × 10 ¹⁵ cm ⁻³ or more.

  In the present embodiment, Fe is not supplied in the gas phase as in the conventional method, and Fe is supplied by diffusion from the group III nitride semiconductor substrate 2, so that without performing an extra step such as purging, It becomes possible to avoid the influence of contamination of the electron supply layer 5 with Fe and to avoid the memory effect.

In the present embodiment, there is no need for purging to remove Fe during production, and it is not necessary to form a cap layer, so that an extra structure and extra steps can be omitted, while improving the throughput, The influence of Si contamination can be suppressed by setting the Fe concentration to 3 times or more of the Si concentration over the entire region where the Si concentration in the first group III nitride semiconductor layer 4 is 2 × 10 ¹⁵ cm ⁻³ or more.

  That is, according to the present invention, it is possible to realize a group III nitride semiconductor epitaxial wafer 1 capable of suppressing the memory effect of Fe without reducing the throughput while suppressing the influence of Si contamination by Fe doping.

  The present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the spirit of the present invention.

Example 1
A GaN substrate containing 2 × 10 ¹⁸ cm ^{−3 of} Fe is used as the group III nitride semiconductor substrate 2, which is immersed in a solution of hydrofluoric acid: nitric acid = 12: 1 for 5 minutes, and then sufficiently rinsed with pure water And N ₂ blow-drying was performed. After drying, the time required to put into the MOCVD glove box is 1 minute, and a high-purity GaN layer is formed on the group III nitride semiconductor substrate 2 using ammonia gas and TMG (Trimethyl Gallium) as raw materials. The group III nitride semiconductor layer 4 was formed with a thickness of about 300 nm. Thereafter, an AlGaN layer having a film thickness of 40 nm was formed as the electron supply layer 5 using ammonia gas, TMA (Tri Methyl Aluminum), and TMG. The growth temperature was 1100 ° C. and the total holding time at the growth temperature was 1200 seconds.

When the depth profile of the Si concentration and the Fe concentration was examined by SIMS analysis after the growth, it was found that the Fe concentration was 3 times or more of the Si concentration over the entire region where the Si concentration was 2 × 10 ¹⁵ cm ⁻³ or more. It could be confirmed. Thereafter, a HEMT structure was fabricated and electrical characteristics were evaluated. As a result, it was confirmed that the leakage current was suppressed as desired and the memory effect was suppressed.

(Example 2)
A GaN substrate containing 1 × 10 ²⁰ cm ^{−3 of} Fe is used as the group III nitride semiconductor substrate 2, which is immersed in a solution of hydrofluoric acid: nitric acid = 12: 1 for 5 minutes, and then sufficiently rinsed with pure water And N ₂ blow-drying was performed. After drying, the time until it is put into the MOCVD glove box is set to 60 minutes, and a high-purity GaN layer is formed on the group III nitride semiconductor substrate 2 using ammonia gas and TMG as raw materials, as a first group III nitride semiconductor. The layer 4 was formed with a thickness of about 300 nm. Thereafter, an AlGaN layer having a thickness of 40 nm was formed as the electron supply layer 5 using ammonia gas, TMA, and TMG. The growth temperature was 1100 ° C. and the total holding time at the growth temperature was 1200 seconds.

When the depth profile of the Si concentration and the Fe concentration was examined by SIMS analysis after the growth, it was found that the Fe concentration was 3 times or more of the Si concentration over the entire region where the Si concentration was 2 × 10 ¹⁵ cm ⁻³ or more. It could be confirmed. Thereafter, a HEMT structure was fabricated and electrical characteristics were evaluated. As a result, it was confirmed that the leakage current was suppressed as desired and the memory effect was suppressed.

(Comparative example)
A GaN substrate containing 1 × 10 ¹⁸ cm ^{−3 of} Fe was used as a group III nitride semiconductor substrate, which was immersed in a solution of hydrofluoric acid: nitric acid = 12: 1 for 5 minutes, and then rinsed sufficiently with pure water. And N ₂ blow dry. It takes 1 minute to put it in the MOCVD glove box after drying, and a high-purity GaN layer is formed on the group III nitride semiconductor substrate using ammonia gas and TMG as raw materials as the first group III nitride semiconductor layer. And having a thickness of about 300 nm. Thereafter, an AlGaN layer having a thickness of 40 nm was formed as an electron supply layer using ammonia gas, TMA, and TMG. The growth temperature was 1100 ° C. and the total holding time at the growth temperature was 1200 seconds.

  After the growth, the depth profile of the Si concentration and the Fe concentration was examined by SIMS analysis. As a result, the Fe concentration was 3 to the depth of 150 nm from the interface between the group III nitride semiconductor substrate and the first group III nitride semiconductor layer. The area was less than doubled. Thereafter, a HEMT structure was fabricated and the electrical characteristics were evaluated. As a result, generation of a leakage current was confirmed, and a desired effect was not obtained.

From the results of Examples 1 and 2 and the comparative example, the memory effect can be suppressed by setting the Fe concentration of the group III nitride semiconductor substrate 2 to 2 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. It turns out that it is.

1 Group III nitride semiconductor epitaxial wafer 2 Group III nitride semiconductor substrate 3 Group III nitride semiconductor layer 4 First group III nitride semiconductor layer 5 Electron supply layer

Claims (5)

A group III nitride semiconductor substrate;
A Group III nitride semiconductor epitaxial wafer comprising at least two Group III nitride semiconductor layers formed on the Group III nitride semiconductor substrate,
As the group III nitride semiconductor substrate, a substrate added with Fe,
The first group III nitride semiconductor layer, which is the group III nitride semiconductor layer formed immediately above the group III nitride semiconductor substrate,
In the vicinity of the interface with the group III nitride semiconductor substrate, Fe is added by diffusion from the group III nitride semiconductor substrate,
A group III nitride semiconductor epitaxial wafer characterized in that the Fe concentration is three times or more of the Si concentration over the entire region where the Si concentration is 2 × 10 ¹⁵ cm ⁻³ or more. The group III nitride semiconductor epitaxial wafer according to claim 1, wherein the group III nitride semiconductor substrate has an Fe concentration of 2 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. 3. The group III nitride semiconductor epitaxial wafer according to claim 2, wherein the group III nitride semiconductor substrate has an Fe concentration of 1 × 10 ¹⁹ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less. A group III nitride semiconductor substrate;
A Group III nitride semiconductor epitaxial wafer comprising at least two Group III nitride semiconductor layers formed on the Group III nitride semiconductor substrate,
As the group III nitride semiconductor substrate, a substrate added with Fe,
In the vicinity of the interface of the first group III nitride semiconductor layer, which is the group III nitride semiconductor layer formed immediately above the group III nitride semiconductor substrate, with the group III nitride semiconductor substrate, the group III nitride Fe is added by diffusion from the semiconductor substrate,
A group III nitride semiconductor epitaxial wafer characterized in that the Fe concentration is made three times or more of the Si concentration over the entire region where the Si concentration of the first group III nitride semiconductor layer is 2 × 10 ¹⁵ cm ⁻³ or more. Manufacturing method. The method for producing a group III nitride semiconductor epitaxial wafer according to claim 4, wherein the growth temperature is set to 1000 ° C to 1200 ° C, and the total holding time at the growth temperature is set to 1000 seconds or more and 8000 seconds or less.