JP2011199191A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device suppressed in an increase in configuration.SOLUTION: In the semiconductor device, a semiconductor substrate is partitioned into a plurality of element forming regions by an insulation separating trench and at least one electronic element is formed in each of the element forming regions. The shape in a plane direction of the insulation separating trench is in the form of a grid so that two element forming regions are mutually adjacent via one insulation separating trench in the plane direction vertical to a thickness direction of the semiconductor substrate.

Description

  The present invention relates to a semiconductor device in which a semiconductor substrate is partitioned into a plurality of element formation regions by insulating isolation trenches, and at least one electronic element is formed in each element formation region.

  Conventionally, for example, Patent Document 1 proposes a semiconductor device in which a semiconductor layer is formed on a support substrate via an insulating layer, and this semiconductor layer is divided into a plurality of element formation regions by insulating isolation trenches. In this semiconductor device, a capacitor having a dielectric thin film as a sidewall insulating film of an insulating isolation trench is formed in a semiconductor layer.

Japanese Patent Laid-Open No. 2003-45588

  Incidentally, in the semiconductor device disclosed in Patent Document 1, as shown in FIG. 5 of Patent Document 1, a plurality of insulating isolation trenches are independently formed in the semiconductor layer, and one insulating isolation trench provides one An element formation region is formed. Therefore, a region for independently forming each of the plurality of insulating isolation trenches must be provided in the semiconductor layer in advance, thereby increasing the size of the semiconductor layer and increasing the size of the semiconductor device. There was a problem.

  In view of the above problems, an object of the present invention is to provide a semiconductor device in which an increase in physique is suppressed.

  In order to achieve the above-described object, the invention according to claim 1 is a semiconductor device in which a semiconductor substrate is partitioned into a plurality of element formation regions by insulating isolation trenches, and at least one electronic element is formed in each element formation region. In the plane direction perpendicular to the thickness direction of the semiconductor substrate, the shape along the plane direction of the insulation isolation trench is such that the two element formation regions are adjacent to each other via one insulation isolation trench, It is characterized by a lattice shape.

  Thus, according to the present invention, the shape of the insulating isolation trench is a lattice shape so that the two element formation regions are adjacent to each other via one insulating isolation trench. According to this, unlike the configuration in which each of the plurality of isolation trenches is independent, it is not necessary to provide a region for independently forming each of the plurality of isolation trenches in the semiconductor substrate. Increase is suppressed. As a result, an increase in the size of the semiconductor device is suppressed.

  According to a second aspect of the present invention, the insulating isolation trench has a sidewall oxide film, and the insulating isolation trench is preferably filled with an insulating material. According to this, the electrical insulation between the element formation regions adjacent via the insulating isolation trench is improved. As the insulating material, silicon oxide can be used as described in claim 3.

  According to a fourth aspect of the present invention, the insulating isolation trench has a side wall oxide film, the insulating isolation trench is filled with a conductive material, and the side wall oxide film is used as a dielectric, and the side wall oxide film is interposed therebetween. It is preferable that a capacitor having an adjacent conductive material region and an element formation region as a counter electrode is formed on a semiconductor substrate.

  According to the first aspect of the present invention, the insulating isolation trench has a lattice shape, and the insulating isolation trench is filled with a conductive material. According to this, among the counter electrodes of the capacitor, an electrode (hereinafter referred to as a first electrode) formed of a conductive material is an electrode formed of an element formation region (hereinafter referred to as a second electrode). Unlikely, each capacitor has the same potential. Therefore, it is not necessary to connect an external wiring to each first electrode. That is, at least one external wiring may be connected to the conductive material constituting the first electrode. As a result, the number of external wirings can be reduced as compared with a configuration in which a capacitor is formed in each of the insulating isolation trenches formed independently. As the conductive material, polysilicon can be used as described in claim 5.

1 is a plan view showing a schematic configuration of a semiconductor device according to a first embodiment. It is sectional drawing which follows the II-II line | wire of FIG. It is sectional drawing for demonstrating the modification of a semiconductor device. It is the schematic which shows the electrical connection of a capacitor | condenser.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view showing a schematic configuration of the semiconductor device according to the first embodiment. 2 is a cross-sectional view taken along line II-II in FIG. In the following, the direction along the thickness of the semiconductor substrate 10 is referred to as the thickness direction, and the direction perpendicular to the thickness direction is referred to as the plane direction. Therefore, hereinafter, when simply describing “thickness”, it indicates the length along the above-described thickness direction, and when simply describing “planar shape”, it indicates the shape along the above-described planar direction.

  As shown in FIGS. 1 and 2, the semiconductor device 100 includes a semiconductor substrate 10 as a main part. The first semiconductor layer 11 of the semiconductor substrate 10 is partitioned into a plurality of element formation regions 21 by insulating isolation trenches 20, and an electronic element (not shown) such as a bipolar transistor is formed in each element formation region 21. Yes. As shown in FIG. 1, the planar shape of the insulating isolation trench 20 is a lattice shape. The planar shape of the insulating isolation trench 20 is a feature point of the semiconductor device 100 according to the present embodiment.

  As shown in FIG. 2, the semiconductor substrate 10 includes a first semiconductor layer 11 in which an electronic element is formed, and a second semiconductor layer 12 that supports the first semiconductor layer 11 via an insulating layer 13. The first semiconductor layer 11 is made of N-type single crystal silicon, the second semiconductor layer 12 is made of P-type single crystal silicon, and the insulating layer 13 is made of silicon oxide. The first semiconductor layer 11 and the second semiconductor layer 12 are mechanically bonded by a known direct bonding technique, and the insulating layer 13 is formed in the bonding process. Although not shown, electronic elements are formed in the first semiconductor layer 11 by selectively introducing N-type impurities or P-type impurities into predetermined portions of the first semiconductor layer 11.

  The insulation isolation trench 20 partitions the first semiconductor layer 11 into a plurality of element formation regions 21. The insulating isolation trench 20 is formed by removing a predetermined portion of the first semiconductor layer 11 in the thickness direction by a well-known trench formation technique, and thermally oxidizing the surface layer of the surface of the first semiconductor layer 11 that is removed and exposed to the outside. Formed with. The insulating isolation trench 20 has a groove shape with the surface of the thermally oxidized first semiconductor layer 11 as a side wall and the insulating layer 13 surrounded by the side wall as a bottom. Hereinafter, the side wall of the insulating isolation trench 20 is referred to as a side wall oxide film 22. In this embodiment, the insulating isolation trench 20 is filled with an insulating material 23 made of silicon oxide.

  Next, the planar shape of the isolation trench 20 that is a characteristic point of the semiconductor device 100 according to the present embodiment and the function and effect thereof will be described. As shown in FIG. 1, the planar shape of the insulating isolation trench 20 is a lattice shape, and two element forming regions 21 are adjacent to each other through one insulating isolation trench 20 constituting the lattice. . According to this, unlike the configuration in which each of the plurality of isolation trenches is independent, the first semiconductor layer 11 (semiconductor substrate 10) is not provided with a region for forming each of the plurality of isolation trenches 20 independently. Both get better.

  That is, in the configuration in which each of the plurality of isolation trenches is independent, a region for forming an isolation trench that partitions one element formation region between two adjacent element formation regions and the other element formation region are provided. It is necessary to provide a region for forming the insulating isolation trench to be partitioned and a region for separating the two insulating isolation trenches by a predetermined distance. However, in the configuration of the present embodiment, a region for forming one insulating isolation trench 20 may be provided between two adjacent element formation regions 21. Thereby, an increase in the size of the semiconductor substrate 10 is suppressed, and an increase in the size of the semiconductor device 100 is suppressed.

  In the present embodiment, the insulating isolation trench 20 is filled with the insulating material 23. According to this, the electrical insulation between the element formation regions 21 adjacent via the insulation isolation trench 20 is improved.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

  In the present embodiment, the example in which the insulating isolation trench 20 is filled with the insulating material 23 is shown. However, as shown in FIG. 3, it is possible to adopt a configuration in which the insulating isolation trench 20 is filled with a conductive material 24 such as polysilicon. In this case, as shown by a broken line in FIG. 3, the sidewall oxide film 22 is a dielectric, and the region 25 of the conductive material 24 and the region 26 of the element formation region 21 adjacent to each other through the sidewall oxide film 22 are counter electrodes. Two capacitors 27 are formed for each insulation isolation trench 20.

  As shown in FIG. 3, the two capacitors 27a and 27b share the same conductive material 24 that constitutes one of the counter electrodes. Therefore, as shown in FIG. 4, the two capacitors 27 a and 27 b are electrically connected via the conductive material 24. External wiring 28 is connected to the conductive material 24. Thereby, the conductive material 24 is electrically connected to the ground via the external wiring 28. FIG. 3 is a cross-sectional view for explaining a modification of the semiconductor device. FIG. 4 is a schematic diagram showing electrical connection of capacitors. Hereinafter, the region 25 is referred to as a first electrode 25 and the region 26 is referred to as a second electrode 26.

  By the way, in this modification, the grid-like insulation isolation trench 20 is filled with the conductive material 24. According to this, the first electrode 25 constituted by the conductive material 24 has the same potential in each capacitor 27 unlike the second electrode 26 constituted by the element forming region 21. Therefore, it is only necessary to connect at least one external wiring 28 to the conductive material 24 constituting the first electrode 25. Compared to a configuration in which a capacitor is formed in each independently formed insulating isolation trench, the external material 28 is externally connected. The number of wirings 28 can be reduced.

  Although not shown, the capacitance of the capacitor 27 may be adjusted by partially removing the conductive material 24 filled in the insulating isolation trench 20 by known photolithography or dry etching. Alternatively, a plurality of electrically independent capacitors 27 may be formed by removing the conductive material 24 so as to be divided into a plurality of regions.

DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate 20 ... Insulation isolation trench 21 ... Element isolation formation region 22 ... Side wall oxide film 23 ... Insulating material 24 ... Conductive material 27 ... Capacitor 100 ... Semiconductor device

Claims (5)

A semiconductor device in which a semiconductor substrate is partitioned into a plurality of element formation regions by insulating isolation trenches, and at least one electronic element is formed in each element formation region,
In the plane direction perpendicular to the thickness direction of the semiconductor substrate, the shape along the plane direction of the insulating isolation trench is such that the two element formation regions are adjacent to each other via one insulating isolation trench, A semiconductor device having a lattice shape. The isolation trench has a sidewall oxide film;
The semiconductor device according to claim 1, wherein the insulating isolation trench is filled with an insulating material.   The semiconductor device according to claim 2, wherein the insulating material is silicon oxide. The isolation trench has a sidewall oxide film;
The isolation trench is filled with a conductive material;
A capacitor is formed on the semiconductor substrate, wherein the sidewall oxide film is a dielectric, and the conductive material region and the element formation region adjacent to each other through the sidewall oxide film are opposed electrodes. The semiconductor device according to claim 1.   The semiconductor device according to claim 4, wherein the conductive material is polysilicon.

Images