JP2011198849A - Method of manufacturing semiconductor wafer, method of manufacturing semiconductor element, semiconductor wafer, semiconductor element, and electronic device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer by which yields are significantly improved.SOLUTION: The method of manufacturing a semiconductor wafer includes a protection film forming step of forming a stripe-shaped protection film 302 on a part on a substrate 301, and a semiconductor layer forming step of forming a semiconductor layer by growing semiconductor crystal on a portion except for a protection film 302 forming portion of the substrate 301. A substrate which satisfies that an absolute value |θp| of an off angle θp in a direction parallel to a length direction of the protection film 302 is smaller than an absolute value |θo| of an off angle θo in a direction orthogonal to the length direction of the protection film 302, and |θp| ≤0.2°, is used as the substrate 301.

Description

  The present invention relates to a method for manufacturing a semiconductor wafer, a method for manufacturing a semiconductor element, a semiconductor wafer, a semiconductor element, and an electronic device.

  Semiconductor elements such as transistors, light emitting diodes (LEDs), and semiconductor lasers (LDs) are important members of various electronic devices. In particular, a semiconductor light emitting element such as an LD is useful for an image display device, an information recording / reproducing device, an optical communication device, and the like. Examples of the LD include a ridge stripe type LD and an inner stripe type LD (Patent Document 1, etc.).

JP 2003-78215 A

  In the manufacture of semiconductor wafers used for the aforementioned ridge stripe LD, inner stripe LD, etc., a significant improvement in yield is required.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor wafer, a method for manufacturing a semiconductor element, a semiconductor wafer, a semiconductor element, and an electronic device with significantly improved yield.

In order to achieve the above object, a method for producing a semiconductor wafer of the present invention comprises:
A protective film forming step of forming a stripe-shaped protective film on a part of the substrate;
A semiconductor layer forming step of forming a semiconductor layer by growing a semiconductor crystal in a portion other than the protective film forming portion on the substrate after the protective film forming step;
As the substrate, the absolute value | θp | of the off angle θp in the direction parallel to the length direction of the protective film is larger than the absolute value | θo | of the off angle θo in the direction perpendicular to the length direction of the protective film. A small size and satisfying | θp | ≦ 0.2 ° is used.

A semiconductor device manufacturing method of the present invention includes a semiconductor wafer manufacturing process for manufacturing the semiconductor wafer by the semiconductor wafer manufacturing method of the present invention,
The semiconductor wafer includes a dividing step of dividing the semiconductor wafer in a direction parallel to a length direction of the protective film at the protective film forming portion.

  The semiconductor wafer of the present invention is manufactured by the method for manufacturing a semiconductor wafer of the present invention.

  The semiconductor element of the present invention is manufactured by the method for manufacturing a semiconductor element of the present invention.

  The electronic device of the present invention includes a light source, and the light source includes the semiconductor element of the present invention which is a semiconductor light emitting element.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of a semiconductor wafer, the manufacturing method of a semiconductor element, a semiconductor wafer, a semiconductor element, and an electronic device with the yield improved significantly can be provided.

FIG. 1 is a cross-sectional view showing a configuration of an example of a ridge stripe LD of the present invention. FIG. 2 is a cross-sectional view showing a configuration of an example of the inner stripe type LD of the present invention. FIG. 3 is a schematic diagram for explaining selective growth during LD manufacturing. FIG. 4 is a graph showing the relationship between the substrate off angle θp and the ridge growth height hr in the direction parallel to the length direction of the stripe-shaped protective film on the substrate surface. FIG. 5 is a graph showing the relationship between the substrate off angle θo and the ridge growth height hr in a direction orthogonal to the length direction of the stripe-shaped protective film on the substrate surface. FIG. 6 is a graph showing the relationship between the substrate off angle θp in the direction parallel to the length direction of the stripe-shaped protective film on the substrate surface and the ridge growth height hr in the example of the present invention and the comparative example. FIG. 7 is a graph showing the relationship between the substrate off angle θp in the direction parallel to the length direction of the stripe-shaped protective film on the substrate surface and the atomic step interval in the direction orthogonal to the length direction of the stripe-shaped protective film. is there.

  The semiconductor wafer manufacturing method of the present invention further includes an active layer stripe forming step of forming an active layer stripe on a part of the semiconductor layer by lithography and etching, and the manufactured semiconductor wafer is used for manufacturing a semiconductor light emitting device. The semiconductor wafer is preferably.

  In the semiconductor wafer manufacturing method of the present invention, the active layer stripe is preferably a ridge stripe. By making the active layer stripe a ridge stripe, the fluctuation of the ridge width can be reduced, and a stable kink level semiconductor wafer can be manufactured with a high yield.

  In the semiconductor wafer manufacturing method of the present invention, the active layer stripe is preferably an inner stripe. By making the active layer stripe an inner stripe, the fluctuation of the width of the current confinement layer opening can be reduced, and a stable kink level semiconductor wafer can be manufactured with a high yield.

In the semiconductor wafer manufacturing method of the present invention, in the semiconductor layer forming step, the composition of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) is set. The semiconductor layer is preferably formed from a group III nitride semiconductor.

  The group III nitride semiconductor has excellent properties such as a sufficiently large forbidden band (band gap) and direct transition between bands. For this reason, group III nitride semiconductors are actively studied for application to various semiconductor elements such as short wavelength light emitting elements. For example, the performance of LEDs in the ultraviolet to blue and green wavelength regions using group III nitride semiconductors has improved dramatically since the mid-1990s. For this reason, the application range of the LED to illumination, various display uses, etc. is remarkably widened, forming a very large market. In particular, as one of the trump cards for countermeasures against global warming, LEDs in the white wavelength region have attracted a great deal of attention as light sources for next-generation lighting. The group III nitride semiconductor is also important as an LD material used for a light source for high-density optical disks such as Blu-ray. For example, development of an LD with an oscillation wavelength of 405 nm has been vigorously advanced, and commercialization has already progressed. In order to increase the writing speed of the optical disc, it is necessary to increase the output of the LD. In order to increase the output of the LD, it is important to increase the carrier injection efficiency. Further, in order to use as a light source for an optical disc, it is necessary to adjust the beam shape in order to narrow down the laser beam of the LD into a spot shape. For this reason, it is important to control the transverse mode of the LD. Furthermore, with the increase in the transfer speed of optical discs, the high-frequency characteristics of the LD are important, and it is necessary to reduce the element resistance and the parasitic capacitance of the element as much as possible.

  In addition to light sources for optical discs, LDs using Group III nitride semiconductors that oscillate in blue (wavelength: about 450 nm) and green (wavelength: about 530 nm) are also actively studied as light sources for displays and the like. As a light source for a display, in order to cope with the enlargement of the screen, it is required to increase the output of the LD, and the lateral mode control is a heavy problem in terms of laser beam shape control.

  As a high power LD of a single transverse mode satisfying such a high required performance, there are a ridge stripe type LD100 shown in FIG. 1 and an inner stripe type LD200 shown in FIG. In FIG. 1 and FIG. 2, the same parts are denoted by the same reference numerals.

  The ridge stripe LD100 is advantageous in terms of high frequency characteristics because of its structurally small parasitic capacitance. In the ridge stripe LD 100, the ridge 111 is produced by using, for example, lithography and etching together. In the group III nitride LD, since chemical etching with a solution is difficult, for example, halogen-based dry etching is used for the etching. The upper portion of the ridge 111 is covered with an insulating film 110 having a stripe-shaped opening, a p-type contact layer 109 is embedded in the opening, and a p-type electrode 112 is provided thereon. In the ridge stripe LD100, current confinement is achieved by the ridge 111. Further, the transverse mode characteristics of the ridge stripe LD100 are controlled by adjusting the stripe width, ridge width and ridge depth of the p-type electrode 112. The accuracy of the stripe width and the ridge width is determined by the accuracy of the lithography. On the other hand, the ridge depth is determined by the etching amount and depends on many parameters such as plasma conditions during etching, an etching gas flow rate, and a substrate temperature. For this reason, in order to manufacture a device over a large area with a high yield, a high degree of control technology is required. Further, the ridge stripe LD 100 has a problem that the active layer is easily damaged by charged particles generated during the etching. Other configurations of the ridge stripe LD 100 will be described later.

  On the other hand, in the inner stripe type LD200, as disclosed in, for example, Patent Document 1, a stripe-shaped opening 114A having a width of about 1 μm to 1.5 μm is formed in a material such as a low refractive index and insulating AlN layer 114. And buried with a p-type cladding layer 108 to control current confinement and transverse mode. The inner stripe LD 200 is similar to the ridge stripe LD 100 using dry etching in terms of controllability, heat dissipation, electrical resistance, and the like of the stripe shape that controls the upper limit (so-called kink level) of the single transverse mode light output. It is superior and is very promising as a structure suitable for high-power lasers. The configuration of the inner stripe LD 200 other than these will be described later.

  The semiconductor element of the present invention is preferably a semiconductor light emitting element. The semiconductor light emitting device obtained in the present invention is not particularly limited, and may be any semiconductor device such as an LD, LED, super luminescent diode (SLD), or the like. The electronic device of the present invention is not particularly limited, and may be any electronic device such as an image display device, an information recording / reproducing device, or an optical communication device.

  Hereinafter, embodiments of the present invention will be described more specifically. However, the following embodiment is an illustration and does not limit the present invention.

A GaN substrate, a sapphire substrate, or the like is used as a substrate for a semiconductor element such as a group III nitride LD. At this time, in order to reduce the defect density and cracks in the laser emission region, a dielectric mask (protective film) such as SiO _{2 is} formed on a part of the substrate surface, and the laser layer structure is formed by selective growth. Can do. In such selective growth, as schematically shown in FIG. 3, the ridge growth portion 305 is formed by a so-called selective growth effect in which the amount of raw material supplied to the surface of the substrate 301 increases in the region near the protective film 302 and the growth rate increases. It is formed. In the ridge growth portion 305, the layer thickness and composition change depending on the distance from the protective film 302. For this reason, it is preferable to form the resonator that becomes the light emitting region of the actual LD in the flat growth portion 304 that is sufficiently separated from the ridge growth portion 305. If the growth layer thickness difference between the ridge growth portion 305 and the flat growth portion 304 is defined as a ridge growth height hr, for example, in the manufacture of a semiconductor wafer for an inner stripe type LD, the growth layer thickness of the flat growth portion 304 is Is 2 μm, the ridge growth height hr varies from 1 μm or less to 2 μm or more. When a stripe-shaped opening having an opening width of about 1.0 μm is formed by lithography on a wafer having a large height difference on such a surface, spots are likely to occur in the photoresist used in the lithography. If the photoresist spots can be eliminated in the above method, the yield in the production of the inner stripe LD can be further greatly improved. It is preferable to eliminate the occurrence of photoresist spots due to the ridge growth portion 305 even in the production of the ridge stripe LD. In FIG. 3, reference numeral 303 denotes a polycrystalline layer deposited on the protective film 302.

As a result of repeated experiments by the present inventors, the spots of the photoresist used in the above-mentioned lithography depend on the ridge growth height hr, and the higher the ridge growth height hr, the more the spots of the photoresist appear. We found that it tends to be prominent. Next, the relationship between the experimentally obtained substrate off angle and the ridge growth height hr will be described. When a striped SiO ₂ mask (protective film) is formed on a part of the GaN substrate in the <1-100> direction, as shown in FIG. 4, <1-100 parallel to the length direction of the protective film. As the absolute value of the substrate off angle θp in the> direction | θp ^<1-100> | decreases, the ridge height hr also decreases, and when | θp ^<1-100> | = 0.3 °, the ridge growth height hr. Is about 2.0 μm, but when | θp ^<1-100> | = 0 °, the ridge growth height hr is about 1.0 μm or less, which is half or less.

On the other hand, as shown in FIG. 5, there was no correlation between the substrate off angle θo ^<11-20> in the <11-20> direction orthogonal to the length direction of the protective film and the ridge growth height hr.

The above results can be explained by the surface diffusion phenomenon of the growth raw material. That is, as shown in FIG. 7, the substrate off-angle θp ^<1-100> in the direction parallel to the length direction of the protective film decreases, and the atomic step interval in the direction orthogonal to the length direction of the protective film is reduced. When spread, it is considered that the lateral growth rate increases and the ridge growth height hr is suppressed.

  Therefore, as the substrate, a substrate in which the absolute value | θp | of the off angle θp in the direction parallel to the length direction of the protective film satisfies the relationship of | θp | ≦ 0.2 ° is used in lithography. As a result, it is possible to greatly reduce the spots of the photoresist to be produced and to greatly improve the yield in the production of the semiconductor wafer.

  Furthermore, by producing the LD structure adjacent to the defect region, the frequency of occurrence of defects and cracks in the resonator can be reduced, and a stable kink level LD can be produced with a high yield.

  In the present embodiment, the present invention will be described by taking as an example the case where the semiconductor wafer to be manufactured is a semiconductor wafer for manufacturing the inner stripe type LD 200 shown in FIG. However, the present invention is not limited by the following description. As described above, the method for manufacturing a semiconductor wafer of the present invention includes a protective film forming step and a semiconductor layer forming step.

(Protective film formation process)
First, a stripe-shaped protective film (dielectric film) is formed on a part of the n-type GaN substrate 101 (not shown). The length direction of the protective film is preferably a <1-100> direction that forms a laser resonator. In the n-type GaN substrate, the absolute value | θp | of the off angle θp in the direction parallel to the length direction of the protective film is the absolute value of the off angle θo in the direction perpendicular to the length direction of the protective film | A material smaller than θo | and satisfying | θp | ≦ 0.2 ° is used.

(Semiconductor layer forming process)
Next, an n-type buffer layer 102, an n-type cladding layer 103, an n-type optical confinement layer 104, a quantum well layer 105, a cap layer 106, and a part other than the protective film formation part on the n-type GaN substrate 101, The p-type guide layer 107 is laminated in the above order. The n-type buffer layer 102 is made of Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 1 μm). The n-type cladding layer 103 is made of Si-doped n-type Al _0.05 Ga _0.95 N (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 2 μm). The n-type optical confinement layer 104 is made of Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 0.1 μm). The quantum well layer 105 has a multi-quantum well (MQW) structure including an In _0.1 Ga _0.9 N (thickness 3 nm) well layer and an undoped GaN barrier layer (thickness 10 nm). It is formed. The cap layer 106 is made of Mg-doped p-type Al _0.2 Ga _0.8 N. The p-type guide layer 107 is made of Mg-doped p-type GaN (Mg concentration 2 × 10 ¹⁹ cm ⁻³ , thickness 0.1 μm). This formation method is not particularly limited, and for example, a usual method such as a vapor deposition method, more specifically, a metal organic vapor phase epitaxy (MOVPE) method can be used. Conditions such as gas concentration and growth temperature at the time of forming each layer can be appropriately set with reference to conditions generally used in the vapor phase growth method, for example.

  Next, an amorphous layer made of AlN is formed on the upper surface of the p-type guide layer 107. This amorphous layer is later crystallized to become the current confinement layer 114.

  The amorphous layer is deposited by a MOVPE method at a low temperature of 600 ° C. or less and about 0.1 μm. This is because if a single crystal AlN layer is formed on the p-type guide layer 107 at a high temperature by the MOVPE method, cracks occur in the AlN layer during deposition.

Next, an opening 114A is formed by removing a part of the amorphous layer by photolithography and wet etching. Specifically, first, SiO ₂ is deposited to a thickness of 100 nm on the amorphous layer to form a SiO ₂ layer. Next, after applying a resist on the upper surface of the SiO ₂ layer, a stripe pattern having a width of 1.5 μm is formed on the resist by photolithography. Next, the SiO ₂ layer is etched with buffered hydrofluoric acid using the resist as a mask, and then the resist is removed with an organic solvent and further washed with water. Next, the amorphous layer is etched using the SiO ₂ layer as a mask. As the etching solution, a phosphoric acid / sulfuric acid mixed solution in which phosphoric acid and sulfuric acid are mixed at a volume ratio of 1: 1 is used. Further, the non-crystalline layer in a region not covered with the SiO ₂ mask is removed by etching for 9 minutes in the solution kept at 90 ° C. to form a stripe-shaped opening 114A. In this example, the step of forming the opening 114A by photolithography and wet etching corresponds to the “active layer stripe forming step”.

In the wet etching, various conditions such as the type of etching solution, the liquid temperature, and the type of mask are not limited to those described above, and can be set as appropriate. For example, in the above description, a phosphoric acid / sulfuric acid mixed solution at 90 ° C. is used, but other etching solutions may be used as long as selective and efficient etching can be realized. In the phosphoric acid / sulfuric acid mixed solution, the etching rate can be adjusted by, for example, the blending amount of sulfuric acid and the liquid temperature. In the above description, since the p-type guide layer 107 (GaN) immediately below the non-crystalline layer is a crystalline layer, the former etching rate is significantly higher than the latter etching rate. Efficient etching is possible. Therefore, the composition, temperature, etc. of the etching solution are appropriately set so that the amorphous layer can be etched efficiently and the etching rate does not unnecessarily etch the p-type guide layer 107. It is preferable. From this viewpoint, the temperature of the etching solution is preferably 50 ° C. or higher and 200 ° C. or lower. In the above description, SiO ₂ is used as the etching mask for the non-crystalline layer. However, an organic material containing SiN _x or a resist may be used as long as the material is not affected by the etching solution.

Next, the p-type cladding layer 108 is formed so as to cover the upper surface of the amorphous layer and the upper surface of the p-type guide layer 107 exposed from the opening 114A (so as to bury the opening 114A). Form (embedded regrowth). At this time, prior to starting the formation of the p-type cladding layer 108, the substrate temperature is raised to the formation temperature of the p-type cladding layer 108. When the formation temperature is sufficiently high, the amorphous layer is heat-treated and crystallized to become the current confinement layer 114 from the start of the temperature rise to the completion of the formation of the p-type cladding layer 108. The p-type cladding layer 108 is made of Mg-doped p-type Al _0.05 Ga _0.95 N (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 0.5 μm).

  The heat treatment (crystallization) of the amorphous layer and the formation of the p-type cladding layer 108 may be separate steps. However, as described above, if the formation of the p-type cladding layer 108 and the heat treatment of the amorphous layer are performed simultaneously, it is necessary to increase the number of steps by separately providing a heat treatment step of the amorphous layer in the manufacture of the semiconductor wafer. It is preferable because it is not. The maximum temperature during the heat treatment of the amorphous layer is preferably 700 to 1300 ° C, more preferably 900 to 1300 ° C. Thereby, the non-crystalline layer can be suitably converted into a crystalline layer (the current confinement layer 114). When the material for forming the amorphous layer is other than AlN, the heat treatment temperature may be appropriately set according to the material for formation.

Next, the p-type contact layer 109 is formed on the upper surface of the p-type cladding layer 108. The p-type contact layer 109 is made of Mg-doped p-type GaN (Mg concentration 2 × 10 ²⁰ cm ⁻³ , thickness 0.02 μm).

  Next, a p-type electrode 112 is formed on the upper surface of the p-type contact layer 109, and an n-type electrode 113 is formed on the bottom surface of the n-type GaN substrate 101. The formation conditions of these electrodes are not particularly limited, and can be set as appropriate with reference to the electrode formation conditions of general semiconductor elements. The inner stripe type LD 200 shown in FIG. 2 can be manufactured by dividing the semiconductor wafer manufactured in this way into a direction parallel to the length direction of the protective film at the protective film forming portion. In the division, accurate cleaving can be performed by forming guide grooves by dry etching on the semiconductor layer and the substrate around the protective film formation site. The inner stripe type LD 200 may be cleaved in a direction perpendicular to the length direction of the protective film, if necessary, as a chip. In this case, by devising the formation pattern of the protective film with respect to the substrate so that guide grooves can be formed in a direction perpendicular to the length direction of the protective film, the vertical direction of the protective film is perpendicular to the length direction of the protective film. Even in the direction, accurate cleavage is possible. The length of the chip (element length) can be appropriately set depending on the characteristics desired for the semiconductor light emitting element. However, the method for dividing and cleaving the semiconductor chip is not limited to the method for forming the guide groove by the dry etching, and any method may be used.

  In this example, since the layer thickness from the n-type buffer layer 102 to the current confinement layer 114 is uniform within the wafer surface, the opening 114A is formed in the current confinement layer 114 by photolithography and wet etching. Variations in the opening width of the are reduced. Thereby, the kink level and threshold value variation of the inner stripe type LD 200 obtained in this example can be suppressed.

  In addition, since variations in the thickness of the p-type cladding layer 108 in the vicinity of the opening 114A can be prevented, deviation from the design of the optical confinement structure can be prevented, and variations in characteristics such as threshold values and kink levels can be suppressed with higher accuracy. it can.

In the semiconductor wafer for manufacturing the ridge stripe LD 100 shown in FIG. 1, for example, the current confinement layer 114 is not formed between the p-type guide layer 107 and the p-type cladding layer 108, and lithography and dry etching are used together. Thus, it can be manufactured in the same manner as the inner stripe type LD 200 shown in FIG. 2 except that the ridge 111 is formed. In the dry etching, for example, the p-type contact layer 109 and the p-type cladding layer 108 are etched with a chlorine (Cl ₂ ) -based dry etching apparatus.

  Next, examples of the present invention will be described together with comparative examples. The present invention is not limited or restricted by the following examples and comparative examples.

(Example)
An inner stripe type LD200 shown in FIG. 2 was produced. The n-type GaN substrate 101 includes a plurality of n-type GaN (0001) substrates having an n-type carrier Si concentration of about 1 × 10 ¹⁸ cm ^{−3 and} an off angle in the <1-100> direction of ± 0.2 ° or less. Used (see FIG. 6). A 400 hPa reduced pressure MOVPE apparatus was used to fabricate the element. A mixed gas of hydrogen and nitrogen was used as the carrier gas. As supply sources of Ga, Al, and In, trimethylgallium (TMG), trimethylammonium (TMA), and trimethylindium (TMIn) were used, respectively. Silane (SiH ₄ ) was used as the n-type dopant. Biscyclopentadienyl magnesium (Cp ₂ Mg) was used as the p-type dopant.

First, in order to reduce defects and prevent cracks, a stripe-shaped protective film (dielectric film) was formed on a part of the n-type GaN substrate 101 (not shown). Hereinafter, this process is referred to as a “protective film forming process”. Specifically, SiO ₂ having a thickness of about 0.2 μm was deposited on the n-type GaN substrate 101 to form a SiO ₂ layer. After applying a resist on the upper surface of the SiO ₂ layer, a stripe pattern having a width of 50 μm extending in the <1-100> direction was formed on the resist at a pitch of 400 μm by photolithography. Next, the SiO ₂ layer was etched with buffered hydrofluoric acid using the resist as a mask. Thereafter, the resist was removed with an organic solvent and washed with water. Thus, the protective film was formed in a stripe shape.

  Next, an n-type buffer layer 102, an n-type cladding layer 103, an n-type optical confinement layer 104, a quantum well layer 105, a cap layer 106, a p-type guide layer 107, a p-type cladding layer 108, and a current confinement layer 114 are formed. Growth of each layer formed from group III nitride was performed. Hereinafter, these steps are collectively referred to as an “active layer growth step”.

That is, first, after the n-type GaN substrate 101 was put into a reduced pressure MOVPE apparatus, the n-type GaN substrate 101 was heated while supplying NH _3, and the growth of each layer was started when the growth temperature was reached. Thereby, the n-type buffer layer 102 formed from Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 1 μm), Si-doped n-type Al _0.05 Ga _0.95 N (Si concentration 4) × 10 ¹⁷ cm ⁻³ , thickness 2 μm) n-type cladding layer 103, Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 0.1 μm) n-type light Confinement layer 104, three-period multiple quantum well (MQW) layer 105 formed from an In _0.1 Ga _0.9 N (thickness 3 nm) well layer and an undoped GaN (thickness 10 nm) barrier layer, Mg-doped p-type A cap layer 106 made of Al _0.2 Ga _0.8 N and a p-type guide layer 107 made of Mg-doped p-type GaN (Mg concentration 2 × 10 ¹⁹ cm ⁻³ , thickness 0.1 μm) order Deposited. GaN growth was performed at a substrate temperature of 1080 ° C., a TMG supply rate of 58 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. AlGaN growth was performed at a substrate temperature of 1080 ° C., a TMA supply rate of 36 μmol / min, a TMG supply rate of 58 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. InGaN MQW growth was performed at a substrate temperature of 850 ° C., a TMG supply rate of 8 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. The TMIn supply amount was 48 μmol / min in the well layer.

Next, the substrate temperature was lowered to about 400 ° C., and an amorphous AlN layer (later crystallized to become the current confinement layer 114) was deposited on the p-type guide layer 107. The supply amounts of TMA and NH ₃ during the deposition of the amorphous AlN layer were 36 μmol / min and 0.36 mol / min, respectively, and the deposited film thickness was 0.1 μm.

  At this stage, a part of the wafer was determined and confirmed by SEM (scanning electron microscope). As shown in FIG. 6, the ridge growth height hr was about 1.2 μm or less for all the wafers.

  Next, a part of the amorphous AlN layer was removed by etching to form a stripe-shaped opening 114A extending in the <1-100> direction. Hereinafter, this process is referred to as an “active layer stripe forming process”.

That is, first, SiO ₂ was deposited to a thickness of 100 nm on the amorphous AlN layer to form a SiO ₂ layer. After applying a resist on the upper surface of the SiO ₂ layer, a stripe pattern having a width of 1.5 μm was formed on the resist by photolithography.

  At this stage, it was confirmed by a microscope that the resist opening with a width of 1.5 μm was clearly removed in most wafers, and no resist residue or the like remained.

Next, the SiO ₂ layer was etched with buffered hydrofluoric acid using the resist as a mask. Thereafter, the resist was removed with an organic solvent and washed with water. The amorphous AlN layer was not etched or damaged in each step of buffered hydrofluoric acid, organic solvent, and water washing. Next, the amorphous AlN layer was etched using the SiO ₂ layer as a mask. As an etching solution, a solution in which phosphoric acid and sulfuric acid were mixed at a volume ratio of 1: 1 was used. The AlN layer in the region not covered with the SiO ₂ mask was removed by etching for 9 minutes in the solution kept at 90 ° C. Thereby, the opening 114A was formed. Thereafter, the SiO ₂ layer used as a mask was removed with buffered hydrofluoric acid. In this way, the active layer stripe forming step could be performed.

  Next, the amorphous AlN layer was converted into a crystalline layer (current confinement layer) 114 by heat treatment. Thereafter, a p-type cladding layer 108 was stacked so as to fill the opening 114A formed in the active layer stripe forming step so as to form an opening buried portion, and a p-type contact layer 109 was further deposited. Hereinafter, these steps are collectively referred to as a “p-type cladding layer regrowth step”.

That is, first, the semiconductor wafer formed by the active layer stripe forming process was put into a MOVPE apparatus. Subsequently, the inside of the MOVPE apparatus was heated to about 700 ° C. with an NH ₃ supply rate of 0.36 mol / min and an N ₂ carrier gas supply rate of 0.9 mol / min. After annealing at 700 ° C. for 10 minutes, a part of the carrier gas is switched to H ₂ , the NH ₃ supply rate is 0.36 mol / min, the N ₂ carrier gas supply rate is 0.45 mol / min, and the H ₂ carrier gas supply rate is 0. The temperature was raised again to 1100 ° C., which is the growth temperature of the p-type cladding layer, at .45 mol / min. After reaching 1100 ° C., a p-type cladding layer 108 formed from Mg-doped p-type Al _0.05 Ga _0.95 N (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 0.5 μm) was deposited. Thereafter, the substrate temperature was lowered to 1080 ° C., and then a p-type contact layer 109 formed from Mg-doped p-type GaN (Mg concentration 1 × 10 ²⁰ cm ⁻³ , thickness 0.02 μm) was deposited. The deposition conditions for p-type AlGaN and p-type GaN were the same as those for forming the n-type AlGaN and the n-type GaN except for the difference in dopant.

  When SEM observation was performed after the p-type cladding layer regrowth step, no defects such as cracks and pits were found on the buried regrowth surface on the opening 114A or the current confinement layer 114, and the amorphous AlN layer Was crystallized and was confirmed to be embedded flat by the p-type cladding layer 108.

  The n-type electrode 113 was formed on the back surface (bottom surface) of the n-type GaN substrate 101 and the p-type electrode 112 was formed on the top surface of the p-type contact layer 109 by the vacuum deposition method. Hereinafter, this process is referred to as an “electrode formation process”. Then, the sample after the electrode formation step was cleaved in a direction perpendicular to the length direction of the protective film to obtain an inner stripe type LD200. The element length was 800 μm.

(Comparative example)
Except that two n-type GaN (0001) substrates having an off angle in the <1-100> direction exceeding ± 0.2 ° were used for the n-type GaN substrate 101 (see FIG. 6), the same as in the example. Thus, an inner stripe type LD was produced. In this comparative example, as shown in FIG. 6, the ridge growth height hr of the two wafers is about 1.5 μm at the same stage where the ridge growth height hr is confirmed in the embodiment. That was all. Moreover, in this comparative example, the resist residue was confirmed on both of the two wafers at the same stage where the resist residue was confirmed in the example.

(Evaluation)
The inner stripe LDs obtained in the examples and comparative examples were each fused to a heat sink, and the light emission characteristics were examined. As a result, 90% or more of the inner stripe type LD of the example oscillated at a threshold current of 40 mA or less and a voltage of about 4.0 V, and the kink level was 600 mW or more. Moreover, the average life at the time of 450 mW output was 10,000 hours or more. On the other hand, the inner stripe type LD of the comparative example has a large variation in characteristics, and it is difficult to obtain an element that can stably operate at 450 mW or more.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary note 1) a protective film forming step of forming a stripe-shaped protective film on a part of the substrate;
A semiconductor layer forming step of forming a semiconductor layer by growing a semiconductor crystal in a portion other than the protective film forming portion on the substrate after the protective film forming step;
As the substrate, the absolute value | θp | of the off angle θp in the direction parallel to the length direction of the protective film is larger than the absolute value | θo | of the off angle θo in the direction perpendicular to the length direction of the protective film. A method for producing a semiconductor wafer, which is small and satisfies | θp | ≦ 0.2 °.

(Appendix 2) Further, an active layer stripe forming step of forming an active layer stripe on a part of the semiconductor layer by lithography and etching,
2. The method of manufacturing a semiconductor wafer according to appendix 1, wherein the semiconductor wafer to be manufactured is a semiconductor wafer for manufacturing a semiconductor light emitting element.

(Additional remark 3) The said active layer stripe is a ridge stripe, The manufacturing method of the semiconductor wafer of Additional remark 2 characterized by the above-mentioned.

(Additional remark 4) The said active layer stripe is an inner stripe, The manufacturing method of the semiconductor wafer of Additional remark 2 characterized by the above-mentioned.

(Supplementary Note 5) Group III nitride semiconductor having a composition of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) in the semiconductor layer forming step. The method for manufacturing a semiconductor wafer according to any one of appendices 1 to 4, wherein the semiconductor layer is formed from the manufacturing method.

(Additional remark 6) The semiconductor wafer manufacturing process which manufactures the said semiconductor wafer with the manufacturing method in any one of Additional remark 1 to 5,
A method of manufacturing a semiconductor element, comprising: a dividing step of dividing the semiconductor wafer in a direction parallel to a length direction of the protective film at the protective film forming portion.

(Appendix 7) A semiconductor wafer manufactured by the manufacturing method according to any one of appendices 1 to 5.

(Appendix 8) A semiconductor device manufactured by the manufacturing method according to Appendix 6.

(Supplementary note 9) The semiconductor device according to supplementary note 8, which is a semiconductor laser.

(Supplementary note 10) An electronic apparatus comprising a semiconductor element according to supplementary note 8, including a light source, wherein the light source is a semiconductor light emitting element.

(Supplementary note 11) The electronic device according to Supplementary note 10, which is an image display device.

(Supplementary note 12) The electronic device according to supplementary note 10, which is an information recording / reproducing device.

(Supplementary note 13) The electronic device according to Supplementary note 10, which is an optical communication device.

100 ridge stripe LD
101, 301 Substrate 102 n-type buffer layer 103 n-type cladding layer 104 n-type optical confinement layer 105 quantum well layer 106 cap layer 107 p-type guide layer 108 p-type cladding layer 109 p-type contact layer 110 insulating film 111 ridge 112 p-type Electrode 113 n-type electrode 114 Current confinement layer 114A Opening 200 Inner stripe LD
302 Protective film (dielectric film)
303 Polycrystalline layer 304 Flat growth portion 305 Ridge growth portion hr Ridge growth height

Claims (10)

A protective film forming step of forming a stripe-shaped protective film on a part of the substrate;
A semiconductor layer forming step of forming a semiconductor layer by growing a semiconductor crystal in a portion other than the protective film forming portion on the substrate after the protective film forming step;
As the substrate, the absolute value | θp | of the off angle θp in the direction parallel to the length direction of the protective film is larger than the absolute value | θo | of the off angle θo in the direction perpendicular to the length direction of the protective film. A method for producing a semiconductor wafer, which is small and satisfies | θp | ≦ 0.2 °. Furthermore, an active layer stripe forming step of forming an active layer stripe on a part of the semiconductor layer by lithography and etching,
The semiconductor wafer manufacturing method according to claim 1, wherein the semiconductor wafer to be manufactured is a semiconductor wafer for manufacturing a semiconductor light emitting device. 3. The method of manufacturing a semiconductor wafer according to claim 2, wherein the active layer stripe is a ridge stripe. 3. The method of manufacturing a semiconductor wafer according to claim 2, wherein the active layer stripe is an inner stripe. In the semiconductor layer forming step, the semiconductor layer is formed of a group III nitride semiconductor having a composition of In _x Al _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1). The method for manufacturing a semiconductor wafer according to claim 1, wherein the semiconductor wafer is formed. A semiconductor wafer manufacturing process for manufacturing the semiconductor wafer by the manufacturing method according to claim 1,
A method of manufacturing a semiconductor element, comprising: a dividing step of dividing the semiconductor wafer in a direction parallel to a length direction of the protective film at the protective film forming portion. A semiconductor wafer manufactured by the manufacturing method according to claim 1. A semiconductor device manufactured by the manufacturing method according to claim 6. 9. The semiconductor element according to claim 8, wherein the semiconductor element is a semiconductor laser. 9. An electronic device comprising a semiconductor element according to claim 8, comprising a light source, wherein the light source is a semiconductor light emitting element.

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