JP2010114238A - Method of manufacturing group iii nitride semiconductor, method of manufacturing group iii nitride semiconductor element, and group iii nitride semiconductor and group iii nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a group III nitride semiconductor which can prevent a semiconductor element including a crystal layer of the group III nitride semiconductor from decreasing in quality and has superior manufacturing efficiency, a method of manufacturing the group III nitride semiconductor element, and the group III nitride semiconductor and group III nitride semiconductor element. <P>SOLUTION: The method of manufacturing the group III nitride semiconductor includes a non-crystal layer forming stage A of forming a non-crystal layer of group III nitride on an upper surface of a base layer, a protective layer forming stage (B) of forming a protective layer on an upper surface of the non-crystal layer, an etching stage (C) of etching away a part of the non-crystal layer, and a semiconductor crystal layer forming stage (D) of heat-treating and crystallizing the non-crystal layer in a state where the protective layer is formed, to convert the non-crystal layer into a crystal layer of the group III nitride semiconductor. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a group III nitride semiconductor, a method for manufacturing a group III nitride semiconductor device, a group III nitride semiconductor, and a group III nitride semiconductor device.

  Group III nitride semiconductor materials have excellent properties such as a sufficiently large forbidden band width and direct transition between bands. For this reason, group III nitride semiconductors are actively studied for application to various semiconductor elements such as short wavelength light emitting elements. For example, the performance of light emitting diodes (LEDs) in the ultraviolet to blue and green wavelength regions using Group III nitride semiconductors has improved dramatically since the mid-1990s. For this reason, the application range of the LED to illumination, various display uses, etc. is remarkably widened, forming a very large market. The group III nitride semiconductor is also important as a material for a semiconductor laser used for, for example, a light source for a high-density optical disk and a display. The semiconductor laser is also referred to as a semiconductor laser or laser diode, and may be abbreviated as “LD”.

  When a group III nitride semiconductor is used for a semiconductor element such as a semiconductor laser, a part of the layer containing the group III nitride semiconductor is often removed. As an example, an inner stripe type laser described in Patent Documents 1 to 5 and the like can be given. This inner stripe type laser can be used as a high-power laser excellent in laser beam shape controllability and transverse mode controllability. The inner stripe laser includes, for example, an active layer, a p-type cladding layer, and a current confinement layer. The current confinement layer is provided on the active layer. A part of the current confinement layer is removed by etching or the like. The p-type cladding layer is provided on the current confinement layer and the current confinement layer removal portion. On the current confinement layer removal portion, the p-type cladding layer is embedded in the current confinement layer removal portion, and the p-type cladding layer is in contact with the upper surface of the active layer. The current confinement layer is made of, for example, AlN having a low refractive index and excellent insulating properties. For example, Patent Document 1 describes an inner stripe type GaN-based laser in which AlN having an opening width (stripe width) of about 2.0 μm is embedded under a p-type cladding layer for current confinement and lateral mode control. ing.

  As a method for removing a part of the group III nitride semiconductor layer, for example, there are the following methods (Patent Documents 1 to 3). That is, first, an amorphous layer of a group III nitride (eg, AlN) is deposited on the active layer at a low temperature (eg, 200 to 700 ° C.). Next, a part of the group III nitride non-crystalline layer is removed by etching (for example, photolithography and wet etching) to form openings (stripes). Subsequently, the group III nitride non-crystalline layer is heat-treated at a high temperature (eg, 700 to 1300 ° C.) to convert the group III nitride from an amorphous state to a semiconductor crystal to form a group III nitride semiconductor crystal layer. Thereafter, the p-type cladding layer (eg, p-type AlGaN cladding layer) is formed (regrown) on the group III nitride semiconductor crystal layer and the opening. According to this method, since the group III nitride semiconductor layer is first formed as an amorphous layer and then etched and then crystallized, the etching rate is faster and easier to process than direct etching of the crystalline layer. For this reason, there are advantages that manufacturing efficiency (yield) is good and controllability at the time of etching is excellent.

JP 2003-78215 A JP 2006-121107 A JP 2007-067432 A JP 2007-251119 A International Publication Pamphlet WO2007 / 066644

  In the methods shown in Patent Documents 1 to 3, when a group III nitride semiconductor layer is converted from amorphous to crystalline by heat treatment at a high temperature, mass transport (atom on the semiconductor surface moves due to heat and the shape changes). The surface flatness may deteriorate. In order to prevent this, in Patent Document 1, mass transport is suppressed by adopting a step of oxidizing the surface of the group III nitride amorphous layer prior to crystallization by the heat treatment. .

However, in the methods of Patent Documents 1 to 3, when the surface of the group III nitride non-crystalline layer is oxidized, the oxygen concentration becomes non-uniform, which may lead to deterioration of the quality of the semiconductor element. For example, if the oxygen concentration on the surface of the AlN non-crystalline layer is non-uniform, the composition of aluminum oxynitride (AlN _x O _1-x ) formed on the AlN surface during crystallization by the heat treatment is uneven. appear. If a semiconductor layer such as a p-type cladding layer is deposited thereon, the growth rate differs between the high and low oxygen concentration regions of AlN _x O _1-x , which may cause pits and irregularities. .

  Further, even in a semiconductor element other than the semiconductor laser, it is considered that if the impurity concentration on the surface of the group III nitride amorphous layer can be improved, the quality of the semiconductor element is improved. However, for that purpose, it is necessary to control the impurity concentration in the manufacture of a semiconductor device. If the impurity concentration control process is complicated, the manufacturing efficiency and the manufacturing cost are reduced.

  In order to solve the above-described problems, the present invention is capable of preventing deterioration in quality in a semiconductor element including a crystal layer of a group III nitride semiconductor, and a method for manufacturing a group III nitride semiconductor having excellent manufacturing efficiency, III It is an object to provide a method for manufacturing a group nitride semiconductor device, a group III nitride semiconductor, and a group III nitride semiconductor device.

In order to achieve the above object, a method for producing a group III nitride semiconductor of the present invention comprises:
An amorphous layer forming step of forming a group III nitride amorphous layer on the upper surface of the underlayer;
A protective layer forming step of forming a protective layer on the upper surface of the amorphous layer;
An etching step of removing a part of the amorphous layer by etching;
A semiconductor crystal layer forming step of converting the amorphous layer into a crystal layer of a group III nitride semiconductor by crystallizing the amorphous layer by heat treatment in a state in which the protective layer is formed.

  The method for producing a group III nitride semiconductor device of the present invention is a method for producing a semiconductor device including a group III nitride semiconductor, and the group III nitride semiconductor is produced by the method for producing a group III nitride semiconductor of the present invention. It is characterized by manufacturing.

  Further, the group III nitride semiconductor of the present invention includes a crystal layer of a group III nitride semiconductor, the crystal layer is partially removed, the crystal layer includes an impurity, and an impurity on an upper surface portion of the crystal layer The average value of the concentration is equal to or less than the average value of the internal impurity concentration, and is manufactured by the method for manufacturing a group III nitride semiconductor of the present invention.

  Furthermore, the group III nitride semiconductor device of the present invention is manufactured by the method for manufacturing a group III nitride semiconductor device of the present invention, and includes the group III nitride semiconductor of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the group III nitride semiconductor element which can prevent a quality fall and is excellent in manufacturing efficiency can be manufactured in the semiconductor element containing the crystal layer of a group III nitride semiconductor.

  Hereinafter, the method for producing a group III nitride semiconductor of the present invention, the method for producing a group III nitride semiconductor device of the present invention, the group III nitride semiconductor of the present invention and the group III nitride semiconductor device of the present invention will be described in more detail. explain.

The manufacturing method of the group III nitride semiconductor of the present invention is as described above.
An amorphous layer forming step of forming a group III nitride amorphous layer on the upper surface of the underlayer;
A protective layer forming step of forming a protective layer on the upper surface of the amorphous layer;
An etching step of removing a part of the amorphous layer by etching;
A semiconductor crystal layer forming step of converting the amorphous layer into a crystal layer of a group III nitride semiconductor by crystallizing the amorphous layer by heat treatment in a state in which the protective layer is formed. Other than this, the method for producing a group III nitride semiconductor of the present invention is not particularly limited, but for example, is as follows.

  The method for producing a group III nitride semiconductor of the present invention preferably further includes a protective layer removing step of removing the protective layer after the semiconductor crystal layer forming step. The protective layer removing step is more preferably a step of removing the protective layer by thermal etching. More preferably, the thermal etching temperature in the protective layer removing step is higher than the heat treatment temperature in the semiconductor crystal layer forming step.

In the group III nitride semiconductor manufacturing method of the present invention, the protective layer is preferably a layer formed of group III nitride. The crystal layer is formed of a group III nitride semiconductor having a composition of In _a Ga _b Al _1-ab N (0 ≦ a <1, 0 ≦ b <1, 0 ≦ a + b <1), the protective layer _is formed of a group III nitride having a composition of _{in c Ga d Al 1-c} -d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 <c + d ≦ 1), and the It is preferable that the In composition ratio a of the crystal layer and the In composition ratio c of the protective layer satisfy at least one of the following mathematical formulas (1) and (2).

a = 0 (1)
a <c (2)

In the Group III nitride semiconductor manufacturing method of the present invention, it is preferable that the protective layer is formed of a Group III nitride having a composition of In _x Ga _1-x N (0 ≦ x ≦ 1). The protective layer is particularly preferably made of InN. The crystal layer is particularly preferably made of AlN.

  In the group III nitride semiconductor manufacturing method of the present invention, the crystal layer preferably includes two or more layers. More preferably, the crystal layer includes a lower layer formed of AlN and an upper layer formed of GaN.

In the method for producing a group III nitride semiconductor of the present invention, when the crystal layer contains impurities, it is preferable that the average value of the impurity concentration of the upper surface portion of the crystal layer is equal to or less than the average value of the internal impurity concentration. In the crystal layer, the upper surface portion is, for example, a portion from the upper surface of the crystal layer to a depth of 50 nm, and the inside is, for example, a portion other than the upper surface portion. The impurity is not particularly limited and is, for example, oxygen. In the crystal layer, it is more preferable that an average value of oxygen concentration in the upper surface portion is 5 × 10 ¹⁸ cm ⁻³ or less.

  The group III nitride semiconductor manufacturing method of the present invention preferably further includes another group III nitride semiconductor-containing layer forming step of forming another group III nitride semiconductor-containing layer on the crystal layer. In this case, the method for producing a group III nitride semiconductor according to the present invention includes a protective layer removing step of removing the protective layer after the semiconductor crystal layer forming step, and the protective layer removing step includes the protection by thermal etching. Forming the other group III nitride semiconductor-containing layer at a temperature equal to or higher than the thermal etching temperature in the protective layer removing step in the step of forming the other group III nitride semiconductor-containing layer. More preferred.

  In the method for producing a group III nitride semiconductor of the present invention, the underlayer is preferably a layer containing a group III nitride semiconductor.

  In the group III nitride semiconductor manufacturing method of the present invention, a layer made of group III nitride may be formed instead of the protective layer. In this case, the function of the layer formed from the group III nitride is not limited at all, and may not have a function as a protective layer, for example.

  Next, as described above, the method for manufacturing a group III nitride semiconductor device of the present invention is a method for manufacturing a semiconductor device including a group III nitride semiconductor, and the group III nitride is manufactured by the method for manufacturing a semiconductor of the present invention. It is characterized by manufacturing a semiconductor.

  In the method for producing a group III nitride semiconductor device of the present invention, the group III nitride semiconductor device is not particularly limited, but is preferably, for example, a semiconductor laser, a field effect transistor, or a photonic crystal surface emitting laser. For example, the group III nitride semiconductor device is preferably a semiconductor laser, and the crystal layer is more preferably a current confinement layer. Further, for example, it is more preferable that the group III nitride semiconductor element is a field effect transistor, and the crystal layer is a contact layer. In addition, for example, it is more preferable that the group III nitride semiconductor element is a photonic crystal surface emitting laser, and the crystal layer is a photonic crystal layer.

Next, as described above, the group III nitride semiconductor of the present invention includes a crystal layer of a group III nitride semiconductor, the crystal layer is partially removed, the crystal layer includes an impurity, and the crystal The average value of the impurity concentration of the upper surface portion of the layer is equal to or less than the average value of the internal impurity concentration, and is manufactured by the Group III nitride semiconductor manufacturing method of the present invention. The upper surface portion is, for example, a portion from the upper surface of the crystal layer to a depth of 50 nm, and the inside is, for example, a portion other than the upper surface portion. The impurity is not particularly limited and is, for example, oxygen. In the crystal layer, it is more preferable that an average value of oxygen concentration in the upper surface portion is 5 × 10 ¹⁸ cm ⁻³ or less.

  In the group III nitride semiconductor of the present invention, it is preferable that the crystal layer is a layer formed of AlN. The crystal layer preferably includes two or more layers. Furthermore, it is more preferable that the crystal layer includes a lower layer formed of AlN and an upper layer formed of GaN.

  The group III nitride semiconductor of the present invention may further include, for example, another group III nitride semiconductor-containing layer on the crystal layer. The group III nitride semiconductor of the present invention may further include the underlayer. The underlayer is preferably a layer containing a group III nitride semiconductor.

  Next, as described above, the group III nitride semiconductor device of the present invention is manufactured by the method for manufacturing a group III nitride semiconductor device of the present invention, and includes the group III nitride semiconductor of the present invention. To do.

  The group III nitride semiconductor device of the present invention is not particularly limited, and is, for example, a semiconductor laser, a field effect transistor, or a photonic crystal surface emitting laser. For example, the group III nitride semiconductor device of the present invention is preferably a semiconductor laser, and the crystal layer is preferably a current confinement layer. For example, the group III nitride semiconductor device of the present invention is preferably a field effect transistor, and the crystal layer is preferably a contact layer. In addition, for example, the group III nitride semiconductor device of the present invention is preferably a photonic crystal surface emitting laser, and the crystal layer is preferably a photonic crystal layer.

[Embodiment 1]
Next, embodiments of the present invention will be described in more detail. In the following, the method for producing a group III nitride semiconductor of the present invention and the method for producing a group III nitride semiconductor device of the present invention may be collectively referred to as “the manufacturing method of the present invention”.

  The method for producing a group III nitride semiconductor of the present invention is as described above. That is, the group III nitride semiconductor manufacturing method of the present invention is a manufacturing method including the following steps (A) to (D). Hereinafter, for convenience, each step in the method for producing a group III nitride semiconductor of the present invention or each step in the method for producing a group III nitride semiconductor device of the present invention will be described with reference to (A), (B), (C). , (D) or the like may be used for explanation.

(A) Non-crystalline layer forming step of forming a non-crystalline layer of group III nitride on the upper surface of the underlayer (B) Protective layer forming step of forming a protective layer on the upper surface of the non-crystalline layer (C) The non-crystalline layer (D) Formation of a semiconductor crystal layer that is converted into a group III nitride semiconductor crystal layer by crystallizing the amorphous layer by heat treatment in a state where the protective layer is formed. Process

  In the manufacturing method of the present invention, as described above, a protective layer is separately formed on the upper surface of the group III nitride amorphous layer, and in this state, the amorphous layer is heat-treated to convert it to the group III nitride semiconductor crystal layer. . For this reason, pits and irregularities do not occur due to non-uniform concentration of impurities such as oxygen on the surface of the group III nitride amorphous layer. As a result, it is possible to prevent variations in characteristics and lifetime of the group III nitride semiconductor device. That is, according to the manufacturing method of the present invention, it is possible to suppress quality degradation such as generation of pits and irregularities without requiring complicated operations and checks for controlling the impurity concentration, etc. A semiconductor element can be manufactured efficiently. In the present invention, the protective layer is not particularly limited. Preferably, the protective layer functions as a mass transport prevention layer. When the protective layer has a function as a mass transport prevention layer, for example, deterioration of surface flatness of the group III nitride semiconductor crystal layer can be prevented.

  The production method of the present invention is not particularly limited except that the steps (A) to (D) are included, but for example, as follows.

  The cross-sectional view of FIG. 1 schematically shows the steps (A) to (D). 1A shows the amorphous layer forming step (A), FIG. 1B shows the protective layer forming step (B), FIG. 1C shows the etching step (C), FIG. 1D shows the semiconductor crystal layer forming step (D). That is, first, as shown in FIG. 1A, a group III nitride amorphous layer 12 'is formed on the upper surface of the foundation layer 11 (step (A)). Next, as shown in FIG. 1B, a protective layer 13 is formed on the upper surface of the amorphous layer 12 '(the step (B)). Further, as shown in FIG. 1C, a part of the amorphous layer 12 'is removed by etching (the step (C)). As a result, an opening 12A is formed as shown in FIG. In FIG. 1C, the protective layer 13 formed on the upper surface of the removed portion of the amorphous layer 12 ′ is also removed by etching together with a part of the amorphous layer 12 ′. Then, the amorphous layer 12 ′ is heat-treated with the protective layer 13 formed to convert it into the group III nitride semiconductor crystal layer 12 (the step (D)). In this manner, as shown in FIG. 1D, a structure 10 including a group III nitride semiconductor can be manufactured. As shown in the figure, this structure 10 has a group III nitride semiconductor crystal layer 12 and a protective layer 13 stacked in this order on the upper surface of the underlayer 11, and a part of the crystal layer 12 and the protective layer 13 is removed by etching. Thus, an opening 12A is formed.

  In the present invention, when there is a component called X and a component called Y, “Y on X” may be in a state where Y is in direct contact with the upper surface of X, unless otherwise specified. There may be other components or the like between the upper surface of X and Y, and the upper surface of X and Y may not be in direct contact. Similarly, “Y under X” may be in a state where Y is in direct contact with the lower surface of X unless otherwise specified, and there are other components or the like between the lower surface of X and Y. The lower surface of X and Y may not be in direct contact. Further, “Y on the upper surface of X” indicates a state where Y is in direct contact with the upper surface of X. Similarly, “Y on the lower surface of X” indicates a state where Y is in direct contact with the lower surface of X.

  In the present invention, the upper surface of the Group III nitride amorphous layer and the protective layer are in direct contact, and the upper surface of the base layer and the Group III nitride amorphous layer are in direct contact. Further, in the group III nitride semiconductor of the present invention and the group III nitride semiconductor device of the present invention, arbitrary components such as other layers exist above the protective layer and the underlying layer, respectively. It may or may not exist.

  In addition, in the manufacturing method of the present invention, the group III nitride semiconductor of the present invention, and the group III nitride semiconductor device, a state in which a part of the group III nitride amorphous layer or the group III nitride semiconductor crystal layer is removed is For example, the following states are indicated. That is, for example, as shown in FIGS. 1C and 1D, in the removed portion, the group III nitride non-crystalline layer or the group III nitride semiconductor crystal layer is completely removed and a through hole is formed. But it ’s okay. Further, for example, in the removed portion, the lower part of the group III nitride non-crystalline layer or the group III nitride semiconductor crystal layer may be left without being removed. These can be appropriately selected according to, for example, characteristics required for the group III nitride semiconductor device to be manufactured.

  The structure 10 shown in FIG. 1D may be used as it is if it can be used as it is as a group III nitride semiconductor device. For example, the structure 10 shown in FIG. 1D can be used as it is as a field effect transistor by alloying the protective layer 13 with an electrode metal. In this case, the group III nitride semiconductor crystal layer 12 becomes, for example, a contact layer of the field effect transistor.

  Further, the structure 10 shown in FIG. 1D is further processed by steps other than the steps (A) to (D) to manufacture a target group III nitride semiconductor or group III nitride semiconductor device. You may do it. That is, the production method of the present invention may or may not include steps other than the steps (A) to (D). Although it does not restrict | limit especially as processes other than the said process (A)-(D), For example, removal of the protective layer mentioned later, lamination | stacking of another layer, etc. are mentioned. Moreover, steps other than the steps (A) to (D) may be performed before, after or simultaneously with the steps (A) to (D) as necessary.

  The underlayer 11 is not particularly limited, but may be a layer including a group III nitride semiconductor, for example. The underlayer 11 may constitute, for example, a part of the manufactured group III nitride semiconductor or group III nitride semiconductor element. Further, as described above, another layer may or may not exist under the base layer 11. The other layer may or may not constitute a part of the group III nitride semiconductor or group III nitride semiconductor device to be manufactured. The crystal layer 12 is not particularly limited, but is preferably a current confinement layer of a semiconductor laser, for example. The crystal layer 12 may be, for example, a contact layer of a field effect transistor, a photonic crystal layer of a photonic crystal surface emitting laser, or the like.

  In FIG. 1, the protective layer forming step (B) is performed prior to the etching step (C). However, in the manufacturing method of the present invention, the steps (B), (C), and Either may be implemented first. However, for example, the step (B) is preferably performed before the step (C) for reasons described later.

  The production method of the present invention preferably further includes, for example, a step (E) of removing the protective layer after the semiconductor crystal layer forming step (D). Although the said protective layer removal process (E) is not restrict | limited in particular, For example, it is more preferable that it is a process of removing the said protective layer by thermal etching. In addition, if the thermal etching temperature in the protective layer removing step (E) is higher than the heat treatment temperature in the semiconductor crystal layer forming step (D), the step is smoothly performed by the temperature increase after the step (D). Since it can transfer to (E), it is especially preferable. Although the heat processing temperature in the said semiconductor crystal layer formation process (D) is not restrict | limited in particular, For example, it is 500-900 degreeC, Preferably it is 600-800 degreeC, More preferably, it is 650-750 degreeC. In addition, the thermal etching temperature in the protective layer removing step (E) is not particularly limited, but is, for example, 700 to 1300 ° C, preferably 800 to 1200 ° C, and more preferably 900 to 1100 ° C.

  The production method of the present invention preferably further includes, for example, another group III nitride semiconductor-containing layer forming step (F) for forming another group III nitride semiconductor-containing layer on the crystal layer. . The other group III nitride semiconductor-containing layer is not particularly limited, and examples thereof include a p-type cladding layer. Further, when the production method of the present invention includes the other group III nitride semiconductor-containing layer forming step (F), for example, the method further includes the protective layer removing step (E), and then the other group III nitride It is preferable to implement a semiconductor content layer formation process (F). In this case, the temperature in each step is not particularly limited. However, for example, in the step (F), it is more preferable to form the other group III nitride semiconductor-containing layer at a temperature equal to or higher than the thermal etching temperature in the step (E). By doing so, it is possible to smoothly shift from the step (E) to the step (F). However, it is not limited to this, For example, the thermal etching temperature in the said process (E) may be higher than the said other group III nitride semiconductor containing layer formation temperature in the said process (F). The thermal etching temperature in the protective layer removing step (E) is not particularly limited, and is as described above, for example. The heat treatment temperature in the other group III nitride semiconductor-containing layer forming step (F) is not particularly limited, but is, for example, 700 to 1300 ° C, preferably 800 to 1200 ° C, more preferably 900 to 1100 ° C.

The reason why the protective layer forming step (B) is preferably performed before the etching step (C) is, for example, as follows. That is, first, the method for performing the etching step (C) is not particularly limited. For example, a mask such as SiO ₂ is formed on the group III nitride non-crystalline layer as in the general etching method. It is preferable to implement. At this time, if a mask is directly formed on the amorphous layer, elements such as silicon and carbon may remain as impurities on the upper surface of the amorphous layer. If unevenness occurs in the concentration of these residual impurities, the performance of the group III nitride semiconductor device may be deteriorated due to this. For example, when another group III nitride semiconductor-containing layer is formed by the step (F), unevenness occurs in the frequency of occurrence of two-dimensional crystal nuclei on the crystal layer surface due to the distribution of the residual impurity concentration. May cause pits and irregularities. For this reason, in the etching step (C), when a mask such as SiO ₂ is directly formed on the group III nitride non-crystalline layer, residual impurities on the non-crystalline layer are sufficiently removed after the mask is removed. It is preferable to do.

  However, if the protective layer forming step (B) is performed first and then the etching step (C) is performed, etching can be performed by forming a mask on the protective layer. That is, it is possible to avoid forming the mask directly on the group III nitride non-crystalline layer. For this reason, it is possible to prevent impurities derived from the mask from remaining on the group III nitride amorphous layer after the mask removal. Therefore, problems of pits and unevenness due to the impurities can be prevented.

  The etching method in the etching step (C) is not particularly limited, and may be wet etching or dry etching, for example. However, wet etching is preferable because, for example, the etching selectivity between the amorphous layer and the crystalline layer is good and the etching depth is easily controlled. That is, according to wet etching, for example, when the underlayer is a layer formed of a group III nitride semiconductor crystal, undesirable etching of the underlayer is prevented, and the group III nitride formed on the upper surface thereof is prevented. It is easy to selectively etch the amorphous layer.

In the manufacturing method of the present invention, for example, when the crystal layer of the group III nitride semiconductor contains impurities, the average value of the impurity concentration of the upper surface portion of the crystal layer is equal to or less than the average value of the impurity concentration inside the crystal layer (internal It is preferably equal to or smaller than the average value of the impurity concentration. If the average value of the impurity concentration of the upper surface portion of the crystal layer is equal to or less than the average value of the impurity concentration inside the crystal layer, for example, when forming another group III nitride-containing layer on the crystal layer, two-dimensional The occurrence of crystal nuclei (unevenness) is suppressed and pits and irregularities are hardly generated. Further, if the average value of the impurity concentration of the upper surface portion of the crystal layer is equal to or lower than the average value of the impurity concentration inside the crystal layer, the crystal layer opening is embedded with the other group III nitride-containing layer, In this case, the embedding shape is stabilized. For example, by disposing the protective layer on the crystal layer without removing the protective layer until just before forming the other group III nitride-containing layer, contamination by impurities on the upper surface of the crystal layer is extremely effective. Can be prevented. The impurity is not particularly limited and is, for example, oxygen. In the group III nitride crystal layer, if the average value of the oxygen concentration in the upper surface portion is equal to or less than the average value of the internal oxygen concentration, unevenness of oxygen concentration (unevenness) hardly occurs in the upper surface portion. Such an effect is particularly easy to obtain. More preferably, in the crystal layer, the upper surface portion has an oxygen concentration of 5 × 10 ¹⁸ cm ⁻³ or less. When the oxygen concentration of the upper surface portion is 5 × 10 ¹⁸ cm ⁻³ or less, the growth rate of the other group III nitride semiconductor-containing layer is hardly affected by the oxygen concentration distribution, so that the flatness is improved. This is extremely effective for stabilizing the embedded shape of the crystal layer opening embedded portion. In order not to increase the impurity concentration of the upper surface portion of the group III nitride semiconductor crystal layer, for example, the group III nitride amorphous layer is not oxidized, or the etching mask is used as the group III nitride amorphous layer. It is only necessary to prevent impurities from remaining by not forming directly on the substrate.

In the crystal layer, the “upper surface portion” is, for example, a portion from the upper surface of the crystal layer to a depth of 50 nm, preferably a portion from the upper surface to a depth of 30 nm, and more preferably from the upper surface. It is a portion up to a depth of 20 nm. The “inside” is, for example, a portion other than the “upper surface portion”. In the present invention, “oxygen concentration” refers to the concentration of oxygen atoms (the number of oxygen atoms per unit volume), not the concentration of oxygen (O ₂ ) as a single substance, unless otherwise specified. For example, “the average value of the oxygen concentration is 5 × 10 ¹⁸ cm ⁻³ or less” in the crystal layer means that the number of oxygen atoms present in the crystal layer 1 cm ³ is 5 × 10 ¹⁸ or less. Point to. The same applies to the concentration of elements other than oxygen.

  The composition of the crystal layer of the group III nitride semiconductor and the protective layer formed thereon is not particularly limited. The protective layer is preferably a layer formed from a group III nitride. If the protective layer is a layer formed from a group III nitride, for example, in the group III nitride semiconductor device manufacturing process of the present invention, the protective layer does not diffuse as an impurity into the group III nitride semiconductor device. An effect can be obtained. In the production method of the present invention, for example, as described above, a layer made of group III nitride may be formed instead of the protective layer. In the case of forming a layer formed of a group III nitride instead of the protective layer, the function of the layer is not limited at all, and may not have a function as a protective layer, for example.

In the present invention, for example, as described above,
Group III nitride semiconductor wherein the group III nitride semiconductor crystal layer has a composition of In _a Ga _b Al _1-ab N (0 ≦ a <1, 0 ≦ b <1, 0 ≦ a + b <1). Formed from
The protective layer _is formed of a group III nitride having a composition of _{In c Ga d Al 1-c} -d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 <c + d ≦ 1), and,
It is preferable that the In composition ratio a of the crystal layer and the In composition ratio c of the protective layer satisfy at least one of the following mathematical formulas (1) and (2).

a = 0 (1)
a <c (2)

Satisfying at least one of the formulas (1) and (2) means that the In composition ratio of the group III nitride semiconductor crystal layer is zero or smaller than the In composition ratio of the protective layer. Means. With this composition, for example, when the crystal layer and the protective layer formed thereon are heated together, the latter is more easily evaporated, and the latter can be selectively removed by thermal etching (see above). Step (E)). Note that when thermal etching is performed, it is preferable to sufficiently perform heat treatment until impurities derived from the protective layer do not remain on the upper surface of the crystal layer. In this way, for example, when another group III nitride semiconductor-containing layer is formed on the crystal layer (step (F)), the problem of pits and unevenness due to the impurities is also prevented. can do. Further, since the crystal layer is difficult to be thermally etched, the thickness of the crystal layer and the embedded shape of the opening embedded portion are also stabilized.

The protective layer has a higher thermal etching rate if it is made of a group III nitride having a composition of In _x Ga _1-x N (0 ≦ x ≦ 1), and particularly if it is made of InN. The thermal etching rate is increased. Since the thermal etching rate of the protective layer is high, the removal efficiency of the protective layer by thermal etching is further improved, and the removal efficiency of the protective layer-derived impurities is further increased. In addition, when the thermal etching rate of the protective layer is high, the thermal etching selectivity (thermal etching rate selection ratio) is further increased. When the thermal etching selectivity is high, the crystal layer is more difficult to be thermally etched, and the layer thickness of the crystal layer and the embedded shape of the opening embedded portion are further stabilized. In addition, when the crystal layer is made of AlN, it is particularly difficult to perform thermal etching, so that the layer thickness of the crystal layer and the embedded shape of the opening embedded portion are particularly stable. The crystal layer may be, for example, GaN, AlGaInN mixed crystal or the like other than AlN.

  In the production method of the present invention, the composition of the group III nitride amorphous layer is not particularly limited, but may be the same as the composition of the group III nitride semiconductor crystal layer, for example. This is because if the composition of the group III nitride amorphous layer is crystallized as it is, it can be converted into the group III nitride semiconductor crystal layer.

  In the production method of the present invention, the group III nitride non-crystalline layer or the group III nitride semiconductor crystal layer obtained by crystallizing it in the step (D) may be a single layer. The layer more than the layer may be included. That is, for example, two or more Group III nitride amorphous layers are formed in the step (A), and a protective layer is formed on the two or more amorphous layers in the step (B). In C), the two or more amorphous layers may be etched together, and in the step (D), the two or more amorphous layers may be collectively converted into a crystalline layer. By making the amorphous layer (converted into a crystalline layer in the step (D)) into two or more layers, the quality of the group III nitride semiconductor device can be further improved. Specifically, for example, the variation in the width of the opening formed by etching and the variation in the layer thickness of the other group III nitride semiconductor-containing layer formed on the opening in the step (F) are further suppressed. It is also possible to obtain effects such as. In the case where the amorphous layer or the crystalline layer is two or more layers, the composition is not particularly limited. For example, the amorphous layer or the crystalline layer may include a lower layer formed of AlN and an upper layer formed of GaN. For example, the non-crystalline layer or the crystalline layer may be composed of only a lower layer made of AlN and an upper layer made of GaN, or may appropriately include other layers.

In each constituent element such as the crystal layer and the protective layer in the present invention, for example, “formed of a group III nitride having a composition of In _x Ga _1-x N (0 ≦ x ≦ 1)” As long as the objects and effects of the present invention can be achieved, elements (impurities) other than In, Ga, and N may be included. The same applies to the case where each of the components has a composition other than In _x Ga _1-x N (0 ≦ x ≦ 1). Further, similarly, each of the above-described constituent elements, for example, “formed from InN” includes elements (impurities) other than In and N as long as the object and effect of the present invention can be achieved. good. The same applies to the case where each of the constituent elements is formed of other than InN. In the group III nitride semiconductor crystal layer, as described above, the average value of the impurity concentration of the upper surface portion is equal to or less than the average value of the internal impurity concentration (is equal to or more than the average value of the internal impurity concentration). Small). When each other component is formed of a group III nitride semiconductor, impurities may be appropriately doped from the viewpoint of conductivity, insulation, etc., and conversely, impurities should be reduced as much as possible. Also good.

  Next, as described above, the group III nitride semiconductor device of the present invention is a group III nitride semiconductor device manufactured by the manufacturing method of the present invention, and includes a crystal layer of a group III nitride semiconductor, A part of the layer is removed, and the average value of the impurity concentration of the upper surface portion of the crystal layer is equal to or less than the average value of the internal impurity concentration. That is, the group III nitride semiconductor device of the present invention is manufactured by the manufacturing method of the present invention, so that the group III nitride semiconductor crystal layer is partially removed, and the impurity on the upper surface of the crystal layer It is possible to obtain a configuration in which the average value of the concentration is equal to or less than the average value of the internal impurity concentration. However, as long as the group III nitride semiconductor device of the present invention has this configuration, the manufacturing method is not particularly limited, and any method may be used. However, it is preferable to manufacture by the manufacturing method of the present invention from the viewpoint of the quality improvement described above. Further, as described above, the production method of the present invention is not particularly limited except that it includes the steps (A) to (D). That is, the configuration of the group III nitride semiconductor device manufactured by the manufacturing method of the present invention is not particularly limited, and any configuration may be used. However, the group III nitride semiconductor crystal layer is partially removed, and has the above-described configuration in which the average impurity concentration in the upper surface portion of the crystal layer is equal to or less than the average impurity concentration in the crystal layer. It is preferable.

In the crystal layer of the group III nitride semiconductor device of the present invention, the “upper surface portion” is, for example, a portion from the upper surface of the crystal layer to a depth of 50 nm, preferably a portion from the upper surface to a depth of 30 nm. More preferably, it is a portion from the upper surface to a depth of 20 nm. The “inside” is, for example, a portion other than the upper surface portion. The impurity is not particularly limited and is, for example, oxygen. Moreover, in the crystal layer, the average value of the oxygen concentration in the upper surface portion is preferably 5 × 10 ¹⁸ cm ⁻³ or less.

  Although the group III nitride semiconductor crystal layer is not particularly limited, for example, a current confinement layer of a semiconductor laser is preferable. The composition of the crystal layer is not particularly limited, but is particularly preferably a layer formed from AlN. When the crystal layer is made of AlN, an effect such as excellent current confinement layer can be obtained due to high insulation.

  In addition, the group III nitride semiconductor device of the present invention may appropriately include components other than the group III nitride semiconductor crystal layer. Specifically, for example, another group III nitride semiconductor-containing layer may be further included on the crystal layer. For example, when manufactured by the manufacturing method of the present invention, the foundation layer may further be included as a part of the group III nitride semiconductor device of the present invention. The underlayer may be, for example, a layer containing a group III nitride semiconductor.

  Examples of the group III nitride semiconductor of the present invention, the group III nitride semiconductor device of the present invention, or the group III nitride semiconductor or group III nitride semiconductor device manufactured by the manufacturing method of the present invention are as follows. You may have the structure. That is, the Group III nitride semiconductor or Group III nitride semiconductor element includes, for example, a first layer (for example, the base layer), a second layer (the “Group III nitride semiconductor crystal layer”), and a third layer. (The “other group III nitride semiconductor-containing layer”) at least, and the first, second and third layers may each include a group III nitride semiconductor. The second layer (the “Group III nitride semiconductor crystal layer”) is provided on the first layer (for example, the base layer), and a part thereof is removed. The state in which a part of the second layer is removed may be a state in which the second layer is completely removed and a through hole is formed in the removed portion, as described above. The lower layer may be left without being removed. The third layer (the “other group III nitride semiconductor-containing layer”) is provided on the second layer and the opening. The opening is embedded by the third layer to form an opening embedded portion. In the opening buried portion, the third layer may or may not be in contact with the upper surface of the first layer, for example, depending on the characteristics of the target semiconductor element. However, this configuration is merely an example, and the group III nitride semiconductor of the present invention, the group III nitride semiconductor device of the present invention, or the group III nitride semiconductor or group III nitride produced by the production method of the present invention The semiconductor element is not limited to this configuration. The group III nitride semiconductor device having such a configuration is not particularly limited, and examples thereof include an inner stripe type GaN-based laser and a photonic crystal surface emitting laser.

  The layer immediately below the group III nitride semiconductor crystal layer (the “underlying layer” or “first layer”) and the layer immediately above (the “other group III nitride semiconductor-containing layer” or “third layer”) ) Is also formed from a group III nitride semiconductor, the group III nitride semiconductor crystal layer or amorphous layer does not diffuse as an impurity in the manufacturing process of the group III nitride semiconductor device. In addition, if the first layer and the third layer are formed of a group III nitride semiconductor, the amorphous layer can be crystallized by heat treatment (the step (D)) relatively easily. it can. Furthermore, as described above, the protective layer is also formed of a group III nitride so that the protective layer does not diffuse as an impurity. This also makes it possible to remove the protective layer by heat treatment (the step (E)) relatively easily.

  The group III nitride semiconductor device of the present invention or the group III nitride semiconductor device manufactured by the manufacturing method of the present invention is, for example, a semiconductor laser, a field effect transistor, or a photonic crystal surface emitting laser, but is not limited thereto. Instead, any group III nitride semiconductor device may be used.

[Embodiment 2]
Next, another embodiment of the present invention will be described. Specifically, in this embodiment, an example of a semiconductor laser and a manufacturing method thereof will be described. In this embodiment, an example of an inner stripe type semiconductor laser and a manufacturing method thereof will be described in detail.

  FIG. 2 is a schematic view showing an example of the production of a group III nitride semiconductor device by the production method of the present invention. The manufacturing process proceeds in the order shown in FIGS. 4A to 4D to manufacture the group III nitride semiconductor device shown in FIG. FIG. 2A is a cross-sectional view in the active layer growth step. FIG. 2B is a view showing a cross section in the step of forming the opening (stripe). FIG. 2C is a cross-sectional view showing a process of regrowing the p-type cladding layer. FIG. 2D is a cross-sectional view showing the group III nitride semiconductor device completed through the electrode formation step. The group III nitride semiconductor device shown in the figure is a semiconductor laser.

  First, the semiconductor laser (group III nitride semiconductor device) shown in FIG. This semiconductor laser is the group III nitride semiconductor device of the present invention. The semiconductor laser can be manufactured according to the manufacturing method of the present invention, as will be described later. As shown, the semiconductor laser 100 includes a first layer (p-type GaN guide layer 107), a second layer (current confinement layer 114), and a third layer (group III nitride semiconductor layers). The p-type cladding layer 108) is a main component. The first layer (p-type GaN guide layer 107) corresponds to the “underlayer”. The second layer (current confinement layer 114) corresponds to the “crystal layer of group III nitride semiconductor”. The third layer (p-type cladding layer 108) corresponds to the “other group III nitride semiconductor-containing layer”. The second layer (current confinement layer 114) is provided on the first layer (p-type GaN guide layer 107), and an opening embedded portion 114A 'is formed. The third layer (p-type cladding layer 108) is provided on the second layer (current confinement layer 114) and the opening buried portion 114A '. On the opening embedded portion 114A ′, the third layer (p-type cladding layer 108) is embedded in the opening embedded portion 114A ′, and the third layer (p-type cladding layer 108) is the first layer (p-type GaN). Guide layer 107) is in contact with the upper surface. That is, the interface between the third layer (p-type cladding layer 108) and the first layer (p-type GaN guide layer 107) is present at the bottom of the opening buried portion 114A '. The interface between the third layer (p-type cladding layer 108) and the first layer (p-type GaN guide layer 107) is the second layer (current confinement layer 114) and the first layer (p-type GaN guide layer 107). 107) and substantially in the same plane. Further, the upper surface of the p-type cladding layer 108 (surface on the p-type contact layer 109 side described later) is substantially flat. The average value of the impurity concentration of the upper surface portion (interface with the third layer on the second layer) of the second layer (current confinement layer 114) is equal to or equal to the average value of the impurity concentration inside the second layer. It is as follows.

  Next, the overall configuration of the semiconductor laser 100 will be described. As shown in FIG. 2 (d), the semiconductor laser 100 has layers 101, 102, 103, 104, 105, 106, 107, 114, 108 and 109 in order from the bottom to the top. Are stacked. More specifically, the semiconductor laser 100 includes an n-type GaN substrate 101 as a semiconductor substrate, a Si-doped n-type GaN layer 102 provided on the n-type GaN substrate 101, and a Si-doped n-type GaN layer 102. An n-type cladding layer 103 provided, an n-type optical confinement layer 104 provided on the n-type cladding layer 103, and a three-period multiple quantum well (MQW) as an active layer provided on the n-type optical confinement layer 104 ) Layer 105, cap layer 106 provided on three-period multiple quantum well (MQW) layer 105, p-type GaN guide layer 107 provided on cap layer 106, and p-type GaN guide layer 107. A current confinement layer 114, a p-type cladding layer 108 provided on the current confinement layer 114, and a p-type contact layer 109 provided on the p-type cladding layer 108. . The first layer (underlying layer, p-type GaN guide layer 107), the second layer (group III nitride semiconductor crystal layer, current confinement layer 114), and the third layer (other group III) which are the main constituent elements The positions and bonding relationships of the nitride semiconductor-containing layer and the p-type cladding layer 108 are as described above. Further, an n-electrode 112 is provided on the lower surface (back surface) side of the n-type GaN substrate 101, and a p-electrode 113 is provided on the p-type contact layer 109.

As described above, the semiconductor layers 102, 103, 104, 105, 106, 107, 114, 108, and 109 are stacked in this order on the front surface (upper surface) side of the n-type GaN substrate 101, and on the rear surface (lower surface) side. Is provided with an n-electrode 112. The Si-doped n-type GaN layer 102 has, for example, a Si concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 1 μm. The n-type cladding layer 103 is a layer composed of, for example, Si-doped n-type Al _0.05 Ga _0.95 N, and has a Si concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 2 μm, for example. The n-type optical confinement layer 104 is made of, for example, Si-doped n-type GaN, and has an Si concentration of 4 × 10 ¹⁷ cm ⁻³ and a thickness of 0.1 μm, for example. Further, the three-period multiple quantum well (MQW) layer 105 includes, for example, an In _0.1 Ga _0.9 N (eg, 3 nm thick) well layer and an undoped GaN (eg, 10 nm thick) barrier layer. Composed. The cap layer 106 is made of, for example, Mg-doped p-type Al _0.2 Ga _0.8 N. The p-type GaN guide layer 107 is made of, for example, Mg-doped p-type GaN, and has an Mg concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 0.1 μm, for example. The composition and thickness of the current confinement layer 114 and the p-type cladding layer 108 will be described later. The p-type contact layer 109 is a layer formed from Mg-doped p-type GaN (for example, an Mg concentration of 2 × 10 ²⁰ cm ⁻³ or less and a thickness of 0.02 μm). A p-electrode 113 is provided on the p-type contact layer 109 as described above.

  Next, a method for manufacturing this semiconductor laser (group III nitride semiconductor device) 100 will be described with reference to FIGS.

  Prior to the implementation of the steps (A) to (F) of the present invention, the “underlayer” and other layers are laminated on a substrate. That is, first, on an n-type GaN substrate 101, a Si-doped n-type GaN layer 102, an n-type cladding layer 103, an n-type optical confinement layer 104, a three-period multiple quantum well (MQW) layer 105, a cap layer 106, a p-type The GaN guide layer 107 is laminated by, for example, a metal organic chemical vapor deposition method (hereinafter referred to as MOVPE method). As described above, the p-type GaN guide layer 107 becomes the “underlayer”.

  Next, as shown in FIG. 2A, a group III nitride amorphous layer 114 ′ is formed on the p-type GaN guide layer 107 (underlying layer) (the step (A)), and further, A protective layer 115 is formed (the step (B)).

The composition of the group III nitride amorphous layer 114 ′ is not particularly limited. As described above, for example, In _a Ga _b Al _1-ab N (0 ≦ a <1, 0 ≦ b <1, 0 ≦ a + b < It is preferably formed from a group III nitride semiconductor having the composition of 1). Is not particularly limited composition of the protective layer 115 has previously described, for example, the composition of _{In c Ga d Al 1-c} -d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 <c + d ≦ 1) It is preferably formed from a group III nitride semiconductor. As described above, the In composition ratio of the amorphous layer 114 ′ is preferably zero or smaller than the In composition ratio of the protective layer 115. For example, the amorphous layer 114 ′ may be an AlN layer having a thickness of 0.1 μm, for example, and the protective layer 115 may be InN having a thickness of 0.01 μm, for example.

  The amorphous layer 114 ′ (for example, amorphous AlN) and the protective layer 115 (for example, amorphous InN) are deposited at a low temperature of 600 ° C. or less by, for example, a metal organic chemical vapor deposition method (hereinafter, MOVPE method). For example, if a single crystal AlN layer is formed on the p-type GaN guide layer 107 at a high temperature by the MOVPE method, cracks are likely to occur in the AlN layer during deposition. In the present invention, the group III nitride semiconductor layer (AlN or the like) is formed as an amorphous layer on the base layer and crystallized after the etching, so that such a crack hardly occurs and the etching is easy. is there.

  The deposition temperature of the protective layer 115 is not particularly limited, and may be set higher than the deposition temperature of the amorphous layer 114 ′, for example. However, if the deposition temperature of the protective layer 115 is too high, the crystallization of the amorphous layer 114 ′ (for example, amorphous AlN) proceeds and the etching rate in the next etching step (C) may decrease. Therefore, the deposition temperature of the protective layer 115 is preferably 600 ° C. or lower as described above, for example.

Further, a mask (not shown) such as SiO ₂ is formed on the protective layer 115 (for example, amorphous InN). Then, as shown in FIG. 2B, the protective layer 115 and the amorphous layer 114 ′ in the region not covered with the mask are removed by etching, and an opening 114A is provided (the step (C)). The etching method is not particularly limited, but can be performed by, for example, photolithography and wet etching. The etching solution is not particularly limited, and a general etching solution such as a phosphoric acid-containing solution can be used as appropriate. The etching solution may be, for example, a 90 ° C. solution in which phosphoric acid and sulfuric acid are mixed at a volume ratio of 1: 1. The etching mask is not particularly limited, but a material that is hardly damaged by an etching solution or the like is preferable. Examples of the etching mask include SiNx and organic substances including a resist other than SiO ₂ .

Next, the laminated body (semiconductor laser wafer) shown in FIG. 2B is again put into the MOVPE furnace, and the substrate temperature is gradually raised. During the temperature increase, the group III nitride amorphous layer 114 ′ is converted into a crystalline layer (current confinement layer) 114 (step (D)). At this time, since the surface of the current confinement layer 114 is protected by the protective layer 115, deterioration of surface flatness due to mass transport or the like can be prevented. After the current confinement layer 114 has been crystallized to some extent, when the temperature is further raised to the growth temperature of the p-type cladding layer 108, the protective layer 115 evaporates (the protective layer removing step (E)). As described above, the protective layer 115 is removed by thermal etching before the regrowth of the p-type cladding layer 108 is started, so that an extremely clean surface of the current confinement layer 114 appears. Since the regrowth of the p-type cladding layer 108 can be performed thereon, an extremely flat p-type cladding layer 108 having no pits and irregularities can be obtained. For example, after the current confinement layer 114 is crystallized, it is effective to improve the thermal etching efficiency and reduce the residual impurity concentration by introducing H ₂ gas before starting the regrowth of the p-type cladding layer. .

Further, as shown in FIG. 2C, a p-type cladding layer 108 is laminated on the surface of the clean current confinement layer 114 from which the protective layer 115 has been completely removed (the other group III nitride semiconductor-containing layer forming step). (F)) Further, a p-type contact layer 109 is laminated. The p-type cladding layer 108 is laminated (regrown) so as to fill the opening 114A and form the opening buried portion 114A ′. The p-type cladding layer 108 is a layer formed from, for example, Mg-doped p-type Al _0.05 Ga _0.95 N, and has an Mg concentration of 1 × 10 ¹⁹ cm ⁻³ and a thickness of 0.5 μm, for example. .

  Thereafter, as shown in FIG. 2D, a p-electrode 113 is provided on the p-type contact layer 109, and an n-electrode 112 is provided on the back surface (lower surface) of the n-type GaN substrate 101. Thereby, the semiconductor laser 100 can be obtained.

In such a semiconductor laser 100, for example, there are few residual impurities such as silicon, oxygen, and carbon at the interface between the current confinement layer 114 and the p-type cladding layer 108 and the average value of the impurity concentration inside the current confinement layer 114 is below. It is preferable. More specifically, for example, the average value of the oxygen concentration, the average value of the silicon concentration, and the average value of the carbon concentration in the upper surface portion of the electrical confinement layer are all preferably about 5 × 10 ¹⁸ cm ⁻³ or less. According to this, when the p-type cladding layer 108 is regrown on the surface of the current confinement layer 114, unevenness (unevenness) in the frequency of occurrence of two-dimensional crystal nuclei is suppressed, pits and irregularities are hardly generated, and variation in thickness is suppressed. Thus, a very flat p-type cladding layer 108 can be obtained. Since the p-type cladding layer 108 is very flat, variation in the operating voltage of the semiconductor laser 100 can be prevented. Furthermore, since variations in the thickness and embedded shape of the p-type cladding layer 108 in the vicinity of the opening embedded portion 114A ′ can be prevented, deviation from the design of the optical confinement structure can be prevented, and characteristics such as threshold values and kink levels can be prevented. Variations can be suppressed.

  In the inner stripe type GaN laser, particularly when a pit is generated in the vicinity of the AlN opening buried portion, unconsumed growth raw material is supplied to the peripheral portion by surface diffusion or the like. For this reason, the layer thickness of the AlN opening burying part partially increases, which causes a variation in the filling shape of the AlN opening burying part. If the embedded shape of the AlN opening embedded portion varies, the LD characteristics such as the operating voltage deteriorate, and the laser beam emission angle and the emission pattern change. It may get worse. However, according to the present invention, these problems can be effectively solved. The solution of these problems by the present invention is effective both in the inner stripe type laser other than the GaN laser and in the case where the current confinement layer is formed of a material other than AlN. Furthermore, according to the present invention, in the inner stripe type laser, it is also possible to suppress an increase in element resistance by stabilizing the embedding shape of the portion where the current confinement layer is partially removed (opening embedding portion). . If the increase in the element resistance of the inner stripe laser is suppressed, the heat generation of the element can also be suppressed, thereby suppressing the carrier overflow and the like. Therefore, according to the present invention, it is possible to increase the carrier injection efficiency of the inner stripe laser, thereby obtaining the effect of increasing the output of the inner stripe laser.

  The current confinement layer 114 is particularly preferably an AlN layer as described above. By using the current confinement layer 114 as a binary compound, a flat surface can be easily obtained when crystallized as compared with a multi-element mixed crystal. Moreover, since AlN has the largest band gap and the smallest refractive index among the group III nitride semiconductors, a current confinement layer having high insulation performance and sufficient optical confinement performance can be realized.

The protective layer 115 is particularly preferably an InN layer as described above. InN decomposes most easily among group III nitride semiconductors and has a very high thermal etching rate in an H ₂ atmosphere. For this reason, when the protective layer 115 is an InN layer, when the temperature is raised to the regrowth temperature of the p-type cladding layer 108 after the crystallization process of the current confinement layer 114, it is completely introduced by introducing H ₂ into the carrier gas. Can be re-evaporated. Accordingly, regrowth can be performed on the surface of the very clean current confinement layer 114, so that the p-type cladding layer 108 with extremely good flatness can be formed.

  Further, the width of the opening embedded portion (stripe) 114A ′ is not particularly limited, but is preferably 2 μm or less, for example. As a result, the p-type cladding layer 108 can be easily obtained by embedding the opening 114A so as to be buried when the opening 114A is filled, and having a smaller surface thickness variation and a flat surface.

  In the present invention, the structure of the semiconductor laser is not particularly limited, and any structure may be used. In the case of a semiconductor laser having a current confinement layer, that is, an inner stripe type semiconductor laser, for example, an n-type clad layer, an active layer, a current confinement layer, and a p-type clad layer are laminated in this order on a substrate. A part of the layer may be removed, and the removed portion may be filled with the p-type cladding layer to form an opening buried portion, and electrodes may be formed under the substrate and on the p-type cladding layer, respectively. The substrate is, for example, an n-type substrate. The electrode under the substrate is, for example, an n electrode. The electrode on the p-type cladding layer is, for example, a p-electrode. Each of the layers may be in direct contact with no other component between them, or another component such as another layer may further exist between the layers. An example of the structure of such an inner stripe type semiconductor laser is the structure shown in FIG. Furthermore, in the present invention, the structure of the inner stripe type semiconductor laser is not limited to this, and any structure may be used.

[Embodiment 3]
Next, still another embodiment of the present invention will be described. Specifically, in the present embodiment, an example of a field effect transistor (hereinafter referred to as FET) and a manufacturing method thereof will be described.

  In the present invention, when the group III nitride semiconductor device is an FET, its structure is not particularly limited. The structure of the FET may be, for example, the structure described in the first embodiment (FIG. 1D) or any other structure. For example, the FET may have a structure described below in the present embodiment.

FIG. 5 schematically shows a cross-sectional structure of the FET according to this embodiment. As shown in the figure, the FET 400 includes a substrate 401, a buffer layer 402, a carrier traveling layer 403, a spacer layer 404 and a carrier supply layer 405, which are stacked in this order from the bottom to the top. An electrode 407, a drain electrode 408, a gate electrode 409, and a contact layer 410 are included. One contact layer 410 is disposed on each of the left and right sides of the carrier supply layer 405. A source electrode 407 is disposed on the left contact layer 410, and a drain electrode 408 is disposed on the right contact layer 410. In the central portion between the left and right contact layers 410, the contact layer 410 is removed to form an opening 410A, and the upper surface of the carrier supply layer 405 is exposed. The shot layer 406 is disposed on the carrier layer 405 in the opening 410A, and the gate electrode 409 is disposed on the shot layer 406. That is, the FET shown in the figure employs a so-called wide recess structure in which a contact layer 410 is provided immediately below the source electrode 407 and the drain electrode 408. The material of each layer is not particularly limited. For example, a c-plane ((0001) plane) sapphire substrate is used as the substrate 401, the AlN low-temperature growth buffer layer (film thickness is 20 nm) as the buffer layer 402, and the GaN operation as the carrier running layer 403. Layer (thickness 1500 nm), AlGaN spacer layer (thickness 5 nm) as the spacer layer 404, and AlGaN layer (Al composition ratio 0.2, thickness 20 nm, Si addition amount 5 × 10 ¹⁸ cm ⁻³ ) as the carrier supply layer 405 Alternatively, InGaN (In composition ratio 0.05, film thickness 10 nm) may be used as the Schottky layer 406, and a GaN layer (film thickness 20 nm) may be used as the contact layer 410.

  For example, in a planar type transistor, a contact layer directly under a source / drain electrode is formed so as to extend under a gate electrode. Therefore, if the carrier concentration under the source / drain electrodes is increased to reduce the contact resistance, the carrier concentration under the gate electrode also increases at the same time, and it may be difficult to obtain the element characteristics as designed. is there. On the other hand, when the wide recess structure is adopted, the contact layer directly under the source / drain electrode does not exist under the gate electrode, and the carrier concentration of the contact layer can be freely set independently of the layer under the gate electrode. . For this reason, the conductivity of the contact layer can be improved and the contact resistance can be effectively reduced. Further, by adopting a wide recess, electric field concentration under the gate electrode can be relaxed, and the breakdown voltage characteristics and the like of the transistor can be improved.

In the present embodiment, the method for forming each layer in FIG. 5 is not particularly limited, but for example, it can be formed by a metal organic vapor phase epitaxy (MOVPE) method as in the second embodiment. In this case, the growth temperature by the MOVPE method is not particularly limited, but is as follows, for example.
Buffer layer 401: 400 to 500 ° C. (for example, 450 ° C.)
Spacer layer 404, carrier supply layer 405 (AlGaN layer): 1040 to 1100 ° C. (for example, 1080 ° C.)
Schottky layer 406 (InGaN layer): 800 to 900 ° C. (for example, 840 ° C.)
Contact layer 410 (GaN layer): 200 to 500 ° C. (eg, 350 ° C.)

  More specifically, the FET shown in FIG. 5 can be manufactured as follows, for example. That is, first, the buffer layer 402, the carrier traveling layer 403, the spacer layer 404, and the carrier supply layer 405 are laminated on the substrate 401 in this order from the bottom to the top. Next, the carrier supply layer 405 is used as a base layer, and a non-crystalline layer of group III nitride is formed on the entire top surface (the amorphous layer forming step (A)). This amorphous layer becomes a precursor layer of the contact layer 410. The method for forming the non-crystalline layer (contact layer 410 precursor layer) is not particularly limited. For example, the non-crystalline layer of GaN is grown at a low temperature at a film forming temperature of 200 to 500 ° C., preferably 300 to 400 ° C. The non-crystalline layer (contact layer 410 precursor layer) may be used. Next, a protective layer (not shown) is formed on the entire upper surface of the amorphous layer (contact layer 410 precursor layer) (protective layer forming step (B)). The material of the protective layer is not particularly limited, but is preferably formed of a group III nitride. For example, from the viewpoint of thermal etching selectivity, the same material as that described in the second embodiment is more preferable.

  Next, the amorphous layer (contact layer 410 precursor layer) and a part of the protective layer are removed by etching to form an opening 410A (the etching step (C)). The etching method is not particularly limited, and wet etching or dry etching may be used. For example, photolithography (a method of applying a photoresist and forming an etching pattern by exposure and development) and a method using wet etching are preferable. As the etching solution, a phosphoric acid-containing solution is preferable, and other acids such as sulfuric acid may be appropriately mixed. The phosphoric acid content is not particularly limited, but is, for example, 10 to 90% on a volume basis with respect to the entire etching solution. After the etching, with the protective layer formed, the amorphous layer (contact layer 410 precursor layer) is heat-treated to convert it into a group III nitride semiconductor crystal layer (contact layer 410) (the semiconductor crystal layer forming step) (D)). The temperature of the heat treatment is not particularly limited, but is 700 to 1300 ° C., preferably 900 to 1200 ° C., for example, when the amorphous layer (contact layer 410 precursor layer) is GaN.

  For example, when the opening is formed by etching the amorphous layer (contact layer 410 precursor layer) without forming the protective layer, the amorphous layer (contact layer 410 precursor layer) is formed during the opening forming step. The surface may be contaminated with impurities. When the impurity contamination occurs, the impurity concentration varies on the upper surface of the contact layer of the FET, which may cause problems such as an increase or variation in contact resistance. However, according to the present invention, those problems caused by the impurity concentration can be solved, and a wide recess type FET having excellent quality can be manufactured.

  Then, after forming the contact layer 410 by the semiconductor crystal layer forming step (D), the protective layer is removed by thermal etching (the protective layer removing step (E)). The temperature of the thermal etching is not particularly limited, but may be the same as that of the second embodiment, for example. Further, a shot layer 406 is formed on the upper surface of the carrier supply layer 405 in the opening 410A. Then, a source electrode 407 is formed on the upper surface of the left contact layer 410, a drain electrode 408 is formed on the upper surface of the right contact layer 410, and a gate electrode 409 is formed on the upper surface of the Schottky layer 406, respectively. Field effect transistor) can be manufactured.

Although the method for forming the shot layer 406 is not particularly limited, for example, after forming a group III nitride semiconductor layer (such as an InGaN layer) so as to fill all the openings 410A, unnecessary portions are removed, and the remaining portions are replaced. The shot layer 406 may be used. A method for removing the unnecessary portion is not particularly limited, and for example, dry etching (ECR method) using Cl ₂ gas may be used. The formation method of the source electrode 407, the drain electrode 408, and the gate electrode 409 is not particularly limited, but is as follows, for example. That is, first, after the formation of the shot layer 406, Ti / Al (Ti layer thickness 10 nm, Al layer thickness 200 nm) is formed on the upper surfaces of the left and right contact layers 410 by electron gun evaporation. . A source electrode 407 and a drain electrode 408 are formed using the first metal layer. Ni / Au (Ni layer thickness: 10 nm, Au layer thickness: 200 nm) is formed as the second metal on the upper surface of the shot layer 406 by electron gun evaporation, and the gate electrode 409 is formed by lift-off.

  A wide recess type FET as shown in FIG. 5 has better contact layer conductivity than a planar type FET. For this reason, according to the wide recess type FET, for example, it is possible to obtain such effects that the contact resistance is remarkably reduced, the electric field concentration under the gate electrode is effectively relaxed, and the withstand voltage characteristics are improved. Further, as described above, the wide recess type FET is manufactured by the method for manufacturing a group III nitride semiconductor device of the present invention, or the wide recess type FET is the group III nitride semiconductor device of the present invention. It is possible to solve problems such as an increase and variation in contact resistance caused by the impurity concentration.

  In the present invention, the structure of the field effect transistor (FET) is not particularly limited. In the case of a wide recess type FET, for example, a contact layer is formed on an underlayer, a part of the contact layer is removed to form an opening, and an electrode is formed on the contact layer. . That is, in FIG. 5, the carrier supply layer 405 and the layer below it may be replaced with other arbitrary structures. The shot layer 406 and the gate electrode 409 may be replaced with other arbitrary structures or may be omitted. Further, in the present invention, the structure of the wide recess type FET is not limited to this, and any structure may be used.

[Embodiment 4]
Next, still another embodiment of the present invention will be described. In the present embodiment, specifically, an example of a photonic crystal surface emitting laser will be described.

  FIG. 6 schematically shows a cross-sectional structure of the photonic crystal surface emitting laser of the present embodiment. As shown in the figure, in this photonic crystal surface emitting laser 500, an n-type cladding layer 502, an active layer 503, a photonic crystal layer 505, and a p-type cladding layer 508 are laminated on a substrate 501 in this order. A portion of the photonic crystal layer 505 is removed by etching, and a large number of opening embedded portions 505A 'are regularly formed. The opening buried portion 505A ′ is buried with a p-type cladding layer 508. An electrode 512 is formed under the substrate 501. An electrode 513 is formed on the p-type cladding layer 508. The substrate 501 is, for example, an n-type substrate. The electrode 512 under the substrate 501 is, for example, an n electrode. The electrode 513 on the p-type cladding layer 508 is, for example, a p-electrode.

  In FIG. 6, the opening buried portion 505 </ b> A ′ is left without completely removing the lower portion of the photonic crystal layer 505. The active layer 503 and the p-type cladding layer 508 are not in direct contact with each other and are separated by the photonic crystal layer 505. However, the structure of the photonic crystal surface emitting laser of the present invention is not limited to this. For example, the photonic crystal layer is completely removed in the opening embedded portion to form a through hole, and the upper surface of the active layer (underlayer) is formed. The p-type cladding layer may be in direct contact.

  In the present embodiment, the material, thickness, and the like of each layer in FIG. 6 are not particularly limited, and can be appropriately selected according to, for example, an existing photonic crystal surface emitting laser. The formation method of each layer in FIG. 6 is not particularly limited, but can be formed by, for example, a metal organic vapor phase epitaxy (MOVPE) method as in the above embodiments. The growth temperature by the MOVPE method is not particularly limited and can be set as appropriate.

  More specifically, the photonic crystal surface emitting laser shown in FIG. 6 can be manufactured as follows, for example. That is, first, the n-type cladding layer 502 and the active layer 503 are laminated on the substrate 501 in this order. Next, the active layer 503 is used as a base layer, and a non-crystalline layer of group III nitride is formed on the entire top surface (the amorphous layer forming step (A)). This amorphous layer becomes a precursor layer of the photonic crystal layer 505. The method for forming the non-crystalline layer (photonic crystal layer 505 precursor layer) is not particularly limited. For example, it may be the same as the non-crystalline layer of GaN in each of the embodiments. Next, a protective layer (not shown) is formed on the entire upper surface of the non-crystalline layer (photonic crystal layer 505 precursor layer) (the protective layer forming step (B)). The material of the protective layer is not particularly limited, but is preferably formed from a group III nitride. The material of the protective layer is more preferably the same material as described in the second embodiment, for example, from the viewpoint of thermal etching selectivity.

  Next, the amorphous layer (photonic crystal layer 505 precursor layer) and a part of the protective layer are removed by etching to form an opening (the etching step (C)). The etching method is not particularly limited, and wet etching or dry etching may be used. For example, a method using photolithography and wet etching is preferable. An etching solution and other etching conditions are not particularly limited, but may be the same as those in the above embodiments, for example. After the etching, with the protective layer formed, the amorphous layer (photonic crystal layer 505 precursor layer) is heat-treated to convert it into a group III nitride semiconductor crystal layer (contact layer 410) (the semiconductor crystal layer) Forming step (D)). The temperature of the heat treatment is not particularly limited, but may be the same as that in each of the embodiments, for example.

  For example, if the opening is formed by etching the amorphous layer (photonic crystal layer 505 precursor layer) without forming the protective layer, the amorphous layer (photonic crystal layer) is formed during the opening forming step. 505 precursor layer) The surface may be contaminated by impurities. When the impurity contamination occurs, the impurity concentration varies on the upper surface of the photonic crystal layer of the photonic crystal surface emitting laser, which may cause problems such as deterioration of the light emission characteristics. However, according to the present invention, it is possible to solve these problems caused by the impurity concentration and manufacture a photonic crystal surface emitting laser having excellent quality.

  Then, after forming the photonic crystal layer 505 by the semiconductor crystal layer forming step (D), the protective layer is removed by thermal etching (the protective layer removing step (E)). The temperature of the thermal etching is not particularly limited, but may be the same as that in each of the embodiments, for example. Further, a p-type cladding layer 508 is formed on the entire upper surface of the photonic crystal layer 505. The opening is filled with a p-type cladding layer 508 to become an opening filling portion 505A ′. Then, the electrode 512 and the electrode 513 can be formed under the substrate 501 and the p-type cladding layer 513, respectively, to form the photonic crystal surface emitting laser shown in FIG.

  In the present invention, the structure of the photonic crystal surface emitting laser is not particularly limited. For example, each layer in FIG. 6 may be in direct contact with no other component between them, or another component such as another layer may exist between the layers. . Furthermore, in the present invention, the structure of the photonic crystal surface-emitting laser is not limited to this, and may be any structure, for example, a structure that conforms appropriately to the structure of a conventional photonic crystal surface-emitting laser.

  Although the present invention can be implemented as described in the first to fourth embodiments, the present invention is not limited to these embodiments, and modifications may be made as appropriate. Specifically, for example, various conditions such as the processing temperature and the etching solution composition in the manufacturing method of each embodiment may be changed in any way, and as long as the steps (A) to (D) are included, Included in the manufacturing method. The configuration of the group III nitride semiconductor or group III nitride semiconductor device manufactured by the manufacturing method of the present invention is not limited to the configuration of each of the above embodiments, and may be any configuration as described above. For example, the thickness of each layer, the number of layers, the composition, and the like may be appropriately changed as necessary. The group III nitride semiconductor and group III nitride semiconductor device of the present invention include a crystal layer of a group III nitride semiconductor as described above, and the crystal layer is partially removed, and the upper surface of the crystal layer The average value of the impurity concentration of the portion is not more than the average value of the internal impurity concentration. Other than this, the configurations of the group III nitride semiconductor and the group III nitride semiconductor device of the present invention are not limited, and any configuration may be used, and any method may be used.

  The present invention can be applied to, for example, an inner stripe type semiconductor laser as described above, and in particular, can be preferably applied to an inner stripe type GaN laser as described in the second embodiment. The inner stripe type laser is superior to the ridge stripe type laser using dry etching in terms of controllability of the stripe shape that dominates the upper limit of the transverse single mode light output, heat dissipation, and electrical resistance. For this reason, the inner stripe type laser is very promising as a structure suitable for a high-power laser. However, the present invention is not limited to the inner stripe type semiconductor laser, and can be applied to any group III nitride semiconductor device. For example, the present invention may be applied to a ridge stripe laser. Further, the present invention is not limited to a semiconductor laser, and can be applied to a field effect transistor, a photonic crystal surface emitting laser, and the like as described above. As the field effect transistor, for example, a wide recess type transistor as described in the third embodiment may be used, or any other transistor such as a planar type may be used. Furthermore, the present invention can be applied to any group III nitride semiconductor device other than these.

  The application of the group III nitride semiconductor device of the present invention or the group III nitride semiconductor device manufactured by the manufacturing method of the present invention is not particularly limited and may be any application. For example, in the case of a semiconductor laser, it can be used for all purposes such as a semiconductor laser used for an optical disk light source and a semiconductor laser used for a display light source. As a light source for optical disks, it is particularly useful as a light source for next-generation high-density optical disks. For display, for example, a group III nitride semiconductor laser that oscillates in a blue (wavelength: about 450 nm) or green (wavelength: about 530 nm) region may be used.

  In order to increase the writing speed in optical disc applications, it is important to increase the output of the LD. Further, in order to narrow the laser beam into a spot shape, it is necessary to adjust the beam shape, and control of the transverse mode is important. Furthermore, high-frequency characteristics have become important as the transfer speed of optical discs increases, and it is necessary to reduce the element resistance and reduce the parasitic capacitance of the element as much as possible. In the display, in order to cope with the enlargement of the screen, the output of the LD is required to be high, and the transverse mode control is important in terms of laser beam shape control. According to the present invention, as described above, generation of pits and irregularities can be suppressed, and a high-quality group III nitride semiconductor device can be efficiently manufactured. Therefore, these requirements can be satisfied as appropriate. is there.

  Next, examples of the present invention will be described. However, the present invention is not limited to the following examples.

Example 1
In accordance with the steps shown in FIGS. 2A to 2D, a group III nitride semiconductor device (semiconductor laser) having the structure shown in FIG. An n-type GaN (0001) substrate 101 having an n-type carrier concentration of about 1 × 10 ¹⁸ cm ⁻³ was used as the substrate. A 300 hPa reduced pressure MOVPE apparatus was used to fabricate the element structure. A mixed gas of hydrogen and nitrogen is used as a carrier gas, trimethylgallium (TMG), trimethylaluminum (TMA), trimethylindium (TMIn) are used as Ga, Al, and In sources, silane (SiH ₄ ) is used as an n-type dopant, p Biscyclopentadienyl magnesium (Cp ₂ Mg) was used as the type dopant.

  First, as shown in FIG. 2A, the active layer, the n-type clad layer, the n-type and p-type clad layers, and the group III nitride amorphous layer that becomes the current confinement layer were grown. Hereinafter, these steps are collectively referred to as an “active layer growth step”.

That is, first, after the n-type GaN substrate 101 was put into a reduced pressure MOVPE apparatus, the n-type GaN substrate 101 was heated while supplying NH _3, and the growth of each layer was started when the growth temperature was reached. Thereby, Si-doped n-type GaN layer 102 (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 1 μm), Si-doped n-type Al _0.05 Ga _0.95 N (Si concentration 4 × 10 ¹⁷ cm ⁻³⁾ , N-type cladding layer 103 formed from a thickness of 2 μm), n-type optical confinement layer 104 formed from Si-doped n-type GaN (Si concentration 4 × 10 ¹⁷ cm ⁻³ , thickness 0.1 μm), In Three-period multiple quantum well (MQW) layer 105 formed from a _0.1 Ga _0.9 N (thickness 3 nm) well layer and an undoped GaN (thickness 10 nm) barrier layer, Mg-doped p-type Al _0.2 Ga _0.8 capping layer 106 formed from N, Mg-doped p-type GaN (Mg concentration 2 × ¹⁰ 19 ^{cm -3,} thickness 0.1 [mu] m) of p-type GaN guide layer 107 formed sequentially from The product. GaN growth is performed at a substrate temperature of 1080 ° C., a TMG supply rate of 58 μmol / min, and an NH ₃ supply rate of 0.36 mol / min, and an AlGaN growth is performed at a substrate temperature of 1080 ° C., a TMA supply rate of 36 μmol / min, and a TMG supply rate of 58 μmol / min. The NH ₃ supply rate was 0.36 mol / min. InGaN MQW growth was performed at a substrate temperature of 850 ° C., a TMG supply rate of 8 μmol / min, and an NH ₃ supply rate of 0.36 mol / min. The supply amount of TMIn was 48 μmol / min in the well layer.

Next, the substrate temperature is lowered to about 400 ° C., and an amorphous AlN layer 114 ′ (later crystallized to become the current confinement layer 114) is deposited on the p-type GaN guide layer 107 (underlying layer) ( The amorphous layer forming step (A)). Further, an amorphous InN layer (protective layer) 115 was deposited thereon (the protective layer forming step (B)). When the amorphous AlN layer 114 ′ was deposited, the supply amounts of TMA and NH ₃ were 36 μmol / min and 0.36 mol / min, respectively, and the deposited film thickness was 0.1 μm. Further, the TMI and NH ₃ supply amounts during deposition of the amorphous InN layer (protective layer) 115 were 96 μmol / min and 0.36 mol / min, respectively, and the deposited film thickness was 0.01 μm.

  As described above, the active layer growth step shown in FIG.

  Next, as shown in FIG. 2B, a part of the amorphous AlN layer 114 'and the amorphous InN layer (protective layer) 115 was removed by etching to form a stripe-shaped opening 114A. This step corresponds to the etching step (C), but may also be referred to as a “stripe formation step” hereinafter.

That is, first, SiO ₂ was deposited to a thickness of 100 nm on the amorphous InN layer (protective layer) 115 to form a SiO ₂ layer. After applying a resist on the upper surface of the SiO ₂ layer, a stripe pattern having a width of 1.5 μm was formed on the resist by photolithography. Next, the SiO ₂ layer was etched with buffered hydrofluoric acid using the resist as a mask. Thereafter, the resist was removed with an organic solvent and washed with water. The amorphous InN layer (protective layer) 115 was not etched or damaged in each step of buffered hydrofluoric acid, organic solvent, and water washing. Next, the amorphous InN layer (protective layer) 115 and the amorphous AlN layer 114 ′ were etched using the SiO ₂ layer as a mask. As an etching solution, a solution in which phosphoric acid and sulfuric acid were mixed at a volume ratio of 1: 1 was used. Specifically, the non-crystalline InN layer (protective layer) 115 and the non-crystalline AlN layer 114 ′ in the region not covered with the SiO ₂ mask were removed by etching for 9 minutes in the solution maintained at 90 ° C. . Thereby, the opening 114A was formed. Thereafter, the SiO ₂ layer used as a mask was removed with buffered hydrofluoric acid. Thus, the stripe formation process (etching process (C)) was able to be implemented.

In this example, SiO ₂ was used as an etching mask on the amorphous InN layer (protective layer) 115. However, the etching mask is not particularly limited as long as it is a material that is not affected by the etchant during wet etching of amorphous InN and amorphous AlN. For example, as described above, an organic material containing SiNx or a resist may be used as an etching mask.

  Next, the amorphous AlN layer 114 'was converted into a crystalline layer (current confinement layer) 114 by heat treatment (the semiconductor crystal layer forming step (D)). Further, the protective layer 115 was removed by thermal etching (the protective layer removing step (E)). Thereafter, as shown in FIG. 2C, the p-type cladding layer 108 is laminated so as to fill the opening 114A formed by the stripe forming step (the etching step (C)) to form the opening embedded portion 114A ′. (The other group III nitride semiconductor-containing layer forming step (F)), and a p-type contact layer 109 was further deposited. Hereinafter, these processes may be collectively referred to as a “p-type cladding regrowth process”.

That is, first, the semiconductor laser wafer in which the opening 114A was formed by the stripe forming process (the etching process (C)) was put into a MOVPE apparatus. Subsequently, the inside of the MOVPE apparatus was heated to about 700 ° C. with an NH ₃ supply rate of 0.36 mol / min and an N ₂ carrier gas supply rate of 0.9 mol / min. The amorphous AlN layer 114 ′ was converted into a crystal layer (current confinement layer) 114 by annealing at 700 ° C. for 10 minutes as it was (the semiconductor crystal layer forming step (D)). Thereafter, part of the carrier gas is switched to H ₂ , and the p-type cladding layer is supplied with an NH ₃ supply rate of 0.36 mol / min, an N ₂ carrier gas supply rate of 0.45 mol / min, and an H ₂ gas supply rate of 0.45 mol / min. The temperature was raised again to 1100 ° C., which is the growth temperature. This temperature raising step played a role of thermal etching, and the protective layer 115 was removed by evaporation (the protective layer removing step (E)), and an extremely clean surface of the current confinement layer 114 appeared. Thereafter, a p-type cladding formed of Mg-doped p-type Al _0.05 Ga _0.95 N (Mg concentration 1 × 10 ¹⁹ cm ⁻³ , thickness 0.5 μm) while maintaining the substrate temperature at 1100 ° C. A layer 108 was deposited (the other group III nitride semiconductor-containing layer forming step (F)). Then, after the substrate temperature was lowered to 1080 ° C., a p-type contact layer 109 made of Mg-doped p-type GaN (Mg concentration 1 × 10 ²⁰ cm ⁻³ , thickness 0.02 μm) was deposited. The deposition conditions for AlGaN and GaN were the same as in the active layer growth step except for the difference in dopant. In this way, the p-type cladding regrowth process could be performed.

When the scanning electron microscope was observed after the p-type cladding regrowth step, defects such as cracks and pits were found on the buried regrowth surface, both on the opening buried portion 114A ′ and on the AlN current confinement layer 114. I couldn't. That is, it was confirmed that the AlN layer (current confinement layer 114) was crystallized and was buried flat by the p-type cladding layer. When the buried regrowth surface on the AlN current confinement layer 114 was observed in more detail, a swell-like morphology was observed in a slight amount, but it was at a level that had no problem in practical use. The cause of this morphology is not clear, but is presumed to be due to, for example, dislocations generated in order to relax the lattice mismatch between the AlN current confinement layer 114 and the p-type AlGaN cladding layer 108. Furthermore, residual impurities were analyzed from the p-type cladding layer to the current confinement layer 114 using a secondary ion mass spectrometer. As a result, the oxygen concentration in the current confinement layer 114 was about 3 × 10 ¹⁸ cm ⁻³ and remained substantially constant near the interface with the p-type cladding layer 108 (upper surface of the current confinement layer 114).

  The structure obtained as described above includes an n-type GaN substrate 101, a Si-doped n-type GaN layer 102, an n-type cladding layer 103, an n-type optical confinement layer 104, and three periods as shown in FIG. It has a multiple quantum well (MQW) layer 105, a cap layer 106, a p-type GaN guide layer 107, a current confinement layer 114, a p-type cladding layer 108, and a p-type contact layer 109.

  An n-electrode 112 is formed on the back surface (lower surface) of the n-type GaN substrate 101 and a p-electrode 113 is formed on the upper surface of the p-type contact layer 109 by the vacuum deposition method (FIG. 2D). ). Hereinafter, this process may be referred to as an “electrode formation process”. Then, the sample (structure) after the electrode formation step was cleaved in a direction orthogonal to the longitudinal direction of the opening embedded portion (strip) 114 </ b> A ′, whereby a group III nitride semiconductor device 100 was obtained. The element length was 500 μm.

When the group III nitride semiconductor device 100 was fused to a heat sink and the light emission characteristics were examined, laser oscillation occurred at an average current density of 2.8 kA / cm ² and a voltage of 4.1 V. Moreover, the average life at the time of 250 mW output was 10,000 hours or more. That is, the group III nitride semiconductor device 100 manufactured in this example had good characteristics and a long life.

  As described above, according to this example, a high-quality group III nitride semiconductor device having good characteristics and a long life could be manufactured efficiently (with a high yield).

(Example 2)
In this example, a group III nitride semiconductor device (semiconductor laser) 100 having the structure shown in FIG. 2D was manufactured according to the steps shown in FIGS. The production conditions were the same as in Example 1 except for the following (i) and (ii).
(I) As the protective layer 115, an amorphous In _0.5 Ga _0.5 N layer was deposited on the amorphous AlN layer 114 ′ instead of the amorphous InN layer.
(Ii) The heat treatment temperature of the amorphous AlN layer 114 ′ in the semiconductor crystal layer forming step (D) was set to 750 ° C.

  That is, first, growth of each of the active layer, the n-type cladding layer, the n-type and p-type cladding layers, and the group III nitride amorphous layer that becomes the current confinement layer shown in FIG. Growth process). This active layer growth step was performed under the same conditions as in Example 1 except for the condition (i).

Next, as shown in FIG. 2B, the same “strip formation step (the etching step (C)) as in Example 1 is performed, and the amorphous AlN layer 114 ′ and the amorphous In _0.5 Ga _{0.5 are formed.} A stripe-shaped opening 114A was formed in the N layer (protective layer) 115. This “stripe formation step” was performed under the same conditions as in Example 1.

  Next, the same “p-type cladding regrowth process” as in Example 1 was performed. This p-type cladding regrowth step was performed under the same conditions as in Example 1 except for the condition (ii).

When the scanning electron microscope was observed after the p-type cladding regrowth step, cracks, pits, etc. were found on the surface of the regrowth regrowth surface, both on the opening buried portion 114A ′ and on the AlN current confinement layer 114, as in Example 1. The defect was not seen. That is, it was confirmed that the AlN layer (current confinement layer 114) was crystallized and was buried flat by the p-type cladding layer. When the buried regrowth surface on the AlN current confinement layer 114 was observed in more detail, a swell-like morphology was observed in a slight amount, but it was at a level that had no problem in practical use. The cause of this morphology is not clear, but is presumed as described in Example 1. Furthermore, residual impurities were analyzed from the p-type cladding layer to the current confinement layer 114 using a secondary ion mass spectrometer. As a result, the oxygen concentration in the current confinement layer 114 was about 3 × 10 ¹⁸ cm ⁻³ and remained substantially constant near the interface with the p-type cladding layer 108 (upper surface of the current confinement layer 114).

  The structure obtained as described above has a structure shown in FIG. The structure in FIG. 2C is as described in the first embodiment.

  Further, the “electrode formation step” shown in FIG. 2D was performed on the structure in the same manner as in Example 1. Then, the sample (structure) after the electrode formation step was cleaved in a direction orthogonal to the longitudinal direction of the opening embedded portion (stripes) 114 </ b> A ′, so that a group III nitride semiconductor device (semiconductor laser) 100 was obtained. The element length was 500 μm.

When the group III nitride semiconductor device (semiconductor laser) 100 was fused to a heat sink and the light emission characteristics were examined, laser oscillation occurred at an average current density of 2.8 kA / cm ² and a voltage of 4.1 V. Moreover, the average life at the time of 250 mW output was 10,000 hours or more.

(Example 3)
In this example, a group III nitride semiconductor device (semiconductor laser) 100 having the structure shown in FIG. 2D was manufactured according to the steps shown in FIGS. The production conditions were the same as in Example 1 except for the following (iii) to (v).
(Iii) As the group III nitride amorphous layer 114 ′, an amorphous Al _0.9 Ga _0.1 N layer was deposited on the p-type GaN guide layer 107 instead of the amorphous AlN layer.
(Iv) As the protective layer 115, an amorphous In _0.5 Ga _0.5 N layer was deposited on the amorphous Al _0.9 Ga _0.1 N layer 114 ′ instead of the amorphous InN.
(V) The heat treatment temperature of the amorphous Al _0.9 Ga _0.1 N layer 114 ′ in the semiconductor crystal layer forming step (D) was 750 ° C.

  That is, first, growth of each of the active layer, the n-type cladding layer, the n-type and p-type cladding layers, and the group III nitride amorphous layer that becomes the current confinement layer shown in FIG. Growth process). This active layer growth step was performed in the same manner as in Example 1 except for the conditions (iii) and (iv).

Next, as shown in FIG. 2B, the same “strip formation step (etching step (C)) as in Example 1 is performed, and an amorphous Al _0.9 Ga _0.1 N layer 114 ′ and an amorphous layer are formed. Striped openings 114A were formed in the In _0.5 Ga _0.5 N layer (protective layer) 115. This “stripe formation step” was performed under exactly the same conditions as in Example 1.

  Next, the same “p-type cladding regrowth process” as in Example 1 was performed. This p-type cladding regrowth step was performed under the same conditions as in Example 1 except for the condition (v).

Scanning electron microscope observation was performed after the p-type cladding regrowth process, and as a result, cracks and cracks were found on the buried regrowth surface, both on the opening buried portion 114A ′ and on the Al _0.9 Ga _0.1 N current confinement layer 114. There were no defects such as pits. That is, it was confirmed that the Al _0.9 Ga _0.1 N layer (current confinement layer 114) was crystallized and was buried flat by the p-type cladding layer 108. Further, when the buried regrowth surface on the Al _0.9 Ga _0.1 N current confinement layer 114 is examined in more detail, the morphology such as waviness is further reduced as compared with the cases of the first and second embodiments. It was observed that the flatness was further improved. Although the cause of this is not clear, for example, the degree of lattice mismatch between the current confinement layer 114 and the p-type AlGaN cladding layer 108 due to the change of the current confinement layer 114 to Al _0.9 Ga _0.1 N. It is presumed that the dislocations and the like generated due to relaxation were reduced. Furthermore, residual impurities were analyzed from the p-type cladding layer to the current confinement layer 114 using a secondary ion mass spectrometer. As a result, the oxygen concentration in the current confinement layer 114 was about 2.7 × 10 ¹⁸ cm ⁻³ and remained substantially constant near the interface with the p-type cladding layer 108 (upper surface of the current confinement layer 114).

  The structure obtained as described above has a structure shown in FIG. The structure in FIG. 2C is as described in the first embodiment.

  Further, the “electrode formation step” shown in FIG. 2D was performed on the structure in the same manner as in Example 1. Then, the sample (structure) after the electrode formation step was cleaved in a direction orthogonal to the longitudinal direction of the opening embedded portion (stripes) 114 </ b> A ′, so that a group III nitride semiconductor device (semiconductor laser) 100 was obtained. The element length was 500 μm.

When the semiconductor device 100 of this example was fused to a heat sink and the light emission characteristics were examined, laser oscillation occurred at an average current density of 2.8 kA / cm ² and a voltage of 4.1 V. Moreover, the average life at the time of 250 mW output was 10,000 hours or more.

Example 4
In this example, the semiconductor laser 200 shown in FIG. The semiconductor laser 200 is the same as the semiconductor laser 100 of the first embodiment except that the current confinement layer has a two-layer structure of a lower layer (AlN crystal layer) 214 and an upper layer (GaN crystal layer) 215.

  This semiconductor laser 200 was manufactured based on the manufacturing method shown in the schematic diagrams (cross-sectional views) of FIGS. Specifically, it is as follows.

First, as shown in FIG. 3 (a), each of an active layer, an n-type cladding layer, an n-type and p-type cladding layer, and a group III nitride amorphous layer to be a current confinement layer was grown (active layer growth). Process). That is, first, similarly to Example 1, an Si-doped n-type GaN layer 102, an n-type cladding layer 103, an n-type optical confinement layer 104, and a three-period multiple quantum well (MQW) layer 105 are formed on an n-type GaN substrate 101. Then, a cap layer 106 and a p-type GaN guide layer 107 were deposited. Next, on the p-type GaN guide layer 107 (underlying layer), an amorphous AlN layer 214 ′ (later crystallized and becomes the lower layer 214 of the current confinement layer) is deposited, and then the amorphous AlN layer 214 ′ An amorphous GaN layer 215 ′ (later crystallized to become the upper layer 215 of the current confinement layer) was deposited at the same growth temperature (the amorphous layer forming step (A)). Further, an amorphous InN layer (protective layer) 216 was deposited thereon (the protective layer forming step (B)). The growth conditions of the amorphous AlN layer 214 ′ are the same as those of the amorphous AlN layer 114 ′ in the first embodiment. In addition, TMG and NH ₃ supply amounts during deposition of amorphous GaN were 12 μmol / min and 0.36 mol / min, respectively, and a deposited film thickness was 0.01 μm. The growth conditions of the amorphous InN layer (protective layer) are the same as those in Example 1.

  Next, as shown in FIG. 3B, the same “stripe formation step (etching step (C))” as in Example 1 is performed, and the amorphous AlN layer 214 ′, the amorphous GaN layer 215 ′, and the amorphous In the InN layer (protective layer) 216, a stripe-shaped opening 214A was formed.

That is, first, SiO ₂ was deposited to a thickness of 100 nm on the amorphous InN layer (protective layer) 216 to form a SiO ₂ layer. After applying a resist on the upper surface of the SiO ₂ layer, a stripe pattern having a width of 1.5 μm was formed on the resist by photolithography. Next, the SiO ₂ layer was etched with buffered hydrofluoric acid using the resist as a mask. Thereafter, the resist was removed with an organic solvent and washed with water. None of the non-crystalline AlN layer 214 ′, the non-crystalline GaN layer 215 ′, and the non-crystalline InN layer 216 were subjected to etching or damage in each step of buffered hydrofluoric acid, organic solvent, and water washing. Next, the amorphous InN layer 216, the amorphous GaN layer 215 ′, and the amorphous AlN layer 214 ′ were etched using the SiO ₂ layer as a mask. As an etching solution, a solution in which phosphoric acid and sulfuric acid were mixed at a volume ratio of 1: 1 was used. Specifically, the non-crystalline InN layer 216, the non-crystalline GaN layer 215 ′ and the non-crystalline AlN layer 214 ′ in the region not covered with the SiO ₂ mask are placed in the solution held at 90 ° C. for 10 minutes. It was removed by etching. Thereby, the opening 114A was formed. Thereafter, the SiO ₂ layer used as a mask was removed with buffered hydrofluoric acid. In this way, the stripe formation step (the etching step (C)) could be performed.

  The etching mask is not particularly limited as described in the first embodiment. For example, as described above, an organic material including SiNx or a resist may be used as the etching mask.

  Next, the amorphous AlN layer 214 'and the amorphous GaN layer 215' were converted into crystalline layers (current confinement layers) 214 and 215 by heat treatment (the semiconductor crystal layer forming step (D)). Further, the protective layer 216 was removed by thermal etching (the protective layer removing step (E)). Thereafter, as shown in FIG. 3C, the p-type cladding layer 108 is laminated so as to fill the opening 214A formed by the stripe forming step (the etching step (C)) to form the opening embedded portion 214A ′. (The other group III nitride semiconductor-containing layer forming step (F)), and a p-type contact layer 109 was further deposited. These “p-type cladding regrowth steps” were performed under the same conditions as in Example 1.

  Scanning electron microscope observation was performed after the p-type cladding regrowth step. As a result, as in Example 1, no defects such as cracks and pits were observed on the surface, and the AlN crystal layer (lower layer) 214 and the GaN crystal layer (upper layer) 215 were both crystallized and embedded flatly. It was confirmed that When the buried regrowth surface on the GaN crystal layer (upper layer) 215 is observed in more detail, the swell-like morphology is further reduced as compared with the case of Example 1 and Example 2, and the flatness is further improved. Was observed. Although the cause of this is not clear, for example, the GaN crystal layer (upper layer) 215 is inserted between the AlN current confinement layer (lower layer) 214 and the p-type AlGaN cladding layer 108, so that the degree of lattice mismatch is further increased. It is presumed that defects such as dislocations generated for relaxation were further reduced.

Furthermore, the residual impurities from the p-type cladding layer 108 to the AlN crystal layer lower layer 214 were analyzed using a secondary ion mass spectrometer. As a result, among the current confinement layers 214 and 215, the oxygen concentration in the AlN crystal layer (lower layer) 214 was constant at about 3 × 10 ¹⁸ cm ⁻³ . Furthermore, the oxygen concentration in the GaN crystal layer (upper layer) 215 was 1 × 10 ¹⁸ cm ⁻³ or less, and remained at 1 × 10 ¹⁸ cm ⁻³ or less even near the interface with the p-type cladding layer 108.

  Further, the “electrode formation step” was performed in the same manner as in Example 1. That is, an n-electrode 112 was formed on the back surface (lower surface) of the n-type GaN substrate 101, and a p-electrode 113 was formed on the upper surface of the p-type contact layer 109 by a vacuum deposition method (FIG. 3D). Then, the sample (structure) after the electrode formation step was cleaved in a direction orthogonal to the longitudinal direction of the opening embedded portion (stripe) 214 </ b> A ′, so that a group III nitride semiconductor device 200 was obtained. The element length was 500 μm.

  The characteristics of group III nitride semiconductor device 200 were confirmed in the same manner as in Example 1. As a result, the threshold current density, operating voltage, and radiation angle of output light were the same as in Example 1 and were good. Further, it was confirmed that the variation in characteristics of the entire group III nitride semiconductor device 200 was further improved by about 20% compared to the case of Example 1. The cause of this is not clear, but, for example, by introducing the GaN crystal layer (upper layer) 215, the regrowth layer thickness of the p-type cladding layer 108 in the opening 214A in the “p-type cladding regrowth step” and the opening buried portion This is considered to be because the distribution in the wafer surface of the variation in the width of 214A ′ is further improved.

  As described above, according to this example, as in Example 1, a high-quality group III nitride semiconductor device having good characteristics and a long life could be manufactured efficiently (with a high yield). Further, the variation in characteristics of the group III nitride semiconductor device could be further improved as compared with Example 1.

(Comparative example)
A semiconductor laser 300 shown in FIG. 4D was manufactured. In this semiconductor laser 300, the current confinement layer 114 of Example 1 is replaced with 314, and the current confinement layer 314 is an AlN crystal layer like the current confinement layer 114. The material and positional relationship of the other components are the same as those of the semiconductor laser 100 of the first embodiment. However, as shown in the drawing, the flatness of the upper layer of the current confinement layer 314 is poor, and defects such as pits 110 are present. Were present.

  This semiconductor laser 300 was manufactured according to the steps shown in the schematic diagrams of FIGS. The manufacturing conditions were almost the same as in Example 1, but differed in that they were manufactured without forming a protective layer on the amorphous AlN layer 314 '(which becomes the current confinement layer 314 by crystallization).

  More specifically, the semiconductor laser 300 was manufactured as follows. That is, first, as shown in FIG. 4A, the active layer, the n-type cladding layer, the n-type and p-type cladding layers, and the current confinement layer were grown. Except that no protective layer was formed on the amorphous AlN layer 314 ', the process was exactly the same as the "active layer growth step" in Example 1 (FIG. 2A). The non-crystalline AlN layer 314 'is the same layer as the non-crystalline AlN layer 114' in FIG. 2A, and the other components are exactly the same as in FIG.

Next, as shown in FIG. 4B, a part of the amorphous AlN layer 314 ′ was etched to form openings (stripes) 314A. Specifically, an SiO ₂ mask is formed directly on the amorphous AlN layer 314 ′, and etching is performed at 90 ° C. for 8.5 minutes with a solution in which phosphoric acid and sulfuric acid are mixed at a volume ratio of 1: 1. An opening 314A was formed. Other conditions are the same as those in the “stripe formation step” (FIG. 2B) in the first embodiment.

Further, as shown in FIG. 4C, a p-type cladding layer 108 is laminated on the current confinement layer 314 and the opening 314A so as to embed the opening 314A to form the opening burying portion 314A ′. A mold contact layer 109 was laminated. Specifically, after a sample (FIG. 4B) in which the opening 314A is formed by the etching is put into the MOVPE apparatus, the NH ₃ supply rate is 0.36 mol / min, and the N ₂ carrier gas supply rate is 0.45 mol / min. Heating was started under gas conditions of min and H ₂ gas supply rate of 0.45 mol / min, and the temperature was raised to 1100 ° C., which is the growth temperature of the p-type cladding layer, without waiting. Other conditions are the same as in the “p-type cladding regrowth step” in the first embodiment.

  Observation with a scanning electron microscope after formation of the p-type cladding layer 108 and the p-type contact layer 109 revealed defects such as pits on the buried regrowth surface on the AlN current confinement layer 314. In particular, a large number of pits 110 were observed on the buried regrowth surface in the vicinity of the opening buried portion 314A 'as shown in FIG. Further, in the vicinity of the opening burying portion 314A ', as shown in FIG. 4C, it was confirmed that the burying layer thickness was thicker than that on the AlN current confinement layer 314 and the flatness was poor.

Next, analysis of residual impurities from the p-type cladding layer 108 to the current confinement layer 314 was performed using a secondary ion mass spectrometer. As a result, the oxygen concentration in the current confinement layer 314 was about 3 × 10 ¹⁸ cm ^{−3 in the} vicinity of the interface on the p-type GaN guide layer 107 side, but 1 × 10 in the vicinity of the interface on the p-type cladding layer 108 side. It was confirmed that it jumped up to ²⁰ cm ⁻³ or more. Although the cause of the high impurity concentration is not clear, it is considered that the surface of the AlN current confinement layer 314 is made of aluminum oxynitride (AlN _x O _1-x ), for example. That is, it is presumed that AlN _x O _1-x composition spots were generated at the time of temperature rise before the p-type cladding layer regrowth, causing the pit 100.

Further, in the same manner as in the “electrode formation step” in the first embodiment, an n electrode 112 is formed on the back surface (lower surface) of the n-type GaN substrate 101, and a p electrode 113 is formed on the upper surface of the p-type contact layer 109, respectively. (FIG. 4D). Then, the sample (structure) after the electrode formation step was cleaved in a direction orthogonal to the longitudinal direction of the opening embedded portion (stripes) 314A ′, and a group III nitride semiconductor device 300 was obtained. However, the semiconductor laser 300 of the comparative example has an average threshold current density of 3.2 kA / cm ² , an average threshold voltage of 4.5 V, an average lifetime of about 2000 hours at 250 mW output, and the characteristics are as described in Examples 1 to 3. It was significantly inferior to the semiconductor laser of No. 4. Furthermore, the semiconductor laser 300 of the comparative example had a large variation in element characteristics more than double that of the semiconductor lasers of Examples 1 to 4, and the reliability was greatly inferior.

It is a schematic diagram which shows each process in one Embodiment of the manufacturing method of this invention. FIG. 1A shows a group III nitride amorphous layer forming step (A). FIG. 1B shows a protective layer forming step (B). FIG. 1C shows an etching process (C). FIG. 1D shows a semiconductor crystal layer forming step (D). It is a figure which shows the manufacturing process of the group III nitride semiconductor element in another embodiment and Example of this invention, and the cross section of a completion element. 2A shows the active layer growth process, FIG. 2B shows the stripe formation process, FIG. 2C shows the p-type cladding regrowth process, and FIG. 2D shows the electrode formation process and the cross section of the completed device. FIG. It is a figure which shows the manufacturing process of the group III nitride semiconductor element in another embodiment and another Example of this invention, and the cross section of a completion element. 3A is an active layer growth process, FIG. 3B is a stripe formation process, FIG. 3C is a p-type cladding regrowth process, and FIG. 3D is an electrode formation process and a cross section of a completed device. FIG. It is a figure which shows the manufacturing process of the group III nitride semiconductor element of a comparative example, and the cross section of a completed element. 4A shows the active layer growth step, FIG. 4B shows the stripe formation step, FIG. 4C shows the p-type cladding regrowth step, and FIG. 4D shows the electrode formation step and the cross section of the completed device. FIG. It is a figure which shows the cross section of the group III nitride semiconductor element in another embodiment of this invention. It is a figure which shows the cross section of the group III nitride semiconductor element in another embodiment of this invention.

Explanation of symbols

11 Underlayer 12 ′ Group III nitride amorphous layer 12 Group III nitride semiconductor crystal layer 13 Protective layer (or layer formed from group III nitride)
100, 200, 300 Semiconductor laser (Group III nitride semiconductor device)
101 Substrate 102 GaN layer 103 n-type cladding layer 104 n-type optical confinement layer 105 multiple quantum well layer 106 cap layer 107 p-type GaN guide layer (underlayer or first layer)
108 p-type cladding layer (another group III nitride semiconductor-containing layer or a third layer)
109 p-type contact layer 110 pit 112 n-electrode 113 p-electrode 114A, 214A, 314A, 414A opening 114A ′, 214A ′, 314A ′, 514A ′ opening buried portion 114, 314 current confinement layer (group III nitride semiconductor crystal layer) Or second layer)
115, 216 Protective layer (or layer formed from group III nitride)
214 Lower layer 215 of current confinement layer (Group III nitride semiconductor crystal layer or second layer) Upper layer 114 ′ of current confinement layer (Group III nitride semiconductor crystal layer or second layer) Non-crystal of Group III nitride Layer 214 ′ group III nitride amorphous layer lower layer 215 ′ group III nitride amorphous layer upper layer 400 field effect transistor (group III nitride semiconductor device)
401 Substrate 402 Buffer layer 403 Carrier travel layer 404 Spacer layer 405 Carrier supply layer 406 Shot layer 407 Source electrode 408 Drain electrode 409 Gate electrode 410 Contact layer 500 Photonic crystal surface emitting laser (Group III nitride semiconductor device)
501 Substrate 502 n-type cladding layer 503 active layer 505 photonic crystal layer 508 p-type cladding layer

Claims (39)

An amorphous layer forming step of forming a group III nitride amorphous layer on the upper surface of the underlayer;
A protective layer forming step of forming a protective layer on the upper surface of the amorphous layer;
An etching step of removing a part of the amorphous layer by etching;
A semiconductor crystal layer forming step of converting the amorphous layer into a crystal layer of a group III nitride semiconductor by heat-treating and crystallizing the amorphous layer in a state in which the protective layer is formed. A method for manufacturing a semiconductor.   The method for producing a group III nitride semiconductor according to claim 1, further comprising a protective layer removing step of removing the protective layer after the semiconductor crystal layer forming step.   3. The method for producing a group III nitride semiconductor according to claim 2, wherein the protective layer removing step is a step of removing the protective layer by thermal etching.   4. The method for producing a group III nitride semiconductor according to claim 3, wherein a thermal etching temperature in the protective layer removing step is higher than a heat treatment temperature in the semiconductor crystal layer forming step.   The method for producing a group III nitride semiconductor according to any one of claims 1 to 4, wherein the protective layer is a layer formed of a group III nitride. The crystal layer is formed of a group III nitride semiconductor having a composition of In _a Ga _b Al _1-ab N (0 ≦ a <1, 0 ≦ b <1, 0 ≦ a + b <1);
The protective layer _is formed of a group III nitride having a composition of _{In c Ga d Al 1-c} -d N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 <c + d ≦ 1), and,
The In composition ratio a of the crystal layer and the In composition ratio c of the protective layer satisfy at least one of the following mathematical formulas (1) and (2). The manufacturing method of the group III nitride semiconductor of description.

a = 0 (1)
a <c (2) The protective layer _{is, In x Ga 1-x N} (0 ≦ x ≦ 1) that is formed of a group III nitride having a composition of claim 1, wherein according to any one of the 6 A method for producing a group III nitride semiconductor.   The method for manufacturing a group III nitride semiconductor according to claim 1, wherein the protective layer is made of InN.   The method for producing a group III nitride semiconductor according to any one of claims 1 to 8, wherein the crystal layer is made of AlN.   The method for producing a group III nitride semiconductor according to claim 1, wherein the crystal layer includes two or more layers.   The method for producing a group III nitride semiconductor according to claim 10, wherein the crystal layer includes a lower layer formed of AlN and an upper layer formed of GaN.   The group III according to any one of claims 1 to 11, wherein the crystal layer includes an impurity, and an average value of impurity concentration of the upper surface portion of the crystal layer is equal to or less than an average value of internal impurity concentration. A method for manufacturing a nitride semiconductor.   13. The group III nitride according to claim 12, wherein in the crystal layer, the upper surface portion is a portion from the upper surface of the crystal layer to a depth of 50 nm, and the inside is a portion other than the upper surface portion. A method for manufacturing a semiconductor.   14. The method for producing a group III nitride semiconductor according to claim 12 or 13, wherein the impurity is oxygen. The method for producing a group III nitride semiconductor according to claim 14, wherein an average value of oxygen concentration in the upper surface portion of the crystal layer is 5 × 10 ¹⁸ cm ⁻³ or less.   16. The method according to claim 1, further comprising another group III nitride semiconductor-containing layer forming step of forming another group III nitride semiconductor-containing layer on the crystal layer. A method for producing a group III nitride semiconductor.   After the semiconductor crystal layer forming step, a protective layer removing step for removing the protective layer is included, and the protective layer removing step is a step of removing the protective layer by thermal etching, and the other group III nitride semiconductor is contained. 17. The method for producing a group III nitride semiconductor according to claim 16, wherein, in the layer forming step, the other group III nitride semiconductor-containing layer is formed at a temperature equal to or higher than a thermal etching temperature in the protective layer removing step.   The method for producing a group III nitride semiconductor according to any one of claims 1 to 17, wherein the underlayer is a layer containing a group III nitride semiconductor.   The method for producing a group III nitride semiconductor according to any one of claims 1 to 18, wherein a layer formed of group III nitride is formed instead of the protective layer.   A method for manufacturing a semiconductor device including a group III nitride semiconductor, wherein the group III nitride semiconductor is manufactured by the manufacturing method according to any one of claims 1 to 19. Device manufacturing method.   21. The method for producing a group III nitride semiconductor device according to claim 20, wherein the group III nitride semiconductor device is a semiconductor laser, a field effect transistor, or a photonic crystal surface emitting laser.   The method for producing a group III nitride semiconductor device according to claim 21, wherein the group III nitride semiconductor device is a semiconductor laser, and the crystal layer is a current confinement layer.   The method for producing a group III nitride semiconductor device according to claim 21, wherein the group III nitride semiconductor device is a field effect transistor, and the crystal layer is a contact layer.   The method for producing a group III nitride semiconductor device according to claim 21, wherein the group III nitride semiconductor device is a photonic crystal surface emitting laser, and the crystal layer is a photonic crystal layer.   A crystal layer of a group III nitride semiconductor is included, the crystal layer is partially removed, the crystal layer includes an impurity, and an average value of the impurity concentration on the upper surface portion of the crystal layer is an average value of an internal impurity concentration A group III nitride semiconductor produced by the production method according to any one of claims 1 to 19 below.   26. The group III nitride according to claim 25, wherein in the crystal layer, the upper surface portion is a portion from the upper surface of the crystal layer to a depth of 50 nm, and the inside is a portion other than the upper surface portion. Semiconductors.   27. The group III nitride semiconductor according to claim 25 or 26, wherein the impurity is oxygen. 28. The group III nitride semiconductor according to claim 27, wherein in the crystal layer, an average value of oxygen concentration in the upper surface portion is 5 × 10 ¹⁸ cm ⁻³ or less.   The group III nitride semiconductor according to any one of claims 25 to 28, wherein the crystal layer is a layer formed of AlN.   The group III nitride semiconductor according to any one of claims 25 to 30, wherein the crystal layer includes two or more layers.   31. The group III nitride semiconductor according to claim 30, wherein the crystal layer includes a lower layer formed of AlN and an upper layer formed of GaN.   32. The group III nitride semiconductor according to claim 25, further comprising another group III nitride semiconductor-containing layer on the crystal layer.   The group III nitride semiconductor according to any one of claims 25 to 32, further comprising the underlayer.   The group III nitride semiconductor according to claim 33, wherein the underlayer is a layer containing a group III nitride semiconductor.   A group III nitride semiconductor device manufactured by the manufacturing method according to any one of claims 20 to 24 and comprising the group III nitride semiconductor according to any one of claims 25 to 34. .   36. The group III nitride semiconductor device according to claim 35, which is a semiconductor laser, a field effect transistor, or a photonic crystal surface emitting laser.   37. The group III nitride semiconductor device according to claim 36, which is a semiconductor laser, wherein the crystal layer is a current confinement layer.   37. The group III nitride semiconductor device according to claim 36, wherein the group III nitride semiconductor device is a field effect transistor, and the crystal layer is a contact layer.   37. The group III nitride semiconductor device according to claim 36, wherein the group III nitride semiconductor device is a photonic crystal surface emitting laser, and the crystal layer is a photonic crystal layer.

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