JP2011198804A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces the possibility that a semiconductor element gets out of order.SOLUTION: The semiconductor device includes: the semiconductor element 10; a first electrode member 21 laminated on the semiconductor element 10; a second electrode member 22 laminated on the opposite side of the first electrode member 21 across the semiconductor element 10; first solder 31 for joining the semiconductor element 10 and first electrode member 21 together; and second solder 32 for joining the semiconductor element 10 and second electrode member 22 together. The second electrode member 22 has a plurality of insulating columns 22a to 22d extending in the laminating direction of the semiconductor element 10 and electrode members 21 and 22. Further, the plurality of insulating columns 22a to 22d are positioned in a region B different from an arrangement region A of the semiconductor element 10, and arranged at irregular intervals (a) and (b) in a rotating direction of the semiconductor element 10 in a region C which comes into contact with the semiconductor element 10 when the semiconductor element 10 rotates.

Description

  The present invention relates to a semiconductor device.

  2. Description of the Related Art Conventionally, there has been proposed a semiconductor device in which a semiconductor element is sandwiched between two heat radiating members and the semiconductor element and each heat radiating member are joined together by a joining member such as solder. In this semiconductor device, the distance between the heat dissipating members is controlled using jigs arranged above and below the semiconductor device. More specifically, the jig has a protrusion extending along the stacking direction of the semiconductor element and each heat radiating member, and each heat radiating member has a through hole through which the protrusion of the jig passes. Further, the protrusion of the jig disposed above the semiconductor element passes through the through hole of the heat radiating member disposed above the semiconductor element and comes into contact with the heat radiating member disposed below the semiconductor element. Similarly, the protrusion of the jig disposed below the semiconductor element passes through the through hole of the heat radiating member disposed below the semiconductor element and contacts the heat radiating member disposed above the semiconductor element. By such contact, the distance between the heat dissipating members (the height of the semiconductor device) is controlled. Therefore, it is not necessary to increase the thickness of the joining member such as solder in consideration of the dimensional tolerance without being affected by the dimensional tolerance of each heat radiating member, and the thickness of the joining member is reduced. The jig becomes unnecessary after use and is removed so as to be pulled out from the through hole (see Patent Document 1).

Japanese Patent No. 3620399

  Here, the manufacturing process of the semiconductor device described in Patent Document 1 includes a process of melting solder in order to join the semiconductor element and the two heat dissipating members. In this step, since the solder is melted, the semiconductor element may be displaced in the lateral direction (specifically, the rotation direction) of the semiconductor element. For this reason, when the jig is pulled out from the through hole after the semiconductor device is completed, there is a possibility that the protrusion of the jig and the semiconductor element displaced in the lateral direction come into contact with each other, leading to a failure of the semiconductor element.

  The present invention has been made to solve such a conventional problem, and an object of the present invention is to provide a semiconductor device capable of reducing the possibility of failure of a semiconductor element.

  The semiconductor device of the present invention includes a semiconductor element, a first energization member laminated on the semiconductor element, a second energization member laminated on the opposite side of the first energization member across the semiconductor element, the semiconductor element, and the first A first joining member that joins the energizing member; and a second joining member that joins the semiconductor element and the second energizing member. At least one of the first and current-carrying members has a plurality of insulating columns extending in the stacking direction of the semiconductor element and the first and second current-carrying members. The plurality of support columns are located in a region different from the region where the semiconductor element is disposed between the first and second current-carrying members, and are not rotated in the rotation direction in the region that contacts the semiconductor element when the semiconductor element rotates. Each of them is arranged at a uniform interval.

According to the present invention, at least one of the first and second current-carrying members has a plurality of columns extending in the stacking direction of the semiconductor element and the first and second current-carrying members. Is controlled. Further, since the plurality of pillars are respectively arranged at non-uniform intervals in the rotation direction in the region in contact with the semiconductor element when the semiconductor element rotates, the semiconductor element is either clockwise or counterclockwise. Even if an attempt is made to rotate in the direction, since the support pillars are unevenly arranged, the semiconductor element easily comes into contact with the support pillars, and displacement in the rotational direction is restricted. In addition, since the post does not need to be pulled out in a subsequent process unlike the jig, it is possible to suppress a failure of the semiconductor element due to the pulling out of the jig while controlling the height control and the displacement in the rotation direction. Therefore, the possibility of failure of the semiconductor element can be reduced.

It is a block diagram which shows the semiconductor device which concerns on this embodiment. FIG. 2 is a top view of the semiconductor device shown in FIG. 1. It is a 1st side view showing the manufacturing method of the semiconductor device concerning this embodiment. It is a 2nd side view which shows the manufacturing method of the semiconductor device which concerns on this embodiment. FIG. 10 is a top view illustrating a modification of the semiconductor device illustrated in FIG. 1. It is a side view which shows the state at the time of use of the semiconductor device shown in FIG. It is a block diagram which shows the semiconductor device which concerns on 2nd Embodiment. It is a block diagram which shows the semiconductor device 3 which concerns on 3rd Embodiment. FIG. 9 is a top view of the semiconductor device illustrated in FIG. 8.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the drawings. FIG. 1 is a configuration diagram showing a semiconductor device 1 according to the present embodiment. 1 is also a cross-sectional view taken along the line II of FIG. 2 described later. As shown in FIG. 1, the semiconductor device 1 includes a semiconductor element 10, a first electrode member (first energizing member) 21, a second electrode member (second energizing member) 22, and a first solder (first joining member) 31. , And a second solder (second bonding member) 32 and a mold resin 40. The semiconductor device 1 has a configuration in which a semiconductor element 10, a first electrode member 21, a second electrode member 22, a first solder 31, and a second solder 32 are molded with a mold resin 40. Next, each part will be described.

The semiconductor element 10 is a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor) or a diode that is driven by a current supplied through the electrode members 21 and 22. The first electrode member 21 is an energization member laminated on the semiconductor element 10. The second electrode member 22 is a current-carrying member that is stacked on the opposite side of the first electrode member 21 with the semiconductor element 10 interposed therebetween. These electrode members 21 and 22 are made of a material having good electrical conductivity and thermal conductivity, and are made of, for example, copper, aluminum, or an alloy thereof. The electrode members 21 and 22 are electrically connected to wiring members outside the semiconductor device 1 and function as power conversion devices.

  The first solder 31 is a bonding member for bonding the main surface on one side of the semiconductor element 10 and the first electrode member 21. Similarly, the second solder 32 is a bonding member for bonding the other main surface of the semiconductor element 10 and the second electrode member 22. Specifically, the first solder 31 and the second solder 32 are sheet solders, but may be solder pastes. When the semiconductor element 10 is an IGBT, the main surface connected to the first solder 31 is an emitter electrode, and the main surface connected to the second solder 32 is a collector electrode.

  Furthermore, in the semiconductor device 1 according to the present embodiment, the second electrode member 22 has a plurality of support posts 22a to 22d. FIG. 2 is a top view of the semiconductor device 1 shown in FIG. 2, illustration of the 1st electrode member 21 and the mold resin 40 is abbreviate | omitted for convenience of explanation.

As shown in FIG. 1, the plurality of pillars 22 a to 22 d are formed of the semiconductor element 10 and the electrode members 21 and 2.
2 is a cylindrical member having an insulating property (for example, a resin such as PPS (Polyphenylenesulfide)) extending in the stacking direction. These struts 22a to 22d are members whose elastic modulus (elastic modulus at the temperature during transfer molding) is larger than that of the semiconductor element 10, the first and second electrode members 21 and 22, and the first and second solders 31 and 32. It is comprised by. Moreover, these support | pillars 22a-22d are integrally formed with the board part 22e of the 2nd electrode member 22 by the metal-resin joining technique etc. FIG.

  As shown in FIG. 2, the plurality of pillars 22 a to 22 d are located in a region B (region on the second electrode member 22 in plan view) different from the arrangement region A of the semiconductor element 10. Furthermore, in this embodiment, the support columns 22a to 22d are disposed in a region C that contacts the semiconductor element 10 when the semiconductor element 10 rotates. Here, “arranged in the area C in contact with” not only includes the case where the entire columns 22 a to 22 d are disposed in the area C, but also includes that part of the columns 22 a to 22 d is disposed in the area C. It is. The case where the semiconductor element 10 is rotated refers to the case where the semiconductor element 10 is rotated with reference to the center O of the semiconductor element 10.

  In addition, the plurality of support columns 22 a to 22 d are arranged at non-uniform intervals in the rotation direction of the semiconductor element 10. If it demonstrates concretely, the space | interval a of the rotation direction of the 1st support | pillar 22a and the 2nd support | pillar 22b will differ from the space | interval b of the rotation direction of the 1st support | pillar 22a and the 4th support | pillar 22d. Similarly, the interval a in the rotation direction between the third column 22c and the fourth column 22d is different from the interval b in the rotation direction between the third column 22c and the second column 22b. In this embodiment, the interval a in the rotation direction between the first column 22a and the second column 22b is the same as the interval a in the rotation direction between the third column 22c and the fourth column 22d. The spacing may be different. Similarly, the interval b in the rotation direction between the first column 22a and the fourth column 22d is the same as the interval b in the rotation direction between the third column 22c and the second column 22b, but these intervals are different. May be. That is, the plurality of support columns 22a to 22d according to the present embodiment need not be the same in each interval but may be different in some portions, and “non-uniform” means that at least some of the intervals are different. It is a concept that means

  Note that it is preferable that at least one of the plurality of support columns 22a to 22d exists for each side when the semiconductor element 10 has a quadrangular shape in plan view. As a result, the plurality of pillars 22a to 22d are positioned so as to surround the semiconductor element 10, and when the semiconductor element 10 is placed on the second solder 32, positioning can be performed without a special jig. Because.

  FIG. 3 is a first side view showing the method for manufacturing the semiconductor device 1 according to the present embodiment, and FIG. 4 is a second side view showing the method for manufacturing the semiconductor device 1 according to the present embodiment.

  As shown in FIG. 3, in manufacturing the semiconductor device 1, first, the second solder 32 is placed on the second electrode member 22, and the semiconductor element 10 and the first solder 31 are placed in this order on the second solder 32. It is mounted with. Further, when these components 10, 31, and 32 are placed on the second electrode member 22, the plurality of columns 22 a to 22 d play a role of positioning, and the semiconductor element 10 can be easily positioned in the lateral direction. It becomes.

  Next, the first electrode member 21 is placed on the first solder 31 and laminated. Then, with the first electrode member 21 placed, these composites are put into a soldering furnace. As a result, the solders 31 and 32 are melted and solidified to be soldered. At this time, by placing a weight on the first electrode member 21, the first electrode member 21 is pressed against the plurality of support columns 22a to 22d, and the height of the semiconductor device 1 is determined.

Thereafter, as shown in FIG. 4, resin sealing is performed in a transfer molding process. In the transfer molding process, first, the semiconductor device 1 is placed in the second mold die 52. Next, the first mold 51 is slid from below and lowered downward, so that both molds 51 and 52 match. After the molds 51 and 52 are matched, a thermosetting mold resin 40 such as an epoxy resin is injected from the opening 53 in a high pressure state. Thereby, the composite is molded, and the semiconductor device 1 is completed.

  A clamping force F1 is applied to the first mold 51 from above, and a clamping force F2 is applied to the second mold 52 from below. Here, in this embodiment, the elastic modulus of the pillars 22a to 22d at the temperature at the time of transfer molding is determined by the semiconductor element 10, the first and second electrode members 21 and 22, and the first and second solders 31 and 32. Is also big. For this reason, even if the mold clamping forces F1 and F2 are increased, the semiconductor element 10 can be hardly damaged. Moreover, the contact surface pressure of the mold dies 51 and 52 can be increased to suppress leakage of the mold resin 40.

  Next, a modification of the semiconductor device 1 according to this embodiment will be described. FIG. 5 is a top view showing a modification of the semiconductor device 1 shown in FIG. In FIG. 5, illustration of the first electrode member 21 and the mold resin 40 is omitted for convenience of explanation.

  As shown in FIG. 5, the semiconductor device 2 according to the modification includes support columns 22 f to 22 i made of quadrangular columns. As described above, the pillars 22f to 22i are not limited to cylinders but may be square pillars as long as the movement of the semiconductor element 10 in the rotation direction can be restricted. Furthermore, the support columns 22f to 22i are not limited to square columns, and may be polygonal columns or elliptic columns.

  Thus, according to the semiconductor device 1 according to the present embodiment, the second electrode member 22 includes the plurality of support posts 22a to 22d extending in the stacking direction of the semiconductor element 10 and the first and second electrode members 21 and 22. , 22f to 22i, the height of the semiconductor device 1 is controlled by the columns 22a to 22d and 22f to 22i. Further, since the plurality of pillars 22a to 22d and 22f to 22i are arranged at non-uniform intervals in the rotation direction in the region C that contacts the semiconductor element 10 when the semiconductor element 10 rotates, the semiconductor element 10 The pillars 22a to 22d and 22f to 22i are non-uniformly arranged regardless of the clockwise or counterclockwise direction, so that the semiconductor element 10 is likely to abut on the pillars and the rotational direction is displaced. Be regulated. In addition, since the columns 22a to 22d and 22f to 22i do not need to be pulled out in a subsequent process like a jig, the semiconductor element 10 is broken due to the jig pulling out while controlling the height control and displacement in the rotation direction. Can be suppressed. Therefore, the possibility of failure of the semiconductor element 10 can be reduced.

  In particular, since the displacement in the rotation direction is restricted, it is possible to prevent a situation in which the terminal for the semiconductor element 10 to be displaced in the rotation direction and wire bonding is buried with the first solder 31 or the second solder 32. it can.

  In addition, the plurality of support posts 22 a to 22 d and 22 f to 22 i are configured by members whose elastic modulus is larger than that of the semiconductor element 10, the first and second electrode members 21 and 22, and the first and second solders 31 and 32. Therefore, in the transfer molding process, the mold clamping forces F1 and F2 of the mold dies 51 and 52 can be more easily transmitted to the support columns 22a to 22d and 22f to 22i than to the semiconductor element 10 side. Thereby, even if the contact surface pressure of the mold dies 51 and 52 is increased, the semiconductor element 10 can be hardly damaged, and the contact surface pressure of the mold dies 51 and 52 is increased to suppress the leakage of the mold resin 40. it can. In addition, post-processes such as polishing for removing the resin 40 due to leakage of the mold resin 40 can be omitted.

  Moreover, since the electrode members 21 and 22 do not have a through hole unlike the heat radiating member described in Patent Document 1, it is possible to increase the heat radiating area and improve the heat radiating property.

  Note that, in such a semiconductor device 1, the amount of heat dissipated from the semiconductor element 10 increases as the power during use increases, and may reach a high temperature. Therefore, a cooler is used when the semiconductor device 1 is used. The cooler is made of a material having good thermal conductivity, and is made of, for example, aluminum or an aluminum alloy. Such a cooler is manufactured by a die casting method, an extrusion method, a friction stir welding method, or the like.

  FIG. 6 is a side view showing a state when the semiconductor device 1 shown in FIG. 1 is used. As shown in FIG. 6, the semiconductor device 1 is disposed so as to be sandwiched between the two coolers 61 and 62 from above and below during use. Further, insulating layers 71 and 72 are provided on the semiconductor device 1 side of the coolers 61 and 62 in order to ensure insulation from the semiconductor device 1. The insulating layers 71 and 72 are made of a ceramic plate such as aluminum nitride or silicon nitride. Moreover, the insulating layers 71 and 72 may be epoxy resins mixed with various fillers. In the case where ceramic plates such as aluminum nitride and silicon nitride are used as the insulating layers 71 and 72, heat radiation grease is applied between the coolers 61 and 62 and the insulating layers 71 and 72.

  Because of such a configuration, the semiconductor device 1 is secured by the insulating layers 71 and 72 while being cooled by the coolers 61 and 62.

  Next, a second embodiment of the present invention will be described. The semiconductor device according to the second embodiment is the same as that of the first embodiment, but the configuration is partially different. Hereinafter, differences from the first embodiment will be described.

  FIG. 7 is a configuration diagram illustrating the semiconductor device 2 according to the second embodiment. As shown in FIG. 7, in the semiconductor device 2 according to the second embodiment, a plurality of through holes 22 j are formed in the plate portion 22 e of the second electrode member 22. The positions of the through holes 22j correspond to the positions of the plurality of pillars 22a to 22d, and the plurality of pillars 22a to 22d are arranged in a state of being inserted into the plurality of through holes 22j. Thereby, the lower surfaces 22k of the plurality of columns 22a to 22d are flush with the lower surface 22l of the plate portion 22e. For this reason, the height of the semiconductor device 2 is more stably controlled by the heights of the first electrode member 21 and the plurality of support columns 22a to 22d.

  As described above, according to the semiconductor device 2 according to the second embodiment, the possibility of failure of the semiconductor element 10 can be reduced as in the first embodiment. Subsequent steps such as polishing can be omitted.

  Furthermore, according to the second embodiment, the second electrode member 22 has a plurality of through holes 22j, and the plurality of support columns 22a to 22d are arranged in a state of being inserted into the plurality of through holes 22j. The height of the semiconductor device 2 is defined by the height of the first electrode member 21 and the support posts 22a to 22d, and the variation in the height of the semiconductor device 2 can be further suppressed.

  Moreover, since the variation in the height of the semiconductor device 2 can be suppressed, when the semiconductor device 2 is cooled by being sandwiched between the coolers 61 and 62, the contact condition between the semiconductor device 2 and the coolers 61 and 62 due to the difference in height. However, it is also possible to suppress a situation in which the cooling effect varies.

  Next, a third embodiment of the present invention will be described. The semiconductor device according to the third embodiment is the same as that of the second embodiment, but the configuration is partially different. Hereinafter, differences from the second embodiment will be described.

FIG. 8 is a configuration diagram showing the semiconductor device 3 according to the third embodiment, and FIG. 9 is a top view of the semiconductor device 3 shown in FIG. In FIG. 9, the mold resin 40 is not shown for convenience of explanation. 8 is also a II-II cross-sectional view of FIG.

  As shown in FIG. 8 and FIG. 9, the plurality of support columns 22m to 22p according to the third embodiment have cutout portions 22m1 to 22p1, respectively. In the third embodiment, the first electrode member 21 is formed to be slightly smaller than the second electrode member 22 when viewed from above, and the first electrode member 21 is aligned with the notches 22m1 to 22p1. Is arranged in. For this reason, the positioning of the first electrode member 21 is facilitated in the manufacturing process.

  As described above, according to the semiconductor device 3 according to the third embodiment, the possibility of failure of the semiconductor element 10 can be reduced as in the second embodiment. Subsequent steps such as polishing can be omitted. In addition, it is possible to further suppress the variation in the height of the semiconductor device 2 and to suppress the occurrence of variations in the cooling effect.

  Furthermore, according to 3rd Embodiment, the some support | pillars 22m-22p have the notch parts 22m1-22p1, respectively, and the 1st electrode member 21 is arrange | positioned in the state corresponding to the notch parts 22m1-22p1. Yes. Thus, since the 1st electrode member 21 corresponds to the notch parts 22m1-22p1, the positioning of the 1st electrode member 21 can be facilitated and it can lead to the improvement of productivity.

  As described above, the present invention has been described based on the embodiments. However, the present invention is not limited to the above embodiments, and modifications may be made and combinations of the embodiments may be made without departing from the spirit of the present invention. It may be.

  For example, in the above embodiment, the columns 22a to 22d, 22f to 22i, and 22m to 22p are configured as a part of the second electrode member 22, but not limited thereto, configured as a part of the first electrode member 21. May be. In other words, the columns 22a to 22d, 22f to 22i, and 22m to 22p may be provided on at least one of the first electrode member 21 and the second electrode member 22.

  Moreover, in 2nd and 3rd embodiment, although the through-hole 22j is formed in the 2nd electrode member 22, when not only this but the 1st electrode member 21 has the support | pillars 22f-22i, 22m-22p, May be formed on the first electrode member 21. That is, the through-hole 22j should just be formed in the electrode member 21 and 22 by the side which has support | pillar 22f-22i, 22m-22p.

  Moreover, in 3rd Embodiment, although the 2nd electrode member 22 has the support | pillars 22m-22p and the 1st electrode member 21 is arrange | positioned in the state corresponding to the notch parts 22m1-22p1, the 1st electrode member 21 is arranged. May have the support columns 22m to 22p, the second electrode member 22 may be disposed in a state of matching the notches 22m1 to 22p1. That is, it is only necessary that the electrode members 21 and 22 on the side of the first electrode member 21 and the second electrode member 22 that do not have the plurality of support columns 22m to 22p be arranged in a state of being aligned with the notches 22m1 to 22p1.

1-3 ... Semiconductor device 10 ... Semiconductor element 21 ... 1st electrode member (1st electricity supply member)
22 ... 2nd electrode member (2nd electricity supply member)
22a to 22d, 22f to 22i, 22m to 22p ... column 22e ... plate portion 22j ... through hole 22k ... bottom surface 22l of plate column ... bottom surface 22m1-22p1 of plate portion ... notch 31 ... first solder 32 ... second solder 40 ... mold resin 51, 52 ... mold die 53 ... openings 61, 62 ... coolers 71, 72 ... insulating layer A ... arrangement area B of semiconductor element 10 ... area C different from arrangement area A ... semiconductor element 10 rotates The regions a, b... That contact the semiconductor element 10

Claims (4)

A semiconductor element, a first energization member laminated on the semiconductor element, a second energization member laminated on the opposite side of the first energization member across the semiconductor element, the semiconductor element and the first energization member A first joining member that joins, and a second joining member that joins the semiconductor element and the second current-carrying member,
At least one of the first and second energization members has a plurality of insulating pillars extending in the stacking direction of the semiconductor element and the first and second energization members,
The plurality of pillars are located in a region different from the region where the semiconductor element is disposed between the first and second current-carrying members and are in contact with the semiconductor element when the semiconductor element rotates In the semiconductor device, each of them is arranged at non-uniform intervals in the rotation direction. Of the first and second energization members, the energization member on the side having the plurality of support columns has a plurality of through holes,
The semiconductor device according to claim 1, wherein the plurality of support columns are arranged in a state of being inserted into the plurality of through holes. The plurality of struts are configured by members having an elastic modulus larger than that of the semiconductor element, the first and second energization members, and the first and second joining members. The semiconductor device according to claim 2. Each of the plurality of struts has a notch,
4. The current-carrying member on the side that does not have the plurality of columns among the first and second current-carrying members is disposed in a state of being aligned with the notch portion. 5. The semiconductor device according to any one of the above.

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