JP2011189032A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve data transmission speed (updating cycle period) of a particular peripheral base board when transmitting the data to the peripheral base board from a sub base board in a game machine having a serial communication route with a daisy chain structure. <P>SOLUTION: The peripheral base boards are classified into a type (44-1) which needs high updating cycle period and a type (44-2, 44-3) which does not. A latch signal is added to the former and, by separating it from the daisy chain structure, the data transmission time is shortened and the updating cycle period is improved. The daisy chain structure part is controllable in a conventional way. Since the structure with the latch signal added thereto can transmit the data without depending on the number of data of the daisy chain structure, the time for data transmission can be less than the one carried out by the daisy chain structure. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a serial data communication system in a gaming machine such as a ball game machine or a revolving game machine (slot machine).

  A ball ball game machine (a so-called pachinko machine) installed in a game machine installation store or the like uses a game ball (also called a game medium) to play a game. The borrowed game balls are launched to the board surface provided on the game board of the ball game machine, and a predetermined number of game balls are paid out each time the game balls enter a predetermined winning opening. The game balls to be paid out are called prize balls.

There are the following winning holes provided on the board of the ball game machine.
(1) Ordinary winning device (2) Start chucker (starting winning device)
(3) Attacker (Large winning device)
(4) Through chucker (winning chucker)

The start chucker (starting winning device) is also called a specific winning device. When a game ball is accepted by the start chucker (start prize-winning device) and enters the winning state, the prize ball is paid out and an electronic lottery is performed. In the case of winning, the game state is advantageous to the player from the normal state. Thus, the attacker (large winning device) is opened.
The attacker (large winning device) is also called a special winning device.

  The through chucker (winning chucker) does not pay out the winning ball directly, but is included in the winning slot in this specification. When it is detected that the game ball has passed through the through-chucker (winning chucker), an electronic lottery is performed. The time is released to make it easier for the game ball to enter the start chucker (start prize winning device). The game ball received by the through chucker (winning chucker) moves on the board as it is, and is received by another winning port or a discharge port (out port) described below.

  In addition to the prize opening, a discharge port (out port) is provided on the board surface of the ball game machine. The discharge port (out port) is an opening provided in the lower part of the guide rail (portion where the game balls are collected by gravity) arranged in a spiral shape to partition the game area on the board surface. Is for accepting a game ball that has not been accepted by any of the normal winning device, start chucker (start winning device), and attacker (large winning device), and discharging it out of the board.

  As described above, an electronic lottery is performed when a game ball is received in a specific winning opening of the ball game machine. In many cases, the lottery uses a random number generated by hardware such as a counter or a register or a random number generated by a counter executed by software.

  In order to perform processing related to a game including electronic lottery, the ball and ball gaming machine obtains processing information generated by a control unit that performs electrical game control processing and generates main processing information. Thus, a sub-control unit that performs control to perform a predetermined output mode process is provided, and further, peripheral boards such as a payout control unit, a game ball payout device, an electrical decoration control unit, and an acoustic control unit connected thereto are provided.

  Boards and devices such as a control unit, sub-control unit, and peripheral board connected in the gaming machine transmit and receive data using a specific communication path. There are parallel communication and serial communication as transmission methods. Recently, serial communication is often used for high-speed communication and cost reduction.

  When serial communication is performed, data including a large number of bits can be easily transferred by connecting each board to a chain structure.

JP 2004-328369 A JP 2004-181203 A JP 2007-236498 A

  By the way, in the case of chain-structured serial communication, there is a problem that the communication speed (in other words, the data update rate) becomes slow. This problem becomes more serious as the number of connected substrates increases.

This will be described with reference to FIG.
FIG. 17A is a schematic diagram of a serial communication system having a chain structure. Reference numerals A to C denote substrates for receiving data. The number of connected substrates is 3 (of course this is an example, and the number may be 2, 4, 5,...). The numbers in the boards indicate the data that each board should receive. That is, data 1 is necessary for the substrate A. Similarly, data 2 and 3 correspond to substrate B and substrate C, respectively.

  In order to simplify the description, hereinafter, the substrate A, the substrate B, and the substrate C are simply referred to as “A”, “B”, and “C”. Similarly, data 1, data 2, and data 3 are simply written as “1”, “2”, and “3”.

  As can be seen from the figure, the three substrates are connected in the order of “C”, “B”, and “A”. Serial data is input to the substrate C, and the serial data propagates from “C” to “A” by a clock (not shown). As can be seen from this, the first data to be input is “1”, and the order is “2” and “3” below. Then, when “1” reaches “A”, “A” takes “1” into the inside thereof by a latch signal (not shown). The same applies to “B” and “C”.

  This will be further described with reference to FIG. This figure is a timing chart showing data propagation. The horizontal axis indicates time, and the vertical axis indicates the state of data propagation (what data is received by each board). The lower square on the horizontal axis indicates transmission data. The time required to transmit one piece of transmission data is T. It is assumed that the transmission data “1”, “2”, and “3” all have the same time, and when the last bit included in each transmission data is transmitted, the transmission is completed at that clock. For example, it is assumed that transmission of “1” is completed at the symbol t (between “1” and “2”) in FIG.

  Reference numerals T1 to T6 indicate a state in which data is transmitted to a shift register (not shown) of the board “A” in response to transmission data. The example in the figure shows six data transmissions, but this is because only a part is shown, and it goes without saying that there are actually more.

  Reference signs T11 to T14 indicate how data is propagated from “C” to “B”. From “C” to “B”, the data received by “C” in the previous period is transferred. Similarly, codes T21 and T22 indicate how data is propagated from “B” to “A”. From “B” to “A”, the data received by “B” in the previous period is indicated. Transferred.

  Since the data required for the substrate A, the substrate B, and the substrate C are the data 1, the data 2, and the data 3, the data is arranged in this correspondence when the transmission of the codes T3 and T6 is completed. By supplying a latch signal (not shown) to the boards A to C at time t1 when the data is collected, the data 1 to 3 are respectively fetched. In this way, each board | substrate AC can acquire the required data 1-3, respectively.

  As can be seen from the above description and FIG. 17B, the data update period of each of the substrates A to C is 3T. This corresponds to the number of boards connected in a chain, and if n boards are connected in a chain, the data update cycle is nT (T means one data transmission time). .

  In other words, in the case of chain structure serial communication, the communication speed (in other words, the data update cycle) becomes slower (longer) as the number of connected boards increases. If the communication speed is to be increased, the time T required for one data transmission must be reduced by increasing the clock speed. For this purpose, a higher-speed IC is used, leading to an increase in cost and a problem of being easily affected by noise.

  On the other hand, the required update cycle of data differs for each board. For example, the update cycle of a substrate that mainly performs electronic processing such as display control of an LED or LCD is short, but the update cycle of a substrate that performs mechanical control such as control of an accessory is long. If a serial communication system is designed in accordance with a board with a short update cycle, problems such as an increase in cost occur, and the update cycle is too high for a board with a long update cycle, which is wasteful. On the other hand, if a serial communication system is designed in accordance with a substrate having a long update cycle, problems such as LED flickering and missing LCD images occur. Since the latter problem is unacceptable, it must be designed for a substrate with a short update cycle.

  The serial communication of the chain structure has some merits, but on the other hand, the above-mentioned problems occur due to a mixture of substrates having different necessary update cycles.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a gaming machine that can set a different update cycle for each board while adopting serial communication of a chain structure.

A gaming machine according to the present invention is connected to a control unit that executes control related to a game, a sub-control unit that executes predetermined processing based on information generated by the control unit, and the control unit or the sub-control unit. A plurality of peripheral boards
The control unit or the sub-control unit and the plurality of peripheral boards are connected by a serial transmission line that transmits a serial signal,
The plurality of peripheral substrates are divided into one or a plurality of first group peripheral substrates and a second group of peripheral substrates more than the first group peripheral substrates,
The first group of peripheral boards is chain-connected to the serial transmission line, the second group of peripheral boards is chain-connected to the serial transmission line separately from the first group of peripheral boards,
further,
A first group data generator for generating data to be sent to the first group of peripheral substrates;
A second group data generator for generating data to be sent to the second group of peripheral substrates;
A selection unit that selects either the data generated by the first group data generation unit or the data generated by the second group data generation unit and sends the data to the serial transmission line;
When the data generated by the first group data generation unit is selected by the selection unit, a signal for transmitting a serial signal of the serial transmission line in the chain connection of the peripheral substrate of the first group (for example, A first group control signal generator for sending a clock (clock) and a signal (for example, a latch signal) for the first group of peripheral boards to receive the data, to the first group of peripheral boards;
When the data generated by the second group data generation unit is selected by the selection unit, a signal for transmitting the serial signal of the serial transmission line in the chain connection of the peripheral substrate of the second group (for example, A second group control signal generator for sending a signal (for example, a latch signal) for the second group of peripheral boards to receive the data to the second group of peripheral boards,
The selection unit selects more data generated by the first group data generation unit than data generated by the second group data generation unit.

  Chain connection means that n (n stages) peripheral substrates are connected (connected) in a chain. Generally, the chain connection is applied to the connection of two or more peripheral boards, and the connection of one peripheral board is a simple connection and is not usually called “chain connection”. However, here, even the connection of one peripheral board is called a chain connection.

  The selection unit may select the data generated by the second group data generation unit once and then repeatedly select the data generated by the first group data generation unit. By doing so, the data update rate of the first group can be made higher than that of the second group (see FIG. 9, FIG. 11 and its description).

The data generated by the second group data generation unit includes a plurality of partial data (for example, “2” and “3” in FIG. 12) corresponding to the plurality of peripheral substrates of the second group,
The selection unit selects one of the plurality of partial data, then selects data generated by the first group data generation unit, and then selects another of the plurality of partial data. Good (see FIG. 12 and its description).

  The selection unit repeatedly selects the data generated by the first group data generation unit a plurality of times while selecting one of the plurality of partial data and the other of the plurality of partial data. (See FIG. 13 and its description).

The invention further provides:
A third group data generator for generating data to be sent to the third group of peripheral substrates;
When the data generated by the third group data generation unit is selected by the selection unit, a signal for transmitting a serial signal of the serial transmission line in the chain connection of the peripheral boards of the third group and the first A third group control signal generation unit for sending a signal for receiving the data to the third group of peripheral boards to the third group of peripheral boards,
Regarding the peripheral substrates of the first group to the third group (the number of peripheral substrates of the first group) <(the number of peripheral substrates of the second group) <(the number of peripheral substrates of the third group) And
Regarding selection of data by the selection unit,
(Number of selections of data generated by the first group data generation unit)> (Number of selections of data generated by the second group data generation unit)> (Number of selections of data generated by the third group data generation unit) The relationship is established.

  According to this invention, the peripheral board is divided into those that require high update frequency and those that do not, and each has a different chain structure, and the number of transmissions is increased with respect to the former, thereby increasing the former data update cycle. Can be shortened. Thereby, data can be transmitted at an appropriate speed according to the necessity for each peripheral substrate.

It is a perspective view which shows the surface structure of a game machine. It is a perspective view which shows the back surface structure of a game machine. It is a figure (front view) which shows the mode of the board surface seen from the player. It is a functional block diagram of the gaming machine according to the embodiment of the invention. It is explanatory drawing of the hardware constitutions of a sub-control part. It is a functional block diagram of the serial communication system which concerns on embodiment of invention. It is explanatory drawing of the transmission data and reception data which concern on embodiment of invention. It is a process flowchart of the serial communication part which concerns on embodiment of invention. It is operation | movement explanatory drawing (timing chart) of the serial communication part which concerns on embodiment of invention. It is operation | movement explanatory drawing (what simplified FIG. 6) of the serial communication system which concerns on embodiment of invention. It is detailed operation explanatory drawing (timing chart) of the serial communication part which concerns on embodiment of invention. It is another detailed operation explanatory view (timing chart) of the serial communication part concerning an embodiment of the invention. It is another detailed operation explanatory view (timing chart) of the serial communication part concerning an embodiment of the invention. It is other operation | movement explanatory drawing (functional block diagram) of the serial communication system which concerns on embodiment of invention. It is another process flowchart of the serial communication part which concerns on embodiment of invention. FIG. 16 is a detailed operation explanatory diagram (timing chart) of the serial communication unit (the one in FIG. 15) according to the embodiment of the present invention. It is the block diagram and detailed operation explanatory drawing (timing chart) of the serial communication part of the conventional gaming machine.

An outline of the structure of the ball game machine will be described with reference to FIGS. 1 and 2.
First, the external structure of the gaming machine according to the embodiment of the present invention will be described with reference to FIG.
The outer frame 50 is a wooden frame member having a vertical rectangular shape for fixing to an installation location (island facilities or the like) provided in a gaming machine installation sales shop.
The main body member 51 is a member that is provided inside the outer frame 50 and serves as a longitudinal rectangular gaming machine base body that is rotatably attached to the outer frame via a hinge portion 51a. The main body member 51 is formed in a frame shape and has a space portion inside thereof.
The opening frame door 52 is mounted on the front surface of the main body member 51 on the front side of the gaming machine so as to be openable and closable, and is configured in a frame shape so that the inside is an opening. It is a door member.
A transparent plate member made of glass or resin is provided at the opening of the opening frame door 52, and an electrical decoration 52a, a speaker 52b, and the like are attached in the vicinity of the opening.
A game board (not shown in FIG. 1), which will be described later, is detachably attached to the main body member 51 using a predetermined fixing member so as to face the space of the main body member 51. After the game board is mounted on the main body member 51, the game area can be observed from the opening.

The door 53 with a ball tray is a door member provided at least with a ball tray for storing a game ball attached to the lower part of the main body member 51 on the front surface of the gaming machine so as to have a lock function and be openable and closable. In addition, the following members are attached to the door with a ball tray in the present embodiment.
(1) A ball tray in which a plurality of game balls can be stored and a passage for guiding the game balls to the firing drive device 48 is provided.
(2) A rotary operation handle 48b for performing an operation of launching the stored game ball guided to the launch drive device 48 to a game area provided on the board surface 11 of the game board 10.
(3) A ball lending-related operation unit provided with buttons for instructing a read-in related to reading a paid card and a lending process related to a borrowed game ball.
(4) A storage ball discharge operation button for a ball tray for releasing the game ball stored in the ball tray into a game ball collecting container (common name, dollar box).

Next, an internal configuration of the gaming machine according to the embodiment of the present invention will be described with reference to FIG.
As described above, reference numeral 40 denotes a control unit that is provided via the main body member 51 or the game board 11 or a support member attached thereto, and performs electrical game control processing to generate main processing information.
40b is provided through the main body member 51 or the game board 11 or a support member provided to the main body member 51, or a sub member that performs control to perform predetermined output mode processing by obtaining processing information generated by the control unit 40. It is a control unit.
A payout control unit 42 performs payout control of prize balls.
43 is a game ball payout device for paying out game balls.
Reference numeral 44 denotes an electric decoration control unit that controls a lamp and electric decoration 52a (not shown).
An acoustic control unit 46 generates sound by controlling and driving the speaker 52b.
49 is a control device for controlling the firing drive device 48, and is a launch control device for controlling the launch of a game ball to a game area provided on the board surface via a rotary operation handle 48b.

FIG. 3 is a front view of the game board of the gaming machine.
In FIG. 3, reference numeral 11 denotes a board surface of the game board 10. The board surface 11 changes the direction of the guide rail 12, the discharge port (out port) 13 that guides the game ball that has fallen through the substantially circular game area defined by the guide rail 12, and the direction of the game ball that moves in the game area. It is a rectangular board surface provided with a plurality of obstacles such as the nailing 14 and the windmill 14a.

  The game area of the board surface 11 described above is partitioned and formed into a substantially circular shape by the guide rail 12 (including a sliding part for sliding the game ball and a regulation part for regulating the game ball), and the movement of the game ball that has been launched It is an area that regulates the range. A restricting portion is provided to follow the sliding portion. The sliding portion is arranged on the board surface 11 in a spiral as a whole.

  The discharge port (out port) 13 is a collection opening provided at a position where the game balls thrown into the game area converge.

  The game nails as the obstacles 14 are a plurality of rod-shaped members that are driven into appropriate positions on the board surface 11 in order to make the movement direction irregular by contacting with the game ball or to restrict the movement direction.

Reference numeral 30a denotes a variable display device (center accessory) that is provided at the center or slightly above the game area and has one or more variable display sections such as an effect display lamp and an LCD (liquid crystal display device).
30b is a through chucker (winning chucker).
30c is a normal winning device having a normal winning opening.
30d is a start chucker (start winning device) having a start winning opening.
30e is an attacker having a big prize opening.
In the following description, 30b to 30d may be collectively referred to as a winning opening 30 or the like.
Although not shown, the ball passage detectors 20b, 20c, and 20d are provided inside the 30b, 30c, and 30d (the reference numerals in parentheses in the figure mean that).

The start winning device of the start chucker 30d is also called a specific winning device, and the big winning device of the attacker 30e is also called a special winning device.
The start chucker (start winning device) 30d is provided with movable pieces on both sides for expanding and contracting the opening range of the winning opening, making a variable display by winning a game ball and winning a prize for a player. Device.
The attacker (large winning device) 30e is driven and controlled by an open state that exposes the winning port and a closed state that closes the winning port. This is a winning device that allows more prize balls to be obtained.

FIG. 4 is a functional block diagram of the gaming machine according to the embodiment of the present invention.
Reference numeral 40 denotes a control unit (also referred to as a “main board”) that performs electrical game control processing and generates main processing information. The control unit 40 moves (flows down) the game area and receives signals from the ball passage detectors 20b to 20d that detect the game balls that have passed through the winning holes 30b to 30d, respectively, and passes the gaming balls through the winning holes 30b to 30d. A winning determination unit 40a for performing a lottery / determination in accordance with this is included.

Reference numeral 42a denotes a first display control unit that controls the lighting of a first display device (such as a 7-segment display) provided in the variable display device (center accessory) 30a.
Reference numeral 42b denotes a second display control unit that controls lighting of a second display device (such as a lamp) provided in the variable display device (center accessory) 30a.
When the lottery is performed by winning the start chucker, the control unit 40 displays the lottery result regarding the special symbol on the first display device (7-segment display) 43a provided on the game board, and the lottery result. And a variation time of a special symbol (a variation symbol on the liquid crystal display device) in a variable display device (liquid crystal display device) 30a described later (the variation time of the special symbol is determined by lottery) to a later-described sub-control unit 40b. To do. The sub-control unit 40b varies the special symbol based on the received lottery result and the variation time of the special symbol.
When the jackpot is reached, the control unit 40 knows the variation time sent to the sub-control unit 40b, and when the control unit 40 finishes timing the variation time, the jackpot processing (the attacker 30e is released). Process).
By the way, when winning the through chucker 30b, the lottery result regarding the normal symbol is displayed on the second display device (lamp) 43b provided on the board surface, and in the case of winning, the movable piece of the start checker 30d is released. . At the same time, the lottery result regarding the normal symbol is displayed also in a predetermined area of the variable display device (liquid crystal display device) 30a.

  The LCD of the variable display device (center accessory) 30a is a device that variably displays a specific symbol related to the big hit state and also displays a background image, various characters, and the like in an animated manner. When it is detected that the game ball has passed through the start chucker (start winning device) 30d, the displayed symbol fluctuates for a predetermined time, and the lottery is drawn when the game ball start chucker (start winning device) 30d passes. The stop symbol determined by the random number for lottery is displayed on the LCD and stopped. The attacker 30e includes an opening / closing plate that can be opened forward. When the symbol after the LCD fluctuation stops is a winning symbol such as “777”, a special game called “big hit” is started, and the opening / closing plate of the attacker 30e is opened a predetermined number of times. After the opening / closing plate of the attacker 30e is opened, the opening / closing plate is closed when a predetermined time elapses or when a predetermined number of game balls are won.

42 is a payout control unit that receives the signal of the winning determination unit 40a and controls the game ball payout device 43 according to the game balls passing through the winning holes 30b to 30d and / or according to the lottery / determination result. .
43 is a game ball payout device provided with a driving source for paying out a predetermined number of game balls according to the result of the lottery / determination according to the game balls passing through the winning openings 30b to 30d and / or as the game profits. .

40b is a sub-control unit (also referred to as “sub-board”) that performs control to perform predetermined output mode processing including effects such as blinking of light and generation of sound by obtaining processing information generated by the control unit 40. It is. The sub-control unit 40b transmits serial data to peripheral substrates such as the peripheral substrate (electric decoration control unit) 44-1 and the peripheral substrate (movable body control unit) 44-2, and is input by the peripheral substrate 44-3. A serial communication unit 40S that receives and analyzes data is included.
Reference numeral 41 denotes a display control unit that controls the variable display device (liquid crystal display device) 30a to display an image related to the effect.

  Reference numeral 44-1 denotes an electric decoration control unit for controlling lighting of a lamp / electric decoration 52a and the like provided on the game board 10 or the gaming machine casing.

44-2 is a movable body control part which controls the movable body 52c provided in the game board 10. FIG.
The movable body 52c is an obstacle that changes the falling action of the game ball launched on the game board 10, and the state is changed by the processing of the sub-control unit 40b (the movable body 52c in FIG. 3). Is omitted). The movable body 52c, for example, moves back and forth between a normal state and a different state. The movable body is, for example, a flat plate shape, a cylindrical shape, a disk shape, a gear shape having irregularities, or the like. Although not shown, a power unit for driving the movable body 52c is provided. The movable body control unit 47 actually drives the power unit. The power unit is, for example, a driving device using electric power or magnetic force such as a motor or a solenoid, or a control device including a driving source.

  The illumination control unit 44-1 and the movable body control unit 44-2 are peripheral boards connected to the sub-control unit 40b including the CPU, and receive units (reception side receivers) that receive data from the CPU of the sub-control unit 40b. Device). In the following description, the electrical decoration control unit 44-1 and the movable body control unit 44-2 may be collectively expressed as a peripheral board without being distinguished. The embodiment of the present invention can be applied to, for example, an acoustic control unit in addition to an electrical decoration control unit and a movable body control unit, and n is an integer of 2 or more ( The present invention can be applied to an n-stage peripheral substrate or a receiving unit (receiving device). FIG. 4 is merely an example.

  44-3 is a peripheral board that receives data from an arbitrary device (input device) provided in the gaming machine and sends the data to the serial communication unit 40S. The device is not particularly limited, but is a jog dial input unit or the like.

  Together with 44-1 and 44-2, 44-3 is also referred to as a peripheral substrate. These are the same in that they are connected to and under the control of the serial communication unit 40S, but the peripheral boards 44-1 and 44-2 receive data from the serial communication unit 40S and based on the data, The peripheral board 44-3 is different in that it controls the devices such as the lamp / electrical decoration 52a and the movable body 52c under control, and transmits the received data to the serial communication unit 40S. In other words, the former is a receiver and the latter is a transmitter. Due to this difference in function, the peripheral boards 44-1 and 44-2 include an output unit, and the peripheral board 44-3 includes an input unit.

  In FIG. 4, the connection method is different between the peripheral board 44-1 and the peripheral boards 44-2 and 44-3. Only the peripheral board 44-1 is connected to the serial communication unit 40S (chain connection by one board), but the peripheral boards 44-2 and 44-3 are connected to the serial communication unit 40S by chain connection and loopback connection. ing. That is, data from the serial communication unit 40S is first received by the peripheral board 44-1 and also by the peripheral board 44-2. Then, the peripheral board 44-2 sends (transfers) the received data to the next peripheral board 44-3 as it is. The peripheral board 44-3 adds a value (data) from the device to the received data, and then sends (returns) the data to the serial communication unit 40S.

  The peripheral board 44-1 and the peripheral boards 44-2 and 44-3 have different communication systems. In other words, in the example of FIG. 4, there are provided two systems of communication routes respectively connected to common serial transmission data.

  Chain connection means that n (n stages) peripheral substrates are connected (connected) in a chain. The loop-back connection means that the connection including the serial communication unit 40S and the n (n stage) peripheral boards is circular, in other words, the peripheral board located at the end of the chain connection. The output is returned to the serial communication unit 40S as the transmission source.

  In general, chain connection is applied to connection of two or more peripheral boards, and the connection of one peripheral board is simply a connection and is not usually called “chain connection”. However, in the description of the embodiment of the present invention (that is, in the present specification), for the convenience of description, even if one peripheral board is connected as in the peripheral board 44-1 in FIGS. This is called chain connection. As will be described later, since the embodiment of the present invention relates to the difference in transmission speed between peripheral boards divided into groups, it is easier to explain that all groups are chain-connected. .

  It should be noted that a plurality of peripheral boards can be provided for the system of the peripheral boards 44-1, and chain-connected like the peripheral boards 44-2 and 44-3. A loopback connection is also possible.

  Note that the chain connection and the loop back connection of the peripheral boards can be applied not only to the sub-control unit 40b but also to the control unit 40. For example, with respect to the control unit 40, the display control units 42a and 42b and the payout control unit 42 may be chain-connected and loop-back connected. In the following, for the sake of convenience, description will be added by taking the connection of the sub-control unit 40b as an example.

  An acoustic control unit 46 generates sound effects / sounds through a speaker 52b provided in the gaming board 10 or the gaming machine casing.

  The winning devices 30b to 30d in which the game balls are provided in the game area are respectively provided with ball passage detectors (for example, switches) 20b to 20d so that the passage of the game balls can be detected. When the position of any of the winning devices 30b to 30d passes, the ball passage detectors 20b to 20d detect this, and the winning determination unit 40a performs a predetermined lottery / determination process. For example, when the ball passage detector 20b detects a game ball that has passed through the through chucker (winning chucker) 30b, a predetermined lottery is performed, and when winning, the start chucker (starting winning device) 30d is released for a predetermined time. That is, a pair of movable pieces provided opposite to each other on both the left and right sides of the start chucker (start winning device) 30d are opened outward. Then, when it is detected that the game ball has passed the start chucker (starting winning device) 30d, a predetermined lottery is performed, and when winning, the big winning device of the attacker 30e is released.

  FIG. 5 is an explanatory diagram of the hardware configuration of the sub-control unit 40b. The sub-control unit 40b shown in FIG. 4 is actually realized by the hardware configuration shown in FIG. In other words, a CPU (processing unit), a ROM (nonvolatile storage unit), a memory M (readable and writable storage unit, RAM), and an I / O (input / output device) are connected to a BUS composed of a plurality of bits (wiring). It is connected. The process related to the game executed by the sub-control unit 40b of FIG. 4 is executed by the CPU operating in accordance with a program stored in advance in the ROM of FIG. The processing of the serial communication unit 40S in FIG. 4 is the same. The CPU performs processing such as storing various data in the memory M when performing processing, reading out processing as necessary, performing processing, and storing again as necessary. The memory M may have received a battery backup, and in this case, the stored contents are retained even during power-off.

  The serial communication unit 40S is realized by software when the CPU executes a program, or is realized by hardware by combining a plurality of ICs.

  FIG. 6 is a connection diagram (conceptual diagram) between the serial communication unit 40 </ b> S and the peripheral board 44. The figure shows an example in which four peripheral boards 44-1 to 44-4 are connected. Therefore, although FIG. 4 and FIG. 6 differ in the point of a structure, there is no point which is substantially different in the point of the process. The peripheral boards 44-1, 44-2, and 44-4 include output units 44-1OUT, 44-2OUT, and 44-4OUT, respectively, and the peripheral board 44-3 includes an input unit 44-3IN.

  The peripheral board 44-1 and the peripheral boards 44-2 to 44-4 have different communication systems. In other words, in FIG. 6, as in FIG. 4, there are provided two systems of communication routes connected to common serial transmission data. For convenience of explanation, the former is referred to as a first group communication system, and the latter is referred to as a second group communication system.

  The first group of peripheral substrates 44-1 has only one peripheral substrate, but loopback connection is also possible. The serial communication unit 40S and the third peripheral board 44 of the second group are chain-connected and loop-back connected.

  In the figure, a square through which signals such as data and clocks pass means an output end or an input end, that is, a board and a harness connector. In the figure, adjacent output ends and input ends are connected by a harness (wiring).

  The output units 44-1OUT, 44-2OUT, 44-4OUT (hereinafter referred to as “output unit 44OUT” collectively when it is not necessary to distinguish them individually) are transmitted data from the serial communication unit 40S (see FIG. 7 (a)), and the data contained therein (output data in FIG. 7A) is acquired. Peripheral substrates 44-1, 44-2, 44-4 (hereinafter, these are collectively referred to as “peripheral substrate 44a”) perform predetermined control based on the acquired data. The output unit 44OUT includes a serial-parallel converter (not shown) that converts serial data into parallel data, and a register (not shown) that receives parallel data converted by the serial-parallel converter. The serial-parallel converter is, for example, a D-type flip-flop (shift register) connected in series corresponding to the number of data (for example, 1 byte) required by the peripheral board 44a. Similarly, the register includes a plurality of D-type flip-flops.

  The serial-parallel converter operates in accordance with a clock received from a control signal generation unit described later, and sequentially stores the received serial data in the flip-flop. The register of the output unit 44OUT receives the converted parallel data from the serial-parallel converter in accordance with a latch signal received from a control signal generation unit described later. Since serial-parallel converters and registers are well known, detailed description thereof is omitted.

  More precisely, the output unit 44OUT of the peripheral board 44 belonging to the first group is controlled by the clock and the latch signal from the first group control signal generation unit 40S-21, and the output unit 44OUT of the peripheral board 44 belonging to the second group. The input unit 44-3IN is controlled by a clock and a latch signal from the second group control signal generation unit 40S-22. That is, a dedicated timing signal (clock, latch signal) is prepared for each group. On the other hand, the data is common.

  The input unit 44-3IN receives transmission data (see FIG. 7A) from the serial communication unit 40S, and inputs the data included therein (input blank data in FIG. 7A) prepared in advance. (In other words, the input value is overwritten with the blank data for input). As a result, the transmission data in FIG. 7A changes to the reception data in FIG. Alternatively, the input unit 44IN includes a register (not shown) that holds data (for example, 1 byte) collected from a device (for example, a jog dial input unit) (not shown) by the peripheral board 44-3, and data ( A parallel-serial converter (shift register, not shown) for converting parallel data) into serial data may be provided. This register and the parallel-serial converter also include a plurality of D-type flip-flops. The register of the output unit 44-3IN transfers the parallel data of the register to the parallel-serial converter in accordance with the latch signal received from the serial communication unit 40S. The parallel-serial converter operates according to the clock received from the serial communication unit 40S and sequentially outputs the received parallel data.

  The serial communication unit 40S is generated by the first group data generation unit 40S-11 that generates transmission data to the first group, the second group data generation unit 40S-12 that generates transmission data to the second group, and the like. A selection unit 40S-G that selects and transmits either the first group data or the second group data, a first group control signal generation unit 40S-21 that generates a clock latch signal to the first group, and a second group Based on the received second data, second group control signal generator 40S-22 for generating a clock latch signal, data receiver 40S-3 for receiving data, received data analyzer 40S-4 for analyzing received data An abnormality determination unit 40S-5 that determines whether there is an abnormality in the loop of FIG. 6 is included.

  The output line of the selection unit 40S-G is a serial transmission line through which serial data flows. Although not shown, the selection unit 40S-G includes a parallel-serial converter (shift register), converts the selected data into a serial signal, and sends it to the serial transmission line. Peripheral boards of each group are connected to the serial transmission line. In other words, the serial transmission line is common to each group.

  The case where the unit of serial data handled by the serial communication unit 40S and the peripheral boards 44a and 44-3 is 1 byte will be described as an example.

  Since the serial communication unit 40S and the plurality of peripheral boards 44 of the first group are connected in a loopback structure, when 1-byte data is transmitted, transmission data is accumulated in the first output unit 44OUT and pushed out. The data stored there is sent to the two input sections 44IN, and the data circulates, and the data there is returned to the serial communication section 40S. In the example of FIG. 4, by transmitting 2 bytes of data, in the example of FIG. 6, by transmitting 3 bytes of data (however, both the output unit and the input unit handle data in units of 1 byte. Data is distributed to all of the peripheral substrates 44 connected in two or more chains.

  In FIG. 6, “data” indicates a serial data signal or a line (= serial transmission line) through which the serial data signal flows. “Clock” is a signal for operating the serial-parallel converter and the parallel-serial converter (shift register). One data is transmitted by one clock. The “latch signal” is a signal for transferring data from the serial-parallel converter of the output unit 44OUT to the register and from the register of the input unit 44-3IN to the parallel-serial converter. The “reset signal” is a signal for resetting the output unit 44OUT and the input unit 44-3IN. The output unit 44OUT and the input unit 44-3IN are in an initial state by the reset signal.

  FIG. 7 shows data (transmission data) transmitted from the serial communication unit 40S to the peripheral board 44a and data (reception data) received by the serial communication unit 40S from the peripheral board 44-3.

  As shown in FIG. 7A, the transmission data is composed of three types: “output data”, “input blank data”, and “abnormality confirmation data”. The transmission data is transmitted at a predetermined first interrupt timing (hereinafter referred to as “phase interrupt”).

  “Output data” is data output to a device controlled by the peripheral board 44a. For example, LED brightness data and control data for movable bodies and solenoids are included.

  The “input blank data” is data that should be replaced when the input unit 44-3IN of the peripheral board 44-3 acquires an input value. The initial value of the input blank data is, for example, “00H”.

  The “abnormality confirmation data” is data for determining whether the loopback is normally performed. Although this data is arbitrary, data in which “1” and “0” are mixed as much as possible is preferable.

  The number of transmission data varies depending on the number of devices such as LEDs, movable bodies, and switches mounted on the gaming machine, specifically, the number of peripheral boards that control them. The number of transmission data is (total number of output unit 44OUT and input unit 44-3IN) +1 (abnormality confirmation data). The unit at this time is one piece of data (word, for example, 1 byte). When transmission of one transmission data is completed by transmitting one more than the total number of output units 44OUT and input units 44-3IN (in other words, when output data and input blank data are distributed to each peripheral board), The first “abnormality confirmation data” is looped back to the serial communication unit 40S. Thereby, the abnormality confirmation data is always returned to the serial communication unit 40S by one transmission, and it is possible to confirm whether or not there is an abnormality in data transmission for each transmission data.

  For example, as shown in FIG. 4, when two output units 44OUT and one input unit 44IN are chain-connected and the data handled by each is 1 byte, (number of transmission data) = (output unit 44OUT Number) + (number of input units 44IN) +1 (abnormality confirmation data) = 2 bytes + 1 byte + 1 byte = 4 bytes.

The order of transmission of the output data and the input blank data is as follows: the first peripheral board 44a (output part 44OUT) and the second peripheral board 44-3 (input part 44-3IN) when viewed from the output end of the serial communication unit 40S. ) Corresponds to the connection order.
As shown in FIG. 6, when viewed from the output end of the serial communication unit 40 </ b> S, the second peripheral board 44-3 and the first peripheral boards 44-4 and 44-2 are connected in order from the far side. The transmission order of the transmission data is in the order of (abnormality confirmation data) (input blank data) (output data) (output data). It is assumed that (abnormality confirmation data) is always at the head.

As shown in FIG. 7B, the reception data is composed of three types of “output data”, “input value”, and “abnormality confirmation data” in which the transmission data is received in a loopback structure.
The order of received data corresponds to the order of transmitted data.

  “Output data” is the same as the transmission data, and is the data that was output last time. This data is unnecessary for the serial communication unit 40S. Therefore, the serial communication unit 40S may not receive “output data”.

  The “input value” is a value input from the input unit 44-3IN in response to the latch signal, and means a signal / data from a device (PUSH switch, index sensor, etc.).

  The “abnormality confirmation data” is the same as that of the transmission data. If the same data (value) as that of the transmitted data can be received, the other data is also considered normal.

  The number of received data is the same as the number of transmitted data. The size and number of “output data”, “input blank data”, that is, “output data”, “input value”, and the order thereof correspond to the number of output units 44OUT and input units 44-3IN and their connection order. ing. When the number of output units 44OUT increases or decreases, the size of “output data” also increases or decreases, and when the number of input units 44-3IN increases or decreases, the size of “input blank data” also increases or decreases. If the connection order is changed, the positions of “output data” and “input blank data” are also changed. Assuming that four peripheral boards 44 are chain-connected and viewed from the output end of the serial communication unit 40S, they are connected in the order of the output unit 44OUT, the input unit 44IN, the output unit 44OUT, and the input unit 44IN in order from the far side. If so, the transmission data is "abnormality confirmation data", "output data", "input blank data", "output data", "input blank data".

  Since the first group does not have an input unit and is not in a loopback connection, “abnormality confirmation data” and “input blank data” are unnecessary. In the example of FIG. 6, only one (output data) is required.

  FIG. 8 is a flowchart of processing performed by the serial communication unit 40S. FIG. 9 is an explanatory diagram (timing chart) of the processing of FIG.

  Next, with reference to FIG. 8 and FIG. 9, the operation of the serial communication according to the embodiment of the invention will be described.

S1: Select the second group of data.
The second group of data is data sent to the peripheral substrates 44-2, 44-4, and 44-3. The selector 40S-G selects the output data of the second group data generator 40S-12. It is assumed that data to be transmitted for both the first group and the second group is generated in advance, is selected and read by the selection unit 40S-G, and is read through each serial transmission channel (serial transmission line). Send to peripheral substrate 44. Note that selecting the second group of data first is an example, and the first group of data may be selected first.

S2: Validate the second group of clocks and invalidate the first group of clocks.
Referring to FIG. 6, the second group control signal generator 40S-22 outputs a clock signal, but the first group control signal generator 40S-21 stops outputting the clock signal. Referring to FIG. 9 to be described later, a signal for prohibiting the shift operation even if the clock is not sent to the peripheral board 44 of the first group during the period in which the first group clock is invalid or the clock is sent. The transmission of data is stopped by sending (shift enable signal = disable). In the latter case, the first group and the second group can share a clock. In the period in which the second group clock is valid, a clock is sent to the peripheral board 44 of the second group (when there is a shift enable signal, this is enabled). The above points are the same for the first group.

  The clock of the second group is made effective by the data of the second group, in the examples of FIGS. 6 and 7, “abnormality confirmation data”, “input blank data”, “output data”, “output data”, This is for sending to 44-2, 44-4, 44-3. The reason for disabling the first group of clocks is to prevent the second group of data from being erroneously sent to the first group. When the output unit 44OUT of the peripheral board 44-1 has a function of not capturing or discarding data unnecessary for itself, the clock may not be invalidated. Although two clocks are used for the first group and the second group, these clocks may be shared.

S3: It is determined whether the second group data transmission is completed.
When the serial communication unit 40S finishes transmitting all the data to be transmitted, it determines that the transmission is complete. For example, if all “abnormality confirmation data”, “input blank data”, “output data”, and “output data” are transmitted, it is determined as “YES”, and if not, transmission is continued.

S4: A second group latch signal is transmitted.
When all the data to be transmitted is transmitted, a latch signal is transmitted from the second group control signal generation unit 40S-22 to the second group, that is, the peripheral substrates 44-2 to 44-4. Specifically, as indicated by the symbol a in FIG. 9, the latch signal is transmitted immediately after the completion of the second group data transmission and at the timing before the next first group data transmission. “Output data” is transferred to the peripheral board by the latch signal, and “input value” is entered in “input blank data”.

S5: Select the first group of data.
The first group of data is data sent to the peripheral board 44-1. The selection unit 40S-G selects the output data of the first group data generation unit 40S-11.

S6: The first group of clocks is enabled and the second group of clocks is disabled.
Referring to FIG. 6, the first group control signal generator 40S-21 outputs a clock signal, but the second control signal generator 40S-22 stops outputting the clock signal.

  The reason why the clock of the first group is made valid is to send “output data” that is the data of the first group to the peripheral board 44-1. The reason for disabling the second group of clocks is to prevent the first group of data from being erroneously sent to the second group. If the output unit 44OUT of the peripheral boards 44-2 and 44-4 has a function of not capturing or discarding data unnecessary for itself, the clock may not be invalidated.

S7: It is determined whether the first group data transmission is completed.
When the serial communication unit 40S finishes transmitting all the data to be transmitted, it determines that the transmission is complete. For example, if all the “output data” is transmitted, it is determined as “YES”, otherwise the transmission is continued.

S8: Transmit the first group latch signal.
When all the data to be transmitted is transmitted, a latch signal is transmitted to the first group, that is, the peripheral board 44-1. Specifically, as indicated by reference symbol 1 in FIG. 9, the latch signal is transmitted immediately after the completion of the first group of data transmissions and at the timing before the next first group of data transmissions. The “output data” is transferred to the peripheral board 44-1 by the latch signal.

S9: S5 to S8 related to the first group are repeated a predetermined number of times (= k).
The reason why the repetitive processing is performed is to make the data update cycle different between the first group and the second group. Although k is an integer, the larger the k is, the higher the data transmission frequency of the first group is compared to that of the second group (in other words, the data update cycle is shortened and the data update rate is increased). If the time required for transmitting the first group of data is the same as the time required for transmitting the second group of data, the data update rate of the first group: the data update rate of the second group = k: 1. It becomes. By assigning peripheral boards frequently requiring data update to the first group and setting k to 2 or more, the data update rate of the peripheral boards can be increased.

  Note that the data update rate of the second group can be increased. In this case, S9 may be performed immediately after S4, and S1 to S4 may be repeated k times.

  FIG. 9 shows the case where k = 2. As indicated by reference characters 1 and 2 in FIG. 9, the first group of latch signals are continuously generated.

  As described above, according to the embodiment of the invention, the data update cycle (data transmission speed) can be made different for each peripheral board (precisely for each group of peripheral boards), and for each peripheral board. The data can be transmitted at an appropriate speed according to the necessity of the data. Thereby, the performance of the entire serial communication system can be improved.

  In the above example, for the second group, serial transmission can be performed at the same transmission speed as the conventional one with the same configuration as the conventional one, and for the first group, the transmission speed is increased by appropriately setting the number of repetitions k. be able to.

  Next, how much the actual update rate is improved will be described.

  FIG. 10 is a simplified view of the serial transmission system according to the embodiment of the present invention shown in FIG. The first group data generator 40S-11, the second group data generator 40S-12, the selector 40S-G, and the peripheral substrates 44-1, 44-2, 44-4 are the same as those shown in FIG. It is. In FIG. 10, the display of the peripheral board 44-3 including the input unit and the loopback connection is omitted. Reference numerals A to C correspond to the peripheral substrates 44-1, 44-4, and 44-2, respectively. In order to simplify the description, hereinafter, the substrate 44-1, the substrate 44-4, and the substrate 44-2 are simply referred to as “A”, “B”, and “C”.

  The numbers in the peripheral boards 44-1, 44-4, and 44-2 in FIG. 10 indicate data that each board should receive. That is, data 1 is necessary for the substrate A. Similarly, data 2 and 3 correspond to substrate B and substrate C, respectively. In order to simplify the description, data 1, data 2, and data 3 are simply indicated as “1”, “2”, and “3” in the following.

  FIG. 11 is a timing chart showing data propagation. The horizontal axis represents time, and the vertical axis represents data propagation (data received by each board). The lower square on the horizontal axis indicates transmission data. The time required to transmit one piece of transmission data is T. It is assumed that the transmission data “1”, “2”, and “3” have the same time for transmission, and the transmission is completed upon completion of the clock that transmitted the last data. A latch signal indicated by a dotted line is generated immediately after the transmission is completed.

  FIG. 11 shows a timing chart when the second group of data “2” “3” is transmitted, and then the first group of data “1” is transmitted twice. This corresponds to the case where k = 2 in FIG. In FIG. 11 and subsequent figures, “abnormality confirmation data” and “input blank data (input value)” are omitted. When a plurality of data “2” and “3” are included as in the second group, “2” and “3” are respectively referred to as partial data.

  As can be seen from the figure, the transmission of the data “1” of the first group is completed in one cycle T. At the stage where “1” reaches “A” (t11, t12, t13, t14 in the figure), “A” takes “1” into the inside by a latch signal.

  Further, the transmission of the data “2” and “3” of the second group is completed in two periods 2T. For the second group, serial data is input to the substrate C, and the serial data propagates from “C” to “B” by the clock. At the stage where “2” reaches “B” (t21, t22 in the figure), “B” and “C” take “2” and “3” into the inside by a latch signal.

  Refer to FIG. 17 and the explanation thereof for the state of data propagation.

  As can be seen from the figure, the data update cycle of the second group is constant interval = 4T. On the other hand, there are two types of data update cycles for the first group: 3T (from t11 to t12 and from t13 to t14) and T (from t12 to t13). If the average is obtained for a sufficiently long period, 2T is obtained. Therefore, the data update cycle of the first group: the data update cycle of the second group = 1: 2. In other words, in the case of k = 1 in the first group of chain connections and the second group of chain connections, the data update rate of the first group: the data update rate of the second group = 2: 1.

  In addition, in the case of k = 1 in the first group chain connection stage 1 and the second group chain connection stage 3 (not shown), the average of the data update cycle of the first group is 2.5T, The data update cycle is 5T, and again, the first group data update rate: the second group data update rate = 2: 1.

  FIG. 12 shows another method for transmitting the first group of data “1” at a higher update rate than the second group of data “2” and “3”. In the figure, “1” is transmitted between “2” and “3”. Even in the case of the figure, it can be said that k = 2 because four sets of continuous transmission data include two first groups and one set of “2” and “3” in the second group.

  As can be seen from the figure, the data update cycle of the second group is constant interval = 4T. Further, the data update cycle of the first group is a constant interval = 2T. Therefore, the data update cycle of the first group: the data update cycle of the second group = 1: 2. In other words, in the case of k = 1 in the first group of chain connections and the second group of chain connections, the data update rate of the first group: the data update rate of the second group = 2: 1.

  In addition, in the case of k = 1 in the first group chain connection stage 1 and the second group chain connection stage 3 (not shown), the data update period of the first group is 2T, and the data update period of the second group is 6T, and the data update rate of the first group: the data update rate of the second group = 3: 1. As shown in FIG. 12, when the first group data and the second group data (data corresponding to one peripheral board) are transmitted alternately, the update rate increases as the number of stages of chain connection in the second group increases. The difference between

  In order to further increase the difference between the update rates, the first group of data may be repeatedly transmitted as shown in FIG. In the figure, two “1” s are transmitted between “2” and “3” and between “3” and “2”. In the case of the figure, it can be said that k = 3 because five sets of continuous transmission data include three first groups and one set of “2” and “3” in the second group.

  As can be seen from the figure, the data update cycle of the second group is a constant interval = 6T. Moreover, the average of the data update period of the first group is 1.5T (4 of the 6 transmission data are the first group, 6 ÷ 4). Therefore, the data update cycle of the first group: the data update cycle of the second group = 1: 4. That is, in the case of k = 3 in one stage of chain connection of the first group and two stages of chain connection of the second group, the data update rate of the first group: the data update rate of the second group = 4: 1.

  Also in the case of FIG. 13, as the number of stages of chain connection in the second group increases, the difference in update rates increases.

  In the description of the prior art, referring to FIG. 17B, the data update cycle of each of the substrates A to C is 3T, but the update cycle of the first group in FIGS. 11 to 13 is 2T, 2T, 1.5T, both of which exceed it. This also shows that according to the embodiment of the invention, the transmission speed of the first group can be increased.

  The above-described example is a case where there are two groups, but the embodiment of the present invention can also be applied to a case where there are three or more groups. FIG. 14 is a block diagram of a serial transmission system having three groups. 14A is a system diagram of data transmission, and FIG. 14B is a system diagram of clocks and latch signals. The number of stages of chain connection in each group is (number of stages in the first group) <(number of stages in the second group) <(number of stages in the third group). Specifically, 1 stage <2 stages <3 stages It is. According to the method of the embodiment of the present invention, the data update rate decreases as the number of stages increases, so that (first group update rate)> (second group update rate)> (third group update rate). is there.

  In order to simplify the description, the substrate 44-1, the substrate 44-4, and the substrate 44-2 are simply referred to as “A”, “B”, and “C” as in FIG. The substrates 44-5, 44-6, and 44-7 are simply referred to as “D”, “E”, and “F”. Similarly to FIG. 10, data 1, data 2, and data 3 are simply denoted as “1”, “2”, and “3”. Then, the data corresponding to “D”, “E”, and “F” are written as “4”, “5”, and “6”.

  FIG. 15 is a process flowchart of the serial communication unit 40S in the system of FIG. The operation of the serial communication in FIG. 14 will be described with reference to this figure.

S10: Transmit the third group of data.
Note that the order of transmission is not limited to that in FIG. 15, and the second group of data may be transmitted first. However, the nested structure of the processing of the first group and the second group regarding the repetition of data transmission is assumed to maintain the state of FIG.

S11: Transmit the second group of data.
For example, S1 in FIG. 8 selects data in the second group, S2: enables the clock in the second group, and disables the clock in the first group. S3: Data in the second group This includes processing equivalent to the three steps of determining whether transmission has been completed. In FIG. 15, the three steps are collectively expressed as one step for easy viewing of the drawing. This is the same for S10 and S12.

S12: Transmit the first group of data.

S13: Data transmission of the first group is repeated a predetermined number of times (= n / m).
However, it is assumed that (update rate of the first group) :( update rate of the second group) :( update rate of the third group) = n: m: 1.

S14: When the repetition of data transmission of the first group is completed, S11: data transmission of the second group is repeated. Since the processes of the first group and the second group are nested, the data transmission of the first group is repeated by repeating the data transmission of the second group. As for the first group, (n / m repetition) × (m repetition) = (n repetition) after all.

  The reason why the repetitive processing is performed in S13 and S14 is to make the data update periods different in the first to third groups. As n increases, the data transmission frequency of the first group becomes higher than that of the second and third groups. In addition, as m is larger, the data transmission frequency of the second group becomes higher than that of the third group. However, n> m.

  FIG. 16 is a timing chart showing data propagation. This corresponds to FIG. 11 and the like, but only the transmission data portion is displayed and greatly simplified for easy viewing of the drawing.

  FIG. 16A shows a case where n = 4, m = 2, (update rate of the first group) :( update rate of the second group) :( update rate of the third group) = 4: 2: 1. Show. The data “1” of the first group is repeated four times, the data “2” and “3” of the second group are repeated twice, and the data “4”, “5” and “6” of the third group are transmitted only once. Has been.

  FIG. 16B shows the case where n = 4 and m = 2, but differs in that the completion of transmission is determined not in units of groups but in units of transmission data (partial data). For example, when the transmission of “4” with respect to the data of the third group, the transmission of the second group is performed as transmission completion. The same applies to “5” and “6”. In this manner, data transmissions of other groups are sandwiched between data transmissions included in the group. In other words, the data transmission timing is dispersed. In the example of the figure, “1” of the first group is transmitted at a substantially constant interval. Therefore, when it is desired to suppress the fluctuation of the data update rate, the method of the figure may be adopted.

  FIG. 16C shows a case where n = 6 and m = 2, (update rate of the first group) :( update rate of the second group) :( update rate of the third group) = 6: 2: 1. Show.

  FIG. 16D shows the case where n = 6 and m = 2, but as shown in FIG. 16B, the data transmissions of other groups are sandwiched between the data transmissions included in the group. Yes. Also in this case, the transmission interval of the first group of data is leveled compared to FIG.

  Embodiments of the present invention can be applied not only to pachinko machines but also to gaming machines such as slot machines.

  The present invention is not limited to the above embodiments, and various modifications can be made within the scope of the invention described in the claims, and these are also included in the scope of the present invention. Needless to say.

40b Sub-control unit 40S Serial communication unit 40S-11 First group data transmission unit 40S-12 Second group data transmission unit 40S-13 Third group data transmission unit 40S-21 First group control signal generation unit 40S-22 Second Group control signal generation unit 40S-23 Third group control signal generation unit 40S-3 Data reception unit 40S-4 Reception data analysis unit 40S-5 Abnormality determination unit 40S-G selection unit 44 Peripheral substrate 44-1 Periphery of the first group Substrates 44-2 to 44-4 Second group peripheral substrates 44-5 to 44-7 Third group peripheral substrates "A" to "F" Peripheral substrates "1" to "6" Peripheral substrates "A" to " Data corresponding to "F"

Claims (5)

A control unit that executes control related to a game, a sub-control unit that executes predetermined processing based on information generated by the control unit, and a plurality of peripheral boards connected to the control unit or the sub-control unit ,
The control unit or the sub-control unit and the plurality of peripheral boards are connected by a serial transmission line that transmits a serial signal,
The plurality of peripheral substrates are divided into one or a plurality of first group peripheral substrates and a second group of peripheral substrates more than the first group peripheral substrates,
The first group of peripheral boards is chain-connected to the serial transmission line, the second group of peripheral boards is chain-connected to the serial transmission line separately from the first group of peripheral boards,
further,
A first group data generator for generating data to be sent to the first group of peripheral substrates;
A second group data generator for generating data to be sent to the second group of peripheral substrates;
A selection unit that selects either the data generated by the first group data generation unit or the data generated by the second group data generation unit and sends the data to the serial transmission line;
When the data generated by the first group data generation unit is selected by the selection unit, a signal for transmitting the serial signal of the serial transmission line in the chain connection of the peripheral substrate of the first group and the first A first group control signal generator for sending a signal for the group of peripheral boards to receive the data to the first group of peripheral boards;
When the data generated by the second group data generation unit is selected by the selection unit, a signal for transmitting a serial signal of the serial transmission line in the chain connection of the peripheral substrate of the second group and the first A second group control signal generation unit for transmitting a signal for receiving the data to the second group of peripheral boards to the second group of peripheral boards;
The gaming machine according to claim 1, wherein the selection unit selects more data generated by the first group data generation unit than data generated by the second group data generation unit.   2. The selection unit according to claim 1, wherein after the data generated by the second group data generation unit is selected once, the selection unit repeatedly selects the data generated by the first group data generation unit. Game machines. The data generated by the second group data generation unit includes a plurality of partial data corresponding to the plurality of peripheral substrates of the second group,
The selection unit selects one of the plurality of partial data, then selects data generated by the first group data generation unit, and then selects another one of the plurality of partial data. The gaming machine according to claim 1.   The selection unit repeatedly selects the data generated by the first group data generation unit a plurality of times while selecting one of the plurality of partial data and the other of the plurality of partial data. The gaming machine according to claim 3. further,
A third group data generator for generating data to be sent to the third group of peripheral substrates;
When the data generated by the third group data generation unit is selected by the selection unit, a signal for transmitting a serial signal of the serial transmission line in the chain connection of the peripheral boards of the third group and the first A third group control signal generation unit for sending a signal for receiving the data to the third group of peripheral boards to the third group of peripheral boards,
Regarding the peripheral substrates of the first group to the third group (the number of peripheral substrates of the first group) <(the number of peripheral substrates of the second group) <(the number of peripheral substrates of the third group) And
Regarding selection of data by the selection unit,
(Number of selections of data generated by the first group data generation unit)> (Number of selections of data generated by the second group data generation unit)> (Number of selections of data generated by the third group data generation unit) The gaming machine according to claim 1, wherein the relationship is established.

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