JP2011188063A - Level shift circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the number of elements constituting a level shift circuit. <P>SOLUTION: A level shift circuit 1 includes: a first switch PM1, which is connected in series with a second power supply VCC, a third transistor PM3 and a first output terminal OUTB; a second switch PM2, which is connected in series with the second power supply VCC, a fourth transistor PM2 and a second output terminal OUT and brought into the same energization state as the first switch PM1; and a third switch NM10, which is connected between the first output terminal OUTB and the second output terminal OUT and brought into an energization state exclusive for the first switch PM1 and the second switch PM2. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a level shift circuit.

  In recent years, level shift circuits that switch signal voltage sizes to different voltage ranges have been used in various electronic devices such as display devices and storage devices. FIG. 2 shows a configuration of the level shift circuit 101 according to the prior art (Patent Document 1). This level shift circuit 101 includes p-type MOS transistors (hereinafter referred to as PMOS) PM101, PM103, PM111 and n-type MOS transistors (hereinafter referred to as NMOS) between the power supply voltage of VCC and the ground voltage of VSS. Are connected in series, and PMOSs PM102, PM104, PM112 and NMOS NM102 are connected in series. Then, an IN voltage level signal is input to the gates of the PM101 and the NM101, an inverted signal INB of an IN voltage level signal is input to the PM102 and the gate of the NM102, and the PM111 and PM112 gates. A TEST signal is input. Further, the gate of the PM 104 and the drain of the NM 101 are connected, and the gate of the PM 103 and the drain of the NM 102 are connected. The drain of the NM 102 is connected to the output terminal OUT, and the drain of the NM 101 is connected to the output terminal OUTB. Become. The NM 111 is connected between the output terminal OUT and the ground voltage VSS, and a TEST signal is input to the gate of the NM 111.

  The level shift circuit 101 configured as described above has a 6Tr + 3Tr = 9Tr configuration. Further, the PM 103 and the PM 104 generally have a large L dimension (gate length) and operate as resistors. IN / INB is a low amplitude input signal, TEST is a high amplitude input signal, OUT / OUTB is a high amplitude output signal, VCC is a high voltage power supply, and VSS is a ground.

  The level conversion circuit 101 converts the voltage level of the signal from the IN voltage level to the VCC voltage level. When TEST is low (normal operation), when IN is high and INB is low, PM101, PM103, NM102, and NM111 are off, PM102, PM104, PM111, PM112, and The NM101 is turned on, OUT becomes VCC (V), and OUTB becomes VSS (V). On the other hand, when IN is low and INB is high, PM102, PM104, NM101, and NM111 are off, PM101, PM103, PM111, PM112, and NM102 are on, and OUT is OUTB becomes VCC (V) at VSS (V). PM101 and PM102 are PMOSs having a large L dimension and function as resistors. Therefore, the through current that flows during inversion can be reduced.

When TEST is high, PM111 and PM112 are turned off and NM111 is turned on, the operation of the level conversion circuit is stopped, and the output terminal OUT can be fixed to the ground voltage (VSS). Table 1 below shows a truth table of operations in the level shift circuit 101.

  When the NM 111 that fixes the output low during the test is added to the normal 6Tr configuration, if IN is high, a current flows from VCC to the output. Then, the PM 111 and the PM 112 that function as a switch for cutting off the current are necessary. Further, when the TEST is high, the operation of the level conversion circuit is stopped. However, although the NM 111 for fixing the output to the output terminal OUT is added, the output terminal OUTB has nothing similar. Therefore, in addition to the 6-element level shift circuit, 3 elements are required, and a total of 9 elements are required. Further, since the output terminal OUTB becomes unstable when IN is low and INB / TEST is high, when the output terminal OUTB is used in a subsequent circuit, a through current or the like flows in the subsequent circuit. A malfunction may occur.

  Patent Document 2 is disclosed as a circuit for solving the above problems. FIG. 3 shows a level shift circuit 201 according to Patent Document 2. The difference from the level shift circuit 101 shown in FIG. 2 is that the PM 111 and the PM 112 are deleted, the TEST signal is input to the gates of the PM 101 and PM 102, and the NMOS NM212 for fixing the output terminal OUTB to a low level. This is an added point. A TEST signal is also input to the gates of the NM 111 and the NM 212. In the level shift circuit 201, when IN is low and INB / TEST is high, two elements are required to fix the output terminal OUT / OUTB to low.

JP 2008-096473 A JP 2009-260817 A

  As described above, the level shift circuit 101 shown in FIG. 2 requires three elements in addition to the six-element level shift circuit, and the output terminal OUTB is undefined when IN is low and INB / TEST is high. There is a bug that becomes. In addition, the level shift circuit 201 shown in FIG. 3 requires two elements in addition to the six-element level shift circuit.

  In one embodiment of the present invention, an input signal is input to a gate, a source has a source connected to a first power supply, a signal in which the input signal is inverted is input to a gate, and a source is the first transistor A second transistor connected to a power source; a first output terminal connected to a drain of the first transistor; a second output terminal connected to a drain of the second transistor; and a gate serving as the second transistor A third transistor connected to the drain of the transistor and the second output terminal, a source connected to the second power supply, a gate connected to the drain of the first transistor and the first output terminal, and a source A fourth transistor connected to the second power source, a first switch connected in series to the second power source, the third transistor, and the first output terminal; A second switch connected in series with the second power source, the fourth transistor, and the second output terminal, and in the same energization state as the first switch, the first output terminal, and the second output terminal. A level shift circuit including a third switch connected between two output terminals and in an exclusive energized state with respect to the first switch and the second switch.

  According to the above aspect, when either the first transistor or the second transistor is on, that is, when either the first or second output terminal is at the first power supply voltage (for example, ground), When the third switch is turned on, both the first and second output terminals are fixed to the first power supply potential by turning off the first switch and the second switch. be able to.

  According to the present invention, it is possible to configure a level shift circuit having a sufficient function with a smaller number of elements than in the prior art.

It is a figure which shows the structure of the level shift circuit which concerns on embodiment of this invention. It is a figure which shows the 1st structural example of the level shift circuit which concerns on a prior art. It is a figure which shows the 2nd structural example of the level shift circuit which concerns on a prior art.

Embodiment 1
FIG. 1 shows a configuration of a level shift circuit 1 according to an embodiment of the present invention. In the level shift circuit 1, between the power supply voltage of VCC and the ground voltage of VSS, PM1 and PM3 that are PMOS and NM1 that is NMOS are connected in series, and PM2 and PM4 that are PMOS, An NMOS transistor NM2 is connected in series. An IN voltage level signal is input to the NM1 gate, an inverted signal INB of the IN voltage level is input to the NM2, and a TEST signal is input to the PM1 gate and the PM2 gate. The gate of PM4 and the drain of NM1 are connected, the gate of PM3 and the drain of NM2 are connected, the drain of NM2 serves as an output terminal OUT, and the drain of NM1 serves as an output terminal OUTB. It becomes.

  In the level shift circuit 1 according to the present embodiment, an NM10 that is an NMOS functioning as a switch is provided between the output terminals OUT and OUTB. A TEST signal is input to the gate of the NM10.

  The difference between the level shift circuit 1 and the level shift circuit 201 according to the prior art shown in FIG. 3 is that the NM 211 and the NM 212 in the level shift circuit 201 are deleted and the NM 10 is added.

  The operation of the level shift circuit 1 will be described below. When TEST is low (normal operation), if IN is high and INB is low, PM3, NM2, and NM10 are off, PM1, PM2, PM4, and NM1 are on, OUT = VCC / OUTB = VSS. On the other hand, when IN is low and INB is high, PM4, NM1, and NM10 are turned off, PM1, PM2, PM3, and NM2 are turned on, and OUT = VSS / OUTB = VCC. Become. The PM1 and PM2 are PMOSs having a large L dimension and function as resistors, so that the through current that flows during inversion can be reduced.

When TEST is high, PM1 and PM2 are turned off and NM10 is turned on, the operation of the level conversion circuit is stopped, and the output terminal OUT / OUTB can be fixed to the ground voltage (VSS). Table 2 below is a truth table of operations in the shift level circuit 1.

  As described above, in the level shift circuit 1, when TEST is high, the PM1 and the PM2 are off, the PM1 and the PM2 are off, and either the NM1 or the NM2 is on, that is, the output terminal Either OUT / OUTB becomes VSS, and the NM10 turns on. Thus, when the TEST signal input to the gate of the NM10 becomes high, both the output terminals OUT and OUTB are fixed to VSS. Thereby, a function equivalent to the conventional circuit can be realized with a smaller number of elements (7 elements).

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit of the present invention. For example, in the above embodiment, the PM1 and the PM2 are provided between the PM3 and the PM4 and the output terminals OUTB and OUT. However, the PM1 and the PM2 are the VCC, It may be provided between the PM3 and the PM4.

1 Level shift circuit PM1 PMOS (first switch)
PM2 PMOS (second switch)
PM3 PMOS (third transistor)
PM4 PMOS (fourth transistor)
NM1 NMOS (first transistor)
NM2 NMOS (second transistor)
NM10 NMOS (third transistor)

Claims (5)

A first transistor having an input signal input to a gate and a source connected to a first power source;
A second transistor in which a signal obtained by inverting the input signal is input to a gate and a source is connected to the first power supply;
A first output terminal to which a drain of the first transistor is connected;
A second output terminal to which a drain of the second transistor is connected;
A third transistor having a gate connected to the drain of the second transistor and the second output terminal, and a source connected to a second power source;
A fourth transistor having a gate connected to the drain of the first transistor and the first output terminal, and a source connected to the second power supply;
A first switch connected in series with the second power source, the third transistor, and the first output terminal;
A second switch connected in series with the second power source, the fourth transistor, and the second output terminal, and in the same energized state as the first switch;
A third switch connected between the first output terminal and the second output terminal, wherein the third switch is in an energized state exclusive to the first switch and the second switch;
A level shift circuit comprising: The first switch, the second switch, and the third switch are controlled by the same control signal.
The level shift circuit according to claim 1. The first switch is connected between the third transistor and the first output terminal;
The second switch is connected between the fourth transistor and the second output terminal.
The level shift circuit according to claim 1 or 2. The input signal is different from the signal for controlling the first to third switches.
The level shift circuit as described in any one of Claims 1-3. In the stop state, only one of the first transistor or the second transistor is energized.
The level shift circuit as described in any one of Claims 1-4.

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