JP5476104B2 - Power-on clear circuit - Google Patents

Description

  The present invention relates to a power-on-clear circuit for resetting and initializing a target circuit in a semiconductor device or the like when power is turned on, and more particularly to a power-on-clear circuit having an even number of inverters in an output stage.

  Conventionally, a circuit composed of a Schmitt trigger having a plurality of inverters, for example, a CMOS inverter, in the output stage, and a power-on-clear circuit having an RC circuit in the preceding stage are known. The power-on-clear circuit generates and outputs a clear signal for resetting based on a signal that rises following the rise of the power supply voltage. For this reason, there is no problem if the rise of the power supply voltage is fast, but if it is slow, for example, when the battery voltage, which is the power supply voltage, drops, the MOS transistors constituting each CMOS inverter are turned on until the power supply voltage is not sufficiently raised. The OFF state is indefinite and the output state is also undefined. On the other hand, since the potential at the connection point between the resistor of the RC circuit and the capacitor increases with the power supply voltage, the capacitor is charged when the power supply voltage is low, and the potential at the connection point of the N-channel MOS transistor that constitutes the CMOS inverter. The clear signal cannot be maintained until the threshold voltage is reached and the circuit to be initialized reaches a voltage at which the target circuit operates sufficiently, and the clear signal may not be generated or output in some cases.

  In order to avoid such a situation, conventionally, the two cascaded inverters are CMOS inverters composed of P-type and N-type MOS transistors, respectively, while the front-side inverter is interposed between the two CMOS inverters. A PMOS transistor connected to the output terminal and the power supply terminal is provided, and by setting the magnitude relationship between the threshold voltage and the drain current of the PMOS transistor and the NMOS transistor of the preceding inverter on a predetermined condition, a clear signal is sent to each of the transistors. It has been proposed to generate and output a clear signal even when the rise of the power supply voltage is slow by determining the DC voltage characteristics (Patent Document 1).

JP 2002-261595 A

  However, although the above-described power-on-clear circuit proposed in the past can generate and output a clear signal even when the rise of the power supply voltage is slow, the rise of the generated clear signal output may be slow. If the rise is dull, some circuits cannot be reset sufficiently at the start of operation, causing malfunction.

The present invention is to solve this problem, generating a clear signal free from the rise of the influence of the supply voltage, both when you output, corresponding to the rising state of the power supply voltage, i.e. follows the rise of the supply voltage An object of the present invention is to provide a power-on-clear circuit that generates and outputs a rising clear signal and generates and outputs two types of clear signals.

To achieve the above Symbol object, the power-on clear circuit according to claim 1 of the present invention includes a pulse generating circuit for generating a pulse by turning on the power, a delay circuit configured to delay the generated pulses, Outputs a clear signal having cascaded even-numbered inverters for inputting delayed pulses, an input terminal for inputting the output of the preceding stage of the delay circuit, and an input terminal for inputting the output of the odd-numbered inverter to consist NOR circuit, while the output of the NOR circuit and the first clear signal, the output of the inverter of the final stage in the inverter even number of stages that the cascaded intended as a second clear signal, the first clear signals are all SANYO free from the rise of the effect of power source voltage, the second clear signal, corresponding to the rising state of the power supply voltage, i.e. the power supply voltage standing Those having a rise that was to follow the rise.

More preferred as a constituent of the present invention for achieving the above Symbol purpose, an inverter even stages connected in cascade to the delay circuit in the structure a plurality of sets connected in cascade, to the input terminal of the NOR circuit "L" The delay circuit and the odd-numbered stage of the inverter may be selected so as to input, specifically, a plurality of sets of even-numbered, for example, two-stage inverters cascaded with the delay circuit in the above configuration, for example, two sets of cascaded When connected, the output of the first stage of the second set of delay circuits, in other words, the output of the first set of the second stage inverter and the output of the first stage of the second set of inverters, It is preferable that the input is made to the input terminal of the NOR circuit.

According to the power-on-clear circuit of the present invention, initialization is performed by generating and outputting a clear signal that is not affected by the rising state of the power supply voltage and a clear signal corresponding to the rising state of the power supply voltage. A clear signal suitable for the power circuit can be output. Further , according to the power-on-clear circuit according to claim 2 of the present invention, since a plurality of delay circuits and even number of stages of inverters are connected in cascade, the clear signal that is not affected by the rising state of the power supply voltage is increased in pulse width. In addition to the clear signal, a clear signal corresponding to the rising state of the power supply voltage can be more reliably generated and output, and the reset operation after the power supply voltage rises can be performed more reliably.

1 is a circuit diagram showing a preferred embodiment of the present invention. The wave form diagram for demonstrating operation | movement of this embodiment. The elements on larger scale of FIG.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of the invention will be described with reference to the accompanying drawings.
As shown in FIG. 1, the power-on-clear circuit includes a pulse generation circuit 1 that generates a pulse when a power supply voltage supplied from a power supply terminal VCC is supplied, and a delay circuit 2 that delays and outputs the generated pulse. Two-stage cascaded CMOS inverters 3 and 4 for receiving delayed pulses, a delay circuit 5 for inputting the output of the CMOS inverter 4, and two-stage cascade for receiving pulses delayed by the delay circuit 5 It consists of connected CMOS inverters 6 and 7, and a NOR circuit 8 having an input terminal for inputting the output of the CMOS inverter 4 and an input terminal for inputting the output of the CMOS inverter 6.

  The output terminal of the CMOS inverter 7 is connected to the output terminal OUT1, and the output terminal of the NOR circuit 8 is connected to the output terminal OUT2. A clear signal is output from these output terminals OUT1 and OUT2. The power-on-clear circuit is connected to the other circuits that are initialized by receiving the clear signal when the power is turned on by the output terminals OUT1 and OUT2, and the clear signal output from the output terminal OUT2 is the power supply voltage. The clear signal is not affected by the rising state, and the clear signal output from the output terminal OUT1 is a clear signal corresponding to the rising state of the power supply voltage.

  The pulse generation circuit 1 is a conventionally known circuit, and initially follows the rise of the power supply voltage. However, when the power supply voltage becomes a constant voltage, the output is switched from “H” to “L” to generate a pulse. Each delay circuit 2, 5 has the same configuration and is a known RC circuit in which a resistor and a capacitor are connected in series, and each CMOS inverter 3, 4, 6, 7 also has the same configuration and a P channel. In this way, the power-on-clear circuit according to the present embodiment includes the delay circuits 2 and 5 and the two-stage CMOS inverter 3. , 4 and 6 and 7 are connected in cascade, and the output of the first set of CMOS inverters 4 and the output of the second set of CMOS inverters 6 are respectively NOR circuits 8. And configured to input to the input terminals.

  Next, the operation of the power-on-clear circuit configured as described above will be described with reference to FIGS. Each of (a) to (i) in FIG. 2 and FIG. 3 shows output waveforms at points A to I in FIG. When the power supply voltage is turned on, the VCC voltage rises and gradually increases (see FIG. 2A). In response to the rise of the power supply voltage, a pulse is output from the pulse generation circuit 1 (see FIG. 2B). In response to this pulse output, the voltage at the point C in FIG. 1 gradually increases. At this time, the capacitor at the delay circuit 2 is charged, so that the output at the point C is delayed and the rise is slow. It becomes a pulse (see FIG. 2 (c)), and the falling of this pulse becomes dull (see FIG. 3 (c)).

  The delayed pulse output is inverted by the CMOS inverter 3 (see FIG. 2D) and becomes “L”, and further inverted again by the CMOS inverter 4 (see FIG. 2E) and becomes “H”. While being input to the delay circuit 5, it is also input to one input terminal of the NOR circuit 8. The pulse output input to the delay circuit 5 is charged to the capacitor, so that the output at the point F is delayed and becomes a pulse with a slow rise (see FIG. 2 (f)). The fall also becomes dull (see FIG. 3 (f)).

  The delayed pulse output is inverted by the CMOS inverter 6 (see FIG. 2G) and becomes “L”, and is input to the other input terminal of the NOR circuit 8, while being further inverted by the CMOS inverter 7. It becomes “H” and is output to the output terminal OUT1 (see FIG. 2H). The pulse output to the output terminal OUT1 becomes the second clear signal. As shown in FIG. 2 (h), the second clear signal is generated when the power supply voltage rises (FIG. 2 (a)). (See reference).

  As shown in FIG. 3B, the pulse output from the pulse generation circuit 1 becomes “L” when 71 microseconds elapses after the power is turned on (t3 in FIG. 3). Therefore, the fall of the output becomes dull and the inversion is delayed at the point C in FIG. 1, so that “H” is maintained from t3 to t4 in FIG. 3 (see FIG. 3C). For this reason, since the output at the point E where the output at the point C is re-inverted is also “H”, even if the output of the above-described CMOS inverter 6, that is, the output at the point G becomes “L”, NOR The output of the circuit 8 still remains “L”.

  When t4 in FIG. 3 is reached, the output at the point C in FIG. 1 exceeds the threshold value of the P-channel MOS transistor constituting the CMOS inverter 3, so the output at the point D is inverted and becomes “H”. The output at the re-inverted point E becomes “L” and is input to the NOR circuit 8. Due to the output of the CMOS inverter 4 inverted to “L” and the input from the CMOS inverter 6 that maintains “L”, “L” is input to each input terminal of the NOR circuit 8. Is inverted to "H" and output to the output terminal OUT2 (see FIGS. 2 (i) and 3 (i)). The pulse output to the output terminal OUT2 becomes the first clear signal. As shown in FIG. 2 (i), the first clear signal is the rise of the power supply voltage (FIG. 2 (a)). This is generated as a pulse that is not affected by reference.

  When t5 in FIG. 3 is reached, the output at the point E in FIG. 1, that is, the output of the CMOS inverter 4 maintains “L”, while the output at the point F that has been delayed to “H” is also “L”. It becomes. Accordingly, since the output at point G, that is, the output of the CMOS inverter 6 is inverted to “H”, the outputs of the CMOS inverter 7 and the NOR circuit 8 become “L”, and the clear signals from the output terminals OUT1 and OUT2 are output. Output also stops.

  The power-on-clear circuit according to the present invention is not limited to the above-described embodiment. For example, the power-on-clear circuit of the pulse generation circuit 1 can be provided without providing the first delay circuit 2 and the CMOS inverters 3 and 4. The output may be input to one input terminal of the NOR circuit 8 from the preceding stage of the delay circuit 5. The inverters 3, 4, 6, and 7 are not limited to two stages, and may be any number of stages such as four stages and six stages, and are not limited to CMOS inverters. Furthermore, the number of combinations of the delay circuit and the CMOS inverter is not limited to two, and may be three or more. Further, the outputs of the output terminals OUT1 and OUT2 may be selectively supplied to a circuit that needs to be initialized.

1 Pulse generation circuit 2, 5 Delay circuit 3, 4, 6, 7 CMOS inverter 8 NOR circuit

Claims (2)

A pulse generation circuit that generates a pulse upon power-on, a delay circuit that delays and outputs the generated pulse, an even-numbered inverter connected in cascade to which the delayed pulse is input, and an output on the preceding stage of the delay circuit And a NOR circuit that outputs a clear signal, and the output of the NOR circuit is used as a first clear signal, while the cascade is connected to the cascade circuit. A power-on-clear circuit characterized in that the output of the last-stage inverter in the connected even-stage inverter is a second clear signal . 2. The power-on-clear circuit according to claim 1 , wherein a plurality of sets of even-numbered inverters connected in cascade are connected in cascade .

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