JP2011187877A - Semiconductor device, and method of manufacturing the same - Google Patents

Semiconductor device, and method of manufacturing the same Download PDF

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JP2011187877A
JP2011187877A JP2010054333A JP2010054333A JP2011187877A JP 2011187877 A JP2011187877 A JP 2011187877A JP 2010054333 A JP2010054333 A JP 2010054333A JP 2010054333 A JP2010054333 A JP 2010054333A JP 2011187877 A JP2011187877 A JP 2011187877A
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sealing resin
semiconductor device
plate
mold
manufacturing
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Shinka Ri
辰華 李
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Panasonic Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
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    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
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  • Engineering & Computer Science (AREA)
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To fix a radiator plate to a sealing resin without using an adhesive. <P>SOLUTION: The semiconductor device includes: a wiring board 10; a semiconductor element 12 fixed to a surface of the wiring board 10; metal wires 13 for electrically connecting the wiring board 10 and the semiconductor element 12 to each other; a sealing resin 18 for sealing the wiring board 10, the semiconductor element 12 and the metal wires 13; and a radiator plate 14 crimped to the sealing resin 18. The front surface of the radiator plate 14 and a part of side faces of the radiator plate 14 are exposed from the sealing resin 18. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、半導体装置及びその製造方法に関し、特に、放熱板を有する半導体装置及びその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a heat sink and a manufacturing method thereof.

近年、デジタル化社会の進化に連れて、日常生活中の情報量は増加の一途である。例えば、無線通信の情報を送信する携帯電話基地局の増幅器では、高周波化又は高出力化が求められている。また例えば、画像デジタル機器では、高機能化、薄型化及び高画質化に伴い、大量のデジタル信号を瞬時に処理し転送する機能が求められている。   In recent years, the amount of information in daily life has been increasing as the digital society has evolved. For example, an amplifier of a mobile phone base station that transmits wireless communication information is required to have a higher frequency or higher output. In addition, for example, image digital devices are required to have a function of instantaneously processing and transferring a large amount of digital signals as the functions, thickness, and image quality are increased.

半導体装置では、半導体素子の熱を放熱することが重要である。特に、高出力化された半導体装置では、半導体素子の発熱量が多いため、半導体素子の熱を放熱することが重要である。そこで、放熱板を設け、放熱板により、半導体素子の熱を放熱する方法がある。   In a semiconductor device, it is important to dissipate heat from the semiconductor element. Particularly in a semiconductor device with high output, it is important to dissipate heat from the semiconductor element because the semiconductor element generates a large amount of heat. Therefore, there is a method in which a heat sink is provided and the heat of the semiconductor element is dissipated by the heat sink.

以下に、放熱板を有する半導体装置の製造方法について、図11〜図16及び図17(a) 〜(b) を参照しながら説明する。図11〜図16は、従来の半導体装置の製造方法を示す断面図である。図17(a) は、従来の半導体装置の構造を示す平面図である。図17(b) は、従来の半導体装置の構造を示す断面図である。具体的には、図17(b) は、図17(a) に示すXVIIb-XVIIb線における断面図である。   Below, the manufacturing method of the semiconductor device which has a heat sink is demonstrated, referring FIGS. 11-16 and FIG. 17 (a)-(b). 11 to 16 are sectional views showing a conventional method for manufacturing a semiconductor device. FIG. 17A is a plan view showing the structure of a conventional semiconductor device. FIG. 17B is a cross-sectional view showing the structure of a conventional semiconductor device. Specifically, FIG. 17 (b) is a cross-sectional view taken along line XVIIb-XVIIb shown in FIG. 17 (a).

まず、図11に示すように、電極パッド101を有する配線用基板100Xの表面に、電極パッド(図示省略)を有する半導体素子102を固着する。その後、金属線103により、配線用基板100Xの電極パッド101と、半導体素子102の電極パッドとを接続する。その後、封止樹脂104により、配線用基板100X、半導体素子102及び金属線103を封止する。このようにして、素子用板Wを形成する。   First, as shown in FIG. 11, a semiconductor element 102 having electrode pads (not shown) is fixed to the surface of a wiring substrate 100X having electrode pads 101. Thereafter, the electrode pad 101 of the wiring substrate 100 </ b> X and the electrode pad of the semiconductor element 102 are connected by the metal wire 103. Thereafter, the wiring substrate 100X, the semiconductor element 102, and the metal wire 103 are sealed with a sealing resin 104. In this way, the element plate W is formed.

次に、図12に示すように、シリンダ105により、封止樹脂104の表面における半導体素子102と対応する領域(塗布領域)に、接着剤106を塗布する。   Next, as shown in FIG. 12, an adhesive 106 is applied to a region (application region) corresponding to the semiconductor element 102 on the surface of the sealing resin 104 by the cylinder 105.

次に、図13に示すように、パッド107に真空吸着させた放熱板108を、接着剤106と対応させる。   Next, as shown in FIG. 13, the heat sink 108 vacuum-adsorbed on the pad 107 is made to correspond to the adhesive 106.

次に、図14に示すように、パッド107を下方に移動させて、放熱板108を接着剤106に圧着する。   Next, as shown in FIG. 14, the pad 107 is moved downward, and the heat sink 108 is pressure-bonded to the adhesive 106.

次に、図15に示すように、窒素環境下で加熱し、接着剤106を硬化させて、接着剤106により、放熱板108を封止樹脂104に固着する。   Next, as shown in FIG. 15, heating is performed in a nitrogen environment to cure the adhesive 106, and the heat radiating plate 108 is fixed to the sealing resin 104 with the adhesive 106.

次に、図16に示すように、ダイシング装置により、素子用板Wを、各半導体素子102毎に分割し、各半導体装置に個片化する。これにより、図17(a) 〜(b) に示すように、配線基板100と、半導体素子102と、金属線103と、封止樹脂104と、接着剤106により封止樹脂104に固着された放熱板108とを有する半導体装置を得る。   Next, as shown in FIG. 16, the element plate W is divided for each semiconductor element 102 by a dicing apparatus and separated into individual semiconductor devices. As a result, as shown in FIGS. 17A to 17B, the wiring substrate 100, the semiconductor element 102, the metal wire 103, the sealing resin 104, and the adhesive 106 are fixed to the sealing resin 104. A semiconductor device having the heat sink 108 is obtained.

以上のようにして、従来の半導体装置を製造する。   As described above, a conventional semiconductor device is manufactured.

特開2002−324816号公報JP 2002-324816 A 特開平9−66335号公報JP-A-9-66335

しかしながら、従来の半導体装置では、以下に示す問題がある。   However, the conventional semiconductor device has the following problems.

例えば、接着剤として、低チクソ性接着剤を用いた場合、低チクソ性接着剤は、ベースレジンの含有量が多いため、加熱時に化学反応により生じたエアが、接着剤中に残留し易い。このため、接着剤により、放熱板を封止樹脂に良好に固着することができず、ひいては、放熱板が剥がれるという問題がある。また、低チクソ性接着剤は、濡れ性が良い。このため、接着剤への放熱板の圧着時に、接着剤が広がり易く、接着剤が、放熱板の側面及び封止樹脂における塗布領域以外の領域にまで広がる。このように、ブリード現象が起こって、外観不良となる虞がある。   For example, when a low thixotropic adhesive is used as the adhesive, the low thixotropic adhesive has a large base resin content, so that air generated by a chemical reaction during heating tends to remain in the adhesive. For this reason, the heat radiation plate cannot be satisfactorily fixed to the sealing resin by the adhesive, and as a result, there is a problem that the heat radiation plate is peeled off. Further, the low thixotropic adhesive has good wettability. For this reason, at the time of pressure bonding of the heat sink to the adhesive, the adhesive easily spreads, and the adhesive spreads to the side surface of the heat sink and the region other than the application region in the sealing resin. In this way, there is a possibility that the bleeding phenomenon occurs and the appearance is deteriorated.

一方、接着剤として、例えば、高チクソ性接着剤を用いた場合、高チクソ性接着剤は、濡れ性が悪い。このため、接着剤への放熱板の圧着時に、接着剤中にボイドが発生し易く、加熱時に、ボイド内のエアが膨張し、放熱板が剥れるという問題がある。また、高チクソ性接着剤は、濡れ性が悪いため、接着剤の塗布量にバラツキが生じる虞がある。   On the other hand, when a high thixotropic adhesive is used as the adhesive, for example, the high thixotropic adhesive has poor wettability. For this reason, when the heat sink is pressure-bonded to the adhesive, voids are likely to be generated in the adhesive, and during heating, the air in the voids expands and the heat sink is peeled off. In addition, since the high thixotropic adhesive has poor wettability, there is a possibility that the amount of adhesive applied may vary.

また、接着剤は、有機樹脂の含有量が多いため、吸湿性が高い。このため、封止樹脂と接着剤との界面、及び接着剤と放熱板との界面に水が溜まり易い。このため、加熱時に、水が気化して水蒸気が発生し、放熱板が剥がれるという問題がある。   In addition, the adhesive has a high hygroscopicity because it contains a large amount of organic resin. For this reason, water easily collects at the interface between the sealing resin and the adhesive and between the adhesive and the heat sink. For this reason, at the time of a heating, water evaporates and water vapor | steam generate | occur | produces and there exists a problem that a heat sink is peeled off.

また、接着剤106により放熱板108を封止樹脂104に固着した場合、次のような製造過程を経る必要がある。即ち、図12に示すように、封止樹脂104の表面における各塗布領域に、各半導体素子102と対応する接着剤106を塗布した後、図14に示すように、各接着剤106に、各半導体素子102と対応する放熱板108を圧着し、その後、図15に示すように、接着剤106を硬化する。このため、生産性の低下及びコストの上昇を招く虞がある。   When the heat sink 108 is fixed to the sealing resin 104 with the adhesive 106, it is necessary to go through the following manufacturing process. That is, as shown in FIG. 12, after applying an adhesive 106 corresponding to each semiconductor element 102 to each application region on the surface of the sealing resin 104, each adhesive 106 is applied to each adhesive 106 as shown in FIG. The heat sink 108 corresponding to the semiconductor element 102 is pressure-bonded, and then the adhesive 106 is cured as shown in FIG. For this reason, there exists a possibility of causing the fall of productivity and the raise of cost.

以上のように、接着剤により放熱板を封止樹脂に固着した場合、放熱板が剥がれるという問題がある。さらに、外観不良、接着剤の塗布量のバラツキ、生産性の低下又はコストの上昇を招く虞がある。   As described above, when the heat sink is fixed to the sealing resin with an adhesive, there is a problem that the heat sink is peeled off. Furthermore, there is a risk of causing poor appearance, variation in the amount of adhesive applied, reduced productivity, or increased cost.

前記に鑑み、本発明の目的は、接着剤を用いずに、放熱板を封止樹脂に固定することである。   In view of the above, an object of the present invention is to fix the heat sink to the sealing resin without using an adhesive.

前記の目的を達成するために、本発明に係る半導体装置は、配線基板と、配線基板の表面に固着された半導体素子と、配線基板と半導体素子とを電気的に接続する金属線と、配線基板、半導体素子及び金属線を封止する封止樹脂と、封止樹脂に圧着された放熱板とを備え、放熱板の表面及び放熱板の側面の一部は、封止樹脂から露出していることを特徴とする。   In order to achieve the above object, a semiconductor device according to the present invention includes a wiring board, a semiconductor element fixed to the surface of the wiring board, a metal wire that electrically connects the wiring board and the semiconductor element, and wiring. A sealing resin that seals the substrate, the semiconductor element, and the metal wire, and a heat sink that is pressure-bonded to the sealing resin. The surface of the heat sink and a part of the side surface of the heat sink are exposed from the sealing resin. It is characterized by being.

本発明に係る半導体装置によると、放熱板が封止樹脂に圧着されている。これにより、接着剤を用いずに、放熱板を封止樹脂に固定することができるため、放熱板が脱落することを防止することができる。   According to the semiconductor device of the present invention, the heat sink is pressure-bonded to the sealing resin. Thereby, since a heat sink can be fixed to sealing resin, without using an adhesive agent, it can prevent that a heat sink falls off.

さらに、放熱板の表面だけでなく、放熱板の側面の一部を、封止樹脂から露出させることにより、放熱板の露出面積を増大させることができるため、放熱板の放熱効率を向上させることができる。   Furthermore, by exposing not only the surface of the heat sink but also part of the side surface of the heat sink from the sealing resin, the exposed area of the heat sink can be increased, thus improving the heat dissipation efficiency of the heat sink. Can do.

本発明に係る半導体装置において、放熱板は、表面が封止樹脂から露出し半導体素子と対応して配置された本体部と、一端が本体部の側面と接続し且つ他端が封止樹脂から露出するリード部とを有していることが好ましい。   In the semiconductor device according to the present invention, the heat radiating plate has a main body portion whose surface is exposed from the sealing resin and disposed corresponding to the semiconductor element, one end connected to the side surface of the main body portion, and the other end from the sealing resin. It is preferable to have an exposed lead portion.

このようにすると、一端が本体部の側面に接続するリード部の他端を、封止樹脂から露出させることにより、放熱板の露出面積を増大させることができるため、放熱板の放熱効率を向上させることができる。   In this way, the exposed area of the heat sink can be increased by exposing the other end of the lead part, one end of which is connected to the side surface of the main body, from the sealing resin, thereby improving the heat dissipation efficiency of the heat sink. Can be made.

さらに、リード部の他端を、封止樹脂から露出させることにより、リード部を、本体部の側面から封止樹脂の側面に向かって延ばすことができるため、半導体装置が反ることを抑制することができる。   Furthermore, by exposing the other end of the lead portion from the sealing resin, the lead portion can be extended from the side surface of the main body portion toward the side surface of the sealing resin, so that the semiconductor device is prevented from warping. be able to.

本発明に係る半導体装置において、放熱板は、放熱板の裏面に設けられ且つ封止樹脂に埋め込まれた第1の凸部を有していることが好ましい。   In the semiconductor device according to the present invention, it is preferable that the heat sink has a first convex portion provided on the back surface of the heat sink and embedded in the sealing resin.

このようにすると、放熱板の裏面に第1の凸部を設け、第1の凸部を封止樹脂に埋め込むことにより、放熱板と封止樹脂との接触面積を増大させることができるため、放熱板を封止樹脂に強固に固定することができる。   In this way, since the first convex portion is provided on the back surface of the heat sink and the first convex portion is embedded in the sealing resin, the contact area between the heat sink and the sealing resin can be increased. The heat sink can be firmly fixed to the sealing resin.

本発明に係る半導体装置において、放熱板は、本体部の側面と接続し且つ封止樹脂に埋め込まれた第2の凸部を有していることが好ましい。   In the semiconductor device according to the present invention, it is preferable that the heat sink has a second convex portion that is connected to the side surface of the main body and is embedded in the sealing resin.

このようにすると、本体部の側面に第2の凸部を接続し、第2の凸部を封止樹脂に埋め込むことにより、放熱板と封止樹脂との接触面積を増大させることができるため、放熱板を封止樹脂に強固に固定することができる。   In this case, the contact area between the heat sink and the sealing resin can be increased by connecting the second convex part to the side surface of the main body part and embedding the second convex part in the sealing resin. The heat sink can be firmly fixed to the sealing resin.

本発明に係る半導体装置において、放熱板における本体部及びリード部は、一体に形成されていることが好ましい。   In the semiconductor device according to the present invention, it is preferable that the main body portion and the lead portion of the heat radiating plate are integrally formed.

本発明に係る半導体装置において、封止樹脂と放熱板との間には接着剤が介在しておらず、放熱板は、封止樹脂と接していることが好ましい。   In the semiconductor device according to the present invention, it is preferable that no adhesive is interposed between the sealing resin and the heat sink, and the heat sink is in contact with the sealing resin.

前記の目的を達成するために、本発明に係る半導体装置の製造方法は、本発明に係る半導体装置を製造する半導体装置の製造方法であって、放熱用板を準備する工程(a)と、配線用基板の表面に複数の半導体素子が固着された素子用板を準備する工程(b)と、第1の金型に、表面が第1の金型の設置面と対向するように放熱用板を設置する工程(c)と、第2の金型に、配線用基板の裏面が第2の金型の設置面と対向するように素子用板を設置する工程(d)と、第1の金型に設置された放熱用板の裏面に、封止樹脂を投入する工程(e)と、工程(e)の後に、第1の金型と第2の金型とを閉じて、封止樹脂を圧縮成形すると共に、放熱用板を封止樹脂に圧着する工程(f)と、第1の金型と第2の金型とを開いて、封止樹脂に放熱用板が圧着された素子用板を取り出す工程(g)と、工程(g)の後に、素子用板を分割し、半導体装置に個片化する工程(h)とを備えることを特徴とする。   In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device according to the present invention, comprising a step (a) of preparing a heat dissipation plate, A step (b) of preparing an element plate in which a plurality of semiconductor elements are fixed to the surface of a wiring substrate; and for heat dissipation so that the surface of the first mold faces the installation surface of the first mold A step (c) of installing a plate, a step (d) of installing an element plate on the second mold so that the back surface of the wiring board faces the installation surface of the second mold, and the first After the step (e) and the step (e) of putting the sealing resin on the back surface of the heat radiating plate installed in the mold, the first mold and the second mold are closed and sealed. The step (f) of compression-molding the stop resin and press-bonding the heat radiation plate to the sealing resin, and opening the first mold and the second mold to release heat to the sealing resin There the step (g) taking out the plate for crimped element, after step (g), by dividing the element for plate, characterized in that it comprises a step (h) singulating the semiconductor device.

本発明に係る半導体装置の製造方法によると、放熱用板を封止樹脂に圧着する。これにより、接着剤を用いずに、放熱板を封止樹脂に固定することができるため、放熱板が脱落することを防止することができる。   According to the method for manufacturing a semiconductor device of the present invention, the heat dissipation plate is pressure-bonded to the sealing resin. Thereby, since a heat sink can be fixed to sealing resin, without using an adhesive agent, it can prevent that a heat sink falls off.

加えて、放熱板を封止樹脂に固着する接着剤を不要にすることができるため、封止樹脂への接着剤の塗布工程、接着剤への放熱板の圧着工程及び接着剤の硬化工程を不要にすることができる。このため、生産性の低下及びコストの上昇を招くことを防止することができる。   In addition, since the adhesive for fixing the heat sink to the sealing resin can be made unnecessary, the application process of the adhesive to the sealing resin, the pressure bonding process of the heat sink to the adhesive and the curing process of the adhesive It can be made unnecessary. For this reason, it is possible to prevent a decrease in productivity and an increase in cost.

さらに、放熱用板の封止樹脂への圧着を、封止樹脂の圧縮成形と共に行うことができる。これにより、生産性の向上及びコストの削減を図ることができる。   Furthermore, the pressure bonding of the heat dissipation plate to the sealing resin can be performed together with the compression molding of the sealing resin. Thereby, productivity can be improved and cost can be reduced.

本発明に係る半導体装置の製造方法において、放熱用板は、枠体部と、複数の本体部と、各々が本体部の側面に接続する複数のリード部とを有し、複数のリード部のうち、隣接するリード部同士は互いに連結し、隣接するリード部以外のリード部は、枠体部と連結していることが好ましい。   In the method of manufacturing a semiconductor device according to the present invention, the heat dissipation plate includes a frame body portion, a plurality of main body portions, and a plurality of lead portions each connected to a side surface of the main body portion. Of these, adjacent lead portions are preferably connected to each other, and lead portions other than the adjacent lead portions are preferably connected to the frame body portion.

本発明に係る半導体装置の製造方法において、放熱用板は、各々が放熱用板の裏面に設けられた複数の第1の凸部を有していることが好ましい。   In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the heat dissipating plate has a plurality of first convex portions each provided on the back surface of the heat dissipating plate.

本発明に係る半導体装置の製造方法において、放熱用板は、各々が本体部の側面に接続する複数の第2の凸部を有していることが好ましい。   In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the heat dissipating plate has a plurality of second convex portions each connected to a side surface of the main body portion.

本発明に係る半導体装置の製造方法において、放熱用板における枠体部、本体部及びリード部は、一体に形成されていることが好ましい。   In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the frame body portion, the main body portion, and the lead portion of the heat dissipation plate are integrally formed.

本発明に係る半導体装置の製造方法において、工程(h)において、リード部同士が連結する部分、及びリード部と枠体部とが連結する部分が切断されることが好ましい。   In the method for manufacturing a semiconductor device according to the present invention, in the step (h), it is preferable that a portion where the lead portions are connected and a portion where the lead portion and the frame body portion are connected are cut.

本発明に係る半導体装置の製造方法において、放熱用板における枠体部には、ガイド孔が設けられており、工程(c)において、ガイド孔に、第1の金型に設けられたガイドピンを貫通させることにより、放熱用板を第1の金型に固定することが好ましい。   In the method for manufacturing a semiconductor device according to the present invention, a guide hole is provided in the frame portion of the heat dissipation plate, and the guide pin provided in the first mold in the guide hole in the step (c). It is preferable that the heat radiating plate is fixed to the first mold by penetrating the plate.

このようにすると、放熱用板の位置ずれを防止することができる。   If it does in this way, position shift of the board for heat dissipation can be prevented.

本発明に係る半導体装置の製造方法において、放熱用板は、その体積が、封止樹脂の熱膨張係数と配線用基板の熱膨張係数とに基づいて調整されていることが好ましい。   In the method for manufacturing a semiconductor device according to the present invention, it is preferable that the volume of the heat dissipation plate is adjusted based on the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the wiring substrate.

このようにすると、半導体装置に反りが発生することを抑制することができる。さらに、配線基板及び封止樹脂の材料を選択する際の制約を少なくすることができる。   In this way, it is possible to suppress the warpage of the semiconductor device. Furthermore, it is possible to reduce restrictions when selecting materials for the wiring board and the sealing resin.

(a) 〜(b) は、本発明の一実施形態に係る半導体装置の構成を示す図であり、(a) は、平面図であり、(b) は、(a) に示すIb-Ib線における断面図である。(a)-(b) is a figure which shows the structure of the semiconductor device which concerns on one Embodiment of this invention, (a) is a top view, (b) is Ib-Ib shown to (a) It is sectional drawing in a line. (a) 〜(b) は、本発明の一実施形態に係る半導体装置の製造方法を示す図であり、(a) は、平面図であり、(b) は、(a) に示すIIb-IIb線における断面図である。(a)-(b) is a diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, (a) is a plan view, (b) is IIb- It is sectional drawing in the IIb line. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. 本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention. (a) 〜(d) は、放熱用板の構成を示す平面図である。(a)-(d) is a top view which shows the structure of the board for thermal radiation. 従来の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. 従来の半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the conventional semiconductor device. (a) 〜(b) は、従来の半導体装置の構造を示す図であり、(a) は、平面図であり、(b) は、(a) に示すXVIIb-XVIIb線における断面図である。(a)-(b) is a figure which shows the structure of the conventional semiconductor device, (a) is a top view, (b) is sectional drawing in the XVIIb-XVIIb line | wire shown in (a) .

以下に、本発明の一実施形態に係る半導体装置について、図1(a) 〜(b) を参照しながら説明する。図1(a) は、本発明の一実施形態に係る半導体装置の構成を示す平面図である。図1(b) は、本発明の一実施形態に係る半導体装置の構成を示す断面図である。具体的には、図1(b) は、図1(a) に示すIb-Ib線における断面図である。なお、図1(a) 〜(b) 、並びに後述の図2〜図9において、簡略的に図示するために、各構成要素の厚み及び長さ等を、実際の厚み及び長さ等と異ならせている。   A semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 1 (a) to 1 (b). FIG. 1A is a plan view showing a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 1B is a cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 1B is a cross-sectional view taken along line Ib-Ib shown in FIG. In FIGS. 1A to 1B and FIGS. 2 to 9 to be described later, the thickness and length of each component are different from the actual thickness and length for the sake of simplicity. It is

図1に示すように、本実施形態に係る半導体装置は、電極パッド11を有する配線基板10と、接着剤(図示省略)により配線基板10の表面に固着され且つ電極パッド(図示省略)を有する高機能の半導体素子12と、配線基板10の電極パッド11と半導体素子12の電極パッドとを電気的に接続する金属線13と、配線基板10、半導体素子12及び金属線13を封止する封止樹脂18と、封止樹脂18に圧着された放熱板14とを備えている。放熱板14の表面及び放熱板14の側面の一部は、封止樹脂18から露出している。   As shown in FIG. 1, the semiconductor device according to the present embodiment has a wiring board 10 having electrode pads 11, and is fixed to the surface of the wiring board 10 with an adhesive (not shown) and has electrode pads (not shown). A high-performance semiconductor element 12, a metal wire 13 that electrically connects the electrode pad 11 of the wiring substrate 10 and the electrode pad of the semiconductor element 12, and a seal that seals the wiring substrate 10, the semiconductor element 12, and the metal wire 13. A stop resin 18 and a heat sink 14 crimped to the sealing resin 18 are provided. The surface of the heat sink 14 and a part of the side surface of the heat sink 14 are exposed from the sealing resin 18.

−放熱板−
放熱板14は、図1(a) 〜(b) に示すように、表面が封止樹脂18から露出し半導体素子12と対応して配置された本体部14aと、一端が本体部14aの側面に接続し且つ他端が封止樹脂18から露出するリード部14bと、放熱板14の裏面に設けられ且つ封止樹脂18に埋め込まれた第1の凸部14cと、本体部14aの側面に接続し且つ封止樹脂18に埋め込まれた第2の凸部14dとを有している。
−Heat sink−
As shown in FIGS. 1A to 1B, the heat radiating plate 14 has a main body portion 14a whose surface is exposed from the sealing resin 18 and arranged in correspondence with the semiconductor element 12, and one end is a side surface of the main body portion 14a. On the side surface of the main body portion 14a, a lead portion 14b whose other end is exposed from the sealing resin 18, a first convex portion 14c provided on the back surface of the heat radiating plate 14 and embedded in the sealing resin 18. And a second convex portion 14 d embedded in the sealing resin 18.

リード部14bは、本体部14aの側面から封止樹脂18の側面に向かって延びている。   The lead portion 14 b extends from the side surface of the main body portion 14 a toward the side surface of the sealing resin 18.

放熱板14における本体部14a、リード部14b、第1の凸部14c及び第2の凸部14dは、一体に形成されている。   The main body portion 14a, the lead portion 14b, the first convex portion 14c, and the second convex portion 14d in the heat radiating plate 14 are integrally formed.

放熱板14と封止樹脂18との間には接着剤が介在しておらず、放熱板14は、封止樹脂18と接している。   There is no adhesive between the heat sink 14 and the sealing resin 18, and the heat sink 14 is in contact with the sealing resin 18.

放熱板14は、高熱を吸収して放出する機能を有している。   The heat sink 14 has a function of absorbing and releasing high heat.

放熱板14としては、例えば、金属板又は合金板等を用いることができる。放熱板14の材料としては、例えば、熱伝導性の良い銅若しくはアルミニウム等の金属材料、銅合金等の合金材料、酸化アルミニウム等のセラミックス材料、又は窒化珪素等の有機材料が挙げられる。   As the heat sink 14, for example, a metal plate or an alloy plate can be used. Examples of the material of the heat radiating plate 14 include a metal material such as copper or aluminum having good thermal conductivity, an alloy material such as a copper alloy, a ceramic material such as aluminum oxide, or an organic material such as silicon nitride.

放熱板14として、封止樹脂18と接する面にめっきが施されたものを用いてもよい。これにより、放熱板14と封止樹脂18との密着性を向上させることができる。   As the heat radiating plate 14, a surface in contact with the sealing resin 18 may be used. Thereby, the adhesiveness of the heat sink 14 and the sealing resin 18 can be improved.

放熱板14における本体部14aの厚さは、例えば、0.1mmt以上であることが好ましい。   The thickness of the main body portion 14a in the heat radiating plate 14 is preferably 0.1 mmt or more, for example.

−配線基板−
配線基板10は、その表面における半導体素子12が固着される素子領域に、配線パターン(図示省略)及び複数の端子(図示省略)を有し、その表面における素子領域の外周に位置する外周領域に、複数の電極パッド11を有している。配線基板10の裏面には、複数列に配列されたランド(図示省略)が設けられている。
-Wiring board-
The wiring board 10 has a wiring pattern (not shown) and a plurality of terminals (not shown) in the element region to which the semiconductor element 12 is fixed on the surface, and the outer peripheral region located on the outer periphery of the element region on the surface. The plurality of electrode pads 11 are provided. Lands (not shown) arranged in a plurality of rows are provided on the back surface of the wiring board 10.

配線基板10は、単層基板であってもよいし、多層基板であってもよい。   The wiring substrate 10 may be a single layer substrate or a multilayer substrate.

配線基板10としては、例えば、樹脂基板を用いることができる。樹脂基板の材料としては、例えば、ガラス繊維若しくは不織布に、エポキシ樹脂、フェノール樹脂若しくはポリイミド樹脂を含浸して硬化させたもの、BTレジン又は液晶ポリマが挙げられる。また、配線基板10として、樹脂基板の代わりに、例えば、セラミック基板を用いてもよい。セラミック基板の材料としては、例えば、酸化アルミニウム、ガラス又は石英が挙げられる。   As the wiring substrate 10, for example, a resin substrate can be used. Examples of the material for the resin substrate include glass fiber or non-woven fabric impregnated with epoxy resin, phenol resin or polyimide resin and cured, BT resin, or liquid crystal polymer. Further, as the wiring substrate 10, for example, a ceramic substrate may be used instead of the resin substrate. Examples of the material for the ceramic substrate include aluminum oxide, glass, and quartz.

配線基板10の厚さは、例えば、60μm〜500μm、好ましくは、100μm〜200μm程度である。   The thickness of the wiring board 10 is, for example, about 60 μm to 500 μm, preferably about 100 μm to 200 μm.

−半導体素子−
半導体素子12は、その表面に内部回路(図示省略)と接続する配線(図示省略)が形成され、その表面における周辺領域に、配線と接続する複数の電極パッド(図示省略)を有している。
-Semiconductor element-
The semiconductor element 12 has wiring (not shown) connected to an internal circuit (not shown) formed on the surface thereof, and has a plurality of electrode pads (not shown) connected to the wiring in a peripheral region on the surface. .

半導体素子12の材料としては、例えば、シリコンを用いるが、シリコン以外の材料を用いてもよい。例えば、ゲルマニウム若しくはグラファイトのような元素材料、又は砒化ガリウム若しくはテルル化亜鉛のような化合物材料を用いてもよい。   As a material of the semiconductor element 12, for example, silicon is used, but a material other than silicon may be used. For example, an elemental material such as germanium or graphite, or a compound material such as gallium arsenide or zinc telluride may be used.

半導体素子12の厚さは、例えば、20μm〜500μm、好ましくは、50μm〜100μm程度である。   The thickness of the semiconductor element 12 is, for example, about 20 μm to 500 μm, preferably about 50 μm to 100 μm.

−接着剤−
配線基板10に半導体素子12を固定する接着剤は、有機物と無機物との混合物であり、該有機物は、例えば、エポキシ系樹脂、ポリイミド系樹脂及びアクリル系樹脂からなる群から選択される少なくとも一つを含む。
-Adhesive-
The adhesive that fixes the semiconductor element 12 to the wiring board 10 is a mixture of an organic substance and an inorganic substance, and the organic substance is, for example, at least one selected from the group consisting of epoxy resins, polyimide resins, and acrylic resins. including.

接着剤は、導電性接着剤であっても、絶縁性接着剤であってもよい。   The adhesive may be a conductive adhesive or an insulating adhesive.

接着剤としては、例えば、光開始剤が配合された紫外線硬化性樹脂が挙げられる。また、導電性接着剤としては、例えば、導電性フィラーとして銀フィラーが添加されたエポキシ系樹脂が挙げられる。   Examples of the adhesive include an ultraviolet curable resin containing a photoinitiator. Moreover, as a conductive adhesive, the epoxy resin to which the silver filler was added as a conductive filler is mentioned, for example.

接着剤は、ペーストであっても、半硬化状のシートであってもよい。   The adhesive may be a paste or a semi-cured sheet.

−金属線−
金属線13は、例えば、銅線、アルミニウム線、銀線又は金線であり、好ましくは、金線である。
-Metal wire-
The metal wire 13 is, for example, a copper wire, an aluminum wire, a silver wire or a gold wire, and is preferably a gold wire.

金属線13のループ高さ(「ループ高さ」とは、半導体素子12から金属線13までの高さをいう)は、例えば、40μm〜300μm、好ましくは、120μm程度である。金属線13の径は、例えば、15μm〜30μm、好ましくは、18μm〜25μm程度である。   The loop height of the metal wire 13 (“loop height” means the height from the semiconductor element 12 to the metal wire 13) is, for example, about 40 μm to 300 μm, and preferably about 120 μm. The diameter of the metal wire 13 is, for example, about 15 μm to 30 μm, preferably about 18 μm to 25 μm.

−封止樹脂−
封止樹脂18としては、例えば、熱硬化性のエポキシ系樹脂を用いることができる。
-Sealing resin-
As the sealing resin 18, for example, a thermosetting epoxy resin can be used.

封止樹脂18は、例えば、ビフェニル系樹脂、フェノール系樹脂、ナフタレン系樹脂及びアントラセン系樹脂からなる群から選択される少なくとも一つを含んでもよい。   The sealing resin 18 may include, for example, at least one selected from the group consisting of a biphenyl resin, a phenol resin, a naphthalene resin, and an anthracene resin.

封止樹脂18は、例えば、硬化剤、硬化促進剤又はフィラーの添加剤を含んでもよい。添加剤により、封止樹脂18の特性、生産性又は品質性を制御することが可能である。硬化剤としては、例えば、フェノール系硬化剤又は酸無水物類が挙げられる。硬化促進剤としては、例えば、リン系有機高分子化合物が挙げられる。フィラーとしては、例えば、溶融シリカ又は結晶シリカが挙げられる。   The sealing resin 18 may include, for example, a curing agent, a curing accelerator, or a filler additive. By the additive, it is possible to control the characteristics, productivity, or quality of the sealing resin 18. Examples of the curing agent include phenolic curing agents or acid anhydrides. As a hardening accelerator, a phosphorus organic polymer compound is mentioned, for example. Examples of the filler include fused silica or crystalline silica.

封止樹脂18の厚さは、例えば、100μm〜800μm、好ましくは、200μm〜650μm程度である。   The thickness of the sealing resin 18 is, for example, about 100 μm to 800 μm, preferably about 200 μm to 650 μm.

以下に、本発明の一実施形態に係る半導体装置の製造方法について、図2(a) 及び(b) 〜図9を参照しながら説明する。図2(a) は、本発明の一実施形態に係る半導体装置の製造方法を示す平面図である。図2(b) は、本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。具体的には、図2(b) は、図2(a) に示すIIb-IIb線における断面図である。図3〜図9は、本発明の一実施形態に係る半導体装置の製造方法を示す断面図である。   A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to FIGS. 2 (a) and (b) to FIG. FIG. 2A is a plan view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG. 2B is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 2B is a cross-sectional view taken along the line IIb-IIb shown in FIG. 3 to 9 are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

まず、図2(a) 及び(b) に示すように、放熱用板14Xを準備する。放熱用板14Xは、枠体部14eと、本体部14aと、本体部14aの側面と接続するリード部14bと、放熱用板14の裏面に設けられた第1の凸部14cと、本体部14aの側面と接続する第2の凸部14dとを有している。   First, as shown in FIGS. 2A and 2B, a heat radiation plate 14X is prepared. The heat radiating plate 14X includes a frame body portion 14e, a main body portion 14a, a lead portion 14b connected to a side surface of the main body portion 14a, a first convex portion 14c provided on the back surface of the heat radiating plate 14, and a main body portion. And a second convex portion 14d connected to the side surface of 14a.

図2(a) に示すように、リード部14bのうち、隣接するリード部14b同士は互いに連結している。リード部14bのうち、隣接するリード部14b以外のリード部14bは、枠体部14eと連結している。   As shown in FIG. 2A, among the lead portions 14b, the adjacent lead portions 14b are connected to each other. Of the lead portions 14b, the lead portions 14b other than the adjacent lead portions 14b are connected to the frame body portion 14e.

枠体部14eには、ガイドピン(後述の図4:15p参照)を貫通させるガイド孔hが設けられている。   The frame body portion 14e is provided with a guide hole h that allows a guide pin (see FIG. 4: 15p described later) to pass therethrough.

本体部14aは、マトリクス状に配列されている。   The main body portions 14a are arranged in a matrix.

放熱用板14Xの形成方法としては、第1に例えば、平板を切削して、放熱用板の形状にする機械加工法が挙げられる。第2に例えば、平板を、放熱用板の形状に打ち抜くプレス加工法が挙げられる。   As a method for forming the heat radiating plate 14X, first, for example, a machining method in which a flat plate is cut into a shape of the heat radiating plate can be mentioned. Secondly, for example, there is a pressing method in which a flat plate is punched into the shape of a heat radiating plate.

一方、図3に示すように、素子用板Wを準備する。素子用板Wは、電極パッド11を有する配線用基板10Xと、各々が電極パッド(図示省略)を有する複数の半導体素子12と、配線用基板10Xの電極パッド11と半導体素子12の電極パッドとを電気的に接続する金属線13とを有している。   On the other hand, as shown in FIG. 3, an element plate W is prepared. The element plate W includes a wiring substrate 10X having electrode pads 11, a plurality of semiconductor elements 12 each having an electrode pad (not shown), an electrode pad 11 of the wiring substrate 10X, and an electrode pad of the semiconductor element 12. Are electrically connected to each other.

半導体素子12は、配線用基板10X上に、マトリクス状に配列されている。   The semiconductor elements 12 are arranged in a matrix on the wiring substrate 10X.

次に、図4に示すように、プレス機(圧縮機)の下金型(第1の金型)15に、リリースフィルム16を固定する。このとき、下金型15に設けた真空吸着孔15hを用いて、リリースフィルム16を下金型15に真空吸着させると共に、下金型15に設けたガイドピン15pを、リリースフィルム16に貫通させる。リリースフィルム16の厚さは、薄いことが好ましく、例えば、50μmであることが好ましい。   Next, as shown in FIG. 4, the release film 16 is fixed to the lower mold (first mold) 15 of the press machine (compressor). At this time, the release film 16 is vacuum-sucked to the lower mold 15 using the vacuum suction holes 15h provided in the lower mold 15, and the guide pins 15p provided to the lower mold 15 are passed through the release film 16. . The release film 16 is preferably thin, for example, 50 μm.

その後、下金型15に、下金型15との間にリリースフィルム16を挟んで、表面が下金型15の設置面と対向するように放熱用板14Xを設置する。このとき、ガイドピン15pを、放熱用板14Xにおける枠体部14eに設けたガイド孔hに貫通させる。これにより、放熱用板14Xを下金型15に固定し、放熱用板14Xが位置ずれすることを防止することができる。   Thereafter, the release film 16 is sandwiched between the lower mold 15 and the lower mold 15, and the heat radiation plate 14 </ b> X is installed so that the surface faces the installation surface of the lower mold 15. At this time, the guide pin 15p is passed through the guide hole h provided in the frame body portion 14e of the heat dissipation plate 14X. Thereby, the heat radiating plate 14X can be fixed to the lower mold 15, and the heat radiating plate 14X can be prevented from being displaced.

一方、図4に示すように、プレス機の上金型(第2の金型)17に、配線用基板10Xの裏面が上金型17の設置面と対向するように素子用板Wを設置する。このとき、上金型17に設けた真空吸着孔17hを用いて、素子用板Wを上金型17に真空吸着させる。   On the other hand, as shown in FIG. 4, the element plate W is installed on the upper mold (second mold) 17 of the press machine so that the back surface of the wiring board 10 </ b> X faces the installation surface of the upper mold 17. To do. At this time, the element plate W is vacuum-sucked to the upper mold 17 using the vacuum suction holes 17 h provided in the upper mold 17.

次に、図5に示すように、放熱用板14Xの裏面に、未硬化の封止樹脂18を投入した後、金型温度を、封止樹脂18の溶融温度以上の温度(例えば165℃〜185℃)とし、封止樹脂18を溶融する。このとき、リリースフィルム16により、溶融した封止樹脂18が、下金型15と放熱用板14Xとの間に入り込むことを防止する。未硬化の封止樹脂18は、粉末状、顆粒状、タブレット状、シート状又は液体状の封止樹脂であり、好ましくは、顆粒状の封止樹脂である。   Next, as shown in FIG. 5, after putting uncured sealing resin 18 on the back surface of heat dissipation plate 14X, the mold temperature is set to a temperature equal to or higher than the melting temperature of sealing resin 18 (for example, 165 ° C. to 185 ° C.) and the sealing resin 18 is melted. At this time, the release film 16 prevents the molten sealing resin 18 from entering between the lower mold 15 and the heat dissipation plate 14X. The uncured sealing resin 18 is a powder, granule, tablet, sheet, or liquid sealing resin, and is preferably a granular sealing resin.

次に、図6に示すように、封止樹脂18が完全に溶融した後、下金型15を駆動し、下金型15を上金型17に合わせて、減圧状態にし、下金型15と上金型17とを閉じる。その後、モータ19により、下金型15を上金型17の方向(矢印参照)に押圧し、封止樹脂18を圧縮成形すると共に、封止樹脂18に放熱用板14Xを圧着する。その後、図7に示すように、封止樹脂18が完全に硬化した後、下金型15と上金型17とを開いて、図8に示すように、封止樹脂18に放熱用板14Xが圧着された素子用板Wを取り出す。   Next, as shown in FIG. 6, after the sealing resin 18 is completely melted, the lower mold 15 is driven, the lower mold 15 is aligned with the upper mold 17, and the pressure is reduced. And the upper mold 17 are closed. Thereafter, the motor 19 presses the lower mold 15 in the direction of the upper mold 17 (see the arrow), compresses the sealing resin 18, and presses the heat radiation plate 14 </ b> X against the sealing resin 18. Thereafter, as shown in FIG. 7, after the sealing resin 18 is completely cured, the lower mold 15 and the upper mold 17 are opened, and as shown in FIG. The element plate W to which is bonded is taken out.

次に、図9に示すように、ダイシング装置により、封止樹脂18に放熱用板14Xが圧着された素子用板Wを、各半導体素子12毎に分割し、各半導体装置に個片化する。このとき、リード部14b同士が連結する部分、及びリード部14bと枠体部14eとが連結する部分を切断する。このため、リード部14bを細く形成することが好ましい。これにより、リード部14bにおける連結部分を容易に切断することができる。   Next, as shown in FIG. 9, the element plate W in which the heat radiating plate 14 </ b> X is pressure-bonded to the sealing resin 18 is divided for each semiconductor element 12 by the dicing apparatus and separated into individual semiconductor devices. . At this time, a portion where the lead portions 14b are connected and a portion where the lead portion 14b and the frame portion 14e are connected are cut. For this reason, it is preferable to form the lead part 14b thin. Thereby, the connection part in the lead part 14b can be cut | disconnected easily.

以上のようにして、本実施形態に係る半導体装置を製造することができる。   As described above, the semiconductor device according to this embodiment can be manufactured.

ここで、封止樹脂は、溶融温度以上の温度で、加熱されると、その状態が、半硬化状態(固体状態)から、溶融状態(液体状態)を経て、硬化状態(固体状態)になる。   Here, when the sealing resin is heated at a temperature equal to or higher than the melting temperature, the state changes from a semi-cured state (solid state) to a cured state (solid state) through a molten state (liquid state). .

このため、封止樹脂の圧縮成形の際に、金属線13が変形する、及び金属線13が変形して金属線13同士が接近することを防止するためには、封止樹脂の圧縮成形を行うタイミングが重要であり、封止樹脂が完全に溶融してからゲル化するまでの間に、封止樹脂の圧縮成形を完了させることが必要である。   For this reason, in order to prevent the metal wire 13 from being deformed and the metal wire 13 from being deformed and approaching the metal wires 13 during compression molding of the sealing resin, compression molding of the sealing resin is performed. The timing to perform is important, and it is necessary to complete the compression molding of the sealing resin between the melting of the sealing resin and the gelation.

封止樹脂が完全に溶融していない状態で、早々に上,下金型を閉じて封止樹脂の圧縮成形を行う、又は封止樹脂がゲル化した状態で、未だに上,下金型を開かずに封止樹脂の圧縮成形を行えば、金属線が変形する、及び金属線が変形して金属線同士が接近する。これにより、品質の低下及び歩留りの低下を招く懸念がある。   While the sealing resin is not completely melted, close the upper and lower molds immediately and perform compression molding of the sealing resin, or with the sealing resin gelled, the upper and lower molds are still If compression molding of sealing resin is performed without opening, a metal wire will deform | transform and a metal wire will deform | transform and metal wires will approach. Thereby, there exists a concern which causes the fall of quality and the fall of a yield.

ところで、半導体装置の製造過程での加熱時に、半導体装置内に応力歪みが発生し、これにより、半導体装置に反りが発生するという懸念がある。   By the way, there is a concern that stress distortion occurs in the semiconductor device during heating in the manufacturing process of the semiconductor device, which causes warpage of the semiconductor device.

ここで、絶対応力σは、下記の[式1]で表される。   Here, the absolute stress σ is expressed by the following [Formula 1].

σ=E×α×△T×n・・・[式1]
(E:弾性率,α:熱膨張係数,△T:温度差,n:物質量)
封止樹脂と配線基板とは、弾性率E及び熱膨張係数αが互いに異なるため、絶対応力σが互いに異なる。このため、封止樹脂と配線基板とを、同一の条件下で加熱すると、半導体装置内に応力歪みが発生し、半導体装置に反りが発生する。
σ = E × α × ΔT × n [Formula 1]
(E: elastic modulus, α: thermal expansion coefficient, ΔT: temperature difference, n: amount of substance)
Since the elastic modulus E and the thermal expansion coefficient α are different between the sealing resin and the wiring board, the absolute stress σ is different from each other. For this reason, when the sealing resin and the wiring substrate are heated under the same conditions, stress distortion occurs in the semiconductor device, and the semiconductor device warps.

またここで、一般に、封止樹脂の熱膨張係数α1,α2は、配線基板の熱膨張係数α1,α2よりも大きい。具体的には例えば、エポキシ樹脂系の封止樹脂の場合、α1(xy)が8〜13ppm、α2(xy)が25〜40ppmである。一方、エポキシ樹脂系又はBTレジン系の配線基板の場合、α1(xy)が9〜15ppm、α2(xy)が4〜8ppmである。   In general, the thermal expansion coefficients α1 and α2 of the sealing resin are larger than the thermal expansion coefficients α1 and α2 of the wiring board. Specifically, for example, in the case of an epoxy resin-based sealing resin, α1 (xy) is 8 to 13 ppm and α2 (xy) is 25 to 40 ppm. On the other hand, in the case of an epoxy resin-based or BT resin-based wiring substrate, α1 (xy) is 9 to 15 ppm and α2 (xy) is 4 to 8 ppm.

このため、封止樹脂の応力は、配線基板の応力よりも大きく、半導体装置の反りに及ぼす影響は、封止樹脂が配線基板よりも大きい。   For this reason, the stress of the sealing resin is larger than the stress of the wiring substrate, and the influence of the sealing resin on the warpage of the semiconductor device is larger than that of the wiring substrate.

そこで、本実施形態では、放熱板により、封止樹脂の応力を調整することで、半導体装置内の応力のバランスを取り、半導体装置に反りが発生することを抑制する。   Therefore, in the present embodiment, the stress in the semiconductor device is balanced by adjusting the stress of the sealing resin by the heat radiating plate, and the occurrence of warpage in the semiconductor device is suppressed.

例えば、図17(a) 〜(b) に示すような半導体装置を実験的に製造する。その結果、半導体装置が反る方向が、谷反り方向であると判明した場合、封止樹脂の応力が、配線基板の応力よりも大きいため、半導体装置が谷方向に反ったことが判る。   For example, a semiconductor device as shown in FIGS. 17A to 17B is experimentally manufactured. As a result, when it is found that the direction in which the semiconductor device warps is the valley warp direction, it can be seen that the stress of the sealing resin is larger than the stress of the wiring substrate, and thus the semiconductor device warps in the valley direction.

そこで、第1に例えば、封止樹脂の熱膨張係数と配線基板の熱膨張係数とに基づいて、放熱板の厚さを厚くする、及び/又は放熱板の平面積を大きくすることで、封止樹脂に圧着される放熱板の体積を大きくする。これにより、封止樹脂の量を減らして、封止樹脂の応力を小さくすることができるため、半導体装置が谷方向に反ることを抑制することができる。第2に例えば、封止樹脂の熱膨張係数と配線基板の熱膨張係数とに基づいて、放熱板の弾性率を大きくする。これにより、半導体装置が谷方向に反ることを抑制することができる。   Therefore, first, for example, by increasing the thickness of the heat sink and / or increasing the plane area of the heat sink based on the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the wiring board, the sealing is performed. Increase the volume of the heat sink that is crimped to the stop resin. Thereby, since the quantity of sealing resin can be reduced and the stress of sealing resin can be made small, it can suppress that a semiconductor device warps in a trough direction. Secondly, for example, the elastic modulus of the heat sink is increased based on the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the wiring board. Thereby, it can suppress that a semiconductor device warps in a trough direction.

このように、放熱用板の体積又は弾性率を、封止樹脂の熱膨張係数と配線基板の熱膨張係数とに基づいて調整することにより、半導体装置に反りが発生することを抑制することができる。さらに、配線基板及び封止樹脂の材料を選択する際の制約を少なくすることができる。   In this way, by adjusting the volume or elastic modulus of the heat dissipation plate based on the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the wiring board, it is possible to suppress the warpage of the semiconductor device. it can. Furthermore, it is possible to reduce restrictions when selecting materials for the wiring board and the sealing resin.

本実施形態によると、放熱板14が封止樹脂18に圧着されている。これにより、接着剤を用いずに、放熱板14を封止樹脂18に固定することができるため、放熱板14が脱落することを防止することができる。   According to this embodiment, the heat sink 14 is pressure-bonded to the sealing resin 18. Thereby, since the heat sink 14 can be fixed to the sealing resin 18 without using an adhesive, the heat sink 14 can be prevented from falling off.

加えて、放熱板14の表面だけでなく、放熱板14の側面の一部を、封止樹脂18から露出させる。具体的には例えば、一端が本体部14aの側面と接続するリード部14bの他端を、封止樹脂18から露出させる。これにより、放熱板14の露出面積を増大させることができるため、放熱板14の放熱効率を向上させることができる。   In addition, not only the surface of the heat sink 14 but also a part of the side surface of the heat sink 14 is exposed from the sealing resin 18. Specifically, for example, the other end of the lead portion 14 b whose one end is connected to the side surface of the main body portion 14 a is exposed from the sealing resin 18. Thereby, since the exposed area of the heat sink 14 can be increased, the heat dissipation efficiency of the heat sink 14 can be improved.

さらに、第1,第2の凸部14c,14dを封止樹脂18に埋め込むことにより、放熱板14と封止樹脂18との接触面積を増大させることができるため、放熱板14を封止樹脂18に強固に固定することができる。   Furthermore, since the contact area between the heat sink 14 and the sealing resin 18 can be increased by embedding the first and second convex portions 14 c and 14 d in the sealing resin 18, the heat sink 14 is sealed with the sealing resin. 18 can be firmly fixed.

さらに、リード部14bの他端を、封止樹脂18から露出させることにより、リード部14bを、本体部14aの側面から封止樹脂18の側面に向かって延ばすことができるため、半導体装置が反ることを抑制することができる。   Furthermore, by exposing the other end of the lead portion 14b from the sealing resin 18, the lead portion 14b can be extended from the side surface of the main body portion 14a toward the side surface of the sealing resin 18, so that the semiconductor device is warped. Can be suppressed.

さらに、放熱板を封止樹脂に固定する接着剤を不要にすることができるため、封止樹脂への接着剤の塗布工程(図12参照)、接着剤への放熱板の圧着工程(図14参照)及び接着剤の硬化工程(図15参照)を不要にすることができる。このため、生産性の低下及びコストの上昇を招くことを防止することができる。   Furthermore, since an adhesive for fixing the heat radiating plate to the sealing resin can be eliminated, an adhesive applying process to the sealing resin (see FIG. 12) and a heat radiating plate pressure bonding process to the adhesive (FIG. 14). Reference) and the adhesive curing step (see FIG. 15) can be eliminated. For this reason, it is possible to prevent a decrease in productivity and an increase in cost.

さらに、図6に示すように、放熱用板14Xの封止樹脂18への圧着を、封止樹脂18の圧縮成形と共に行うことができる。これにより、生産性の向上及びコストの削減を図ることができる。   Further, as shown in FIG. 6, the heat radiation plate 14 </ b> X can be crimped to the sealing resin 18 together with the compression molding of the sealing resin 18. Thereby, productivity can be improved and cost can be reduced.

なお、本実施形態では、例えば、図1(a) 〜(b) に示すように、放熱板14が、本体部14aと、リード部14bと、第1の凸部14cと、第2の凸部14dとを有する場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。例えば、本体部及びリード部のみを有する放熱板でもよい。   In the present embodiment, for example, as shown in FIGS. 1A to 1B, the heat radiating plate 14 includes a main body portion 14a, a lead portion 14b, a first convex portion 14c, and a second convex portion. The case of having the part 14d has been described as a specific example, but the present invention is not limited to this. For example, a heat radiating plate having only a main body portion and a lead portion may be used.

また、本実施形態では、放熱用板として、図2(a) 〜(b) に示すような放熱用板を用いた場合を具体例に挙げて説明したが、本発明はこれに限定されるものではなく、例えば、図10(a) 〜(d) に示すような放熱用板を用いてもよい。   Further, in this embodiment, the case where the heat radiating plate as shown in FIGS. 2A to 2B is used as the heat radiating plate has been described as a specific example, but the present invention is limited to this. For example, a heat radiating plate as shown in FIGS. 10 (a) to 10 (d) may be used.

図10(a) に示す放熱用板24Xは、平面形状が正方形状の本体部24a、リード部24b、及び凸部24dを有している。   The heat radiating plate 24X shown in FIG. 10 (a) has a main body portion 24a, a lead portion 24b, and a convex portion 24d whose planar shape is a square shape.

図10(b) に示す放熱用板34Xは、中央に開口が設けられた本体部34a、及びリード部34bを有している。本体部34aの中央に開口を設けることにより、開口面を封止樹脂と接触させることができるため、放熱用板34Xと封止樹脂との接触面積を増大させることができる。   A heat radiating plate 34X shown in FIG. 10B has a main body portion 34a having an opening at the center and a lead portion 34b. By providing the opening in the center of the main body 34a, the opening surface can be brought into contact with the sealing resin, so that the contact area between the heat radiation plate 34X and the sealing resin can be increased.

図10(c) に示す放熱用板44Xは、中央に凹みが設けられた本体部44a、及びリード部44bを有している。本体部44aの中央に、封止樹脂側に凹む凹みを設けることにより、放熱用板44Xと封止樹脂との接触面積を増大させることができる。   The heat radiating plate 44X shown in FIG. 10 (c) has a main body portion 44a having a recess at the center and a lead portion 44b. The contact area between the heat radiation plate 44X and the sealing resin can be increased by providing a recess that is recessed toward the sealing resin in the center of the main body 44a.

図10(d) に示す放熱用板54Xは、平面形状が円形状の本体部54a、リード部54b、及び凸部54dを有している。   The heat radiating plate 54X shown in FIG. 10 (d) has a main body portion 54a, a lead portion 54b, and a convex portion 54d having a circular planar shape.

また、本実施形態では、図1(a) 〜(b) に示すように、放熱板14におけるリード14部bの裏面に、第1の凸部14cを設ける場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。第1に例えば、放熱板における本体部の裏面に、第1の凸部を設けてもよい。第2に例えば、放熱板におけるリード部の裏面及び本体部の裏面に跨る第1の凸部を設けてもよい。但し、第1の凸部と、電極パッド、半導体素子及び金属線(特に、金属線)とが接触することがないように、第1の凸部を放熱板の裏面に設ける必要がある。   Further, in the present embodiment, as shown in FIGS. 1A to 1B, the case where the first convex portion 14 c is provided on the back surface of the lead 14 portion b in the heat radiating plate 14 has been described as a specific example. However, the present invention is not limited to this. 1st convex part may be provided in the back surface of the main-body part in a heat sink, for example. 2ndly, you may provide the 1st convex part over the back surface of the lead | read | reed part in a heat sink, and the back surface of a main-body part, for example. However, it is necessary to provide the first convex portion on the back surface of the heat sink so that the first convex portion does not contact the electrode pad, the semiconductor element, and the metal wire (particularly, the metal wire).

また、本実施形態では、図1(a) 〜(b) に示すように、半導体素子12のスタック数が、1層の場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。例えば、半導体素子のスタック数は、2〜20層でもよい。好ましくは、半導体素子のスタック数は、例えば、1〜15層以下であり、スタックされた半導体素子の総高さは、例えば、5mm以下である。   Further, in the present embodiment, as shown in FIGS. 1A to 1B, the case where the number of stacks of the semiconductor elements 12 is one has been described as a specific example, but the present invention is not limited to this. It is not something. For example, the number of stacked semiconductor elements may be 2 to 20 layers. Preferably, the number of stacked semiconductor elements is, for example, 1 to 15 layers or less, and the total height of the stacked semiconductor elements is, for example, 5 mm or less.

本発明は、接着剤を用いずに、放熱板を封止樹脂に固定することができ、放熱板を有する半導体装置及びその製造方法に有用である。   INDUSTRIAL APPLICATION This invention can fix a heat sink to sealing resin, without using an adhesive agent, and is useful for the semiconductor device which has a heat sink, and its manufacturing method.

10 配線基板
10X 配線用基板
11 電極パッド
12 半導体素子
13 金属線
14 放熱板
14X 放熱用板
14a 本体部
14b リード部
14c 第1の凸部
14d 第2の凸部
14e 枠体部
15 下金型(第1の金型)
15h 真空吸着孔
15p ガイドピン
16 リリースフィルム
17 上金型(第2の金型)
17h 真空吸着孔
18 封止樹脂
19 モーター
W 素子用板
h ガイド孔
24X,34X,44X,54X 放熱用板
24a,34a,44a,54a 本体部
24b,34b,44b,54b リード部
24d,54d 凸部
DESCRIPTION OF SYMBOLS 10 Wiring board 10X Wiring board 11 Electrode pad 12 Semiconductor element 13 Metal wire 14 Heat sink 14X Heat sink 14a Main body part 14b Lead part 14c First convex part 14d Second convex part 14e Frame part 15 Lower mold ( First mold)
15h Vacuum suction hole 15p Guide pin 16 Release film 17 Upper mold (second mold)
17h Vacuum suction hole 18 Sealing resin 19 Motor W Element plate h Guide holes 24X, 34X, 44X, 54X Heat radiation plates 24a, 34a, 44a, 54a Main body portions 24b, 34b, 44b, 54b Lead portions 24d, 54d Convex portions

Claims (14)

配線基板と、
前記配線基板の表面に固着された半導体素子と、
前記配線基板と前記半導体素子とを電気的に接続する金属線と、
前記配線基板、前記半導体素子及び前記金属線を封止する封止樹脂と、
前記封止樹脂に圧着された放熱板とを備え、
前記放熱板の表面及び前記放熱板の側面の一部は、前記封止樹脂から露出していることを特徴とする半導体装置。
A wiring board;
A semiconductor element fixed to the surface of the wiring board;
A metal wire that electrically connects the wiring board and the semiconductor element;
A sealing resin for sealing the wiring board, the semiconductor element, and the metal wire;
A heat dissipation plate crimped to the sealing resin,
A surface of the heat sink and a part of a side surface of the heat sink are exposed from the sealing resin.
前記放熱板は、
表面が前記封止樹脂から露出し前記半導体素子と対応して配置された本体部と、
一端が前記本体部の側面と接続し且つ他端が前記封止樹脂から露出するリード部とを有していることを特徴とする請求項1に記載の半導体装置。
The heat sink is
A main body having a surface exposed from the sealing resin and disposed corresponding to the semiconductor element;
The semiconductor device according to claim 1, further comprising: a lead portion having one end connected to a side surface of the main body portion and the other end exposed from the sealing resin.
前記放熱板は、前記放熱板の裏面に設けられ且つ前記封止樹脂に埋め込まれた第1の凸部を有していることを特徴とする請求項2に記載の半導体装置。   The semiconductor device according to claim 2, wherein the heat radiating plate has a first convex portion provided on a back surface of the heat radiating plate and embedded in the sealing resin. 前記放熱板は、前記本体部の側面と接続し且つ前記封止樹脂に埋め込まれた第2の凸部を有していることを特徴とする請求項2に記載の半導体装置。   The semiconductor device according to claim 2, wherein the heat radiating plate includes a second convex portion that is connected to a side surface of the main body and is embedded in the sealing resin. 前記放熱板における前記本体部及び前記リード部は、一体に形成されていることを特徴とする請求項2に記載の半導体装置。   The semiconductor device according to claim 2, wherein the main body portion and the lead portion of the heat radiating plate are integrally formed. 前記封止樹脂と前記放熱板との間には接着剤が介在しておらず、前記放熱板は、前記封止樹脂と接していることを特徴とする請求項1〜5のうちいずれか1項に記載の半導体装置。   The adhesive is not interposed between the sealing resin and the heat radiating plate, and the heat radiating plate is in contact with the sealing resin. The semiconductor device according to item. 請求項1〜6のうちいずれか1項に記載の前記半導体装置を製造する半導体装置の製造方法であって、
放熱用板を準備する工程(a)と、
配線用基板の表面に複数の前記半導体素子が固着された素子用板を準備する工程(b)と、
第1の金型に、表面が前記第1の金型の設置面と対向するように前記放熱用板を設置する工程(c)と、
第2の金型に、前記配線用基板の裏面が前記第2の金型の設置面と対向するように前記素子用板を設置する工程(d)と、
前記第1の金型に設置された前記放熱用板の裏面に、前記封止樹脂を投入する工程(e)と、
前記工程(e)の後に、前記第1の金型と前記第2の金型とを閉じて、前記封止樹脂を圧縮成形すると共に、前記放熱用板を前記封止樹脂に圧着する工程(f)と、
前記第1の金型と前記第2の金型とを開いて、前記封止樹脂に前記放熱用板が圧着された前記素子用板を取り出す工程(g)と、
前記工程(g)の後に、前記素子用板を分割し、前記半導体装置に個片化する工程(h)とを備えることを特徴とする半導体装置の製造方法。
A semiconductor device manufacturing method for manufacturing the semiconductor device according to claim 1,
A step (a) of preparing a heat dissipation plate;
A step (b) of preparing a device plate in which a plurality of the semiconductor devices are fixed to the surface of the wiring substrate;
(C) installing the heat radiating plate on the first mold such that the surface faces the installation surface of the first mold;
(D) installing the element plate on a second mold such that the back surface of the wiring board faces the installation surface of the second mold;
A step (e) of injecting the sealing resin to the back surface of the heat radiating plate installed in the first mold;
After the step (e), the first mold and the second mold are closed, the sealing resin is compression-molded, and the heat dissipation plate is pressure-bonded to the sealing resin ( f) and
Opening the first mold and the second mold and taking out the element plate in which the heat dissipation plate is pressure-bonded to the sealing resin (g);
After the step (g), the method includes a step (h) of dividing the element plate into pieces into the semiconductor device.
前記放熱用板は、
枠体部と、
複数の本体部と、
各々が前記本体部の側面に接続する複数のリード部とを有し、
前記複数のリード部のうち、隣接する前記リード部同士は互いに連結し、隣接する前記リード部以外の前記リード部は、前記枠体部と連結していることを特徴とする請求項7に記載の半導体装置の製造方法。
The heat dissipation plate is
A frame part;
A plurality of body parts;
Each having a plurality of lead portions connected to the side surface of the main body portion;
The lead parts adjacent to each other among the plurality of lead parts are connected to each other, and the lead parts other than the adjacent lead parts are connected to the frame body part. Semiconductor device manufacturing method.
前記放熱用板は、各々が前記放熱用板の裏面に設けられた複数の第1の凸部を有していることを特徴とする請求項8に記載の半導体装置の製造方法。   9. The method of manufacturing a semiconductor device according to claim 8, wherein the heat dissipation plate has a plurality of first protrusions each provided on a back surface of the heat dissipation plate. 前記放熱用板は、各々が前記本体部の側面に接続する複数の第2の凸部を有していることを特徴とする請求項8に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 8, wherein the heat dissipation plate has a plurality of second protrusions each connected to a side surface of the main body. 前記放熱用板における前記枠体部、前記本体部及び前記リード部は、一体に形成されていることを特徴とする請求項8に記載の半導体装置の製造方法。   The method of manufacturing a semiconductor device according to claim 8, wherein the frame body portion, the main body portion, and the lead portion of the heat radiating plate are integrally formed. 前記工程(h)において、前記リード部同士が連結する部分、及び前記リード部と前記枠体部とが連結する部分が切断されることを特徴とする請求項8〜11のうちいずれか1項に記載の半導体装置の製造方法。   The step (h) includes cutting a portion where the lead portions are connected to each other and a portion where the lead portions and the frame body portion are connected. The manufacturing method of the semiconductor device as described in any one of. 前記放熱用板における前記枠体部には、ガイド孔が設けられており、
前記工程(c)において、前記ガイド孔に、前記第1の金型に設けられたガイドピンを貫通させることにより、前記放熱用板を前記第1の金型に固定することを特徴とする請求項8〜12のうちいずれか1項に記載の半導体装置の製造方法。
A guide hole is provided in the frame body portion of the heat dissipation plate,
In the step (c), the heat dissipation plate is fixed to the first mold by passing a guide pin provided in the first mold through the guide hole. Item 13. The method for manufacturing a semiconductor device according to any one of Items 8 to 12.
前記放熱用板は、その体積が、前記封止樹脂の熱膨張係数と前記配線用基板の熱膨張係数とに基づいて調整されていることを特徴とする請求項7〜13のうちいずれか1項に記載の半導体装置の製造方法。   The volume of the heat dissipation plate is adjusted based on the thermal expansion coefficient of the sealing resin and the thermal expansion coefficient of the wiring board. A method for manufacturing the semiconductor device according to the item.
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JP2015037146A (en) * 2013-08-15 2015-02-23 信越化学工業株式会社 Semiconductor device manufacturing method and semiconductor device
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