JP2011187538A - 半導体装置 - Google Patents
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- 238000000034 method Methods 0.000 description 9
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- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11835—Degree of specialisation for implementing specific functions
- H01L2027/11837—Implementation of digital circuits
- H01L2027/11838—Implementation of memory functions
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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Abstract
【解決手段】並列に並ぶゲートパターン21,22の端部と、並列に並ぶゲートパターン23,24の対向端部とにおいて、ゲートパターン21の端部はゲートパターン22の端部よりもゲートパターン23,24の方に突き出ており、ゲートパターン24の対向端部はゲートパターン23の対向端部よりも、ゲートパターン21,22の方に突き出ている。引っ込んでいる方の、ゲートパターン22の端部およびゲートパターン23の対向端部について、仕上がり形状において後退が生じない程度に、補正量を大きく設定することができる。
【選択図】図2
Description
図1は実施形態1に係る半導体装置におけるゲートパターンの特徴を示す図である。同図中、(a)はゲートパターンのレイアウト形状、(b)はゲートパターンの仕上がり形状を示す。図1において、第1および第2のゲートパターン11,12は、活性領域10aの上に配置されており、第1の方向(図面縦方向)に延びており、第1の方向に垂直な第2の方向(図面横方向)に並んでいる。また、第3および第4のゲートパターン13,14は、活性領域10bの上に配置されており、第1の方向に延びており、第2の方向に並んでいる。そして、第1および第2のゲートパターン11,12の端部a1,a2は、第3および第4のゲートパターン13,14の対向端部b1,b2とそれぞれ対向している。
図5は実施形態2に係る半導体装置のレイアウトの一例を示す図である。図5において、論理セル3,4,5が縦方向(第1の方向)において並べて配置されている。論理セル3,4,5はそれぞれ、縦方向に延びるゲートパターンが複数個、横方向(第1の方向に直交する第2の方向)に並んでいる、ゲート列3a,4a,5aを有している。
図7は実施形態3を説明するための図であり、(a)は一般的な1ビットメモリセルの回路構成、(b)は(a)のメモリセルのレイアウトパターンである。図7(a),(b)に示すメモリセルは、PMOSトランジスタからなるロードトランジスタTP1,TP2と、NMOSトランジスタからなるドライブトランジスタTN1,TN2と、NMOSトランジスタからなるアクセストランジスタTN3,TN4とを備えている。ロードトランジスタTP1とドライブトランジスタTN1とはゲート同士が接続されており、第1のインバータINV1を構成する。同様に、ロードトランジスタTP2とドライブトランジスタTN2とはゲート同士が接続されており、第2のインバータINV2を構成する。
2 第2の論理セル
3,4,5 論理セル
3a,4a,5a ゲート列
11,21,31 第1のゲートパターン
12,22,32 第2のゲートパターン
13,23,33 第3のゲートパターン
14,24,34 第4のゲートパターン
a1,a2 端部
b1,b2 対向端部
c1〜c10 端部
d1〜d10 端部
MC1〜MC4 メモリセル
Claims (9)
- 第1の方向に延びるゲートパターンが、複数個、前記第1の方向に直交する第2の方向に並ぶ、第1のゲート列と、
前記第1のゲート列の各ゲートパターンの端部に対向するように配置された、ゲートパターンからなる複数の対向端部とを備え、
前記端部とこれに対向する前記対向端部との組からなる端部ペアは、前記第2の方向において、ジグザグ状に、配置されている
ことを特徴とする半導体装置。 - 請求項1記載の半導体装置において、
前記第1のゲート列の各ゲートパターンの端部は、前記対向端部の方に突き出ているものが細く、そうでないものが太く、形成されており、
前記複数の対向端部は、前記端部の方に突き出ているものが細く、そうでないものが太く、形成されている
ことを特徴とする半導体装置。 - 第1の方向に延びるゲートパターンが、複数個、前記第1の方向に直交する第2の方向に並ぶ、第1のゲート列と、
前記第1のゲート列の各ゲートパターンの端部に対向するように配置された、ゲートパターンからなる複数の対向端部とを備え、
前記第1のゲート列の各ゲートパターンの端部は、太いものと細いものとが、交互に形成されており、
前記対向端部は、太い前記端部に対向するものが細く、細い前記端部に対向するものが太く、形成されている
ことを特徴とする半導体装置。 - 請求項1または3記載の半導体装置において、
前記第1のゲート列のゲートパターンは、8本以上である
ことを特徴とする半導体装置。 - 請求項1または3記載の半導体装置において、
前記第1のゲート列は、論理セルに含まれている
ことを特徴とする半導体装置。 - 第1の方向に延びており、前記第1の方向に直交する第2の方向に並ぶ、第1および第2のゲートパターンと、
前記第1の方向に延びており、前記第2の方向に並んでおり、前記第1および第2のゲートパターンの端部にそれぞれ対向するように配置された対向端部を有する、第3および第4のゲートパターンとを備え、
前記第1のゲートパターンの端部は、前記第2のゲートパターンの端部よりも、前記第3および第4のゲートパターンの方に突き出ており、
前記第4のゲートパターンの対向端部は、前記第3のゲートパターンの対向端部よりも、前記第1および第2のゲートパターンの方に突き出ている
ことを特徴とする半導体装置。 - 請求項6記載の半導体装置において、
前記第2のゲートパターンの端部は、前記第1のゲートパターンの端部よりも、太く形成されており、
前記第3のゲートパターンの対向端部は、前記第4のゲートパターンの対向端部よりも、太く形成されている
ことを特徴とする半導体装置。 - 第1の方向に延びており、前記第1の方向に直交する第2の方向に並ぶ、第1および第2のゲートパターンと、
前記第1の方向に延びており、前記第2の方向に並んでおり、前記第1および第2のゲートパターンの端部にそれぞれ対向するように配置された対向端部を有する、第3および第4のゲートパターンとを備え、
前記第2のゲートパターンの端部は、前記第1のゲートパターンの端部よりも、太く形成されており、
前記第3のゲートパターンの対向端部は、前記第4のゲートパターンの対向端部よりも、太く形成されている
ことを特徴とする半導体装置。 - 請求項6または8記載の半導体装置において、
前記第1〜第4のゲートパターンは、互いに異なるメモリセルの、ドライブトランジスタを構成するものである
ことを特徴とする半導体装置。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010049052A JP5364015B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置 |
CN201180012262.4A CN102782857B (zh) | 2010-03-05 | 2011-01-14 | 半导体装置 |
PCT/JP2011/000165 WO2011108178A1 (ja) | 2010-03-05 | 2011-01-14 | 半導体装置 |
US13/560,230 US8669596B2 (en) | 2010-03-05 | 2012-07-27 | Semiconductor device |
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---|---|---|---|
JP2010049052A JP5364015B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置 |
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Publication Number | Publication Date |
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JP2011187538A true JP2011187538A (ja) | 2011-09-22 |
JP5364015B2 JP5364015B2 (ja) | 2013-12-11 |
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JP2010049052A Expired - Fee Related JP5364015B2 (ja) | 2010-03-05 | 2010-03-05 | 半導体装置 |
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US (1) | US8669596B2 (ja) |
JP (1) | JP5364015B2 (ja) |
CN (1) | CN102782857B (ja) |
WO (1) | WO2011108178A1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013157498A (ja) * | 2012-01-31 | 2013-08-15 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP2014010295A (ja) * | 2012-06-29 | 2014-01-20 | Fujitsu Semiconductor Ltd | マスクパターンの形成方法 |
KR101727804B1 (ko) | 2014-09-12 | 2017-04-17 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 레이아웃 설계를 형성하는 방법 |
JP2023506525A (ja) * | 2020-03-25 | 2023-02-16 | 蘇州能訊高能半導体有限公司 | 半導体デバイス及びその製造方法 |
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US8654562B2 (en) * | 2012-01-17 | 2014-02-18 | Texas Instruments Incorporated | Static random access memory cell with single-sided buffer and asymmetric construction |
US8735994B2 (en) * | 2012-03-27 | 2014-05-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Electrical-free dummy gate |
US9209182B2 (en) * | 2012-12-28 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dummy metal gate structures to reduce dishing during chemical-mechanical polishing |
US9614088B2 (en) * | 2014-08-20 | 2017-04-04 | Taiwan Semiconductor Manufacturing Company Ltd. | Metal gate structure and manufacturing method thereof |
KR102237713B1 (ko) | 2014-11-17 | 2021-04-08 | 삼성전자주식회사 | 반도체 장치의 제조 방법 |
US9583493B2 (en) | 2015-04-08 | 2017-02-28 | Samsung Electronics Co., Ltd. | Integrated circuit and semiconductor device |
US9735157B1 (en) | 2016-03-18 | 2017-08-15 | Samsung Electronics Co., Ltd. | Semiconductor device and method of fabricating the same |
US11545495B2 (en) | 2017-06-29 | 2023-01-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Preventing gate-to-contact bridging by reducing contact dimensions in FinFET SRAM |
US11183576B2 (en) * | 2019-02-13 | 2021-11-23 | Micron Technology, Inc. | Gate electrode layout with expanded portions over active and isolation regions |
US11557590B2 (en) * | 2020-02-19 | 2023-01-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor gate profile optimization |
CN114695532A (zh) * | 2020-12-29 | 2022-07-01 | 苏州能讯高能半导体有限公司 | 一种半导体器件及其制备方法 |
US12027520B2 (en) * | 2021-05-10 | 2024-07-02 | Sandisk Technologies Llc | Transistor circuits including fringeless transistors and method of making the same |
US12094944B2 (en) | 2021-05-10 | 2024-09-17 | Sandisk Technologies Llc | Transistor circuits including fringeless transistors and method of making the same |
US20230049938A1 (en) * | 2021-08-12 | 2023-02-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-Gate Field-Effect Transistors And Methods Of Forming The Same |
CN114371596A (zh) * | 2022-03-22 | 2022-04-19 | 合肥晶合集成电路股份有限公司 | 掩模版及其修正方法 |
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JP2010074125A (ja) * | 2008-08-19 | 2010-04-02 | Renesas Technology Corp | 半導体装置 |
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2010
- 2010-03-05 JP JP2010049052A patent/JP5364015B2/ja not_active Expired - Fee Related
-
2011
- 2011-01-14 CN CN201180012262.4A patent/CN102782857B/zh not_active Expired - Fee Related
- 2011-01-14 WO PCT/JP2011/000165 patent/WO2011108178A1/ja active Application Filing
-
2012
- 2012-07-27 US US13/560,230 patent/US8669596B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH05251671A (ja) * | 1992-03-06 | 1993-09-28 | Nec Ic Microcomput Syst Ltd | ゲートアレイ方式の半導体集積回路装置 |
JP2010074125A (ja) * | 2008-08-19 | 2010-04-02 | Renesas Technology Corp | 半導体装置 |
Cited By (5)
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JP2013157498A (ja) * | 2012-01-31 | 2013-08-15 | Renesas Electronics Corp | 半導体装置及びその製造方法 |
JP2014010295A (ja) * | 2012-06-29 | 2014-01-20 | Fujitsu Semiconductor Ltd | マスクパターンの形成方法 |
KR101727804B1 (ko) | 2014-09-12 | 2017-04-17 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 레이아웃 설계를 형성하는 방법 |
US9899263B2 (en) | 2014-09-12 | 2018-02-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming layout design |
JP2023506525A (ja) * | 2020-03-25 | 2023-02-16 | 蘇州能訊高能半導体有限公司 | 半導体デバイス及びその製造方法 |
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US20120292666A1 (en) | 2012-11-22 |
US8669596B2 (en) | 2014-03-11 |
JP5364015B2 (ja) | 2013-12-11 |
WO2011108178A1 (ja) | 2011-09-09 |
CN102782857A (zh) | 2012-11-14 |
CN102782857B (zh) | 2015-01-07 |
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