JP2011186362A - Electro-optic device and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high reliability in an electro-optic device such as a liquid crystal device. <P>SOLUTION: The electro-optic device includes: a plurality of pixel electrodes (9) arrayed along a first direction and a second direction crossing the first direction; a first data line (6a) and a second data line (6b) which supply image signals respectively to a first pixel electrode group and a second pixel electrode group of the plurality of pixel electrodes arrayed in the first direction, and extend in the first direction; a first transistor (77a) and a second transistor (77b) which are electrically connected with the first and the second data lines respectively to control the supply of the image signals and arranged side by side in the first direction; a first selection signal line (171) provided between the first and the second transistors to supply selection signals to the first and the second transistors and extend along the second direction; and first pull-out wiring (231, 232) which electrically connect the first selection signal line and the gate electrode of the first transistor and the first selection signal line and the gate electrode of the second transistor, respectively. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a technical field of an electro-optical device such as a liquid crystal device and an electronic apparatus such as a liquid crystal projector including the electro-optical device.

  As this type of electro-optical device, for example, there is a device that includes a thin film transistor (TFT) on a substrate, and controls supply of various signals in the device by switching on and off. Transistors are arranged in various layouts on a substrate in order to efficiently use the arrangement space. For example, Patent Document 1 proposes a layout in which two transistor groups (specifically, Pch transfer 7 and Pch transfer 8) are arranged side by side in the vertical direction.

JP 2001-156184 A

  However, in the layout according to Patent Document 1 described above, since the transistors are arranged in the vertical direction, there is a relatively large difference in the length of the lead-out wiring that supplies the gate signal between two transistors having different arrangement positions. End up. When the lengths of the lead-out wirings are different, for example, the gate signal may be rounded to a different degree due to wiring resistance, and the device may not operate normally. In other words, the above-described technique has a technical problem that there is a risk that a malfunction may occur in the operation of the apparatus.

  SUMMARY An advantage of some aspects of the invention is that it provides an electro-optical device and an electronic apparatus having high reliability.

  In order to solve the above problems, an electro-optical device according to an aspect of the invention includes a plurality of pixel electrodes arranged along a first direction and a second direction intersecting the first direction, and the pixel electrodes arranged side by side in the first direction. Among the plurality of pixel electrodes, an image signal is supplied to each of the first pixel electrode group and the second pixel electrode group, and a first data line and a second data line provided extending in the first direction; The first and second data lines are electrically connected to control the supply of the image signal, respectively, and the first and second transistors arranged side by side in the first direction; Supplying a selection signal to the second transistor, and a first selection signal line provided between the first and second transistors so as to extend along the second direction; and the first selection signal line; A gate electrode of the first transistor; During, and and a first lead wire for connecting between the respective electrically with the gate electrode of the second transistor and the first selection signal line.

  In the electro-optical device of the present invention, for example, wirings such as scanning lines and data lines and electronic elements such as pixel switching transistors are stacked on the substrate as necessary while being insulated from each other via an insulating film. Thus, a circuit for driving the pixel electrode is configured, and arranged on the upper layer side along the first direction and the second direction intersecting the first direction (in other words, arranged in a matrix) A plurality of pixel electrodes are provided.

  When the electro-optical device of the present invention operates, for example, the switching operation of the pixel switching TFT electrically connected to the pixel electrode is controlled through the scanning line, and the image signal is supplied through the data line. A voltage corresponding to the image signal is applied to the pixel electrode through the TFT. Thereby, it is possible to display an image in a pixel region in which a plurality of pixel electrodes are arranged.

  In the present invention, image signals for displaying an image are collectively supplied as corresponding to, for example, a plurality of data lines, and by switching control of the first transistor and the second transistor electrically connected to the data lines, The data is distributed and supplied to each data line. More specifically, the image signals corresponding to the first and second data lines are supplied to the sources of the first transistor and the second transistor, and the gates of the first transistor and the second transistor are supplied from the first selection signal line. When the selection signal is supplied and the first transistor and the second transistor are turned on and off, the image signal lines are distributed to the data lines. The image signal distributed to the first data line is supplied to the first pixel electrode group, and the image signal distributed to the second data line is supplied to the second pixel electrode group.

  In particular, the first transistor and the second transistor are provided side by side along the first direction. The first selection signal line is provided between the first transistor and the second transistor along a second direction that intersects the first direction. That is, the first transistor and the second transistor are provided at positions facing each other with the gate signal line interposed therebetween. The first and second transistors are electrically connected to the gate signal line by the first lead wiring. That is, the first lead-out wiring has a portion extending from the first selection signal line to the first transistor (hereinafter referred to as “first portion” as appropriate) and a portion extending from the first selection signal line to the second transistor (hereinafter referred to as appropriate). (Referred to as “second part”). Note that a plurality of first transistors and second transistors are typically provided along the second direction. That is, a plurality of first transistors and second transistors are provided along the first selection signal line.

  According to the above-described layout, for example, the distance from the gate signal line to the first transistor and the gate signal are compared with the case where the first transistor and the second transistor are arranged in the same direction as viewed from the first selection signal line. It is possible to bring the distance from the line to the second transistor close to each other. Therefore, the lengths of the first part and the second part in the first lead-out wiring can be brought close to each other.

  If the lengths of the first part and the second part are greatly different, there is a risk that the operation of the apparatus may be defective due to, for example, a difference in wiring resistance. Specifically, the selection signal on the side with the longer wiring length (that is, the side with higher wiring resistance) becomes larger, and the selection signal is supplied to the first transistor and the second transistor under different conditions. Therefore, there is a possibility that the device does not operate normally.

  However, in the present invention, as described above, the lengths of the first portion and the second portion in the first lead-out wiring can be made closer to each other. Therefore, the selection signal can be supplied to the first transistor and the second transistor under the same conditions. Therefore, it is possible to improve the reliability of the apparatus.

  As described above, according to the electro-optical device of the present invention, since the gate signal can be appropriately supplied to the first transistor and the second transistor, high reliability can be realized.

  In one aspect of the electro-optical device of the present invention, an image signal is supplied to each of the third and fourth pixel electrode groups that are adjacent to the first and second pixel electrode groups and arranged in the first direction. The third data line and the fourth data line provided extending in the first direction, and the third and fourth data lines are electrically connected to control the supply of the image signal, respectively. A third transistor and a fourth transistor arranged side by side in the first direction, a selection signal is supplied to the third and fourth transistors, and the third transistor extends in the second direction. And a second selection signal line provided between the fourth transistor and the fourth transistor, between the second selection signal line and the gate electrode of the third transistor, and between the second selection signal line and the gate electrode of the fourth transistor. Connect each one electrically And a second lead wire, said first and second lead wires are the same length each other.

  According to this aspect, the third and fourth pixel electrodes are arranged so as to be adjacent to the first and second pixel electrode groups. Image signals are supplied to the third and fourth pixel electrode groups through the third data line and the fourth data line, respectively. An image signal is supplied to the third and fourth data lines via the third transistor and the fourth transistor. A selection signal is supplied to the third transistor and the fourth transistor through the second selection signal line. That is, on / off of the third and fourth transistors is switched according to the selection signal supplied by the second selection signal line, and the supply of the image signal to the third and fourth data lines is controlled.

  In this aspect, the second selection signal line is provided between the third and fourth transistors so as to extend along the second direction. The second selection signal line is electrically connected to the third and fourth transistors by the second lead wiring. Thus, the positional relationship between the second selection signal line and the third and fourth transistors is the same as the positional relationship between the first selection signal line and the first and second transistors.

  Here, in particular, the lengths of the first lead-out wiring and the second lead-out wiring are the same. The “length of the first lead-out wiring” here is the total of the first portion extending from the first selection signal line to the first transistor and the second portion extending from the first selection signal line to the second transistor. The “length of the second lead-out wiring” refers to a portion extending from the second selection signal line to the third transistor (hereinafter referred to as “third portion” as appropriate), and from the second selection signal line to the second selection signal line. This is the total length of the portions extending to the four transistors (hereinafter referred to as “fourth portion” where appropriate). Therefore, as long as the lengths of the first and second lead wires are the same, the lengths of the first portion and the second portion, and the third portion and the fourth portion may be different from each other.

  According to the configuration described above, the difference between the wiring resistance in the first lead wiring and the wiring resistance in the second lead wiring can be extremely reduced. Therefore, since the selection signal can be appropriately supplied to the first and second transistors and the third and fourth transistors, the reliability can be effectively improved.

  Even if the lengths of the first and second lead wires are not completely the same, if the lengths of the first and second lead wires can be made close to each other, the above-described effects are correspondingly achieved. can get.

  In the aspect including the third transistor, the fourth transistor, and the second selection signal line, the first selection signal that is supplied via the first selection signal line and selects the first and second transistors, The second selection signal supplied via the two selection signal lines and selecting the third and fourth transistors is a signal sequentially supplied in time series.

  In this case, the first selection signal is supplied to the first and second transistors via the first selection signal line. On the other hand, the second selection signal is supplied to the third and fourth transistors via the second selection signal line. In particular, the first selection signal and the second selection signal are sequentially supplied in time series. That is, the first selection signal and the second selection signal are not supplied at the same time. For example, after the supply of the first selection signal is finished, the supply of the second selection signal is started.

  According to the configuration described above, the image signal corresponding to the first data line or the second data line and the image signal corresponding to the third data line or the fourth data line can be supplied together by one wiring. Since the first transistor or the second transistor and the third transistor or the fourth transistor are switched on and off at different timings, the image signal can be suitably distributed to the data line to be supplied. Therefore, an image signal can be efficiently supplied to each pixel electrode, and a high-quality image can be suitably displayed.

  In order to solve the above problems, an electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention (including various aspects thereof).

  According to the electronic apparatus of the present invention, since the electro-optical device according to the present invention described above is provided, a highly reliable projection display device, television, mobile phone, electronic notebook, word processor, viewfinder type, or monitor direct view Various electronic devices such as video tape recorders, workstations, videophones, POS terminals, and touch panels can be realized. In addition, as an electronic apparatus of the present invention, for example, an electrophoretic device such as electronic paper can be realized.

  The effect | action and other gain of this invention are clarified from the form for implementing invention demonstrated below.

1 is a plan view illustrating an overall configuration of an electro-optical device according to an embodiment. It is the HH 'sectional view taken on the line of FIG. FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the electro-optical device according to the embodiment. 6 is a timing chart illustrating input / output timings of various control signals input / output inside the electro-optical device according to the embodiment. FIG. 6 is a schematic diagram transparently showing a positional relationship between electrodes and wirings arranged in an image display area of the electro-optical device according to the embodiment. FIG. 6 is a cross-sectional view taken along line AA ′ in FIG. 5. FIG. 6 is a sectional view taken along line BB ′ in FIG. 5. It is the schematic diagram which showed the area | region where the capacitive electrode on the TFT array substrate was arrange | positioned with the data line and the scanning line. FIG. 3 is a plan view illustrating a configuration of a demultiplexer of the electro-optical device according to the embodiment. It is a top view which shows the structure of the demultiplexer of the electro-optical apparatus which concerns on a comparative example. It is a top view which shows the structure of the projector which is an example of the electronic device to which the electro-optical apparatus is applied.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<Electro-optical device>
An electro-optical device according to this embodiment will be described with reference to FIGS. In the following embodiments, a TFT active matrix driving type liquid crystal device with a built-in driving circuit will be described as an example of the electro-optical device of the present invention.

  First, the overall configuration of the electro-optical device according to the present embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a plan view showing the overall configuration of the electro-optical device according to this embodiment, and FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.

  1 and 2, in the electro-optical device according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are disposed to face each other. The TFT array substrate 10 is, for example, a transparent substrate such as a quartz substrate or a glass substrate, a silicon substrate, or the like. The counter substrate 20 is a transparent substrate such as a quartz substrate or a glass substrate. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between a pair of alignment films.

  The TFT array substrate 10 and the counter substrate 20 are bonded to each other by a sealing material 52 provided in a sealing region located around the image display region 10a provided with a plurality of pixel electrodes.

  The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like for bonding the two substrates, and is applied on the TFT array substrate 10 in the manufacturing process and then cured by ultraviolet irradiation, heating, or the like. It is. In the sealing material 52, a gap material such as glass fiber or glass beads for dispersing the distance between the TFT array substrate 10 and the counter substrate 20 (that is, the inter-substrate gap) to a predetermined value is dispersed. Note that the gap material may be arranged in the image display region 10a or a peripheral region located around the image display region 10a in addition to or instead of the material mixed in the seal material 52.

  A light-shielding frame light-shielding film 53 that defines the frame area of the image display area 10a is provided on the counter substrate 20 side in parallel with the inside of the seal area where the sealing material 52 is disposed. A part or all of the frame light shielding film 53 may be provided as a built-in light shielding film on the TFT array substrate 10 side.

  On the TFT array substrate 10, a demultiplexer 7, a scanning line driving circuit 104, an external circuit connection terminal 102, and the like are formed around the image display area 10a.

  A demultiplexer is provided on the inner side of the seal region material 52 as viewed in plan on the TFT array substrate 10 along one side of the image display region 10a along one side of the TFT array substrate 10 and covered with the frame light shielding film 53. 7 is arranged.

  The scanning line driving circuit 104 is provided along two sides adjacent to the one side so as to be covered with the frame light shielding film 53. Further, in order to connect the two scanning line driving circuits 104 provided on both sides of the image display region 10 a in this way, a plurality of the pixel lines are covered along the remaining side of the TFT array substrate 10 and covered with the frame light shielding film 53. Wiring 105 is provided.

  In a region facing the four corners of the counter substrate 20 on the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with a vertical conduction material are arranged. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  In FIG. 2, on the TFT array substrate 10, a layered structure is formed in which pixel switching TFTs as drive elements, wiring lines such as scanning lines and data lines are formed. Although the detailed structure of this laminated structure is not shown in FIG. 2, pixel electrodes 9 made of a transparent material such as ITO (Indium Tin Oxide) are provided on the laminated structure with a predetermined pattern for each pixel. It is formed in an island shape.

  The pixel electrode 9 is formed in the image display area 10 a on the TFT array substrate 10 so as to face the counter electrode 21. On the surface of the TFT array substrate 10 facing the liquid crystal layer 50, that is, on the pixel electrode 9, an alignment film 16 is formed so as to cover the pixel electrode 9.

  A light shielding film 23 is formed on the surface of the counter substrate 20 facing the TFT array substrate 10. For example, the light shielding film 23 is formed in a lattice shape when viewed in plan on the facing surface of the facing substrate 20. In the counter substrate 20, a non-opening area is defined by the light shielding film 23, and an area partitioned by the light shielding film 23 is an opening area through which light emitted from, for example, a projector lamp or a direct viewing backlight is transmitted. The light shielding film 23 may be formed in a stripe shape, and the non-opening region may be defined by the light shielding film 23 and various components such as data lines provided on the TFT array substrate 10 side.

  On the light shielding film 23, a counter electrode 21 made of a transparent material such as ITO is formed so as to face the plurality of pixel electrodes 9. Further, in order to perform color display in the image display area 10a, a color filter (not shown in FIG. 2) may be formed on the light shielding film 23 in an area including a part of the opening area and the non-opening area. Good. An alignment film 22 is formed on the counter electrode 21 on the counter surface of the counter substrate 20.

  Although not shown here, a precharge signal is provided on the TFT array substrate 10 shown in FIGS. 1 and 2 in addition to the driving circuits such as the demultiplexer 7 and the scanning line driving circuit 104 described above. And a precharge circuit for supplying the image, an inspection circuit for inspecting the quality, defects, and the like of the electro-optical device during manufacture or at the time of shipment may be provided.

  Next, the electrical configuration of the electro-optical device according to the present embodiment will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the electro-optical device according to this embodiment.

  In FIG. 3, the electro-optical device according to this embodiment includes a demultiplexer 7, a scanning line driving circuit 104, and a driving signal line 171 on the TFT array substrate 10. Of the external circuit connection terminals 102 on the TFT array substrate 10, an image signal supply circuit 500 as an external circuit is electrically connected to the image signal terminal 102 v.

  The scanning line driving circuit 104 has a shift register and supplies a scanning signal scanning signal Gi (i = 1,..., M) to the scanning line 11a. Specifically, the scanning line driving circuit 104 selects m scanning lines 11 in a predetermined order described below, and sets the scanning signal to the selected scanning line 11 to the H level corresponding to the selection voltage. The scanning signal to other scanning lines is set to the L level corresponding to the non-selection voltage.

  The image signal supply circuit 500 has a separate configuration from the TFT array substrate 10 and is electrically connected to the TFT array substrate 10 via the image signal terminal 102v during display operation. The image signal supply circuit 500 is connected to the pixel electrode 9 corresponding to the scanning line 11 selected by the scanning line driving circuit 104 and the data line 6 selected by the demultiplexer 7. An image signal having a voltage corresponding to the tone is output.

  In the image display area 10a, the data line 6 is formed extending along the Y direction. Here, the data line 6 includes n (n is a natural number of 2 or more) upper layer data lines 6a and lower layer data lines 6b. The upper layer side data line 6a is disposed so as to overlap the lower layer side data line 6b when viewed in plan on the TFT array substrate 10. In particular, the upper layer data line 6a is an example of the “first data line” in the present invention, and the lower layer data line 6b is an example of the “second data line” in the present invention. In the following description, when simply referring to the “data line 6”, it means both the upper layer side data line 6a and the lower layer side data line 6b.

  An image data signal Sij is supplied to the data line 6 from the image signal supply circuit 500 via the demultiplexer 7. Here, the demultiplexer 7 includes a plurality of transistors 77. The transistor 77 includes an upper layer side transistor 77a corresponding to the upper layer side data line 6a and a lower layer side transistor 77b corresponding to the lower layer side data line 6b.

  A drive signal line 171 is connected to the gate electrode of the transistor 77, and the transistor 77 can be driven at a timing based on the drive signal DRV supplied from the drive signal line 171.

  The gate electrodes of the pair of transistors 77 connected to the pair of data lines 6 that overlap each other when viewed in plan on the TFT array substrate 10 (that is, the upper layer data line 6a and the lower layer data line 6b) are common. Is electrically connected to one drive signal line 171. Therefore, the pair of transistors are driven at the same timing.

  The six drive signal lines 171 are connected to the gate electrodes of the six pairs of transistors 77, respectively. For example, by supplying drive signals in order from the upper side of the six drive signal lines 171, these six pairs of transistors 77 can be sequentially driven one by one.

  Thus, in synchronization with the timing at which the transistor 77 is driven, the image signal supply circuit 500 supplies the corresponding image data signal Sij to the upper layer side data line 6a and the lower layer side data line 6b. Specifically, from the image signal supply circuit 500, the image data signal Si1 corresponding to the upper layer side data line 6a and the image data signal Si2 corresponding to the lower layer side data line 6b, which are different from each other, are respectively transmitted to the upper layer side data line. 6a and lower data line 6b are supplied to the connected pixels.

  From the scanning line driving circuit 104, m scanning lines 11 (m is a natural number of 2 or more) extend along the X direction. Each of the scanning lines 11 is electrically connected to the gate electrode of the TFT 30, and the TFT 30 arranged on the scanning line 11 can be driven based on the supply timing of the scanning signal. The source region of the TFT 30 whose gate electrode is connected to the odd-numbered scanning lines 11 is electrically connected to the upper layer data line 6a. On the other hand, the source region of the TFT 30 whose gate electrode is connected to the even-numbered scanning line 11 is electrically connected to the lower layer data line 6b.

  In the image display area 10 a, the pixels are arranged in a matrix corresponding to the intersections of the data lines 6 and the scanning lines 11. One pixel includes a pixel electrode 9 (see FIG. 2) that forms a liquid crystal element by sandwiching the counter electrode 20 and the liquid crystal 50, a pixel switching TFT 30, and a storage capacitor.

  The gate electrode of the TFT 30 is electrically connected to the scanning line 11 so that the TFT 30 is switching-controlled according to the scanning signal. When the TFT 30 is turned on, the image data signal Sij supplied to the source region electrically connected to the data line 6 is supplied from the drain region of the TFT 30 to the pixel electrode 9.

  One electrode constituting the storage capacitor 70 is electrically connected to the common potential line 91. The common potential line 91 extends to the peripheral region and is connected to the connection terminal 102c. The connection terminal 102c is a part of the external connection terminal 102 (see FIG. 1). The connection terminal 102c is held at the LCCOM voltage by a power supply circuit that is built in an external device connected to the external connection terminal 102 and outputs the LCCOM voltage.

  In this embodiment, the image signal supply circuit 500 is connected as an external circuit to 102v, which is a part of the external connection terminal 102, and the image data signal is taken in. However, the data signal supply circuit that outputs the image data signal is used. Alternatively, they may be formed on the TFT array substrate 10 together. That is, the image signal supply circuit 500 may be incorporated as a data signal supply circuit inside the liquid crystal device.

  Here, various control signals input / output inside the electro-optical device according to the present embodiment will be specifically described with reference to FIG. 4 in addition to FIG. 3. FIG. 4 is a timing chart showing input / output timings of various control signals input / output inside the electro-optical device according to the present embodiment.

  First, the supply timing of the scanning signal Gm supplied from the scanning line driving circuit 104 to each pixel via the scanning line 11 will be described with reference to FIG.

  The scanning signal Gm is supplied to the two adjacent scanning lines 11 among the m scanning lines 11 at the same timing. That is, the pixels arranged on the two continuous scanning lines 11 are driven at the same timing. Specifically, scanning signals G1 and G2, G3 and G4,..., Gm−1 and Gm are applied in a pulsed manner at a predetermined timing from the scanning line 11.

  Next, referring to FIGS. 4B and 4C, the timing at which the drive signal DRV is supplied from the drive signal line 171 to the transistor 77 of the demultiplexer 7 and the writing to the pixels arranged in the image display area 10a. The potential to be described will be described.

  While the scanning signals G1 and G2 are supplied to the scanning line 11 (see period 1 in FIG. 4), the driving signals DRV1, DRV2,..., DRV6 are sequentially supplied to the six driving signal lines 171.

  As shown in FIG. 3, when the drive signal DRV1 is supplied, the transistors 77 corresponding to the pixels 100 (11) and 100 (21) are driven, and the pixels 100 (11) and 100 (21) are writable. It becomes a state. At the same time, the drive signal DRV1 is also supplied to the transistors 77 corresponding to the pixels belonging to other data line groups such as the pixels 100 (17) and 100 (27), so that these pixels can also be written. become.

  Subsequently, when the drive signal DRV2 is supplied, the transistors 77 corresponding to the pixels 100 (12) and 100 (22) are driven, and the pixels 100 (12) and 100 (22) are in a writable state. At the same time, the drive signal DRV1 is also supplied to the transistors 77 corresponding to the pixels belonging to other data line groups, such as the pixels 100 (18) and 100 (28), so that these pixels are also writable. become. The image data signal Sij supplied from the data line driving circuit is applied to the pixels in the writable state. In this way, when writing is completed for all the pixels in the image display region 10a, the display image is updated for each field by repeating the above operation again. Note that the image data signal Sij written in the pixel is held until writing is performed again in the next field.

  Next, the laminated structure formed on the TFT array substrate 10 in the electro-optical device according to the present embodiment will be described in detail with reference to FIGS. FIG. 5 is a schematic diagram transparently showing the positional relationship between the electrodes and wirings arranged for performing the electro-optic operation in the image display region 10a of the electro-optic device according to the present embodiment. 6 and 7 are cross-sectional views taken along lines AA ′ and BB ′ in FIG. 5, respectively. In FIGS. 5 to 7, the scales of the respective layers and members are different from each other in order to make each layer and each member recognizable on the drawing. In order to facilitate understanding of the illustrated contents, a part of the structure shown in FIGS. 5 to 7 is partially omitted.

  Here, to explain supplementarily, FIG. 6 is the same as FIG. 3 except that the pixels corresponding to the odd-numbered scanning lines 11 among the m scanning lines 11 (that is, the TFTs 30 are connected to the lower data line 6b). It is sectional drawing which shows the laminated structure of a pixel. 7 is a cross-sectional view of the pixel corresponding to the even-numbered scanning line 11 among the m scanning lines 11 in FIG. 3 (that is, the pixel in which the TFT 30 is connected to the upper data line 6a). It is sectional drawing which shows a laminated structure.

  First, with reference to FIGS. 5 and 6, a stacked structure of pixels corresponding to the odd-numbered scanning lines 11 among the m scanning lines 11 will be described.

  Scan lines 11 are formed on the TFT array substrate 10. Here, the scanning line 11 is formed on the TFT array substrate 10 so as to extend in the X direction when seen in a plan view. The scanning line 11 is formed of a light-shielding conductive material, for example, W (tungsten), Ti (titanium), TiN (titanium nitride), and the like, and the back side of the TFT array substrate 10 (that is, from the lower side in FIG. 5). By shielding the light which is going to enter from above, the wiring, elements, etc. formed on the upper layer side from the scanning line 11 are prevented from being exposed to the light.

  In the present embodiment, the scanning line 11 is planar on the TFT array substrate 10 in order to prevent a leakage current from being generated due to exposure of the semiconductor layer of the TFT 30 to light and deterioration of the retention characteristics of the TFT. As can be seen, it is formed wider than the region where the TFT 30 is formed. By forming the scanning lines 11 in this manner, the reflected light can be reflected from the back surface of the TFT array substrate 10 or returned light such as light emitted from other electro-optical devices by a multi-plate projector or the like and penetrating the composite optical system. On the other hand, the semiconductor layer of the TFT 30 can be shielded almost or completely. As a result, light leakage current generated during operation of the electro-optical device is reduced. Therefore, the contrast ratio of the display image is improved, and high-quality image display is possible.

  A TFT 30 is formed on the upper layer side of the scanning line 11 via the first interlayer insulating film 12. The TFT 30 corresponds to the intersection of the scanning line 11 formed so as to extend in the X direction and the data line 6 formed so as to extend in the Y direction when viewed in plan on the TFT array substrate 10. It arrange | positions for every pixel so that it may.

  The TFT 30 includes a semiconductor layer 30a and a gate electrode 30b disposed on the upper layer side with a gate insulating film 13 interposed therebetween. Here, the semiconductor layer 30a includes a source region 30a1, a channel region 30a2, and a drain region 30a3 (see FIG. 6). An LDD (Lightly Doped Drain) region may be formed at the interface between the channel region 30a2 and the source region 30a1 or between the channel region 30a2 and the drain region 30a3.

  The gate electrode 30b is formed on the upper layer side of the semiconductor layer 30a with the gate insulating film 13 therebetween so as to face the channel region 30a2. The gate electrode 30b is electrically connected to the scanning line 11 through a contact hole 51 formed in the interlayer insulating film 12 and the gate insulating film 13 (see FIG. 5).

  The source region 30a1 is electrically connected to a lower layer data line 6b formed on the upper layer side of the source region 30a through a contact hole 32 opened in the gate insulating film 13 and the second interlayer insulating film 14. Yes. The lower layer side data line 6b is made of a light-shielding conductive material, for example, Al (aluminum) or the like, and shields light that is about to enter from the front side of the TFT array substrate 10 (that is, from the upper side in FIG. 5). This prevents the wiring, elements, etc. formed on the lower layer side from the lower layer data line 6b from being exposed to light. As a result, the TFT 30 can be almost or completely shielded from the back-light reflection on the TFT array substrate 10 and the return light such as light emitted from other electro-optical devices by a multi-plate projector or the like and penetrating the composite optical system. High-quality image display becomes possible.

  The drain region 30 a 3 is electrically connected to the first relay layer 41 through a contact hole 35 opened in the gate insulating film 13 and the second interlayer insulating film 14. Here, the first relay layer 41 is formed in the same layer as the lower layer data line 6b. The first relay layer 41 is made of the same material as that of the lower layer data line 6b. For example, by patterning a solid conductive layer on the second interlayer insulating film 14, the first relay layer 41 is connected to the lower layer data line 6b. It is formed in the same layer.

  The second relay layer 42 is formed on the upper layer side of the first relay layer 7 and is electrically connected to the first relay layer 41 via the contact hole 36 opened in the third interlayer insulating film 15. Yes.

  The third relay layer 43 is formed further on the upper layer side than the second relay layer 42 and is electrically connected to the second relay layer 42 through a contact hole 37 formed in the fourth interlayer insulating film 16. ing.

  The pixel electrode 9 is formed on the upper layer side of the third relay layer 43, and is electrically connected to the third relay layer 43 through a contact hole 38 opened in the fifth interlayer insulating film 17 and the sixth interlayer insulating film 18. Connected. Thus, the pixel electrode 9 is electrically connected to the drain region 30a3 of the TFT 30 through the first relay layer 41, the second relay layer 42, and the third relay layer 43. As a result, an image signal is supplied to the pixel electrode 9 at a timing at which the TFT 30 is turned on.

  A capacitor electrode 71 is formed on the lower layer side of the pixel electrode 9 via the capacitor insulating film 72. That is, the storage capacitor 70 is formed by the pixel electrode 9 and the capacitor electrode 71 sandwiching the capacitor insulating film 72.

  Particularly in the present embodiment, the pixel electrode 9 and the capacitor electrode 71 are both made of ITO. Since ITO is a transparent conductive material, the capacitor electrode can be formed widely in the opening region, and the storage capacitor 70 having a large capacitance value can be formed.

  Here, FIG. 8 is a schematic view showing a region where the capacitor electrode 71 is arranged on the TFT array substrate 10 together with the data lines 6 and the scanning lines 11. In FIG. 8, for convenience of explanation, the data lines 6 and the scanning lines 11 formed on the lower layer side of the capacitor electrode 71 are transparently shown, and each layer and each member have a size that can be recognized on the drawing. Therefore, the scales are different for each layer and each member.

  The data line 6 and the scanning line 11 extend in the Y direction and the X direction, respectively. Each pixel is divided by a data line 6 and a scanning line 11. The capacitor electrode 71 has an opening region 5a for each pixel, and the opening region 5a is formed so that the contact hole 38 is located inside thereof. Since the opening region 5a is formed wider than the contact hole 38, even if the pixel electrode 9 and the third relay layer 43 are electrically connected via the contact hole 38, the pixel electrode 9 and the third relay are formed. The layers 43 can be safely connected without being short-circuited to the capacitor electrode 71.

  Further, as described above, since the capacitor electrode 71 is made of ITO, which is a transparent conductive material, it can be formed over a wide range of the image display region as shown in FIG. As a result, the storage capacitor 70 having a relatively large capacitance value can be formed, and the retention characteristic of the pixel can be improved.

  In the present embodiment, since the data lines 6 are formed twice, the laminated structure near the TFT array substrate 10 tends to be complicated. In such a case, the storage capacitor 70 can be easily added by forming the storage capacitor 70 on the pixel electrode 9 side having a relatively simple laminated structure. In particular, if the pixel electrode 9 is used as one of the electrodes constituting the storage capacitor 70, it is possible to effectively prevent the laminated structure from becoming complicated.

  A shield layer 8 is formed on the upper layer side of the lower layer data line 6b with a third interlayer insulating film 15 interposed therebetween. In the shield layer 8, coupling occurs between the lower data line 6 b and the upper data line 6 a formed on the upper layer side of the shield layer 8 via the fourth interlayer insulating film 16 (that is, the upper layer). It is formed in order to suppress or prevent the image signals being applied from being disturbed by the electric field generated due to the potential difference between the side data line 6a and the lower layer data line 6b.

  Here, as shown in FIG. 5, the shield layer 8 is formed wider than the data line 6 in the non-opening region excluding the intersecting region where the data line 6 and the scanning line 11 intersect. Since the electric field generated between the upper layer side data line 6a and the lower layer side data line 6b has more or less a component in the plane direction parallel to the TFT array substrate 10, a part thereof goes around the end of the shield layer 8. It becomes. Even in such a case, by forming the shield layer 8 sufficiently larger than the upper data line 6a and the lower data line 6b, it is possible to effectively reduce the electric field that wraps around the outside of the end portion. it can.

  In the pixels corresponding to the odd-numbered scanning lines 11 among the m scanning lines 11, the upper layer data line 6a is not electrically connected at all.

  Next, with reference to FIGS. 5 and 7, a stacked structure of pixels corresponding to the even-numbered scanning lines 11 among the m scanning lines 11 will be described. Of the m scanning lines 11, description of wirings and elements that are common to the stacked structure of pixels corresponding to the odd-numbered scanning lines 11 is omitted as appropriate, and common reference numerals are given.

  The source region 30a1 is electrically connected to a fourth relay layer 44 formed on the upper side of the source region 30a through a contact hole 32 opened in the gate insulating film 13 and the second interlayer insulating film 14. Yes. The fourth relay layer 44 is electrically connected through a contact hole 33 to a fifth relay layer 45 formed on the upper layer side through the third interlayer insulating film 15. The fifth relay layer 45 is electrically connected via the contact hole 34 to the upper layer side data line 6 a formed further on the upper layer side via the fourth interlayer insulating film 16.

  Here, the upper data line 6a is formed of a light-shielding conductive material, for example, Al (aluminum), like the lower data line 6b. Therefore, the upper layer side data line 6a is a wiring formed on the lower layer side of the upper layer side data line 6a by blocking the light to be incident from the front side of the TFT array substrate 10 (that is, from the upper side in FIG. 7). Prevents elements and the like from being exposed to light. As a result, the TFT 30 can be almost or completely shielded from the back-light reflection on the TFT array substrate 10 and the return light such as light emitted from other electro-optical devices by a multi-plate projector or the like and penetrating the composite optical system. High-quality image display becomes possible. In the present embodiment, in particular, since the semiconductor layer 30a of the TFT 30 can be double shielded in combination with the lower layer data line 6b described above, excellent light shielding properties can be obtained.

  Similar to FIG. 6, a shield layer 8 is formed on the lower layer side of the upper layer data line 6a. In the shield layer 8, coupling occurs between the upper data line 6 a and the lower data line 6 b formed via the third interlayer insulating film 15 on the lower layer side than the shield layer 8 (that is, the upper layer). It is formed in order to suppress or prevent the image signals being applied from being disturbed by the electric field generated due to the potential difference between the side data line 6a and the lower layer data line 6b.

  Note that in the pixels corresponding to the even-numbered scanning lines 11 among the m scanning lines 11, the lower layer data lines 6b are not electrically connected at all.

  The other stacked structure in the pixels corresponding to the even-numbered scanning lines 11 among the m scanning lines 11 is the stacked structure in the pixels corresponding to the odd-numbered scanning lines 11 in the m scanning lines 11 (see FIG. 6). (See FIG. 5 and FIG. 6).

  As described above, according to the electro-optical device according to the present embodiment, the data lines are formed by overlapping the lines, so that the writing efficiency to the pixels is remarkably improved and the display image is improved in quality. Can do.

  Next, the configuration of the demultiplexer 7 (see FIG. 3) provided in the electro-optical device according to the present embodiment will be specifically described with reference to FIGS. FIG. 9 is a plan view showing the configuration of the demultiplexer of the electro-optical device according to this embodiment, and FIG. 10 is a plan view showing the configuration of the demultiplexer of the electro-optical device according to the comparative example.

  In FIG. 9, the demultiplexer 7 of the electro-optical device according to this embodiment includes a transistor 77a corresponding to the upper layer data line 6a and a transistor 77b corresponding to the lower layer data line 6b. Here, in particular, the transistor 77a is an example of the “first transistor” in the present invention, and is provided below the drive signal line 171 (that is, on the outer peripheral side of the TFT array substrate 10). The transistor 77b is an example of the “second transistor” in the present invention, and is provided above the drive signal line 171 (that is, on the image display region 10a side).

  The wiring for supplying DRV1 among the six drive signal lines 171 is an example of the “first selection signal line” in the present invention, and is electrically connected to the transistors 77a and 77b through the contact holes 281, respectively. . A first lead wiring is formed in the contact hole 281. A first portion 231 extends below the contact hole 281 and is electrically connected to the gate of the transistor 77a. On the other hand, a second portion 232 is formed above the contact hole 281 and is electrically connected to the gate of the transistor 77b.

  In the transistor 77 a, the image signal supply line 211 is electrically connected to the source side through a contact hole 251. Further, an image signal output line 212 is electrically connected to the drain side through a contact hole 252. In the transistor 77a, switching control is performed according to the first selection signal DRV1 supplied from the drive signal line 171 via the first lead wiring 231, and the image signal input from the image signal supply line 211 is output as an image signal. Output to line 212. The image signal output from the transistor 77a via the image signal output line 212 is supplied to the upper layer side data line 6a.

  The image signal supply line 221 is electrically connected to the source side of the transistor 77b through the contact hole 253. Further, the image signal output line 222 is electrically connected to the drain side via a contact hole 254. In the transistor 77b, switching control is performed according to the first selection signal DRV1 supplied from the drive signal line 171 via the second lead-out wiring 232, and the image signal input from the image signal supply line 221 is output as an image signal. Output to line 222. The image signal output from the transistor 77b via the image signal output line 222 is supplied to the lower layer data line 6b.

  A plurality of transistors 77 a and 77 b are provided along the drive signal line 171, and transistors adjacent to each other are electrically connected to different drive signal lines 171. Specifically, the transistors 77a and 77b arranged on the right side of the transistors 77a and 77b electrically connected to the drive signal line 171 that supplies DRV1 through the contact hole 281 are connected to the DRV2 through the contact hole 282. Is electrically connected to a drive signal line 171 for supplying the signal.

  The drive signal line 171 for supplying the DRV 2 described above is an example of the “second selection signal line” in the present invention, and the transistors 77a and 77b connected thereto are the “third transistor” in the present invention and It is an example of a “fourth transistor”. A second lead wiring extends from the drive signal line 171 that supplies DRV2 to the transistors 77a and 77b. The second lead wiring has a third portion 233 that electrically connects the transistor 77a from the contact hole 282, and a third portion 234 that electrically connects the transistor 77b from the contact hole 282.

  In the demultiplexer 7 according to the present embodiment, as described above, the two transistors 77a and 77b are provided at positions facing each other with the drive signal line 171 interposed therebetween. According to such a layout, the distance from the drive signal line 171 to the transistor 77a and the distance from the drive signal line 171 to the transistor 77b can be made closer to each other. Therefore, the lengths of the first portion 231 and the second portion 232 can be made closer to each other.

  In FIG. 10, for example, in a layout in which the transistors 77a and 77b are arranged in the same direction as viewed from the drive signal line 171, there is a large difference in the length of the lead-out wiring 230 to each transistor. That is, the length of the lead-out line differs between the transistor 77a disposed on the side closer to the drive signal line 171 and the transistor 77b disposed on the side far from the drive signal line 171. If the lengths of the lead-out wirings 230 are greatly different in this way, there is a risk that the operation of the apparatus may malfunction due to, for example, a difference in wiring resistance of the lead-out wiring 230 or parasitic capacitance.

  On the other hand, in the layout according to this embodiment shown in FIG. 9, the lengths of the first portion 231 and the second portion 232 can be made closer to each other as described above. Therefore, a drive signal can be supplied from the drive signal line 171 to the two transistors 77a and 77b under substantially the same conditions. Therefore, the malfunction of the apparatus is prevented and the reliability is improved.

  In the layout shown in FIG. 9, there is a difference between the lengths of the first lead-out wiring 231 and the second lead-out wiring 232, but the first lead-out wiring 231 and the second lead-out wiring 232 have the same length. Preferably it is done. However, as shown in FIG. 9, if each of the transistors 77a and 77b is arranged so as to sandwich the drive signal line 171, the difference in length between the first extraction wiring 231 and the second extraction wiring 232 is somewhat small. Thus, the effects according to the above-described embodiment can be obtained accordingly.

  In the present embodiment, the lengths of the first lead wiring having the first portion 231 and the second portion 232 and the second lead wiring having the third portion 233 and the fourth portion can be made closer to each other. Specifically, the sum of the length of the first portion 231 and the length of the second portion 232 and the sum of the length of the third portion 233 and the length of the fourth portion 234 can be brought close to each other.

  If the lengths of the first lead-out wiring and the second lead-out wiring are made closer, the selection signal can be supplied to the transistors 77a or 77b adjacent to each other under the same conditions. That is, the first selection signal DRV1 and the second selection signal DRV2 are supplied to the transistors 77a and 77b under the same conditions as each other. Therefore, the malfunction of the apparatus is more effectively prevented and the reliability is further improved.

  Here, four transistors have been described as an example, but the same effect can be obtained by arranging the other transistors 77a and 77b to face each other via the drive signal line 171. .

  As described above, according to the electro-optical device according to the present embodiment, a drive signal can be appropriately supplied to the transistors 77a and 77b in the demultiplexer 7, so that high reliability can be realized. It is.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described. FIG. 11 is a plan view showing a configuration example of the projector. Hereinafter, a projector using the liquid crystal device as a light valve will be described.

  As shown in FIG. 11, a lamp unit 1102 including a white light source such as a halogen lamp is provided inside the projector 1100. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In the dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Therefore, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R and 1110B.

  Since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 11, a mobile personal computer, a mobile phone, an LCD TV, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic device Examples include notebooks, calculators, word processors, workstations, videophones, POS terminals, and devices with touch panels. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal devices described in the above embodiments, the present invention includes a reflective liquid crystal device (LCOS), a plasma display (PDP), a field emission display (FED, SED), an organic EL display, and a digital micromirror device. (DMD), electrophoresis apparatus and the like are also applicable.

  The present invention is not limited to the above-described embodiments, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change. In addition, an electronic apparatus including the electro-optical device is also included in the technical scope of the present invention.

  6a ... upper layer side data line, 6b ... lower layer side data line, 7 ... demultiplexer, 9 ... pixel electrode, 10 ... TFT array substrate, 10a ... image display area, 11 ... scanning line, 20 ... counter substrate, 30 ... TFT, 30a ... semiconductor layer, 30b ... gate electrode, 50 ... liquid crystal layer, 70 ... storage capacitor, 77a, 77b ... transistor, 102 ... external circuit connection terminal, 104 ... scanning line drive circuit, 171 ... drive signal line, 500 ... image signal Supply circuit, 211, 221 ... image signal supply line, 212, 222 ... image signal output line, 231 ... first part, 232 ... second part, 233 ... third part, 234 ... fourth part

Claims (4)

A plurality of pixel electrodes arranged along a first direction and a second direction intersecting the first direction;
Among the plurality of pixel electrodes arranged side by side in the first direction, an image signal is supplied to the first pixel electrode group and the second pixel electrode group, respectively, and is provided to extend in the first direction. One data line and a second data line;
A first transistor and a second transistor, which are electrically connected to the first and second data lines, respectively, to control the supply of the image signal, and are arranged side by side in the first direction;
Supplying a selection signal to the first and second transistors, and a first selection signal line provided between the first and second transistors so as to extend along the second direction;
And a first lead line electrically connecting the first selection signal line and the gate electrode of the first transistor, and the first selection signal line and the gate electrode of the second transistor. An electro-optical device. An image signal is supplied to each of the third and fourth pixel electrode groups that are adjacent to the first and second pixel electrode groups and arranged in the first direction, and extends in the first direction. A third data line and a fourth data line formed,
A third transistor and a fourth transistor, which are electrically connected to the third data line and the fourth data line, respectively, to control the supply of the image signal, and are arranged side by side in the first direction;
Supplying a selection signal to the third and fourth transistors, and a second selection signal line provided between the third and fourth transistors so as to extend along the second direction;
A second lead line for electrically connecting the second selection signal line and the gate electrode of the third transistor, and the second selection signal line and the gate electrode of the fourth transistor, respectively.
The electro-optical device according to claim 1, wherein the first and second lead wires have the same length. A first selection signal supplied via the first selection signal line and selecting the first and second transistors, and a second selection signal supplied via the second selection signal line and selecting the third and fourth transistors. The electro-optical device according to claim 2, wherein the selection signal is a signal that is sequentially supplied in time series.   An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 3.

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