JP2011164189A - Electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device which has stable electro-optical characteristics in a pixel region and its peripheral region, and an electronic apparatus including the electro-optical device. <P>SOLUTION: A liquid crystal device 100 as the electro-optical device has a liquid crystal layer as an electro-optical element held in between a pair of substrates and includes: a pixel region E which is provided on the side of an element substrate 10 out of the pair of substrates and has a plurality of pixel circuits; peripheral circuit regions E1, E2, and E3 which are provided at the periphery of the pixel region E and have peripheral circuits involved in driving the pixel electrodes; a dummy pixel region Ed which is provided between the pixel region E and the peripheral circuit regions E1, E2, and E3 to surround the pixel region E and has dummy pixels. The dummy pixels imitate the pixel circuits, and a pattern density of the pixel circuits in the pixel region E is substantially equal to that of the dummy pixels in the dummy pixel region Ed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an electro-optical device and an electronic apparatus equipped with the electro-optical device.

  The electro-optical device includes a semiconductor substrate on which a driving circuit and a pixel layer are formed, a transparent substrate, a liquid crystal injected between these substrates, and a dummy pattern provided in a peripheral region of the pixel region. A type liquid crystal device is known (Patent Document 1).

In the reflection type liquid crystal device, the dummy pattern is provided in the same range as the drive circuit and the pixel layer in the height direction from the semiconductor substrate, and the surface of the pixel region and the surface of the peripheral region are located in substantially the same plane. If so. Thereby, the display unevenness can be reduced by making the thickness of the liquid crystal layer made of the liquid crystal injected between the semiconductor substrate and the transparent substrate uniform not only in the pixel region but also in the peripheral region.
In addition, as a method of positioning the surface of the pixel region and the surface of the peripheral region in substantially the same plane, a CMP (Chemical Mechanical Polishing) process is performed on the surface layer covering the pixel region and the peripheral region, or a flat interlayer An SOG (Spin On Glass) treatment for obtaining an insulating film is disclosed. By arranging the dummy pattern in the peripheral region, the flatness of the surface to be processed after the CMP process or the SOG process is ensured.

JP 2000-231113 A

  However, if there is a difference between the pattern density of the drive circuit or pixel layer (pixel electrode or the like) in the pixel region and the pattern density of the wiring and dummy pattern connected to the drive circuit in the peripheral region, CMP processing is performed. In this case, the polishing rate may be uneven. When unevenness of the polishing rate in the CMP process occurs, the surface to be processed is not necessarily flat, and the variation in the thickness of the liquid crystal layer is not improved. Therefore, there is a problem that display unevenness is not eliminated as expected.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 An electro-optical device according to this application example is an electro-optical device in which an electro-optical element is sandwiched between a pair of substrates, and is provided on one substrate side of the pair of substrates. Provided between a pixel region having a pixel circuit, a peripheral circuit region provided around the pixel region and having a peripheral circuit for driving the pixel circuit, and the peripheral circuit region so as to surround the pixel region A dummy pixel area having dummy pixels, the dummy pixel imitating the pixel circuit, and a pattern density of the pixel circuit in the pixel area and a pattern density of the dummy pixel in the dummy pixel area Are substantially equal to each other.

According to this configuration, the dummy pixel region having the dummy pixels having the pattern density substantially the same as the pattern density of the pixel circuit is provided so as to surround the pixel region. Therefore, a pair of the electro-optic elements sandwiched at least around the pixel region. The distance between the substrates can be made equal to the pixel region. That is, it is possible to provide an electro-optical device in which unevenness of electro-optical characteristics is not noticeable in the pixel region and the dummy pixel region surrounding the pixel region.
Note that the pattern density includes not only the ratio of the area occupied by the pattern to the unit area but also the ratio associated with the presence or absence of pattern arrangement in the thickness direction on the substrate.
Note that the electro-optical element includes, for example, a liquid crystal layer or an electrophoretic layer having electro-optical anisotropy.

Application Example 2 In the electro-optical device according to the application example, the pixel circuit includes at least a pixel electrode, a switching element of the pixel electrode, a data line and a scanning line connected to the switching element, and a capacitor electrode. The dummy pixel is provided in the same layer as the pixel circuit on the one substrate, at least one of a dummy data line and a dummy scanning line, a dummy capacitance electrode, It is characterized by having.
According to this configuration, since the configuration of the dummy pixel faithfully reflects the configuration of the pixel circuit, the difference in the pattern density can be reduced.

Application Example 3 In the electro-optical device according to the application example, the capacitor electrode is provided on a layer different from the pixel electrode on the one substrate, and is electrically connected to the pixel electrode. A second capacitor electrode provided to face the first capacitor electrode through a dielectric layer, the second capacitor electrode is connected to a capacitor line provided in the same layer, and the dummy pixel is The dummy capacitor electrode includes a dummy first capacitor electrode and a dummy second capacitor electrode, and a dummy capacitor line.
According to this configuration, since the storage capacitor is configured by the first capacitor electrode and the second capacitor electrode as compared with the case where the pixel electrode and the capacitor electrode are opposed to each other as the storage capacitor, a desired electric capacity is ensured. The degree of freedom of configuration to be increased. Further, by providing a dummy pixel configuration corresponding to the first capacitor electrode and the second capacitor electrode, the pattern density in the dummy pixel can be made closer to the pixel circuit.

Application Example 4 In the electro-optical device according to the application example described above, it is preferable that the same potential is applied to each of the plurality of dummy pixel electrodes and / or the plurality of dummy capacitance electrodes.
According to this configuration, it is possible to avoid the generation of parasitic capacitance between dummy pixel electrodes, between dummy capacitance electrodes, or between a dummy pixel electrode and a dummy capacitance electrode. That is, even if the dummy pixel electrode or the dummy capacitance electrode is connected to, for example, another wiring, it is possible to prevent the occurrence of the electro-optical characteristic defect due to the parasitic capacitance.

Application Example 5 In the electro-optical device according to the application example described above, the same potential may be the same as the potential applied to the common electrode provided on the other substrate of the pair of substrates.
According to this configuration, since the potential is the same as the potential applied to the common electrode of the other substrate facing the one substrate, the generation of parasitic capacitance between the common electrode and the dummy pixel electrode or the dummy capacitance electrode can be prevented. .

Application Example 6 In the electro-optical device according to the application example described above, the dummy data line and the dummy at the intersection of the data line or the dummy data line and the scanning line or the dummy scanning line in the dummy pixel region. Any one of the scanning lines is notched, and a dummy pattern portion having an area corresponding to the notched portion is formed in the wiring layer provided with the dummy data line or the dummy scanning line. It is preferable to arrange in the vicinity of the portion.
If two wirings are simply crossed in the dummy pixel region, the surface of the crossing portion facing the electro-optical element becomes convex. According to this configuration, since the dummy pattern portion having an area corresponding to the cut-out intersection is left in the same layer, the surface density in the dummy pixel region of one substrate is reduced while the pattern density for the pixel circuit is substantially equal. can do. Furthermore, if two wirings are simply crossed in the dummy pixel region, a parasitic capacitance is generated at the crossing portion. According to this configuration, since the two wirings do not intersect each other in the notched portion, generation of unnecessary parasitic capacitance due to the two wirings being stacked and arranged can be reduced.

Application Example 7 In the electro-optical device according to the application example described above, the dummy pattern portion may be connected to the dummy data line or the dummy scanning line.
According to this configuration, it is possible to avoid the dummy pattern portion from being isolated and electrically floating. That is, electrical problems caused by the dummy pattern portion can be reduced.

Application Example 8 In the electro-optical device according to the application example described above, the pair of substrates are bonded via a seal at a predetermined interval, and the peripheral circuit is planarly surrounded by the seal on the one substrate. Preferably, at least the dummy pixel electrode of the dummy pixels is provided between the peripheral circuit region and the dummy pixel region and the seal.
According to this configuration, the distance between the pair of substrates can be made substantially equal to that of the pixel region even in a portion away from the pixel region to the seal side.

Application Example 9 In the electro-optical device according to the application example, the adjacent dummy pixel electrodes may be patterned so as to be connected to each other.
According to this configuration, when the dummy pixel electrodes adjacent to each other are electrically connected and a predetermined potential is applied to a part of them, the plurality of dummy pixel electrodes can be made substantially the same potential.

Application Example 10 In the electro-optical device according to the application example described above, the other substrate of the pair of substrates is provided in a frame shape so as to overlap at least the peripheral circuit region on the side facing the electro-optical element. It is preferable to have a light-shielding parting part.
According to this configuration, due to the provision of the peripheral circuit on one substrate, the distance between the pair of substrates varies, and the portion where electro-optical characteristic unevenness occurs is shielded from light by the parting portion, so that it becomes inconspicuous. it can. In addition, it is possible to prevent the peripheral circuit from malfunctioning due to the light incident on the other substrate. Furthermore, since the dummy pixel region is provided between the parting part and the pixel region as compared with the case where the parting part is provided so as to overlap with the dummy pixel region, the stray light reflected by the parting part is generated in the pixel region. It is possible to reduce the probability of mixing with light and causing optical unevenness.

Application Example 11 An electronic apparatus according to this application example includes the electro-optical device according to the application example described above.
According to this configuration, an electronic apparatus having stable electro-optical characteristics can be provided.

It is the schematic which shows the structure of a liquid crystal device, (a) is a front view, (b) is sectional drawing cut | disconnected by the AA 'line of (a). FIG. 3 is an equivalent circuit diagram illustrating an electrical configuration of the liquid crystal device. FIG. 3 is a schematic plan view showing an arrangement of various circuits in the liquid crystal device. FIG. 2 is a schematic plan view illustrating a configuration of a pixel. FIG. 5 is a schematic cross-sectional view illustrating a structure of a pixel cut along a B-B ′ line in FIG. 4. (A) is a schematic plan view which shows the structure of a dummy pixel, (b) is a schematic plan view which shows a dummy pixel electrode. FIG. 7 is a schematic cross-sectional view illustrating a structure of a dummy pixel cut along a C-C ′ line in FIG. FIG. 3 is a schematic cross-sectional view showing the arrangement of dummy pixel electrodes in a peripheral circuit region. (A) is a schematic plan view which shows arrangement | positioning of the dummy pattern in a slit structure area | region, (b) is a schematic sectional drawing which shows the structure of the dummy pattern cut | disconnected by F-F 'line of (a). (A) is a schematic plan view which shows the structure of the dummy pixel in another area | region, (b) is a schematic sectional drawing which shows the structure of the dummy pixel cut | disconnected by the G-G 'line | wire of (a). (A) And (b) is a schematic plan view which shows arrangement | positioning of the dummy pattern of a modification. The schematic diagram which shows the structure of a projection type display apparatus.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, embodiments of the invention will be described with reference to the drawings. Note that the drawings to be used are appropriately enlarged or reduced so that the part to be described can be recognized.

(First embodiment)
In the present embodiment, an active matrix type liquid crystal device including a thin film transistor (TFT) as a pixel switching element will be described as an example of an electro-optical device. This liquid crystal device can be suitably used as, for example, a light modulation element (liquid crystal light valve) of a projection type display device (liquid crystal projector) described later.

<Electro-optical device>
First, a liquid crystal device as an electro-optical device according to the present embodiment will be described with reference to FIGS. 1A and 1B are schematic views showing the configuration of a liquid crystal device, where FIG. 1A is a front view, FIG. 1B is a cross-sectional view taken along the line AA 'in FIG. 1A, and FIG. FIG. 3 is a schematic plan view showing the arrangement of various circuits in the liquid crystal device.

As shown in FIGS. 1A and 1B, a liquid crystal device 100 as an electro-optical device of this embodiment is sandwiched between an element substrate 10 and a counter substrate 20 as a pair of substrates, and the pair of substrates. And a liquid crystal layer 50 as an electro-optical element.
A transparent substrate such as a quartz substrate or an opaque substrate such as a silicon substrate can be used as the element substrate 10 as one of the pair of substrates. The size is larger than that of the counter substrate 20, and the terminal portion 10 a protrudes to one side of the counter substrate 20.
For example, a transparent quartz substrate can be used as the counter substrate 20 as the other of the pair of substrates. Both substrates are joined via a seal 40, and a liquid crystal having negative dielectric anisotropy is sealed in the gap to form a liquid crystal layer 50. Specifically, after the seal 40 is disposed in a frame shape on one of the pair of substrates, the substrate on which the seal 40 is disposed is directed downward, and both the substrates are disposed to face each other in a reduced-pressure atmosphere. Then, after a predetermined amount of liquid crystal is dropped inside the seal 40, the liquid crystal is sealed by an ODF (One Drop Fill) method in which both substrates are overlapped and joined. The method of sealing the liquid crystal is not limited to the ODF, and a method of sealing the injection port after providing the injection port in the seal 40 and injecting the liquid crystal may be used.

A pixel region E in which a plurality of pixels P are arranged in a matrix is provided inside the seal 40 arranged in a frame shape. A data line driving circuit 101 is provided between the pixel region E and the seal 40 along the terminal portion 10 a of the element substrate 10. A scanning line driving circuit 102 is provided along the other two sides orthogonal to the terminal portion 10a and facing each other. An inspection circuit 103 is provided along one other side facing the terminal portion 10a. These data line driving circuit 101, scanning line driving circuit 102, and inspection circuit 103 are called peripheral circuits.
Among the peripheral circuits, wirings 105a electrically connected to the data line driving circuit 101 and the scanning line driving circuit 102 are connected to a plurality of external connection terminals 104 arranged in the terminal portion 10a. In addition, a plurality of wirings 105b connecting the two scanning line driving circuits 102 are provided between the inspection circuit 103 along the other one side facing the terminal portion 10a.

  As shown in FIG. 2B, the liquid crystal layer 50 side surface of the element substrate 10 has a light-reflective pixel electrode 15 provided for each pixel P, and electrical control of the pixel electrode 15. A thin film transistor (TFT) 30 as a switching element, signal lines connected to the TFT 30, a protective film 17 that covers the pixel electrode 15, and an alignment film 18 that covers the protective film 17 are formed.

  On the surface of the counter substrate 20 on the liquid crystal layer 50 side, a frame-shaped parting portion 21, a planarizing layer 22 covering the parting portion 21, a common electrode 23 formed so as to cover the planarizing layer 22, and a common An alignment film 24 covering the electrode 23 is formed.

  The parting part 21 is formed using a resin material containing a light shielding property, for example, a metal material such as Ni or Cr or a metal compound such as an oxide thereof, a light shielding pigment, or the like.

  The planarizing layer 22 is formed using a transparent inorganic material such as a silicon oxide film or an organic material such as an acrylic resin.

  The common electrode 23 is transparent, and is formed by a vapor deposition method or a sputtering method using a conductive material such as ITO (Indium Tin Oxide).

  The alignment film 18 and the alignment film 24 are inorganic alignment films made of, for example, an inorganic material, and are obtained by oblique deposition of SiO 2 (silicon oxide) as an inorganic material. The liquid crystal molecules in the liquid crystal layer 50 are given a predetermined azimuth angle and pretilt angle on the surfaces of the alignment films 18 and 24, and are aligned substantially perpendicular to the alignment film surface.

  The common electrode 23 provided on the counter substrate 20 is electrically connected to the wiring 105c on the element substrate 10 side by the vertical conduction portions 106 provided at the four corners of the counter substrate 20 as shown in FIG. . One end of the wiring 105 c extends toward the terminal portion 10 a and is connected to the external connection terminal 104.

  The wirings 105a, 105b, and 105c are made of a low-resistance metal material such as Al (aluminum) or an alloy thereof, and the external connection terminal 104 connected to the wiring 105a, 105b, and 105c is connected to a base made of the low-resistance metal material. Furthermore, it is plated with low resistance Au (gold) or the like. Although not shown, the wirings 105a, 105b, and 105c connected to the external connection terminal 104 are covered with a protective film 17 so that only the external connection terminal 104 is exposed to the terminal portion 10a.

  As shown in FIG. 2, the liquid crystal device 100 includes a plurality of scanning lines 3a and a plurality of data lines 6a as signal lines that are insulated and orthogonal to each other at least in the pixel region E. In addition, the capacitor line 3b is arranged so as to be parallel to the scanning line 3a at a predetermined interval.

  A pixel electrode 15, a TFT 30, and a storage capacitor 16 are provided in a region partitioned in a grid pattern by the scanning line 3 a, the data line 6 a, the capacitor line 3 b, and these signal lines, and these are the pixels of the pixel P The circuit is configured.

The scanning line 3 a is electrically connected to the gate of the TFT 30, and the data line 6 a is electrically connected to the source of the TFT 30. The pixel electrode 15 is electrically connected to the drain of the TFT 30.
The data line 6a is connected to the data line driving circuit 101 (see FIG. 1), and supplies image signals D1, D2,..., Dn supplied from the data line driving circuit 101 to the pixels P. The scanning line 3a is connected to a scanning line driving circuit 102 (see FIG. 1), and supplies scanning signals SC1, SC2,..., SCm supplied from the scanning line driving circuit 102 to each pixel P. The image signals D1 to Dn supplied from the data line driving circuit 101 to the data lines 6a may be supplied line-sequentially in this order, or may be supplied for each of a plurality of adjacent data lines 6a for each group. Good. The scanning line driving circuit 102 supplies the scanning signals SC1 to SCm to the scanning line 3a in a pulse-sequential manner at a predetermined timing.

In the liquid crystal device 100, the TFT 30 that is a switching element is turned on for a certain period by the input of the scanning signals SC1 to SCm, so that the image signals D1 to Dn supplied from the data line 6a are supplied to the pixel electrode 15 at a predetermined timing. It is the structure written in. The predetermined level of image signals D1 to Dn written to the liquid crystal layer 50 via the pixel electrode 15 is held for a certain period between the pixel electrode 15 and the common electrode 23 arranged to face each other via the liquid crystal layer 50. The
In order to prevent the held image signals D1 to Dn from leaking, the holding capacitor 16 is connected in parallel with the liquid crystal capacitor formed between the pixel electrode 15 and the common electrode 23. The storage capacitor 16 is provided between the drain of the TFT 30 and the capacitor line 3b.

  Note that a data line 6a is connected to the inspection circuit 103 shown in FIG. 1A, and an operation defect or the like of the liquid crystal device 100 is confirmed by detecting the image signal in the manufacturing process of the liquid crystal device 100. Although it can be configured, it is omitted in the equivalent circuit of FIG. The inspection circuit 103 includes a sampling circuit that samples the image signal and supplies it to the data line 6a, and a precharge circuit that supplies a precharge signal of a predetermined voltage level to the data line 6a prior to the image signal. Also good.

  Next, the arrangement of various circuits in the liquid crystal device 100 will be described with reference to FIG. FIG. 3 schematically shows a planar arrangement of various circuits on the element substrate 10.

  As shown in FIG. 3, in the element substrate 10, the pixel circuits described above are arranged in a matrix in the pixel region E located substantially at the center. The area having the data line driving circuit 101 located around the pixel area E is the data line driving circuit area E1, the area having the scanning line driving circuit 102 is the scanning line driving circuit area E2, and the area having the inspection circuit 103 is the inspection circuit. This is referred to as region E3. In addition, a region where these peripheral circuits are provided may be collectively referred to as peripheral circuit regions E1 to E3. The peripheral circuit regions E1 to E3 are provided with a space from the pixel region E. Between the pixel region E and the peripheral circuit regions E1 to E3, a dummy pixel region Ed having dummy pixels that surround the pixel region E and imitate a pixel circuit is provided.

  Another region E6 is provided between the dummy pixel region Ed and the peripheral circuit regions E1 to E3 and the seal 40, and slit structure regions E4 and E5 are provided along opposite sides of the other region E6. . The seal 40 is provided in a frame shape so as to overlap the slit structure regions E4 and E5.

On the other hand, on the side facing the liquid crystal layer 50 of the counter substrate 20, the dummy pixel region Ed that overlaps at least the peripheral circuit regions E1 to E3 and partitions the dummy pixel region Ed, that is, does not overlap the dummy pixel region Ed. A frame-shaped parting portion 21 is provided in the outer region. This is because when the frame-shaped parting portion 21 is arranged around the vicinity of the pixel region E, the incident light is reflected by the frame-shaped parting portion 21 and is prevented from entering the pixel region E as stray light. Because.
In consideration of the formation position accuracy of the parting part 21 in the counter substrate 20 and the position accuracy in joining the element substrate 10 and the counter substrate 20 via the seal 40, a part of the frame-like parting part 21 is slightly. The dummy pixel region Ed may enter and overlap.

As shown in FIG. 2, the pixel circuit in the pixel region E has orthogonal data lines 6a, scanning lines 3a, and capacitance lines 3b parallel to the scanning lines 3a. Therefore, the data line 6a extending from the data line driving circuit 101 exists in the dummy pixel area Ed between the pixel area E and the data line driving circuit area E1 and between the pixel area E and the inspection circuit area E3. Further, in the dummy pixel region Ed between the pixel region E and the scanning line driving circuit region E2, there are scanning lines 3a and capacitor lines 3b extending from the scanning line driving circuit 102.
In the dummy pixel area Ed of the present embodiment, dummy pixels including data lines 6a, scanning lines 3a, and capacitor lines 3b extending from these peripheral circuits are provided to simulate the pixel circuit. The pattern density of the circuit and the pattern density of the dummy pixels in the dummy pixel region Ed are substantially equal.

  Next, details of the pixel circuit and the dummy pixel will be described with reference to FIGS. 4 is a schematic plan view showing the configuration of the pixel, FIG. 5 is a schematic cross-sectional view showing the structure of the pixel cut along the line BB ′ in FIG. 4, and FIG. 6A is a schematic plan view showing the configuration of the dummy pixel. FIGS. 7A and 7B are schematic plan views showing dummy pixel electrodes, and FIG. 7 is a schematic cross-sectional view showing the structure of a dummy pixel cut along the line CC ′ in FIG.

<Pixel area>
As shown in FIG. 4, the pixel P (pixel circuit) of the liquid crystal device 100 includes a data line 6a and a scanning line 3a that are orthogonal to each other, and a capacitor line 3b that is arranged in parallel to the scanning line 3a. The capacitance line 3b is provided with an expansion portion 3c whose width is expanded in the pixel P and functions as a second capacitance electrode. A relay electrode 16a that functions as a first capacitor electrode is provided so as to overlap the capacitor line 3b including the extended portion 3c in a plane. A dielectric layer is sandwiched between the extended portion 3c connected to the capacitor line 3b and the relay electrode 16a disposed so as to constitute the storage capacitor 16.

  The TFT 30 is provided near the intersection of the data line 6a and the scanning line 3a. In addition, the elongated semiconductor layer 30a intersects the scanning line 3a, the source 30s of the semiconductor layer 30a overlaps with the protruding portion 6b protruding into the pixel P from the data line 6a, and the drain 30d side of the semiconductor layer 30a overlaps with the relay electrode 16a. Are arranged as follows.

  The pixel electrode 15 is made of a metal material such as Al (aluminum) or an alloy thereof and has light reflectivity. Further, the data line 6 a, the scanning line 3 a, the capacitor line 3 b, the relay electrode 16 a, and the TFT 30 are arranged so as to overlap.

  As shown in FIG. 5, the TFT 30 includes a semiconductor layer 30 a having an LDD (Lightly Doped Drain) structure made of, for example, high-temperature polysilicon formed on the element substrate 10. The semiconductor layer 30a is covered with a gate insulating film 11 made of, for example, silicon oxide, and a scanning line 3a is provided on the gate insulating film 11 so as to overlap the channel region of the semiconductor layer 30a. That is, the TFT 30 is a thin film transistor having a top gate structure in which a part of the scanning line 3a serves as a gate electrode.

  A first interlayer insulating film 12 is provided so as to cover the scanning line 3 a, and the capacitor line 3 b and its extended portion 3 c are provided on the first interlayer insulating film 12. A second interlayer insulating film 13 is provided so as to cover the capacitor line 3b and the extended portion 3c, and the data line 6a, the protruding portion 6b, and the relay electrode 16a are formed on the second interlayer insulating film 13 by patterning. The second interlayer insulating film 13 functions as a dielectric layer in the storage capacitor 16.

  A third interlayer insulating film 14 is provided so as to cover the data line 6a, the protruding portion 6b, and the relay electrode 16a, and a pixel electrode 15 is provided on the third interlayer insulating film 14. Further, a protective film 17 and an alignment film 18 are sequentially formed so as to cover the pixel electrode 15.

  The scanning line 3a, the capacitor line 3b, the data line 6a, and the relay electrode 16a are all made of a low resistance wiring material such as Al or an alloy thereof, and the protruding portion 6b of the data line 6a is formed of the gate insulating film 11 and the first interlayer insulating film. An opening provided so as to penetrate the film 12 and the second interlayer insulating film 13 is connected to the source 30s of the semiconductor layer 30a through a contact hole 13a filled with a low resistance wiring material.

  The relay electrode 16a is connected to the semiconductor layer 30a via a contact hole 13b in which an opening provided so as to penetrate the gate insulating film 11, the first interlayer insulating film 12, and the second interlayer insulating film 13 is filled with a low resistance wiring material. Connected to the drain 30d.

  The relay electrode 16 a is connected to the pixel electrode 15 through a contact hole 14 a in which an opening provided so as to penetrate the third interlayer insulating film 14 is filled with a material for forming the pixel electrode 15.

<Dummy pixel area>
With respect to the configuration of the pixel P (pixel circuit) and the three-dimensional arrangement in the planar and thickness direction, the dummy pixel provided in the dummy pixel region Ed has a configuration and a structure imitating this. .

  Specifically, as shown in FIG. 6A, the dummy pixel Pd is similar to the configuration of the pixel circuit except the TFT 30, and includes a dummy scanning line 3d, a dummy capacitance line 3e, a dummy circuit. Based on the arrangement position of the dummy pixel Pd in the dummy pixel region Ed from among the configuration of the extended portion 3f (dummy second capacitance electrode), dummy relay electrode 16d (dummy first capacitance electrode), and dummy data line 6d of the capacitance line 3e. Selected and configured.

More specifically, in the dummy pixel region Ed between the data line drive circuit region E1 and the pixel region E, the data line 6a extends as shown in FIG. Therefore, the dummy pixel Pd arranged in the dummy pixel region Ed does not need to have the dummy data line 6d, and the data line 6a and the protruding portion 6b, the dummy scanning line 3d, the dummy capacitance line 3e and the extension portion 3f, And a dummy relay electrode 16d.
Similarly, in the dummy pixel region Ed between the scanning line drive circuit region E2 and the pixel region E, the scanning line 3a and the capacitor line 3b extend as shown in FIG. Therefore, the dummy pixel Pd arranged in the dummy pixel region Ed is composed of the scanning line 3a, the capacitor line 3b and its extended portion 3c, the dummy relay electrode 16d, the dummy data line 6d and its protruding portion 6e.
At the four corners of the dummy pixel area Ed surrounding the pixel area E, the scanning lines 3a, the capacitor lines 3b, and the data lines 6a used for actual driving are not arranged, so the dummy pixels Pd arranged in the dummy pixel area Ed. Consists of a dummy scanning line 3d, a dummy capacitance line 3e, an extended portion 3f of the dummy capacitance line 3e, a dummy relay electrode 16d, and a dummy data line 6d.

  As shown in FIG. 7, in the element substrate 10, the dummy scanning line 3 d is provided on the gate insulating film 11, and the dummy capacitance line 3 e and its extension 3 f are provided on the first interlayer insulating film 12. Similarly, the dummy relay electrode 16 d and the dummy data line 6 d are provided on the second interlayer insulating film 13, and the dummy pixel electrode 15 d is provided on the third interlayer insulating film 14. That is, since each is provided in the same layer as each configuration of the pixel circuit, not only the ratio of the dummy pattern per unit area but also the ratio of the dummy pattern in the thickness direction in the element substrate 10 is the same as the pixel circuit. It is the same.

As a result, the pattern density of the pixel circuit in the pixel region E and the pattern density of the dummy pixel Pd in the dummy pixel region Ed become substantially equal. For example, the unevenness on the surface of the third interlayer insulating film 14 is alleviated and flattened. When the CMP process is performed for this purpose, uneven polishing in the CMP process is reduced, and a flatter processing surface can be obtained. Such a CMP process may be applied to the protective film 17 covering the pixel electrode 15 and the dummy pixel electrode 15d.
By making the processing surface of the CMP process flatter, it is possible to reduce the variation in the distance between the element substrate 10 and the counter substrate 20 and make it uniform. In other words, the liquid crystal device 50 having a uniform thickness, reduced display unevenness, and stable display quality can be realized.

  As shown in FIG. 6A, the dummy pixel electrode 15d of the dummy pixel Pd may be isolated in an island shape in the dummy pixel region Ed. There is a possibility that parasitic capacitance is generated between the pixel Pd and other components. As described above, depending on where the dummy pixel Pd is arranged, the dummy pixel Pd may include any of the scanning line 3a, the capacitor line 3b, and the data line 6a used for actual driving. When dullness occurs in various drive signals to be transmitted to the pixel P, display irregularities such as crosstalk are caused.

  Therefore, in the present embodiment, as shown in FIG. 6B, the pattern is formed so that adjacent dummy pixel electrodes 15d among the plurality of dummy pixels Pd provided in the dummy pixel region Ed are connected to each other. Thereby, the dummy pixel electrodes 15d connected to each other can have the same potential.

  If the same technical idea is applied to the dummy relay electrode 16d, for example, in FIG. 6A, a contact hole 13c may be provided so as to overlap the dummy relay electrode 16d and connected to the wiring connecting the dummy relay electrodes 16d. Good.

Further, the dummy pixel electrode 15d and the dummy relay electrode 16d connected to each other may be connected to have the same potential. In particular, the same potential is a common (COM) potential applied to the common electrode 23 from the viewpoint that the same potential is stable and that no parasitic capacitance is generated between the common electrode 23 provided on the counter substrate 20. Is preferred.
As shown in FIG. 1A, since the element substrate 10 has wiring 105c connected to the common electrode 23 through the vertical conduction portions 106 provided at the four corners, the wiring 105c and the dummy pixel electrode are provided. It is preferable to pattern so that 15d and the dummy relay electrode 16d are connected.

  Next, the configuration of the dummy pattern in the region other than the dummy pixel region Ed will be described with reference to FIGS. 8 is a schematic cross-sectional view showing the arrangement of dummy pixel electrodes in the peripheral circuit region, FIG. 9A is a schematic plan view showing the arrangement of dummy patterns in the slit structure region, and FIG. 8B is a diagram of FIG. FIG. 10A is a schematic cross-sectional view showing the structure of a dummy pattern cut along the line FF ′, FIG. 10A is a schematic plan view showing the configuration of dummy pixels in other regions, and FIG. FIGS. 11A and 11B are schematic cross-sectional views showing the structure of a dummy pixel cut along the line GG ′, and FIGS.

<Peripheral circuit area>
As shown in FIG. 8, the peripheral circuits of the data line driving circuit 101, the scanning line driving circuit 102, and the inspection circuit 103 are simultaneously formed on the element substrate 10 in the manufacturing process of the pixel circuit in the pixel region E. Therefore, it is configured to include a thin film transistor having the same configuration as the TFT 30 provided in the pixel circuit, and the data line driving circuit 101 and the inspection circuit 103 naturally include the data line 6a, and the scanning line driving circuit. 102 includes a scanning line 3a. In the present embodiment, the dummy pixel electrode 15d is also provided on the third interlayer insulating film 14 covering the peripheral circuits 101, 102, and 103.

  That is, at least four peripheral circuit areas of the data line driving circuit area E1, the two scanning line driving circuit areas E2, and the inspection circuit area E3 shown in FIG. 3 are adjacent to each other as shown in FIG. 6B, for example. It is preferable to form a dummy pattern by connecting the matching dummy pixel electrodes 15d.

<Slit structure area>
As shown in FIG. 3, the slit structure regions E <b> 4 and E <b> 5 in the element substrate 10 are provided at positions overlapping the seal 40. The seal 40 joins the element substrate 10 and the counter substrate 20 at a predetermined interval, and includes a particle such as glass having a certain diameter and a gap agent such as fiber (glass fiber). Still, if the unevenness is generated on the surface of the substrate at the bonding site, the predetermined interval is not stable. Therefore, the flatness of the substrate surface is required even in the region overlapping with the seal 40. Therefore, it is desirable to arrange a dummy pattern in the same manner as the peripheral circuit region. In this region, a plurality of wirings 105a, 105b, 105, 105b connected to a plurality of external connection terminals 104 as shown in FIG. 105c is arranged. Therefore, it is difficult to arrange a dummy pattern having the same structure as that of the peripheral circuit region.

  In this embodiment, an ultraviolet curable adhesive is used as the seal 40. Therefore, if a large number of dummy patterns are arranged in addition to the light-shielding wirings 105a, 105b, and 105c in the region overlapping with the seal 40, there is a problem that the irradiation of ultraviolet rays is hindered and the seal 40 is not sufficiently cured.

  Therefore, in the present embodiment, as shown in FIG. 9A, the slit structure regions E4 and E5 are provided with dummy patterns 15e that are spaced apart from each other.

  Further, as shown in FIG. 9B, the dummy pattern 15e is disposed on the third interlayer insulating film 14, and in the element substrate 10, the dummy pattern 15e corresponds to the dummy pattern 15e. Similarly, it is preferable to arrange dummy patterns 3d, 3f (3e), and 16d in each wiring layer below. Thereby, the ultraviolet rays irradiated from the outside easily reach the seal 40 evenly. Further, for example, when the CMP process is performed on the third interlayer insulating film 14, it becomes easy to ensure the flatness of the processing surface.

  As described above, the wirings 105a, 105b, and 105c are arranged in the slit structure regions E4 and E5. In which wiring layer of the element substrate 10 each wiring 105a, 105b, 105c is arranged is a design problem. Therefore, the dummy patterns 3d, 3f (3e), 15e, and 16d take into consideration the extending direction of the wirings 105a, 105b, and 105c in the element substrate 10 so that they do not get in the way along the extending direction. It is preferable to arrange.

<Other areas>
As shown in FIG. 3, the other region E6 is inside the seal 40 and includes a data line driving circuit region E1, a scanning line driving circuit region E2, a peripheral circuit region of the inspection circuit region E3, and a dummy pixel region Ed. It is an area between. Wirings 105a and 105b are provided in part of the other region E6 as shown in FIG. Accordingly, dummy patterns similar to the slit structure regions E4 and E5 described above are arranged so as not to interfere with the wirings 105a and 105b.

  On the other hand, in a portion close to the peripheral circuit region or the dummy pixel region Ed, it is preferable to dispose a dummy pixel Pd1 imitating the configuration of the pixel circuit as shown in FIG.

  Specifically, the dummy pixel Pd1 includes a dummy scanning line 3d, a dummy capacitance line 3e, an extension part 3f, a dummy data line 6d, and a dummy pixel electrode 15d. The arrangement structure of these dummy patterns in the element substrate 10 is provided in the same layer corresponding to the configuration of the pixel circuit, as shown in FIG.

  In the dummy pixel Pd1, the dummy relay electrode 16d is deleted from the dummy pixel Pd arranged in the dummy pixel region Ed. By deleting the dummy relay electrode 16d, it is possible to prevent unnecessary parasitic capacitance from being generated between the extended portion 3f and the dummy pixel electrode 15d.

  As shown in FIG. 3, most of the other region E6 where the dummy pixel Pd1 can be provided is shielded from light by the parting portion 21 provided on the counter substrate 20, and thus the flatness of this portion is summarized. Defects are not noticeable. Therefore, the pattern density of the dummy pattern does not have to be strictly equal to the pixel circuit in the pixel region E.

  Next, a modified example of the dummy pattern that intersects each other like the dummy scanning line 3d and the dummy data line 6d will be described with reference to FIG. FIGS. 11A and 11B are schematic plan views showing the arrangement of dummy patterns of a modification.

  For example, when the dummy scanning lines 3d and the dummy data lines 6d are arranged so as to intersect with each other in a plane, each of them is formed in a separate wiring layer on the element substrate 10; Unevenness is likely to occur on the film 14. Further, when each has a different potential, parasitic capacitance is generated.

  In the modified example, as shown in FIG. 11A, the dummy data line 6d at the intersecting portion is cut out, and the dummy pattern portion 6c having the same area as the notched portion is arranged in the vicinity of the intersection. As a result, the dummy pattern can be arranged without changing the pattern density, that is, without causing unevenness. In addition, since the two wirings do not intersect each other in the notched portion, generation of unnecessary parasitic capacitance due to the stacking of the wirings having two different potentials can be reduced. In the modification, the dummy data line 6d is cut out, but the dummy scanning line 3d may be cut out.

  As described above, such a crossing is predicted in the dummy pixel region Ed, and a part thereof includes the scanning line 3a, the capacitor line 3b, and the data line 6a used for driving. So you can't cut them out. Therefore, it goes without saying that the dummy pattern which is not a problem is cut out.

  Further, as shown in FIG. 11B, a dummy pattern portion 6c having the same area as the notched portion may be connected to the dummy data line 6d. Since the dummy pattern portion 6c is not isolated in the same layer, generation of unnecessary parasitic capacitance can be prevented.

  Based on the same concept, the dummy pixel Pd in FIG. 6A may be patterned so that the dummy data line 6d provided in the same layer of the element substrate 10 and the dummy relay electrode 16d are connected. According to this, between the dummy pixels Pd, the dummy relay electrodes 16d can be electrically set to the same potential by using the dummy data line 6d.

According to the first embodiment described above, the dummy pixel region Ed surrounding the pixel region E and having the dummy pixels Pd is provided, and the pattern density of the pixel circuit and the pattern density of the dummy pixels Pd are substantially equal. Therefore, the processing surface can be flattened by the CMP process.
Therefore, the distance between the element substrate 10 and the counter substrate 20 can be made uniform at least in the region extending over the pixel region E and the dummy pixel region Ed. That is, since the thickness of the liquid crystal layer 50 is uniform in the region, the display unevenness is reduced, and the liquid crystal device 100 having excellent display quality can be realized.

(Second Embodiment)
<Electronic equipment>
Next, a projection type display device (liquid crystal projector) as an electronic apparatus of this embodiment will be described with reference to FIG. FIG. 12 is a schematic diagram showing the configuration of the projection display device.

  As shown in FIG. 12, a projection display device (liquid crystal projector) 1000 as an electronic apparatus according to this embodiment includes a light source unit 710, an integrator lens 720, and a polarization conversion element 730 arranged along the system optical axis L. And a polarization illumination device 700 that is schematically configured. In addition, the polarization beam splitter 740 that reflects the S-polarized light beam emitted from the polarization illumination device 700 by the S-polarized light beam reflection surface 741 and the blue light among the light reflected from the S-polarization light beam reflection surface 741 of the polarization beam splitter 740. A dichroic mirror 742 that separates the component of light (B) and a reflective liquid crystal light valve 745B that modulates the separated blue light (B) are provided. Similarly, a dichroic mirror 743 that reflects and separates the red light (R) component of the luminous flux after the blue light is separated, and a reflective liquid crystal light that modulates the separated red light (R). And a valve 745R. Further, a reflective liquid crystal light valve 745G that modulates the remaining green light (G) passing through the dichroic mirror 743 is provided. Further, the light modulated by the three reflective liquid crystal light valves 745R, 745G, and 745B is synthesized by the dichroic mirrors 743 and 742 and the polarization beam splitter 740, and this synthesized light is projected from the projection lens that projects the screen 760. The projection optical system 750 is provided.

The randomly polarized light beam emitted from the light source unit 710 is divided into a plurality of intermediate light beams by the integrator lens 720, and then the polarized light beam is substantially aligned by the polarization conversion element 730 having the second integrator lens on the light incident side. After being converted into a kind of polarized light beam (S-polarized light beam), it reaches the polarization beam splitter 740. The S-polarized light beam emitted from the polarization conversion element 730 is reflected by the S-polarized light beam reflecting surface 741 of the polarization beam splitter 740, and among the reflected light beams, the blue light (B) light beam is the blue light of the dichroic mirror 742. Reflected by the reflective layer and modulated by the reflective liquid crystal light valve 745B. Of the light beams transmitted through the blue light reflection layer of the dichroic mirror 742, the red light (R) light beam is reflected by the red light reflection layer of the dichroic mirror 743 and modulated by the reflective liquid crystal light valve 745R. . On the other hand, the luminous flux of green light (G) transmitted through the red light reflecting layer of the dichroic mirror 743 is modulated by the reflective liquid crystal light valve 745G. As described above, the color light is modulated by the reflective liquid crystal light valves 745R, 745G, and 745B.
Of the color light reflected from the pixels of these reflective liquid crystal light valves 745R, 745G, and 745B, the S-polarized light component does not pass through the polarization beam splitter 740 that reflects S-polarized light, and the P-polarized light component passes therethrough. An image is formed by the light transmitted through the polarization beam splitter 740.

  The reflective liquid crystal light valves 745R, 745G, and 745B are obtained by applying the liquid crystal device 100 of the first embodiment. Specifically, it arrange | positions so that a polarized light beam may inject from the opposing board | substrate 20 side. The parting part 21 provided on the counter substrate 20 is provided outside the dummy pixel area Ed surrounding the pixel area E where an actual image is displayed so as to surround the pixel area E. Therefore, compared with the case where the parting part 21 is provided so as to be close to the pixel area E, a part of the polarized light beam reflected by the parting part 21 is reflected and modulated from the pixel electrode 15 arranged in the pixel area E. It is difficult to mix with reflected light. For example, when black display is performed in the pixel region E, the black display state is maintained also in the dummy pixel region Ed, and the influence of stray light due to the reflection of the polarized light beam from the parting portion 21 is reduced. High-contrast image display is possible.

  According to the present embodiment, it is possible to provide a projection display device (liquid crystal projector) 1000 capable of displaying an image with higher contrast than the conventional one.

  An optical compensation element that optically compensates for a phase difference (retardation) caused by a pretilt of liquid crystal molecules in the liquid crystal layer 50 on the incident (and exit) side of the polarized light flux of the reflective liquid crystal light valves 745R, 745G, and 745B. It is good also as a structure which has arranged.

In the present embodiment, the projection display device 1000 including the liquid crystal device 100 of the first embodiment has been described as an example of an electronic apparatus. However, the liquid crystal device 100 of the first embodiment is not limited to the projection display device 1000. It can be mounted on various electronic devices.
Examples of such electronic devices include electronic books, personal computers, digital still cameras, LCD TVs, viewfinder type or monitor direct view type video recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, There are POS terminals, information devices equipped with a touch panel, and the like, and the liquid crystal device 100 can be suitably used as these display means.

  Various modifications other than the above embodiment are conceivable. Hereinafter, a modification will be described.

  (Modification 1) Although the liquid crystal device 100 of the first embodiment is of a reflective type, it is not limited to this. If the element substrate 10 is made of a transparent substrate material and the pixel electrode 15 is a transparent conductive film such as ITO, the transmissive liquid crystal device 100 can be provided. In addition, it is possible to configure a projection display device that can obtain a high-contrast image display even when the transmissive liquid crystal device 100 is used.

  (Modification 2) The configuration of the pixel P (pixel circuit) in the liquid crystal device 100 of the first embodiment is not limited to this. In particular, in the reflective liquid crystal device 100, the TFTs 30 arranged below the pixel electrode 15 and the wirings connected thereto in the element substrate 10 do not affect the display, and thus are freely arranged as compared with the transmissive type. be able to.

  (Modification 3) Although the liquid crystal device 100 has been described as an example of the electro-optical device in the first embodiment, the invention is not limited to this. For example, the present invention can also be applied to an electrophoresis apparatus including an electrophoretic layer as an electro-optical element between a pair of substrates each having an electrode.

  3a ... scanning line, 3b ... capacitor line, 3c ... expansion part as second capacitance electrode, 3d ... dummy scanning line, 3e ... dummy capacitance line, 3f ... expansion part as dummy second capacitance electrode, 6a ... data line, 6c ... dummy pattern portion, 6d ... dummy data line, 10 ... element substrate as one of a pair of substrates, 15 ... pixel electrode, 15d ... dummy pixel electrode, 16a ... relay electrode as first capacitor electrode, 16d ... dummy relay electrode as dummy first capacitor electrode, 20 ... counter substrate as the other of the pair of substrates, 21 ... parting part, 23 ... common electrode, 30 ... TFT as switching element, 40 ... seal , 50: a liquid crystal layer as an electro-optical element, 100: a liquid crystal device as an electro-optical device, 101: a data line driving circuit as a peripheral circuit, 102: a scanning line driver as a peripheral circuit Circuit, 103 ... inspection circuit as a peripheral circuit, 1000 ... projection display device as an electronic device, E ... pixel area, Ed ... dummy pixel regions, E1 to E3 ... peripheral circuit region.

Claims (11)

An electro-optical device in which an electro-optical element is sandwiched between a pair of substrates,
Provided on one of the pair of substrates;
A pixel region having a plurality of pixel circuits;
A peripheral circuit region provided around the pixel region and having a peripheral circuit for driving the pixel circuit;
A dummy pixel region provided between the peripheral circuit region and surrounding the pixel region, and having a dummy pixel;
The electro-optical device, wherein the dummy pixel imitates the pixel circuit, and a pattern density of the pixel circuit in the pixel region is substantially equal to a pattern density of the dummy pixel in the dummy pixel region. . The pixel circuit includes at least a pixel electrode, a switching element of the pixel electrode, a data line and a scanning line connected to the switching element, and a capacitor electrode,
The dummy pixel includes a dummy pixel electrode, at least one of a dummy data line and a dummy scanning line, and a dummy capacitor electrode, which are provided on the same layer as the pixel circuit on the one substrate. The electro-optical device according to claim 1. The capacitor electrode is provided on a layer different from the pixel electrode on the one substrate, and is opposed to the first capacitor electrode electrically connected to the pixel electrode via a dielectric layer. A second capacitance electrode provided as follows:
The second capacitor electrode is connected to a capacitor line provided in the same layer,
The electro-optical device according to claim 2, wherein the dummy pixel includes a dummy first capacitor electrode and a dummy second capacitor electrode as the dummy capacitor electrode, and a dummy capacitor line.   The electro-optical device according to claim 2, wherein the same potential is applied to each of the plurality of dummy pixel electrodes and / or the plurality of dummy capacitance electrodes.   The electro-optical device according to claim 4, wherein the same potential is the same as a potential applied to a common electrode provided on the other of the pair of substrates.   At the intersection of the data line or the dummy data line and the scanning line or the dummy scanning line in the dummy pixel region, one of the dummy data line and the dummy scanning line is notched. The dummy pattern portion having an area corresponding to the notched portion is disposed in the vicinity of the intersecting portion in the wiring layer provided with the dummy data line or the dummy scanning line. Item 6. The electro-optical device according to any one of Items 2 to 5.   The electro-optical device according to claim 6, wherein the dummy pattern portion is connected to the dummy data line or the dummy scanning line. The pair of substrates are bonded via a seal at a predetermined interval,
The peripheral circuit is provided in a region surrounded by the seal in a plane on the one substrate.
8. The device according to claim 2, wherein at least the dummy pixel electrode among the dummy pixels is provided between the peripheral circuit region and the dummy pixel region and the seal. 9. The electro-optical device described.   9. The electro-optical device according to claim 8, wherein the adjacent dummy pixel electrodes are patterned so as to be connected to each other.   The light-shielding parting part provided in a frame shape so as to overlap at least the peripheral circuit region on the side facing the electro-optical element of the other substrate of the pair of substrates. The electro-optical device according to any one of 1 to 9.   An electronic apparatus comprising the electro-optical device according to claim 1.

Images