JP2011161084A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine having simplified processing performed when cutting or recovering power and allowing a storage capacity needed for processing when cutting or recovering power to be reduced. <P>SOLUTION: When a lowering detection signal is issued by a power monitoring means while main control processing is repeatedly executed, power lowering information showing that the voltage of power supply lowers is set, and game information acquired by returning to the main control processing is stored into a data storage means to execute power cut processing. When the power is recovered, contents stored in a transmission storage means is cleared and the game information stored into the data storage means is transmitted by a command transmitting means. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a gaming machine that returns to a state before power interruption when power is restored after power interruption occurs.

  In game machines such as pachinko machines, various proposals have conventionally been made regarding program control when a game is resumed by returning the power after an interruption state in which the supplied power is cut off. For example, the following has been proposed as a control process when power is restored.

  It is preferable that when the power is restored, the game state when the power interruption occurs can be reproduced to resume the game. For this reason, when a power interruption occurs, commands transmitted and received between the main control device and the sub control device are stored in both the main control device and the sub control device, and are stored when the power is restored. There is a gaming machine that reads out the placed command and tries to reproduce the gaming state when the power interruption occurs. In such a gaming machine, both the main control device and the sub-control device check the command transmission status and reception status, and decide whether to overwrite or ignore the command according to the reception status. That is, first, when a power interruption occurs, the main control device distinguishes and stores transmitted commands and unsent commands, and the sub control device stores received commands. After that, when the power was restored, it was determined whether all of the commands sent from the main control device could be received by the sub control device. If the command could not be received, it could not be received by the sub control device. A process of searching for a command and transmitting the command to the sub-control device again is performed (see, for example, Patent Document 1).

  Also, considering the case where only 1 byte of a 2-byte command could be sent when power interruption occurred, when the power returns, the control command set to the command output port is cleared, In some cases, the transmission side retransmits the command from the beginning (see, for example, Patent Document 2).

Japanese Patent No. 3891804 JP 2003-135798 A

  As described above, when a power failure occurs, there is a gaming machine in which the main control device distinguishes and stores the transmitted command and the untransmitted command, and the sub control device stores the received command. It was. In this conventional gaming machine, when the power is restored, it is necessary to search for an unreceived command and to start transmission to the sub-control device again from the command. For this reason, it is necessary to align the phase of communication between the main control device and the sub control device, and it is also necessary to manage unsent commands and determine the change point between transmitted and untransmitted. The process at the time and the process at the time of power recovery must be complicated.

  In addition, as described above, there is a gaming machine in which a control command is cleared when power is restored and retransmitted from the beginning of the command. In the case of such a conventional gaming machine, although the problem of communication phase alignment can be solved, a problem in NMI processing (non-maskable processing) described later newly arises.

  Problems in the NMI processing include the following. There are two types of interrupt processing in the main control device: power interruption interrupt processing (non-maskable interrupt) and system timer interrupt processing (maskable interrupt). The power interruption interrupt processing is generated by outputting a power interruption detection signal when the power supply board detects a power failure and inputting it to the XNMI terminal of the power interruption detection circuit provided in the main control device. In this power interruption interrupt process, the power interruption interrupt process is prioritized over other processes, and game information data, etc. at the time of interrupt processing occurrence is saved and backed up in the memory, and a predetermined voltage guarantee time is reached. The power is shut off after a lapse. When the power interruption process is performed by the interrupt process having the highest priority, such as a non-maskable interrupt, it is necessary to be able to perform a process when the game information is updated during the execution of the process. For this reason, the program has to be complicated as compared with the maskable interrupt processing which is interrupted and executed at a predetermined timing. In order to reduce the capacity of the program, a program that permits interruption in a predetermined process is preferable.

  The present invention has been made in view of the foregoing points, and an object of the present invention is to simplify processing at power interruption and power recovery, and to store memory required for processing at power interruption and power recovery. The object is to provide a gaming machine capable of reducing the capacity.

The features according to the embodiment of the present invention are as follows:
Game control means for controlling the progress of the game;
Power supply monitoring means for monitoring the voltage of the power supply supplied to the game control means, and issuing a drop detection signal when power interruption occurs when the voltage of the power supply drops below a predetermined voltage;
Command transmitting means for storing a transmission command, a command transmitting means for reading the transmission command from the transmission storing means, and transmitting the transmission command to a sub-control means for controlling the production;
Data storage means capable of holding data even after the voltage of the power supply to the game control means falls below the predetermined voltage;
The game control means executes the following processing.
(A) When the drop detection signal is issued from the power supply monitoring means, the power drop information indicating that the voltage of the power supply is lowered is set by the non-maskable interrupt process, and then the original before the non-maskable interrupt Power drop information set processing to return to processing,
(B) Main control processing for advancing the game,
(B-1) interrupt disable processing for disabling interrupts;
(B-2) A determination process for determining whether or not the power supply lowering information is set after the interrupt prohibition process;
(B-3) an interrupt permission process for permitting an interrupt after the determination process;
(B-4) After the interrupt permission process, it is possible to repeatedly execute a game control process for controlling a game and a game information acquisition process for acquiring game information necessary to advance the game,
(B-5) In (b-4), when the power reduction information setting process (a) is executed after the interrupt permission process, the process returns from the power reduction information setting process (a). A main game process for executing the game control process and the game information acquisition process,
(C) A game that stores the game information acquired in the process (b-4) in the data storage means when it is determined in the determination process (b-2) that the power supply lowering information is set. Information storage processing, and (d) when the voltage of the power supply to the game control means becomes higher than a predetermined voltage, after clearing the contents stored in the storage means for transmission as the power is restored, A process of transmitting the game information stored in the data storage means in the process of (c) from the command transmission means to the sub-control means as a transmission command.

  According to this configuration, since the timing for executing the power interruption process is adjusted, the information necessary for the power recovery process can be accurately obtained and then the power interruption can be performed. Also, when the power is restored, the contents stored in the transmission storage means are cleared, and the stored game information is only transmitted as a transmission command from the command transmission means. The processing at the time can be simplified and the storage capacity required for the processing can be reduced.

The features according to the embodiment of the present invention are as follows:
An interrupt process executed by an interrupt generated every predetermined time executes a predetermined process when the power supply lowering information is not set, and executes the predetermined process when the power supply lowering information is set. The execution of the process is omitted.

  According to this configuration, it is possible to shorten the time required for processing to acquire and store various types of information necessary for processing after power recovery, and processing required within a predetermined time, for example, within a voltage guarantee time. Can be cut off.

Furthermore, the features according to the embodiment of the present invention are as follows:
The process (b-4)
(B-4-1) After executing the interrupt permission process of (b-3), a process of determining whether or not the timer value has reached a predetermined value;
(B-4-2) When the timer value is less than the predetermined value, a process of returning to the process of (b-1);
(B-4-3) When the timer value is equal to or greater than the predetermined value, the game control process and the game information acquisition process are included.
In the process (b-5), when the timer value is equal to or greater than the predetermined value in the process (b-4-3), the power reduction information setting process (a) is executed. Returning from the power supply lowering information setting process of (a), executing the game control process and the game information acquisition process.

  According to this configuration, while forming a timing at which it can be repeatedly determined whether or not the power supply lowering information is set, even if the power supply lowering information is set when a predetermined time has elapsed, By executing the game information acquisition process, it is possible to accurately acquire information necessary for power recovery.

  In addition to simplifying the processing at the time of power interruption and power recovery, the storage capacity required for the processing at power interruption and power recovery can be reduced.

It is a front view which shows the external appearance of the pachinko machine by this Embodiment. It is a block diagram which shows the main structures of the electronic circuit which carries out process control of the game operation | movement of the pachinko machine shown in FIG. It is a figure which shows the input / output terminal of power supply monitoring IC. It is a time chart which shows operation | movement of a power supply monitoring IC. It is a figure which shows the input / output terminal of reset IC. It is a time chart which shows operation | movement of reset IC. It is a flowchart which shows a main process. It is a flowchart which shows the process following the main process. It is a flowchart which shows the process following the main process. It is a flowchart which shows the process following the main process. It is a flowchart which shows the process following the main process. It is a flowchart which shows an effect control command transmission interruption process. It is a flowchart which shows a system timer interruption process. It is a flowchart which shows a non-maskable interruption process. It is a flowchart which shows the subroutine of a power interruption process.

<<< Configuration and Outline of Game Machine of Embodiment of the Present Invention >>>
The gaming machine according to the embodiment of the present invention includes game control means, power supply monitoring means, command transmission means, and data storage means.

  The game control means controls the progress of the game. A predetermined voltage is supplied as a supply power to the game control means. The power monitoring means monitors the voltage of the supply power supplied to the game control means. The power supply monitoring means issues a drop detection signal that power interruption has occurred when the voltage of the power supply drops below a predetermined voltage.

  The command transmission means includes a transmission storage means for storing a transmission command. For example, a transmission storage unit is configured by a ring buffer. The command transmission means reads the transmission command stored in the transmission storage means, and transmits the transmission command. Note that it is only necessary that the transmission command can be transmitted not only to the sub-control unit that controls the production but also to other control devices that are communicably connected to the game control unit.

  The data storage means can hold the stored data even after the power interruption occurs. In the present specification, a state in which the supply of power to a gaming machine such as the pachinko machine 1 is cut off is referred to as a power-off state or a power-off state.

  The game control means executes the following processing.

  Process (a) is a power supply lowering information set process. In this power supply lowering information setting process, when a power reduction monitoring signal is issued from the power supply monitoring means, the power supply lowering information is set by non-maskable interrupt processing. The power supply lowering information is information indicating that the voltage of the power supply has been reduced. Thereafter, the original processing before the non-maskable interrupt is restored.

  In this way, when a decrease detection signal is issued, the power supply decrease information can be set immediately. Furthermore, immediately after setting the power supply lowering information, it is possible to return to the original process before the interruption, and it is possible to reduce the burden on other processes by the power supply lowering information setting process.

  Process (b) is a main control process for advancing the game. This main control process is a process for executing the following processes (b-1) to (b-4) at least once.

  The process (b-1) is an interrupt prohibition process for prohibiting an interrupt. The interrupt process here is preferably a maskable process.

  The process (b-2) is a process for determining whether or not the power supply lowering information is set after the interrupt prohibition process of (b-1). Further, the process (b-3) is an interrupt permission process for permitting an interrupt after the determination process (b-2).

  As described above, the determination process (b-2) is a process performed only between the interrupt prohibition process (b-1) and the interrupt permission process (b-3). The determination of whether or not it is set is executed only in this fixed processing section in the main control process.

  The process (b-4) is a process for executing a game control process and a game information acquisition process after the interrupt permission process. The game control process is a process for controlling a game in the gaming machine. For example, it is a process for determining the progress of the game by generating random numbers or receiving signals from various sensors. The game information acquisition process is a process for acquiring game information necessary to advance the game.

  As described above, the main game process is a process of repeatedly executing these processes (b-1) to (b-4) at least once, for example.

  Further, in the process of (b-4), when the power reduction information setting process of (a) is executed after the interrupt permission process, the process returns from the power reduction information setting process of (a), and (b-4 ) Game control process and game information acquisition process.

  The process (c) is a process for executing the game information storage process when it is determined in the determination process (b-2) that the power supply lowering information is set. This game information storage process is a process for storing the game information acquired in the process (b-4) in the data storage means. Thus, the main control process in which the process of (b-1) to (b-4) is repeatedly executed instead of immediately executing the power interruption process when the power supply monitoring unit issues the drop detection signal. Then, after executing the interrupt prohibition process of (b-1), it is determined whether or not the power supply lowering information is set. Thereafter, the process exits from the main control process and executes this game information storage process.

  In the process (d), when the voltage of the power supply to the game control means becomes higher than a predetermined voltage, that is, when the power is restored, the contents stored in the transmission storage means are cleared and the data This is processing for transmitting game information stored in the storage means as a transmission command from the command transmission means.

  When the voltage of the power supply decreases, only the processing for setting the power supply decrease information is executed. That is, even when the voltage of the power supply is lowered, the power interruption process is not immediately executed. Therefore, when the voltage of the power supply decreases while executing the main control process, the power supply lowering information is set, and then the process returns to the main control process again. Game information can be acquired in accordance with the processing when returning to the main control processing. Further, interruption is prohibited in the returned main control process, and the power interruption process is executed only when the power supply lowering information is set. As described above, since the timing for executing the power interruption process is adjusted, the power interruption can be performed after acquiring information necessary for the power recovery process.

  Also, when the power is restored, the contents stored in the transmission storage means are cleared, and the game information stored in the data storage means by the power interruption process is simply transmitted as a transmission command from the command transmission means. Since power recovery processing can be completed, communication phase alignment at power recovery can be facilitated. In addition, the power can be restored without considering the transmission state of the communication command when the power interruption occurs, such as transmitted, untransmitted, received, and not received. Furthermore, since the timing for executing the power interruption process is determined in advance, the processing of the program is not complicated, and the capacity of the program can be reduced.

In addition, the gaming machine of the embodiment of the present invention,
An interrupt process executed by an interrupt generated every predetermined time executes a predetermined process when the power supply lowering information is not set, and executes the predetermined process when the power supply lowering information is set. What omits execution of a process is preferable.

  When the voltage of the power supply is lowered, the time required for the processing can be shortened by simplifying the processing and executing only the necessary processing. By doing in this way, it is possible to accurately acquire and store only the minimum necessary various information necessary for processing after the power is restored. Therefore, when the voltage of the power supply decreases, the necessary minimum processing is completed within a predetermined time, for example, within the voltage guarantee time, and it is possible to cope with power interruption.

Furthermore, in the gaming machine of the embodiment of the present invention,
The process (b-4)
(B-4-1) After executing the interrupt permission process of (b-3), a process of determining whether or not the timer value has reached a predetermined value;
(B-4-2) When the timer value is less than the predetermined value, a process of returning to the process of (b-1);
(B-4-3) When the timer value is equal to or greater than the predetermined value, the game control process and the game information acquisition process are included.
When the process of (b-5) is performed in the process of (b-4-3) and the timer value is equal to or greater than the predetermined value, the power supply lowering information set process of (a) is executed. It is preferable that the game control process and the game information acquisition process are executed after returning from the power supply lowering information set process of (a).

  When the timer value is less than the predetermined value, the process returns to the process (b-1), so that it can be repeatedly determined whether or not the power supply lowering information is set. Therefore, it can be accurately determined whether or not the voltage of the power supply has dropped below a predetermined voltage. In addition, when the timer value is equal to or greater than the predetermined value, even when the power supply lowering information is set, the game control process and the game information acquisition process are preferentially executed, and the information necessary for power recovery is accurately determined. Can be obtained.

  As described above, the process (a) is preferably a process in which the power drop information is set by the non-maskable interrupt process when the drop detection signal is issued from the power monitoring means, and then the process returns to the original process before the interruption. . When the timer value is less than the predetermined value, when returning from the non-maskable interrupt process, the process returns to the process (b-1) by the process (b-4-2), and the power supply lowering information by the process (b-2). It is determined whether or not is set. On the other hand, when the timer value is equal to or greater than the predetermined value, when returning from the non-maskable interrupt process, the game information acquisition process is executed by the process (b-4-3). Therefore, even if a drop detection signal is issued from the power supply monitoring means, the power interruption process is not executed immediately, but the process (b-4-3) is prioritized and the game information is acquired. Execute power interruption processing.

  That is, even if the voltage of the power supply drops below a predetermined voltage, the power interruption process is not executed immediately. Instead, the game information is acquired before the power interruption process is performed, and then the power interruption process is executed. In particular, the game information can be made effective by allowing the game information to be acquired in a time within the voltage guarantee time. Here, the voltage guarantee time is a time during which the power supply voltage within a range in which the game control means can be normally operated can be supplied to the game control means. As described above, since the game information is obtained in a time during the voltage guarantee time during which the game control means is operating normally, that is, within the time during which the game control means is in a stable state, the processing (b-4) All contents of the game information acquired by the game information acquisition process can be handled as valid.

  In this way, by acquiring game information that is valid for all contents, the voltage guarantee time before the power interruption process is performed by reading and using the acquired game information in the power recovery process. The state inside can be reproduced. That is, by the process (d), in the power recovery process, all the game information stored in the transmission storage means at the time of power recovery is cleared, and the game information stored in the data storage means is transmitted from the command transmission means to the transmission command. Send as. Even if game information is stored in the transmission storage means at the time of power recovery, the transmission storage means becomes unstable due to power interruption, and the contents of the transmission storage means are altered (the work area is damaged later). There is. Even in such a case, since all the transmission storage means are cleared, the contents of the altered transmission storage means are not used, and it is possible to prevent inappropriate contents from being transmitted as a command.

  As described above, since all the contents of the game information acquired by the game information acquisition process of the process (b-4) are valid, the storage means for transmission is initialized once, and the acquired game information is renewed from the command transmission means. By simply transmitting, the state before the power interruption process can be reproduced, the power recovery process can be easily and easily performed, and the capacity of the program required for the process can be reduced. In this way, even if the transmission storage means becomes unstable due to power interruption and the contents of the transmission storage means are altered, the state before the power interruption processing can be easily reproduced without being affected by this. can do.

More specifically, the gaming machine according to the embodiment of the present invention will be described below.
When the power supply device detects a voltage drop, it outputs a power interruption detection signal to the NMI terminal (non-maskable terminal) of the main control device. When the power interruption detection signal is input, the main control device performs non-maskable interrupt processing, sets the NMI flag, and performs power interruption processing in a predetermined processing within the main processing. The predetermined process in the main process is performed before the execution of the process after elapse of the system timer in the main game process repeatedly executed at a predetermined cycle. The post-system timer process is a process executed after the timer value of the system timer becomes equal to or greater than a predetermined value.

  Further, interrupts are prohibited before the power interruption process is executed, and interrupts are permitted again after the NMI flag confirmation process, the power interruption process, and the initial value random number update process. As described above, since the power interruption process is executed only in a predetermined processing part in the main process, the program is simplified compared to the case where the power interruption process is interrupted at an unspecified place in the program. be able to.

  Furthermore, since the power interruption process is executed only in a predetermined processing part in the main process, preparing for the power interruption process by acquiring the latest game information when the power interruption occurs. Can do. For example, if a power interruption occurs during the execution of the special symbol control process, the conventional gaming machine executes the power interruption process immediately after the occurrence of the power interruption, and the game information at that time is backed up. I will prepare for power interruption. On the other hand, the gaming machine according to the present invention does not immediately execute the power interruption process even if the NMI flag is set during the execution of the special symbol control process, and after the special symbol control process, the main game process such as the normal symbol control process. After executing the above, the power interruption process is executed by a predetermined process. In this way, it is possible to prepare for the power interruption process after executing the main game process once and acquiring the latest information, so that the game information at the time of power interruption can be backed up more accurately than conventional gaming machines. Can do.

  The program is set so that the time from when the NMI flag is set to when the main game process is executed once and the power interruption process is performed is within the voltage guarantee time.

  Specifically, in an interrupt process (for example, an effect control command transmission interrupt process, a system timer interrupt process, etc.) executed at a predetermined time that is not a non-maskable interrupt, the process is performed after the NMI flag is set. It does not perform, but it is made to return immediately from these interruption processes. Thereby, the game information is not updated after the occurrence of the power interruption, so that the game information at the time when the power interruption occurs can be held as the latest game information. Further, after the NMI flag is set, the process immediately returns from interrupt processing such as effect control command transmission interrupt processing and system timer interrupt processing. For this reason, the process of acquiring game information can be completed in a short time, and the voltage guarantee time is not exceeded, so that the game information can be acquired in a stable state.

  Further, when the input voltage to the reset IC exceeds a predetermined value, a power recovery process is performed. In the power interruption recovery process, a communication data storage area clear process, that is, a ring buffer clear process is performed. Then, in the power interruption recovery command transmission reservation process, a command at the time of power recovery is transmitted. Here, the latest game information acquired at the time of power interruption is added as a parameter and transmitted.

  By doing in this way, the phase alignment of communication at the time of a power return can be made easy. For example, phase alignment of communication performed between the main control device and the sub control device can be facilitated. Further, when a power interruption occurs while a command consisting of N bytes is being transmitted, an untransmitted part being transmitted or an untransmitted command remaining on the ring buffer may occur. Even in such a case, when the power is restored, it is initialized (clearing the ring buffer), and the latest game information is added to the power interruption restoration command as a parameter and transmitted. It is possible to prevent problems caused by power interruption such as transmission again.

<<< Configuration of Pachinko Machine 1 >>>
FIG. 1 is a front view of a pachinko machine 1 according to the present embodiment.

  A game board 2 is provided in front of the pachinko machine 1. Pachinko balls, which are game balls, flow down the game board 2. Many nails are planted on the surface of the game board 2. The nail changes the flow direction of the pachinko ball flowing down the game board 2. FIG. 1 shows only some of the nails. An upper plate 3 is provided below the game board 2. A firing handle 5 is provided on the lower right side of the upper plate 3. The launch handle 5 is operated by the player when a pachinko ball is driven into the game board 2 via the rail 4. An upper frame decoration lamp 6 is provided above the game board 2.

  A special symbol display device 10 is provided in the center of the board surface of the game board 2. The special symbol display device 10 is composed of a liquid crystal display device, and variably displays the special symbols as identification information in three columns. Above the special symbol display device 10, there is provided a normal symbol display device 11 in which green LEDs (light emitting diodes) and red LEDs constituting the normal symbol are arranged side by side. On the left and right of the normal symbol display device 11, there are provided normal symbol start memorized number display units 13 made up of four LEDs. On the lower side of the special symbol display device 10, a special symbol start memory number display unit 12 composed of four LEDs is provided. On the left and right sides of the special symbol display device 10, there are provided passage gates 14 that constitute a normal symbol start passage. Below the special symbol display device 10, a normal electric accessory 15 constituting a special symbol start winning opening is provided.

  Above the upper plate 3, a ball lending button 7a, a return button 7b (not shown), a selection button 7c (not shown) and a decision button 7d (not shown) are provided. The ball lending button 7a is operated by the player when lending a pachinko ball. The pachinko machine 1 is provided with a card unit 65 (see FIG. 2). Pachinko balls are lent out within the balance of the prepaid card inserted into the card unit 65. The return button 7b is operated when the card inserted in the card unit 65 is returned. The selection button 7c is operated when an information item displayed on the special symbol display device 10 is selected. The determination button 7d is operated when determining an information item to be displayed on the special symbol display device 10.

<< Configuration of electronic circuit >>
FIG. 2 is a block diagram showing a main configuration of an electronic circuit that controls the gaming operation of the pachinko machine 1 according to the present embodiment.

  This electronic circuit includes a main control circuit, a sub control circuit, a launch control circuit, a payout control circuit, and the like. The main control circuit is provided on the main control board 30. The sub control circuit is provided on the sub control board 40. The launch control circuit is provided on the launch control board 60. The payout control circuit is provided on the payout control board 61. The main control board 30 is a game control board that performs electrical control related to the progress of the pachinko game on the game board 2. The sub-control board 40 is an effect control board that performs electrical control of game effects by various effect devices based on control signals and game information from the main control board 30. The launch control circuit of the launch control board 60 and the payout control circuit of the payout control board 61 control the launch of pachinko balls and the payout of prize balls and rental balls based on the control signal and game information from the main control board 30.

  A main CPU 31 is mounted on the main control board 30 as control means for controlling game processing. The main CPU 31 includes a main ROM (read only memory) 33 and a main RAM (random access memory) 34. The main ROM 33 stores a program for processing and controlling the game operation of the pachinko machine 1. The main RAM 34 constitutes storage means having a stack area. In the stack area, register values used for control of the main CPU 31 are saved.

  In the above-described example, the configuration in which the main ROM 33 and the main RAM 34 are built in the main CPU 31 is shown. In addition to such a configuration, a read-only memory or a random access memory may be provided separately from the main CPU 31 and connected to the main CPU 31 via an input / output bus (not shown). Even in such a configuration, a desired program and data can be read and various data can be written.

  In the present embodiment, when the power supply monitoring IC 71 detects a decrease in the voltage of the power supply, the power supply monitoring IC 71 reduces the voltage level of the power interruption detection signal D from the high level (H) to the low level (L), thereby The power failure detection signal D indicates that the current voltage has decreased to a predetermined voltage. The power interruption detection signal D is input to the NMI terminal of the main CPU 31. When the voltage level of the power interruption detection signal D falls from the high level (H) to the low level (L), a non-maskable interrupt process is executed (see FIG. 14). Specifically, when the voltage level of the power interruption detection signal D falls from a high level (H) to a low level (L) while the main game process is regularly executed as will be described later, Is temporarily transferred from the main game process to the non-maskable interrupt process (see FIG. 14).

  By this non-maskable interrupt process, the NMI flag is set (step S1413). As described above, in the present embodiment, when the voltage of the power supply decreases to a predetermined voltage, only the process of setting the NMI flag is executed. In addition, since the power interruption detection signal D is input to the NMI terminal of the main CPU 31, when the voltage level of the power interruption detection signal D falls from the high level (H) to the low level (L), the non-maskable interrupt process must be performed. The NMI flag can be set accurately.

  After executing the non-maskable interrupt process, the process returns to the main game process, acquires game information data necessary for recovery, and stores the acquired game information data (processes of steps S1111 to S1127 described later). Subsequently, in the main game process, after interrupt is prohibited (step S1011), if the NMI flag is set (step S1015), the power interruption process is executed (step S1017). If the NMI flag is not set (step S1015), the interrupt is permitted (step S1021), and the main game process is continued. As described above, since the timing for executing the power interruption process is adjusted, even when a power interruption occurs, it is possible to return to the main game process and execute the post-system timer process (steps S1111 to S1127). The game information data can be obtained as the latest data when the power interruption occurs.

  As described above, in the present embodiment, when the power interruption detection signal is output, the game information data already collected at that time is not immediately saved, but once the main game process is returned, All necessary game information data is collected, and the game information data is stored in the main RAM 34. It should be noted that the time required to return to the main game process, collect all the game information data, and store the game information data in the main RAM 34 may be within the voltage guarantee time described later. As will be described later, the stored contents of the main RAM 34 are retained by a backup power supply (large-capacity capacitor) even when power interruption occurs and power is not supplied.

  Thereafter, when recovering from the power interruption, first, the communication data storage area is cleared (step S815). By doing in this way, it is possible to prevent an inappropriate command generated by power interruption from being transmitted to the sub control circuit (sub control board 40). In addition, when the power supply is restored, the game information data (latest information) acquired when the power interruption occurs is transmitted to the sub control circuit (step S823). Can be received, and the sub-control circuit can be accurately returned to the state at the time of power interruption (before power interruption).

  The pachinko machine 1 has a power supply board 70. The power supply board 70 is provided with a power supply circuit as a supply power supply. AC24V is input to the power supply circuit. The power supply circuit converts the input AC24V into a DC power supply and supplies it to the main control board 30, the sub control board 40, the launch control board 60, the payout control board 61, and the like.

<Backup power supply (capacitor)>
A large capacity capacitor that functions as a backup power source is mounted on the power supply board 70 (not shown). This capacitor is connected to a backup terminal VBB (not shown) of the main CPU 31. This capacitor is charged while power is supplied (when power is supplied). On the other hand, while power is not supplied (when power supply is interrupted), a voltage of 5 [V] is supplied from the charged capacitor to the main CPU 31 as a backup power supply via the backup terminal VBB. Is done. By doing so, the stored contents of the main RAM 34 of the main CPU 31 can be held by the backup power from the capacitor even when the power is not supplied. The main RAM 34 has a stack area. When power is not supplied, register contents can be held by saving register values in the stack area.

  The main RAM 34 of the main CPU 31 corresponds to “data storage means” and stores “game information necessary to advance the game”. Even when power interruption occurs and no power is supplied, the “game information” is held by the backup power supply (large-capacity capacitor).

  In addition, when the power supply is cut off, the supply voltage does not immediately become zero, but the power supply within a range in which the main control board 30 (game control means) can be normally operated within the voltage guarantee time. A voltage is supplied to the main control board 30. Thus, the voltage guarantee time is a time during which the power supply voltage in a range in which the main control board 30 can be operated normally can be supplied to the main control board 30. The voltage guarantee time is determined according to the capacity of a capacitor (not shown) constituting the power supply board 70 and the power consumption of the main control board 30. Therefore, the voltage guarantee time can be determined by appropriately changing the capacitance of the capacitor constituting the power supply substrate 70.

<Power supply monitoring IC 71 (power supply monitoring means)>
A power supply monitoring IC 71 is mounted on the power supply board 70 as power supply monitoring means. The power supply monitoring IC 71 monitors the voltage of the power supply output from the power supply circuit. When the voltage of the power supply drops below a predetermined voltage, the power supply monitoring IC 71 reduces the voltage of the power supply to a predetermined voltage on the main CPU 31 of the main control board 30 and the payout control CPU 68 on the payout control board 61. A power interruption detection signal D indicating that is output.

  FIG. 3 is a diagram illustrating a configuration of terminals of the power supply monitoring IC 71. The power monitoring IC 71 has a VSB terminal and a RESET terminal. The RESET terminal is connected to each NMI terminal of the main CPU 31 of the main control board 30 and the payout control CPU 68 of the payout control board 61.

  In a steady state, the power supply circuit of the power supply board 70 generates a supply power with a voltage of 33 [V] based on the supplied AC24V. When the voltage of the power supply output from the power supply circuit is lower than 17.2 [V], the power supply voltage V input to the VSB terminal of the power supply monitoring IC 71 is 33 as shown in FIG. [V] is lower than 17.2 [V]. The power monitoring IC 71 detects a decrease in the voltage of the power supply due to a decrease in the power supply voltage V input to the VSB terminal. When the power supply monitoring IC 71 detects a decrease in the voltage of the power supply, as shown in FIG. 4B, the power supply monitoring IC 71 reduces the voltage level of the power interruption detection signal D from the high level (H) to the low level (L). The power interruption detection signal D is output from the RESET terminal. The power interruption detection signal D is output to each NMI terminal such as the main CPU 31 or the payout control CPU 68 as the detection signal described above. When the main CPU 31 and the payout control CPU 68 detect the fall of the power interruption detection signal D input to these NMI terminals, the main CPU 31 and the payout control CPU 68 execute non-maskable processing (see FIG. 14).

  Further, when the power supply voltage V exceeds 17.2 [V] after the power is turned on or off, charging of the capacitor connected to the CT terminal (see FIG. 3) of the power supply monitoring IC 71 starts. Is done. When the capacitor is charged and the voltage output to the CT terminal rises to a predetermined voltage, as shown in FIG. 4B, the power interruption detection signal D has a value of the power supply voltage V of 17.2 [V]. After exceeding the voltage level, the voltage level rises from a low level (L) to a high level (H) with a predetermined time delay.

  The main CPU 31 constitutes access permission control means. The main CPU 31 monitors the power interruption detection signal D input from the RESET terminal of the power monitoring IC 71 to the NMI terminal after power supply from the power supply circuit is started and control is started. When the main CPU 31 detects that the power failure detection signal D has fallen, the voltage of the power supply, which is 33 [V] in a steady state, is greater than a predetermined voltage, that is, 17.2 [V]. In such a state, the state is not lowered, and access to the main RAM 34 is permitted (see step S719 in FIG. 7).

The reason why the threshold value for detecting a decrease in the voltage of the power supply, which is 33 [V] in the steady state, is set to 17.2 [V] is as follows. In the pachinko machine 1, switches 14s, 15s, and 16s, which will be described later, are used to detect the game ball. Voltage signals are output from these switches 14s, 15s and 16s and input to the main CPU 31. The main CPU 31 determines that each switch 14s, 15s, or 16s has detected a game ball when the voltage level of the input voltage signal falls from a high level (H) to a low level (L). The voltage of the voltage signal output from these switches 14s, 15s and 16s is 12 [V] at the high level (H). Therefore, when the voltage of the power supply, which is 33 [V] in a steady state, falls below 12 [V], it is erroneously detected that there is a switch input even though there is no switch input in the switches 14s, 15s and 16s. There is a case. For this reason, such a false detection is prevented by setting the threshold value V _SH for detecting a decrease in the power supply to 17.2 [V] higher than 12 [V].

<Reset IC 32>
As shown in FIG. 2, the main CPU 31 has an SRST terminal. This SRST terminal is connected to the RESET terminal of the reset IC 32 mounted on the main control board 30.

  FIG. 5 is a diagram illustrating the configuration of the terminals of the reset IC 32. As shown in FIG. 5, the reset IC 32 has terminals such as a VCC terminal, a CK terminal, a TC terminal, and a RESET terminal. An input voltage Vcc shown in FIG. 6A is applied to the VCC terminal. A watchdog clear signal C shown in FIG. 6B is input to the CK terminal. The watchdog timer signal T shown in FIG. 6C is input to the TC terminal by charging a capacitor of 0.22 [μF]. The RESET terminal outputs a system reset signal R to the main CPU 31.

  The VCC terminal of the reset IC 32 is supplied with an input voltage Vcc of 5 [V] from the power supply circuit of the power supply board 70 in a steady state. When the input voltage Vcc applied to the VCC terminal exceeds 4.3 [V] (see FIG. 6A), it is connected to the TC terminal of the reset IC 32 as shown in FIG. 6C. The capacitor starts charging. Further, the watchdog timer signal T input to the TC terminal reaches a predetermined voltage when a delay time elapses after charging of the capacitor is started (see FIG. 6C). This delay time can be determined by the capacitance of the capacitor connected to the TC terminal. For example, a value obtained by multiplying the capacitance 0.22 [μF] of the capacitor connected to the TC terminal by 1000 can be set as the delay time 220 [msec].

  When the watchdog timer signal T reaches the predetermined voltage, as shown in FIG. 6D, the reset IC 32 changes the voltage level of the system reset signal R output from the RESET terminal from the low level (L) to the high level ( H). The system reset signal R is input to the SRST terminal of the main CPU 31. When the voltage level of the system reset signal R input to the SRST terminal of the main CPU 31 is changed from the low level (L) to the high level (H), the system reset state of the main CPU 31 is released. When the system reset state of the main CPU 31 is released, the main CPU 31 starts control of main processing (see FIGS. 7 to 11) described later according to a program stored in the main ROM 33.

  When starting the control, the main CPU 31 executes a system timer interrupt process (see FIG. 13) described later every 2 [msec]. The main CPU 31 outputs a watchdog clear signal C to the CK terminal of the reset IC 32 as shown in FIG. The watchdog clear signal C is a signal whose voltage level alternately changes between a high level (H) and a low level (L) every 2 [msec] by the system timer interrupt process. The watchdog timer signal T is reset when the watchdog clear signal C input to the CK terminal of the reset IC 32 falls (high level (H) → low level (L)), and the voltage level drops to zero. (See FIG. 6C). Thereafter, the voltage level of the watchdog timer signal T rises again as the capacitor connected to the TC terminal is charged. Thereafter, the watchdog timer signal T is reset again by the watchdog clear signal C input to the CK terminal of the reset IC 32. Thereafter, after the voltage level of the watchdog timer signal T has decreased to zero, the voltage level is increased again as the capacitor is charged again.

  Therefore, as long as the watchdog clear signal C is output from the main CPU 31 by the system timer interrupt process and is input to the CK terminal of the reset IC 32, the watchdog timer signal T does not reach a predetermined voltage. In this case, the system reset signal is not output from the RESET terminal of the reset IC 32 and is not input to the SRST terminal of the main CPU 31.

  On the other hand, when the control of the main CPU 31 runs away for some reason, the watchdog clear signal C is not output from the main CPU 31 and is not input to the CK terminal of the reset IC 32. In such a case, as shown in FIG. 6 (c), the watchdog timer signal T reaches a predetermined voltage, and as a result, the voltage level of the system reset signal R is set as shown in FIG. 6 (d). It changes from high level (H) to low level (L).

  The system reset signal R is input to the SRST terminal of the main CPU 31. A system reset is applied to the main CPU 31 for a predetermined time by a change in the voltage level of the system reset signal R (high level (H) → low level (L)). By the system reset, the main CPU 31 returns the process to the beginning of the program and resumes the main process. That is, when the main CPU 31 runs out of control, the system is automatically reset and the processing of the main CPU 31 is resumed.

  As shown in FIG. 2, an I / O port (input / output port) 35 and a command output port 36 are connected to the main CPU 31. The I / O port 35 is for exchanging signals between peripheral devices such as various switches and solenoids described later and the main CPU 31. The command output port 36 outputs a command including a control signal and game information to the sub control circuit of the sub control board 40, the launch control circuit of the launch control board 60, and the payout control circuit of the payout control board 61. Is for. Control signals and game information sent from the main CPU 31 via the I / O port 35 and the command output port 36 are sent to each control board such as the sub-control board 40, the launch control board 60, and the payout control board 61 and peripheral devices. Sent.

<Various switches>
The main control board 30 is connected with a passing gate switch 14s and a start winning a prize opening switch 15s. The passage gate switch 14 s is provided inside the passage gate 14 described above, and detects that the pachinko ball passes through the passage gate 14. The start winning port switch 15s detects a pachinko ball that has won the ordinary electric accessory 15.

  The main control board 30 is connected to a count switch 16s and a general winning a prize port switch 17s. The count switch 16 s detects a pachinko ball that has won the grand prize opening 16. The general winning opening switch 17 s detects a pachinko ball that has won the general winning opening 17.

  The main control board 30 is connected to a start winning port solenoid 15v, a large winning port solenoid 16v, and the like. The start winning opening solenoid 15v expands the ball receiving port of the ordinary electric accessory 15 as an actuator. The big prize opening solenoid 16v opens and closes the door of the big prize opening 16.

  A backup clear switch board is connected to the main control board 30. A backup clear switch 19 is mounted on the backup clear switch board. The backup clear switch 19 outputs a backup clear signal. The backup clear signal instructs the clearing of the backup contents of the main RAM 34 provided in the main CPU 31 constituting the main control circuit of the main control board 30 and the RAM (not shown) constituting the payout control circuit of the payout control board 61. It is a signal to do.

  Each of the switches 14s, 16s and 17s, and the actuators 15v and 16v described above is connected to the main control board 30 via the panel relay board 80. When each of the switches 14s, 15s, 16s, and 17s detects a pachinko ball, the detection signal is input to the main CPU 31 of the main control board 30. The main CPU 31 drives and controls each of the actuators 15v and 16v described above according to the input detection signal.

<Sub control board 40>
The sub control board 40 is connected to a special symbol display device 10 (hereinafter referred to as “LCD 10”), and the sub control board 40 performs image display control for displaying images on the LCD 10. Is connected to the lamp / LED 48 and the speaker 49. The sub-control board 40 controls the lighting of the lamp / LED 48 according to the gaming state, and the sound control for emitting the sound effect from the speaker 49. The lamp / LED 48 includes an upper frame decoration lamp 6, a normal symbol display device 11, a special symbol start memory number display unit 12, a normal symbol start memory number display unit 13, and the like.

  A sub CPU 41, a program ROM 42, and a work RAM 43 are mounted on the sub control board 40. The sub CPU 41 receives a command transmitted from the main control board 30 via the relay board 37 and the command input port 47. The sub CPU 41 interprets the received command and issues a control command to the image control circuit 44, the lamp control circuit 45, and the sound control circuit 46. The program ROM 42 stores a control program. This control program is a program for the sub CPU 41 to control the operations of the LCD 10, the lamp / LED 48, and the speaker 49. The work RAM 43 serves as a temporary storage unit when the sub CPU 41 performs process control according to the control program stored in the program ROM 42.

<Image control circuit 44>
The image control circuit 44 generates image data to be displayed on the LCD 10 in accordance with a control command from the sub CPU 41. The main CPU 31 determines a big hit when a pachinko ball wins the normal electric accessory 15 and a start win occurs, and transmits the result of the big hit determination to the sub-control circuit. The sub control circuit sequentially stops and displays the special symbols on the LCD 10 in a manner corresponding to the result of the jackpot determination. The sub-control circuit performs a reach effect on the LCD 10 using the special symbol and the effect image when the left symbol and the right symbol are stopped and displayed in the same symbol and the reach state is reached. The lamp control circuit 45 controls the light emission of the lamp / LED 48 according to the gaming state of the pachinko machine 1 according to the drive signal from the sub CPU 41. The sound control circuit 46 controls the speaker 49 by a drive signal from the sub CPU 41.

  The program ROM 42 constitutes an effect storage unit that stores a plurality of effect modes in a pattern. The main CPU 31, main ROM 33 and main RAM 34 on the main control board 30 and the sub CPU 41, program ROM 42 and work RAM 43 on the sub control board 40 constitute an effect determining means. The effect determining unit determines an effect mode corresponding to the effect to be executed from the effect modes stored in the effect storage unit. The LCD 10 and the image control circuit 44, the lamp / LED 48 and the lamp control circuit 45, the speaker 49 and the sound control circuit 46 constitute a production means. The effect means executes an effect corresponding to the effect mode determined by the effect determining means.

<Launch control board 60>
A launch device 64 is connected to the launch control board 60. The firing device 64 is driven in accordance with the operation of the firing handle 5. The firing control board 60 constitutes a firing control circuit. The launch control circuit drives and controls the launch device 64 according to the operation of the launch handle 5 by the player, and launches the pachinko ball to the game board 2.

<Discharge control board 61>
A CPU 68 is mounted on the payout control board 61 as a control means for controlling game processing related to payout control. The payout control board 61 is connected to a payout device 63 for paying out winning balls and rental balls. The payout control circuit configured by the payout control board 61 receives a payout command output from the main control board 30 via the frame relay board 62 according to various winnings. In accordance with the received payout command, the payout control circuit drives and controls the payout device 63 to pay out the winning ball.

  Connected to the payout control board 61 is a card unit 65 that requests lending of pachinko balls. Connected to the card unit 65 is a ball lending operation panel 66 including the above-described ball lending button 7a and return button 7b. The card unit 65 communicates with the payout control circuit of the payout control board 61 according to the operation of the ball lending button 7a and the return button 7b. The payout control circuit drives and controls the payout device 63 in accordance with a signal output from the card unit 65, and pays out a rented ball.

<< Main processing >>
7 to 11 are flowcharts showing the main process. This main process is executed by the main CPU 31 of the main control board 30.

  First, the main CPU 31 initializes the watchdog timer (step S711).

  Next, the main CPU 31 performs initial setting of input / output ports (step S713).

  Next, the main CPU 31 determines whether or not it is in a power interruption detection state (step S715). Whether or not the power failure detection state is present is determined by waiting until the power failure detection signal bit (bit 0) becomes 1 and the power failure detection signal bit (bit 0) becomes 1. The contents of the input port at that time are defined as “initial input port value”. The contents of this input port are determined by the voltage level of the power interruption detection signal D output from the power supply monitoring IC 71. When the main CPU 31 determines in the determination process in step S715 that the power interruption detection state is present (YES), the main CPU 31 repeats the process in step S715.

  On the other hand, when the main CPU 31 determines in the determination process of step S715 that it is not in the power interruption detection state (NO), it executes a sub-control reception acceptance wait process (step S717). This sub-control reception acceptance wait process is a process of setting a wait time, for example, 500 [msec] in the main RAM 34 and waiting until the wait time elapses. The wait time is for waiting for the process of the main CPU 31 until the initial setting process in the sub-control board 40 is completed.

  Next, the main CPU 31 permits writing to the RWM (read / write memory) (step S719). In this specification, RWM (read / write memory) means a readable / writable memory such as the main RAM 34 described above. In this RWM (read / write memory), game information data to be described later, that is, various data (“game information necessary for advancing the game”) acquired by each processing in steps S1111-S1127 is stored. . Further, the RWM (read / write memory) can hold the stored contents by the backup power supply from the capacitor even when the power is not supplied.

  Next, the main CPU 31 sets an initial setting address, for example, 8000H in the stack pointer (step S721).

  Next, the main CPU 31 determines whether or not the backup switch is on (step S723). As described above, the backup clear signal is output from the backup clear switch 19. Step S723 is processing to determine whether or not a backup clear signal is output from the backup clear switch 19.

  When the main CPU 31 determines that the backup switch is not on in the determination process in step S723 (NO), the main CPU 31 determines whether or not the power interruption detection flag is set (step S725). The power interruption detection flag is a flag indicating that a power interruption has occurred and a power interruption process described later (see FIG. 15) has been executed. The power interruption detection flag is set in the process of step S1513 in FIG.

  When the main CPU 31 determines that the power interruption detection flag is set in the determination process in step S725 (YES), the main CPU 31 checks the work area for damage (step S727) and determines whether the work area is damaged. (Step S729). The damage to the work area means that the voltage supplied by the power interruption decreases, the work area becomes unstable, and the contents of the work area change.

  When the main CPU 31 determines that the work area is not damaged (NO), the main CPU 31 shifts the process to step S811 shown in FIG. The main CPU 31 determines that the backup switch is on in the determination process in step S723 (YES), determines that the power failure detection flag is not set in the determination process in step S725 (NO), or If it is determined in step S729 that the work area is damaged (YES), the process proceeds to step S911 shown in FIG. By the processing of steps S911 to S921 shown in FIG. 9, processing when the gaming machine is turned on is executed. This process is mainly performed when the RWM is initialized when the backup switch is being pressed (when “YES” is determined in the step S723).

<Power failure recovery processing>
When the main CPU 31 determines that the work area is not damaged in the determination processing in step S729 of FIG. 7 (NO), the main CPU 31 corrects the stack pointer to an appropriate stack pointer (step S811). This process is a process of restoring the stack pointer when the stack pointer is saved in the main RAM 34, for example, in a power interruption process (FIG. 15) described later.

  Next, the main CPU 31 performs initial setting of the work area (step S813). Through the processing in step S813, the work area is initialized when the power is restored.

  Next, the main CPU 31 clears the communication data storage area (step S815). For example, the process of step S815 is a process of storing “0” in the communication data storage area length (for example, 70 bytes) in order from the address of the communication data storage area. By this processing, processing for clearing the communication data storage area, that is, processing for clearing the ring buffer is performed. The communication data storage area and the ring buffer correspond to “transmission storage means”. A transmission command is stored as communication data in a communication data storage area or a ring buffer.

  Next, the main CPU 31 makes a setting for notifying the high probability gaming state (step S817). A special symbol gaming state confirmation process is performed by the process of step S817. In the process of step S817, nothing is performed in the low probability state, and a notification flag representing the probability value is set in the high probability state.

  Next, the main CPU 31 sets an internal state flag when the power is restored (step S819). In the process of step S819, the door / frame open / close state area and the illegal prize information management flag area are calculated, and the security information generation process and the power return internal state flag storage process are performed.

  Next, the main CPU 31 sets a game state flag when the power is restored (step S821). The processing of this step S821 takes the logical product of the game state parameter area and the information master value per special symbol, and logically sums the operation result and the contents of the special symbol game state flag area, Store in the status flag area.

  Next, the main CPU 31 transmits a power return command to the sub control circuit (sub control board 40) (step S823). In the process of step S823, the latest information obtained at the time of power interruption is added as a parameter and transmitted to the sub-control circuit.

  Specifically, the process of step S823 reads various data stored in the RWM (main RAM 34) in each process of steps S1111 to S1127, which will be described later, and combines the read various data into parameter information. The parameter information is added to the command and transmitted to the sub-control circuit. The various data stored in the RWM (main RAM 34) corresponds to “game information necessary to advance the game”.

  As described above, when the power is restored, the process of clearing the communication data storage area is first executed by the process of step S815. By processing in this way, even when an inappropriate command is generated due to a power interruption, for example, even when an unsent command exists, an unsent command is restored when power is restored. Need not be transmitted to the sub-control circuit (sub-control board 40), and the processing can be prevented from becoming complicated.

  Further, when the power is restored, the process of step S823 is executed to transmit various data (latest information) obtained at the time of power interruption to the sub-control circuit. Therefore, the sub control circuit can accurately return the sub control circuit to the state at the time of power interruption (before power interruption) by receiving all of the various data at the time of power interruption.

  Next, the main CPU 31 sets the operation of the main CPU 31 (step S825), and ends the main process. The processing in step S825 is processing for prohibiting interruption to the main CPU 31, performing CTC operation setting processing and serial circuit initialization processing, and initializing peripheral devices of the main CPU 31. Here, the CTC operation setting process is a process of setting the operation of the built-in clock that generates an interrupt every predetermined time, for example, every 2 [msec]. The serial circuit initialization processing is processing for setting serial in / out operation so that serial communication to the sub-control board 40 and the like can be performed normally.

<Power-on processing>
When the main CPU 31 determines that the backup switch is on in the determination process in step S723 of FIG. 7 described above (YES), and determines that the power failure detection flag is not set in the determination process in step S725 (NO) ), Or when it is determined that the work area is damaged in the determination process of step S729 (YES), a random number is acquired for the initial value related to determination of special symbol (step S911).

  Next, the main CPU 31 clears the entire work area (step S913). For example, when “0” is written in the area from address 7E00H to 7FFFH, the area is checked for 0. If there is an area other than “0”, the same processing is repeated from 7E00H.

  Specifically, the process of step S913 includes the following processes. First, the main CPU 31 initializes a stack pointer stored in the main RAM 34. Next, the main CPU 31 sets the start address of the work area of the main RAM 34, for example, 7E00H. Thereafter, the main CPU 31 sets clear data and determines whether or not the data at the set head address has been cleared. If the data at the set top address has not been cleared, the main CPU 31 repeats the above-described process of initializing the stack pointer, setting the top address, and setting the clear data again.

  On the other hand, if the data at the set head address has been cleared, the main CPU 31 sets the next address after the cleared head address. The main CPU 31 determines whether or not the set address is the final address of the work area of the main RAM 34, for example, 7FFFH. When the main address is not the final address, the main CPU 31 repeats the process of setting the clear data, the determination of whether or not the data has been cleared, and the next address setting again. To clear.

  Next, the main CPU 31 sets an initial value related to the special symbol hit determination using the random number acquired in step S911 (step S915).

  Next, the main CPU 31 initializes a work area when the RWM (read / write memory) is initialized (step S917). The processing in step S917 is processing for setting the address of the work area initialization data as the table address of the input register and executing data storage processing.

  Next, the main CPU 31 transmits a command for initializing the RWM (read / write memory) to the sub-control board 40 (step S919). The sub control board 40 is initialized by the command transmitted by the process of step S919.

  Next, the main CPU 31 initializes peripheral devices of the main CPU 31 (step S921). In step S921, the interrupt is prohibited, the CTC operation setting process and the serial circuit initialization process are performed, and the peripheral devices of the main CPU 31 are initialized. Again, the CTC operation setting process is a process for setting the operation of the built-in clock that generates an interrupt every predetermined time, for example, every 2 [msec]. The serial circuit initialization processing is processing for setting serial in / out operation so that serial communication to the sub-control board 40 and the like can be performed normally.

<< Main game processing >>
The following steps S1011 to S1127 are main game processes that are repeatedly executed while the power is constantly supplied to the pachinko machine 1. In this main game process, interruption is prohibited, the NMI flag area is loaded, and when the value of the NMI flag area is [A5H], the power interruption process (step S1017 in FIG. 10) is executed. When the value of [A5H] is not [A5H], the power interruption process is not performed and the normal process is executed.

  The power interruption process is executed only in the main game process at this time, and the power interruption process is not executed by the interrupt process while the other processes are being executed. Also, since the main process that was performed before the occurrence of the power interruption is performed until the NMI occurrence information is confirmed, the process after the system timer elapses is performed if the process after the system timer elapses after the NMI flag is detected. The power interruption process is started after the latest game information at the time of power interruption is acquired.

  After executing the processing of step S921, the main CPU 31 prohibits interruption (step S1011). The process of step S1011 performs an interrupt prohibition process so as to mask execution of the interrupt process.

  Next, the main CPU 31 loads the data stored in the NMI flag area (step S1013), and determines whether or not the NMI flag is set (step S1015). When the NMI flag is set, [A5H] is stored in the NMI flag area, and when the NMI flag is not set, a value other than [A5H] is stored in the NMI flag area. .

  Next, when determining that the NMI flag is set (YES), the main CPU 31 calls and executes the power interruption process shown in FIG. 15 (step S1017).

  When the main CPU 31 determines that the NMI flag is not set in the determination process in step S1015 (NO) or executes the process in step S1017, the main CPU 31 updates various random numbers for initial values (step S1019).

  Next, the main CPU 31 permits an interrupt (step S1021). Thus, the interrupt disabled state is released and various interrupts are permitted.

  Next, the main CPU 31 updates the random number for production (step S1023).

  Next, the main CPU 31 monitors a system timer (step S1025). The process of step S1025 is to determine whether or not a predetermined time has elapsed by determining whether or not the timer value of the system timer has reached a predetermined value. If the timer value has not reached the predetermined value, it is determined that the predetermined time has not elapsed, and the process returns to step S1011 described above. On the other hand, when the timer value reaches the predetermined value, the following processing after the system timer elapses is executed assuming that the predetermined time has elapsed.

  When the timer value of the system timer reaches a predetermined value, the system timer monitoring timer is reset. Further, the timer value of the system timer is updated by the process of step S1319 in FIG.

  As described above, if the predetermined time has not elapsed, the process returns to step S1011. This makes it possible to repeatedly determine whether or not the NMI flag (power supply lowering information) is set. Therefore, it can be accurately determined whether or not the voltage of the power supply has dropped below a predetermined voltage.

  When a predetermined time has elapsed, the following processing after the system timer elapses is executed. Therefore, even when the NMI flag (power supply lowering information) is set, if the predetermined time has elapsed, the following steps S1111 to S1127 are executed. As will be described later, in each process of steps S1111-S1127, various data acquired by these processes are stored in the RWM. In this way, it is possible to preferentially execute processing for acquiring various types of data and accurately acquire information necessary for power recovery.

<Process after system timer elapse>
The following steps S1111 to S1127 are sequentially executed as post-system timer processing in the main game process.

  Next, the main CPU 31 updates the timer value (step S1111). By this process, an initial setting process and a 2-byte timer value update process are executed. Specifically, various timers such as a waiting time timer for synchronizing the main control circuit of the main control board 30 and the sub control circuit of the sub control board 40 by the main CPU 31 and a special prize opening time timer are provided. Update processing is executed.

  Next, the main CPU 31 controls special symbols (special symbol control processing) (step S1113). The process of step S1113 performs a special symbol waiting time check process, and according to the contents of the special symbol control state flag area, a special symbol memory check process, a special symbol variation time management process, a special symbol display time management process, a grand prize Processing for opening the mouth 16, processing for opening the special winning opening 16, and end interval processing per special symbol are performed.

  Next, the main CPU 31 controls the normal symbol (common symbol control process) (step S1115). In step S1115, a normal symbol waiting time check process is performed, and a normal symbol memory check process, a normal symbol variation time management process, a normal symbol display time management process, and a big prize are performed according to the contents of the normal symbol control state flag area. The pre-opening process of the mouth 16, the process during the opening of the special winning opening 16, and the normal symbol end interval process are performed.

  Next, the main CPU 31 controls the symbol display device (step S1117). The process of step S1117 controls the special symbol display device 10 and the normal symbol display device 11. Normal symbol display device control processing and special symbol display device control processing are performed. If the game board 2 of the pachinko machine 1 is provided with the launch position notification LED, the launch position notification LED display control process is also performed in the process of step S1117. The launch position notification LED notifies the player of information regarding the optimal launch position of the pachinko ball on the game board 2.

  Next, the main CPU 31 generates game information data (step S1119). The illegal winning monitoring control timer update process, the start port signal process, the external terminal board related signal generation process, the electric member operating signal generation process, and the trial test signal generation process are performed. The game information generated in step S1119 is mainly transmitted to a management device connected to the pachinko machine 1 such as a hall computer.

Next, the main CPU 31 generates symbol reservation number data (step S1121).
Normal symbol reservation number data generation processing and special symbol reservation number data generation processing are performed. The game information data generated in step S1121 also corresponds to “game information necessary to advance the game”.

  Next, the main CPU 31 executes a port output process (step S1123), and executes a game ball payout process (step S1125). In step S1125, a prize ball counter is determined, and a payout request command is transmitted.

  Next, the main CPU 31 executes processing for a fraud detection-related command (step S1127). In step S1127, fraud detection related setting processing and fraud detection determination processing are performed. In the case of fraud detection, fraud detection related command transmission reservation processing is performed.

  In each process of steps S1111 to S1127 described above, various data acquired by these processes is also stored in the RWM along with each process of steps S1111 to S1127. For example, information such as the special symbol control process in step S1113, the general symbol control process in step S1115 and the stop symbol information determined by the payout process in step S1125, the changing time information, the winning prize winning number information and the prize ball information, Along with these processes, it is stored in the RWM. When the power is restored, the information can be read from the RWM to return to the gaming state when the power interruption occurs. In addition to the various types of information described above, the symbol reservation number data generated in step S1121 may be stored in the RWM. In this way, after various data is stored in the RWM by the processes of steps S1111-S1127, the power interruption process is performed by the process of FIG. Various types of data such as stop symbol information, variable time information, big prize opening prize number information, prize ball information, and symbol hold number data correspond to “game information necessary to advance the game”.

  As described above, the stored content of the RWM (main RAM 34) can be held by the backup power from the capacitor mounted on the power supply board 70 even when the power is not supplied. As described above, since various types of data are stored in the RWM (main RAM 34) in each of steps S1111-S1127, the latest various types of data are stored in the RWM (main RAM 34) each time the main game process is repeatedly executed. And various data can be stored while being constantly updated.

  Next, when the power of the pachinko machine 1 is restored, various data stored in the RWM are read and transmitted as command parameters to the sub control circuit of the sub control board 40 (see step S823).

<< Direction control command interrupt processing >>
FIG. 12 is a flowchart showing an effect control command interrupt process. This interrupt process is a maskable interrupt process, and is a process that is accepted only when an executing program designates an interrupt acceptance permission.

  First, the main CPU 31 saves the value of the AF register indicating the value of the program counter when the system timer interrupt occurs in the stack area of the main RAM 34 (step S1211).

  Next, the main CPU 31 determines whether or not the NMI flag is set (step S1213). The NMI flag is a flag set in the process of step S1413 in the flowchart shown in FIG. As will be described later, the NMI flag is a flag indicating whether or not the voltage of the power supply output from the power supply circuit has dropped. When the main CPU 31 determines that the NMI flag is set (YES), that is, when the voltage of the power supply decreases, the main CPU 31 shifts the processing to step S1225 described later.

  On the other hand, when the main CPU 31 determines that the NMI flag is not set (NO), that is, when the voltage of the power supply is not lowered, the main CPU 31 determines that the BC register and the DE register at the time when the interrupt is permitted. And the HL register are saved in the stack area of the main RAM 34 (step S1215). The BC register and the DE register are general-purpose registers, and the HL register is an indirect reference register.

  Next, the main CPU 31 adjusts the interrupt timing (step S1217).

  Next, the main CPU 31 performs setting for clearing the watch dog timer (step S1219). By this processing, the watchdog clear signal C is output to the CK terminal of the reset IC 32.

  Next, the main CPU 31 confirms preparation for transmission (step S1221). All block transmission check processing and transmission buffer content check processing are performed by the transmission preparation confirmation processing. As a result, if the result of all block transmission check processing is “waiting to send” and the result of the transmission buffer content check processing is “empty”, index processing, data output processing, communication completion confirmation processing, Is done.

  Next, the main CPU 31 reads the values of the BC register, DE register, and HL register saved in the process of step S1215 from the stack area of the main RAM 34, and restores the BC register, DE register, and HL register ( Step S1223).

  Next, the main CPU 31 reads the value of the AF register saved in the process of step S1211 from the stack area of the main RAM 34, and restores the AF register (step S1225).

  Next, the main CPU 31 permits interruption (step S1227), and ends the effect control command interrupt process. Thus, the interrupt disabled state is released and various interrupts are permitted.

<< System timer interrupt processing >>
FIG. 13 is a flowchart showing the system timer interrupt process. This interrupt process is a maskable interrupt process, and is a process that is accepted only when an executing program designates an interrupt acceptance permission.

  First, the main CPU 31 saves the value of the AF register indicating the value of the program counter when the system timer interrupt occurs in the stack area of the main RAM 34 (step S1311).

  Next, the main CPU 31 determines whether or not the NMI flag is set (step S1313). The NMI flag is a flag set in the process of step S1413 in the flowchart shown in FIG. As will be described later, the NMI flag is a flag indicating whether or not the voltage of the power supply output from the power supply circuit has dropped. When the main CPU 31 determines that the NMI flag is set (YES), that is, when the voltage of the power supply decreases, the main CPU 31 shifts the processing to step S1335 described later.

  On the other hand, when the main CPU 31 determines that the NMI flag is not set (NO), that is, when the voltage of the power supply is not lowered, the main CPU 31 executes the following normal processing.

  First, the main CPU 31 permits an interrupt (step S1315). Thus, the interrupt disabled state is released and various interrupts are permitted.

  Next, the main CPU 31 saves the values of the BC register, DE register, and HL register at the time when the interrupt is permitted to the stack area of the main RAM 34 (step S1317). The BC register and the DE register are general-purpose registers, and the HL register is an indirect reference register.

  Next, the main CPU 31 updates the value of the system timer monitoring timer (step S1319). For example, 1 is added to the timer value of the system timer monitoring timer.

  Next, the main CPU 31 inverts the voltage level of the watchdog clear signal C and outputs it to the CK terminal of the reset IC 32 (step S1321). By the processing in step S1321, the watchdog timer signal T is reset before reaching a predetermined voltage as shown in FIG. 6C.

  Next, the main CPU 31 updates the random number (step S1323). By updating the random number, the value of the jackpot determination random number used for the jackpot determination and the initial value random number described above are updated. The jackpot determination random number is referred to by the main CPU 31 when determining whether or not to play the jackpot game in the special symbol control process (step S1113 in FIG. 11) described above.

  Next, the main CPU 31 reads an input port (step S1325).

  Next, the main CPU 31 detects a switch input (step S1327). In the process of detecting the switch input, based on the detection signals output from the switches 14s to 17s described above, whether or not the pachinko ball has passed through the passage gate 14, the ordinary electric accessory 15 and the big prize opening 16 are displayed. Then, a process of detecting whether or not the pachinko ball has won the general winning opening 17 or the like is performed.

  Next, the main CPU 31 turns on the dynamic LED (step S1329). This dynamic LED is an LED (light emitting diode) which is controlled by the main control board 30 to be turned on or off.

  Next, the main CPU 31 executes a prize-related command (step S1331). The prize winning related command 16 and the general winning prize opening 17 are controlled by this winning related command.

  Next, the main CPU 31 reads the values of the BC register, DE register, and HL register saved in the process of step S1317 from the stack area of the main RAM 34, and restores the BC register, DE register, and HL register (step S1333). ).

  Next, the main CPU 31 reads the value of the AF register saved in the process of step S1311 from the stack area of the main RAM 34, restores the AF register (step S1335), and ends the system timer interrupt process.

<< Non-maskable interrupt processing >>
FIG. 14 is a flowchart showing the non-maskable interrupt process. This non-maskable interrupt process is executed as a non-maskable interrupt process when the voltage level of the power interruption detection signal D input to the NMI terminal of the main CPU 31 falls from a high level (H) to a low level (L). The The power interruption detection signal D is output from the RESET terminal of the power supply monitoring IC 71 and input to the NMI terminal of the main CPU 31. Since this process is executed as a non-maskable interrupt process, it is an interrupt that cannot be masked and can be accepted at any timing. In this way, processing can be executed immediately when the voltage of the power supply decreases.

  First, the main CPU 31 saves the value of the AF register indicating the value of the program counter when the non-maskable interrupt occurs in the stack area of the main RAM 34 (step S1411).

  Next, the main CPU 31 sets an NMI flag (step S1413). The NMI flag is a flag indicating that the non-maskable interrupt processing has been executed due to the occurrence of power interruption. That is, the flag indicates that the power supply voltage output from the power supply circuit has dropped and the power interruption detection signal D output from the power supply monitoring IC 71 has fallen from (H) to (L). This NMI flag corresponds to “power supply lowering information”.

  By storing [A5H] in the NMI flag area, the NMI flag is set, and by storing values other than [A5H] in the NMI flag area, the setting of the NMI flag is canceled.

  Next, in step S1411, the main CPU 31 restores the AF register value saved in the stack area of the main RAM 34 to the AF register (step S1415), and ends this subroutine. By returning the AF register, it is possible to return to the state immediately before the occurrence of the non-maskable interrupt.

<< Power interruption process >>
FIG. 15 is a flowchart illustrating a subroutine for power interruption processing. This power interruption process is called and executed in the process of step S1017 of FIG.

  First, the main CPU 31 executes a work area damage check data generation process to calculate a work area damage check value (step S1511).

  Next, the main CPU 31 sets a power interruption detection flag (step S1513). The power interruption detection flag is a flag indicating that power interruption has occurred and this power interruption processing has been executed. The power interruption detection flag is referred to in step S725 of the main process.

  Next, the main CPU 31 prohibits writing to the RWM (step S1515) and executes an infinite loop.

  As described above, in the pachinko machine 1 according to the present embodiment, before executing the power interruption process in step S1011 in FIG. 10, the various data acquired by the processes in steps S1111 to S1127 in FIG. The RWM (main RAM 34) stores it in accordance with each processing of steps S1111 to S1127.

By doing in this way, since various data are memorize | stored in RWM (main RAM34) before performing an electrical disconnection process, the various data required at the time of a power return can be memorize | stored exactly. While the power is not supplied, various data stored in the RWM (main RAM 34) is held by the backup power from the capacitor mounted on the power supply board 70.
<<< Outline of Pachinko Machine 1 >>>

The pachinko machine 1 in the present embodiment is
Game control means (main control board 30 and main control circuit) for controlling the progress of the game,
Power supply monitoring means (power supply monitoring IC 71) that monitors the voltage of the power supply supplied to the game control means and issues a drop detection signal when power interruption occurs when the voltage of the power supply drops below a predetermined voltage;
Sub-control means (sub-control board 40 or sub-control circuit) that includes a transmission storage means (communication data storage area or ring buffer) for storing a transmission command, reads the transmission command from the transmission storage means, and controls the production. Command transmission means (main CPU, command output port 36) for transmitting the transmission command to
Data storage means (main RAM 34) capable of holding data even after the voltage of the power supply to the game control means falls below the predetermined voltage;
The game control means executes the following processing.
(A) When the drop detection signal is issued from the power supply monitoring means, power drop information (NMI flag) indicating that the voltage of the power supply has dropped is set by non-maskable interrupt processing, and then non-maskable split Power supply drop information set processing (non-maskable interrupt processing in FIG. 14) to return to the original processing before loading,
(B) A main control process (main game process in FIGS. 10 and 11) for proceeding with the game,
(B-1) Interrupt prohibition processing (step S1011 in FIG. 10) for prohibiting an interrupt,
(B-2) A determination process (step S1015 in FIG. 10) for determining whether or not the power supply lowering information is set after the interrupt prohibition process;
(B-3) After the determination process, an interrupt permission process for permitting an interrupt (step S1021 in FIG. 10);
(B-4) After the interrupt permission process, a game control process for controlling a game and a game information acquisition process for acquiring game information necessary to advance the game (steps S1111 to S1127 in FIG. 11), Can be repeated,
(B-5) In (b-4), when the power reduction information setting process (a) is executed after the interrupt permission process (step S1413 in FIG. 14), the power supply (a) Returning from the decline information set process, a main game process for executing the game control process and the game information acquisition process (steps S1111 to S1127 in FIG. 11),
(C) A game that stores the game information acquired in the process (b-4) in the data storage means when it is determined in the determination process (b-2) that the power supply lowering information is set. (D) Information storage processing (power interruption processing in FIG. 15), and (d) when the power supply voltage to the game control means becomes higher than a predetermined voltage (step S715 in FIG. 7), The content stored in the credit storage means is cleared (step S815 in FIG. 8), and the game information stored in the data storage means is transmitted as a transmission command from the command transmission means (step S823 in FIG. 8).

  According to this configuration, since the timing for executing the power interruption process is adjusted, the information necessary for the power recovery process can be accurately obtained and then the power interruption can be performed. Also, when the power is restored, the contents stored in the transmission storage means are cleared, and the stored game information is only transmitted as a transmission command from the command transmission means. The processing at the time can be simplified and the storage capacity required for the processing can be reduced.

Further, the pachinko machine 1 according to the present embodiment has the above-described configuration.
In the interrupt process (the effect control command transmission interrupt process in FIG. 12 or the system timer interrupt process in FIG. 13) executed by an interrupt that occurs every predetermined time, the power supply lowering information is not set (FIG. 12). In the case of “NO” in step S1213 or “NO” in step S1313 in FIG. 13, predetermined processing (steps S steps S1215 to S1223 in FIG. 12 or steps Ssteps S1315 to S1333 in FIG. 13) is executed. When the power supply lowering information is set (in the case of “YES” in step S1213 in FIG. 12 or “YES” in step S1313 in FIG. 13), the execution of the predetermined process is omitted. .

  According to this configuration, it is possible to shorten the time required for processing to acquire and store various types of information necessary for processing after power recovery, and processing required within a predetermined time, for example, within a voltage guarantee time. Can be cut off.

Furthermore, the pachinko machine 1 in the present embodiment has the above-described configuration,
The process (b-4) is as follows.
(B-4-1) After executing the interrupt permission process of (b-3), a process for determining whether or not the timer value (system timer value) has reached a predetermined value or more (step S1025 in FIG. 10) ),
(B-4-2) When the timer value is less than the predetermined value, a process of returning to the process of (b-1);
(B-4-3) When the timer value is equal to or greater than the predetermined value, the game control process and the game information acquisition process are included.
In the process (b-5), when the timer value is equal to or greater than the predetermined value in the process (b-4-3), the power reduction information setting process (a) is executed. Returning from the power supply lowering information setting process (a), the game control process and the game information acquisition process are executed (step S1025 in FIG. 10).

  According to this configuration, while forming a timing at which it can be repeatedly determined whether or not the power supply lowering information is set, even if the power supply lowering information is set when a predetermined time has elapsed, By executing the game information acquisition process, it is possible to accurately acquire information necessary for power recovery.

1 Pachinko machine (game machine)
2 Game board 10 Special symbol display device 11 Normal symbol display device 15 Normal electric accessory 30 Main control board (game control means)
31 Main CPU (command transmission means)
32 Reset IC
33 Main ROM
34 Main RAM (data storage means)
36 Command output port (command transmission means)
40 Sub control board 61 Discharge control board 70 Power supply board 71 Power supply monitoring IC (Power supply monitoring means)

Claims (3)

Game control means for controlling the progress of the game;
Power supply monitoring means for monitoring the voltage of the power supply supplied to the game control means, and issuing a drop detection signal when power interruption occurs when the voltage of the power supply drops below a predetermined voltage;
Command transmitting means for storing a transmission command, a command transmitting means for reading the transmission command from the transmission storing means, and transmitting the transmission command to a sub-control means for controlling the production;
Data storage means capable of holding data even after the voltage of the power supply to the game control means falls below the predetermined voltage;
The gaming machine is characterized by executing the following processing.
(A) When the drop detection signal is issued from the power supply monitoring means, the power drop information indicating that the voltage of the power supply is lowered is set by the non-maskable interrupt process, and then the original before the non-maskable interrupt Power drop information set processing to return to processing,
(B) Main control processing for advancing the game,
(B-1) interrupt disable processing for disabling interrupts;
(B-2) A determination process for determining whether or not the power supply lowering information is set after the interrupt prohibition process;
(B-3) an interrupt permission process for permitting an interrupt after the determination process;
(B-4) After the interrupt permission process, it is possible to repeatedly execute a game control process for controlling a game and a game information acquisition process for acquiring game information necessary to advance the game,
(B-5) In (b-4), when the power reduction information setting process (a) is executed after the interrupt permission process, the process returns from the power reduction information setting process (a). A main game process for executing the game control process and the game information acquisition process,
(C) A game that stores the game information acquired in the process (b-4) in the data storage means when it is determined in the determination process (b-2) that the power supply lowering information is set. Information storage processing, and (d) when the voltage of the power supply to the game control means becomes higher than a predetermined voltage, after clearing the contents stored in the storage means for transmission as the power is restored, A process of transmitting the game information stored in the data storage means in the process of (c) from the command transmission means to the sub-control means as a transmission command.   The interrupt process executed by an interrupt generated every predetermined time executes a predetermined process when the power supply lowering information is not set, and executes the predetermined process when the power supply lowering information is set. The gaming machine according to claim 1, wherein execution of the process is omitted. The process (b-4) is as follows.
(B-4-1) After executing the interrupt permission process of (b-3), a process of determining whether or not the timer value has reached a predetermined value;
(B-4-2) When the timer value is less than the predetermined value, a process of returning to the process of (b-1);
(B-4-3) When the timer value is equal to or greater than the predetermined value, the game control process and the game information acquisition process are included.
In the process (b-5), when the timer value is equal to or greater than the predetermined value in the process (b-4-3), the power reduction information setting process (a) is executed. 2. The gaming machine according to claim 1, wherein the game control process and the game information acquisition process are executed after returning from the power supply lowering information setting process of (a).

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