JP6392712B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine or a slot gaming machine, and more particularly to command transmission processing of a main control means.

JP 2007-330539 A

For pachinko machines, slot machines, etc., the main control means for overall control of game operations and the output of control commands related to game operations, and the necessary processing operations are performed according to the commands from the main control means Peripheral control means are provided.
For example, Patent Document 1 discloses a configuration in which commands are transmitted from a main control board to a payout control board that performs payout control of game balls and a sub control board that performs effect control.

  In such a gaming machine, it is important to reduce the processing load of the main control means. Therefore, the present invention aims to improve the efficiency of transmission of control commands and reduce the processing load.

The gaming machine according to the present invention performs overall control of gaming operations, and also performs a control operation based on a main control means for outputting a control command related to the gaming operation, and a control command output from the main control means. Ru and a sub-control unit.

The main control means includes a main control CPU, and performs a series of processes having a generation opportunity of a plurality of control commands as a scheduled process executed at a predetermined interval, and the main control means performs a single scheduled process. When the maximum value of the number of control commands to be transmitted is x and the number of bits of the control command is y, the main control means includes a transmission data storage unit having a capacity of at least (x × y) bits and the transmission Serial transmission means for serially transmitting and outputting transmission data for each transmission unit transferred from the data storage unit is provided, and one control command is constituted by the amount of data for which command transmission is completed by transmission of a plurality of transmission units The main control means generates a control command each time a command transmission generation condition is met during the scheduled processing, and generates the generated control command. It is confirmed whether transmission from the serial transmission means is possible for each transmission unit. If transmission is possible, the transmission command is written in the transmission data storage unit, and the control commands written in the transmission data storage unit are sequentially The data is transferred to the transmitting means and serially transmitted to the sub-control means.

By providing a transmission data storage unit having a capacity of (x × y) bits or more in the main control means, it is possible to buffer all control commands to be transmitted in one scheduled process in the serial transmission circuit without waiting time. .

  According to the present invention, efficient command transmission processing can be realized, and the processing load on the main control means can be reduced.

1 is a perspective view of a pachinko gaming machine according to an embodiment of the present invention. It is a front view of the board surface of the pachinko game machine of an embodiment. It is a block diagram of a control configuration of the pachinko gaming machine of the embodiment. It is a block diagram of the internal structure of the main control part of an embodiment. It is a block diagram of the serial communication circuit of an embodiment. It is explanatory drawing of the transmission / reception data in the serial communication of embodiment. It is a flowchart of the main control main process of an embodiment. It is a flowchart of the main control timer interruption process of an embodiment. It is a flowchart of the input management process of an embodiment. It is a flowchart of prize ball management processing of an embodiment. It is a flowchart of the command transmission process of an embodiment. It is a flowchart of the process at the time of the command transmission opportunity generation | occurrence | production of embodiment. It is a flowchart of the command transmission process of an embodiment. It is a flowchart of other command transmission processing of an embodiment.

Hereinafter, as an embodiment of the gaming machine according to the present invention, a pachinko gaming machine will be taken as an example and described in the following order.
<1. Pachinko machine structure>
<2. Control configuration of pachinko machine>
<3. Configuration of main control unit>
<4. Configuration of serial communication circuit>
<5. Control processing of embodiment>
[5-1: Main processing]
[5-2: Timer interrupt processing]
[5-3: Processing related to command transmission]
<6. Summary and Modification>

<1. Pachinko machine structure>

First, with reference to FIG. 1 and FIG. 2, the structure of the pachinko gaming machine 1 as an embodiment of the present invention will be schematically described.
FIG. 1 is a front perspective view showing the appearance of a pachinko gaming machine 1 according to the embodiment, and FIG. 2 is a front view of the game board.
The pachinko gaming machine 1 shown in FIGS. 1 and 2 mainly includes a “frame portion” and a “game board portion”.
The “frame portion” includes a front frame 2, an outer frame 4, a glass door 5, and an operation panel 7 described below. The “game board part” comprises the game board 3 of FIG. In the following description, “frame part” and “frame side” are a general term for the front frame 2, the outer frame 4, the glass door 5, and the operation panel 7. “Board” and “board side” indicate the game board 3.

As shown in FIG. 1, the pachinko gaming machine 1 has a frame-shaped front frame 2 attached to the front surface of a wooden outer frame 4 so as to be opened and closed. Although not shown, a game board storage frame is formed on the rear surface of the front frame 2, and the game board 3 shown in FIG. 2 is mounted in the game board storage frame. As a result, the gaming area 3a formed on the surface of the gaming board 3 faces the front side of the pachinko gaming machine 1 in FIG. 1 from the opening 2a of the front frame 2.
A glass door 5 supporting transparent glass is provided on the front side of the game area 3a, and the game area 3a is exposed to the player on the front side through the transparent glass.

The glass door 5 is attached to the front frame 2 by a shaft support mechanism 6 so as to be opened and closed. Then, by operating a door lock release key cylinder (not shown) provided at a predetermined position of the glass door 5, the glass door 5 is unlocked from the front frame 2, and the glass door 5 can be opened to the front side. ing. Further, the lock state of the front frame 2 with respect to the outer frame 4 can be released by operating the door lock releasing key cylinder.
On the front side of the glass door 5, decorative lamps 20w are provided in various places as light emitting means on the frame side. The decorative lamp 20w performs, for example, a light emitting operation for effects, a light emitting operation for error notification, and a light emitting operation according to an operation state as a light emitting operation by an LED.

An operation panel 7 is provided below the glass door 5. The operation panel 7 can also be opened and closed with respect to the front frame 2 by a shaft support mechanism (not shown).
The operation panel 7 is provided with an upper tray unit 8, a lower tray unit 9, and a firing operation handle 10.

The upper tray unit 8 is formed with an upper tray 8a for storing game balls to be used as bullets. The lower tray unit 9 is formed with a lower tray 9a that stores game balls that cannot be stored in the upper tray 8a.
The upper tray unit 8 is provided with a ball removal button 16 for removing the game balls stored in the upper tray 8a toward the lower tray 9a. The lower tray unit 9 is provided with a ball release lever 17 for pulling out the game balls stored in the lower tray 9a to the lower side of the pachinko gaming machine 1.
The upper tray unit 8 has a ball lending button 14 for requesting a game ball lending device (not shown) and a card for requesting return of a valuable medium inserted in the game ball lending device. A return button 15 is provided.
Further, the upper tray unit 8 is provided with a patrol switch 11, an effect button 12, and a cross key 13. The patrol light switch 11 and the effect button 12 are push buttons that can be operated by turning on the built-in lamp during a predetermined input reception period and can be changed when the built-in lamp is turned on. Further, the cross key 13 is an operator for the player to perform an operation for an operation or an effect setting according to the effect situation.

The firing operation handle 10 is provided on the right end side of the operation panel 7 and is an operator for operating the launching device 56 shown in FIG.
In addition, speakers 25 that sound production effects are provided on both sides of the upper portion of the front frame 2 and in the vicinity of the firing operation handle 10.

  Next, the configuration of the game board 3 will be described with reference to FIG. The game board 3 is mainly composed of a substantially square wooden plywood or resin board. The game board 3 is provided with a ball guide rail 31 for guiding the launched game ball in a ring shape as a board surface partition member, and a substantially circular area surrounded by the ball guide rail 31 is a game area 3a. It has become.

A main liquid crystal display device 32M (LCD: Liquid Crystal Display) is provided at a substantially central portion of the game area 3a, and a sub liquid crystal display device 32S is provided on the right side of the main liquid crystal display device 32M.
In the main liquid crystal display device 32M, under the control of an effect control unit 51, which will be described later, for example, three decorative symbols of left, middle, and right are displayed on the background image. Various effect images such as a normal effect, a reach effect, and a super reach effect are also displayed. Similarly, the sub liquid crystal display device 32S performs display according to various effects.

A center decoration 35C is provided in the game area 3a so as to surround the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
The center decoration 35C not only exhibits a decorative effect due to its design, but also has an action of protecting the display surfaces of the main liquid crystal display device 32M and the sub liquid crystal display device 32S from surrounding game balls. Furthermore, the center decoration 35C also functions as a member that enables the right and left shots of the flow path of the game ball depending on the strength or stroke length of the game ball. That is, the flow path of the game ball launched to the upper part of the game area 3a via the ball guide rail 31 flows down either the left game area 3b or the right game area 3c divided by the center decoration 35C. In the case of so-called left hit, the game ball flows down the left game area 3b, and in the case of right hit, the game ball flows down the right game area 3c.

In addition, a lower left decoration 35L is provided below the left game area 3b to exhibit a decorative effect and define a range as the left game area 3b.
Similarly, a lower right decoration 35R is provided below the right game area 3c, which exhibits a decorative effect and defines a range as the left game area 3b.
In the game area 3a (the left game area 3b and the right game area 3c), nails 49 and windmills 47 are provided at various places to form various flow paths for game balls.
Further, a center stage 35S is provided below the main liquid crystal display device 32M, which exhibits a decorative effect and functions as a play area for a game ball.
Although not shown in the drawing, the center ornament 35C is provided with a movable body accessory that provides a visual effect in an appropriate place.

In the vicinity of the upper right edge of the game area 3a, a symbol display unit 33 is provided by a dot display formed by arranging a plurality of LEDs.
In the symbol display unit 33, a first special symbol display unit, a second special symbol display unit, and a normal symbol display unit are formed by a predetermined dot area, and the first special symbol, the second special symbol, and the normal symbol are displayed. Each variation display operation (variation display operation for setting variation start and variation stop as one set) is performed.
The main liquid crystal display device 32M described above variably displays the decorative symbol by the image in time synchronization with the variable display of the first and second special symbols by the symbol display unit 33.

A winning device having an upper start port 41 (first special symbol start port) is provided below the center ornament 35C, and a lower start port 42a (second special symbol start port) is further provided below that. A variable winning device 42 is provided.
Inside the upper start opening 41 and the lower start opening 42a, detection sensors (upper start opening sensor 71 and lower start opening sensor 72 shown in FIG. 3) for detecting the passage of the game ball are formed.

  The upper starting port 41 is a winning port related to the starting condition of the variable display operation of the first special symbol in the symbol display unit 33, and does not have a starting port opening / closing means (means for opening or expanding the starting port). It is a type winning device.

The normal variation winning device 42 having the lower starting port 42a is configured as a winning rate variation type winning device capable of changing the winning rate of the game ball at the starting port by the starting port opening / closing means. That is, it is a so-called electric tulip-type winning device including a pair of left and right movable wing pieces (movable members) 42b that can open or enlarge the lower start opening 42a.
The lower start opening 42 a of the normal variation winning device 42 is a winning opening relating to the start condition of the variable display operation of the second special symbol in the symbol display unit 33. The winning rate of the lower start port 42a varies depending on the operating state of the movable blade piece 42b. That is, the winning is easy when the movable wing piece 42b is open, and the winning is difficult or impossible when the movable wing piece 42b is closed.

In addition, a plurality of general winning ports 43 are provided on the left and right sides of the normal variation winning device 42. A detection sensor (general winning opening sensor 74 shown in FIG. 3) for detecting the passage of the game ball is formed inside each general winning opening 42.
In addition, a normal symbol start port 44 including a gate (specific passage region) through which a game ball can pass is provided on the lower side of the right game region 3c. The normal symbol starting port 44 is a winning port related to a normal symbol variation display operation in the symbol display unit 33, and a sensor (gate sensor 73 shown in FIG. 3) for detecting a passing game ball is formed in the normal symbol starting port 44. Has been.

A first special variable winning device 45 (special electric accessory) is provided along the flow path from the normal symbol starting port 44 to the normal variable winning device 42 in the right game area 3c.
The first special variable winning device 45 is configured to close / open the first big winning opening 45a by a retractable opening door 45b. In addition, a sensor for detecting the passage of the game ball to the first big prize opening 45a (the first big prize port sensor 75 in FIG. 3) is formed inside.
The lower right decoration 35R bulges from the surface of the game board 3 around the first grand prize winning opening 45a, and the upper side of the bulged portion and the upper surface of the open door 45b guide downstream of the right flow path 3c. Forming part. Therefore, when the opening door 45b is drawn into the board, the game ball that has reached the downstream guide portion easily enters the first big winning opening 45a.

A second special variable winning device 46 (special electric accessory) is provided below the normal variable winning device 42. The second special variable winning device 46 is configured to close / open the second large winning port 46a on the inside by an open door 46b that is pivotally supported at the lower part and can be opened and closed. In addition, a sensor (second big prize port sensor 76 in FIG. 3) for detecting the passage of the game ball to the second big prize port 46a is formed therein.
The second big prize opening 46a is opened by opening the open door 46b. In this state, the game balls that have flowed down the left game area 3b or the right game area 3c will enter the second big prize opening 50 with a high probability.

As described above, the upper starting port 41, the lower starting port 42a, the normal symbol starting port 44, the first large winning port 45a, the second large winning port 46a, and the general winning port 43 are formed in the game area of the board as winning ports. Has been.
In the pachinko gaming machine 1 according to the present embodiment, when a winning is made to a winning port other than the normal symbol starting port 44 among these winning ports, per winning ball set for each winning port. The number of prize balls is paid out from the game ball payout device 55 (see FIG. 3).
For example, the upper start opening 41 and the lower start opening 42a are set to three, the first big winning opening 45a and the second big winning opening 46a are set to 13, the general winning opening 43 is set to 10 and the like.
Note that the game balls that have not won the prize holes are discharged from the game area 3 a through the out port 48.
Here, “winning” means that the winning opening takes the game ball inside, or the game ball passes through the gate. Actually, when a game ball is detected by a sensor (each winning detection switch) formed for each winning opening, it is treated that a “winning” has occurred in that winning opening. The game ball related to the winning is also referred to as “winning ball”.

On the board as described above, the center ornament 35C, the lower left ornament 35L, the lower right ornament 35R, the center stage 35S, the first special variable winning device 45, the second special variable winning device 46, and a movable object not shown in the figure. Although not shown in detail, decorative lamps 20b are provided as light emitting means on the panel side at various places.
The decorative lamp 20b performs, for example, a light emitting operation for production, a light emitting operation for error notification, and a light emitting operation according to an operation state as a light emitting operation by an LED.

<2. Control configuration of pachinko machine>

Next, the configuration of the control system of the pachinko gaming machine 1 according to the present embodiment will be described. FIG. 3 is a schematic block diagram of the internal configuration of the pachinko gaming machine 1.
The pachinko gaming machine 1 according to the present embodiment mainly has a main control board 50, an effect control board 51, a liquid crystal control board 52, a payout control board 53, a launch control board 54, and a power supply board 58 as the boards forming the control configuration. Is provided.

The main control board 50 is equipped with a microcomputer or the like, and performs overall control related to the entire game operation of the pachinko gaming machine 1. In the following description, a component of the main control board 50 including a microcomputer mounted on the main control board 50 is referred to as a “main control unit 50”.
The effect control board 51 is equipped with a microcomputer or the like, and receives an effect control command from the main control unit 50 and performs control for executing various effect operations using image display, light emission, and sound output. Hereinafter, the structure of the effect control board 51 including the microcomputer mounted on the effect control board 51 is referred to as an “effect control unit 51”.

The liquid crystal control board 52 is equipped with a microcomputer, a video processor, etc., and receives display control commands from the effect control unit 51 to control display operations by the main liquid crystal display device 32M and the sub liquid crystal display device 32S.
Note that the main liquid crystal control substrate and the sub liquid crystal control substrate may be provided independently as the liquid crystal control substrate for controlling the display operation by the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The payout control board 53 is equipped with a microcomputer or the like and receives payout control commands from the main control unit 50 and performs payout control of prize balls by the game ball payout device 55. Hereinafter, a component of the payout control board 53 including a microcomputer or the like mounted on the payout control board 51 is referred to as a “payout control unit 53”.
In the present embodiment, the payout control unit 53 controls the operation of actually paying out the prize balls by the game ball payout device 55, but the payout control unit 53 performs the actual prize ball payout control. Instead, a process of counting the number of balls held by the player may be performed. For example, in the case of a so-called enclosed game machine that does not pay out game balls, at the end of the game, the ball data is recorded on a card or the like for settlement. A ball counting process necessary for this is performed.

The launch control board 54 controls the launch operation of the game ball by the launch device 56 provided in the pachinko gaming machine 1.
The power supply board 58 performs AC / DC conversion and further DC / DC conversion from an external power supply (for example, AC 24 V), and supplies an operation power supply voltage Vcc to each unit. The power supply path is not shown.

First, the main controller 50 and its peripheral circuits will be described.
The main control unit 50 includes a microprocessor incorporating a CPU 100 (hereinafter referred to as “main control CPU 100”), a ROM 101 (hereinafter referred to as “main control ROM 101”), and a RAM 102 (hereinafter referred to as “main control RAM 102”). A microcomputer is configured.
The main control CPU 100 executes various calculations and control processes according to the progress of the game based on the control program.
The main control ROM 101 stores a game operation control program by the main control CPU 100 and various data necessary for game operation control.
The main control RAM 102 is used as a work area used by the main control CPU 100 for various arithmetic processing, and as a buffer area for various input / output data and processing data.
As will be described later with reference to FIG. 4, the main control unit 50 includes an interface circuit (external bus I / F 109, etc.) with each unit, a random number circuit 104 that generates random numbers, and a CTC (Counter Timer Circuit) for various time counts. Circuit 106), an interrupt controller 105 for giving an interrupt signal to the main control CPU 100, and the like.
Further, the main control RAM 102 holds data even after the main control unit 50 is turned off by supplying power separately to a backup power supply terminal (not shown) formed in the main control unit 50. Yes.

As described above, the main control unit 50 receives each winning means in the game area on the board (upper start port 41, lower start port 42a, normal symbol start port 44, first big win port 45a, second big win port 46a, general It is configured to receive a detection signal of a sensor provided at the winning opening 43).
That is, the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76 are sent to the main control unit 50. Supplied.
These sensors (71 to 76) are configured by detection switches that detect a game ball that has entered, but specifically, contactless switches such as photoswitches and proximity switches, and contact points such as microswitches. It can consist of switches.

  The main control unit 50 receives the detection signals of the upper start opening sensor 71, the lower start opening sensor 72, the gate sensor 73, the general winning opening sensor 74, the first large winning opening sensor 75, and the second large winning opening sensor 76. Depending on the process. For example, lottery processing, symbol variation control, prize ball payout control, effect control command transmission control, external data transmission processing, and the like are performed.

The main control unit 50 is connected to a normal electric accessory solenoid 77 that opens and closes the movable wing piece 42b of the lower start port 42, and the main control unit 50 transmits a control signal according to the progress of the game to perform normal electric operation. The driving operation of the accessory solenoid 77 is executed, and the opening / closing operation of the movable blade piece 42b is executed.
Further, the main control unit 50 has a first grand prize opening solenoid 78 that opens and closes the opening door 45b of the first big prize opening 45 and a second big prize that opens and closes the opening door 46b of the second big prize opening 46. A mouth solenoid 79 is connected. The main control unit 50 drives and controls the first big prize opening solenoid 78 or the second big prize opening solenoid 79 in accordance with the so-called jackpot situation, and opens the first big prize opening 45 or the second big prize opening 46. Is executed.

  In addition, a symbol display unit 33 is connected to the main control unit 50, and a control signal is transmitted to the symbol display unit 33 to execute various symbol displays (LED OFF / ON / flashing). Thereby, the display operation in the 1st special symbol display part 80 in the symbol display part 33, the 2nd special symbol display part 81, and the normal symbol display part 82 is performed.

  The main control unit 50 is connected to a frame external terminal board 57. The main control unit 50 can transmit information related to game progress to a hall computer (not shown) via the frame external terminal board 57. The information related to the game progress is information such as jackpot winning information, prize ball number information, symbol variation display execution number information, and the like. The hall computer is a management computer that manages the pachinko gaming machine 1 in the pachinko hall in an integrated manner, and is installed outside the pachinko gaming machine 1.

Further, a payout control unit (payout control board) 53 is connected to the main control unit 50. The payout control unit 53 includes a microprocessor, a ROM, and a RAM that incorporate a CPU (not shown) and constitutes a microcomputer.
The payout control unit 53 is connected to a launch control board 54 that controls the launch device 56 and a game ball payout device 55 that pays out game balls.
The main control unit 50 transmits a payout control command (payout control command for designating the number of prize balls) to the payout control unit 53. The payout control unit 53 controls the game ball payout device 55 in accordance with the control command to cause the game ball to be paid out.
Also, the payout control unit 53 can transmit information (payout state signal) regarding the payout operation state to the main control unit 50. The main controller 50 monitors whether or not the game ball payout device 55 is functioning normally based on this payout state signal. Specifically, it is monitored whether or not a problem such as clogged balls or insufficient payout of prize balls has occurred during the prize ball payout operation.

  The main control unit 50 transmits an effect control command including information related to the special symbol variation display to the effect control unit 51. The transmission of the effect control command from the main control unit 50 to the effect control unit 51 is executed by one-way communication. This is to prevent an unauthorized signal due to an illegal act from the outside from being input to the main control unit 50 via the effect control unit 51.

Next, the production control unit 51 and its peripheral circuits will be described.
The effect control unit 51 includes a microprocessor incorporating a CPU 200 (hereinafter referred to as “effect control CPU 200”), a ROM 201 (hereinafter referred to as “effect control ROM 201”), and a RAM 202 (hereinafter referred to as “effect control RAM 202”). A microcomputer is configured.
The effect control CPU 200 performs arithmetic processing for various effect operations and controls each effect means based on the effect control program and the effect control command received from the main control unit 50. In the case of the pachinko gaming machine 1 according to the present embodiment, the effect means is the main liquid crystal display device 32M, the sub liquid crystal display device 32S, the decorative lamps 20w and 20b, the speaker 59, and a movable object that is not shown.
The effect control ROM 201 stores a control program of the effect operation by the effect control CPU 200 and various data necessary for effect operation control.
The effect control RAM 202 is used as a work area used by the effect control CPU 200 for various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like.
Although illustration is omitted, the production control unit 51 gives an interrupt signal to the interface circuit with each unit, a random number generation circuit for generating random numbers for lottery for production, CTC for various time counting, and the production control CPU 200. It also has an interrupt controller circuit.
The main roles of the effect control unit 51 are to receive an effect control command from the main control unit 50, to select an effect based on the effect control command, and to provide an effect control command to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. , Output sound control by the speaker 25, light emission control of the decorative lamps 20w and 20b (LED), operation control of the movable body accessory, and the like.

  The effect control unit 51 transmits an effect control command to the main liquid crystal display device 32M and the sub liquid crystal display device 32S, and the effect control command is sent to the liquid crystal control substrate 52 via the liquid crystal interface substrate 66.

The liquid crystal control board 52 performs display control of the main liquid crystal display device 32M and the sub liquid crystal display device 32S. Although not shown, the liquid crystal control board 52 includes a VDP (Video Display Processor), an image ROM, a VRAM (Video RAM), a liquid crystal control CPU, a liquid crystal control ROM, and a liquid crystal control RAM.
The VDP performs overall control of video output processing such as image development processing and image drawing.
The image ROM stores image data (effect image data) on which the VDP performs image expansion processing.
The VRAM is an image memory area that temporarily stores image data developed by the VDP.
The liquid crystal control CPU outputs control data necessary for the VDP to perform display control.
The liquid crystal control ROM stores a program describing a display control operation procedure of the liquid crystal control CPU and various data necessary for the display control.
The liquid crystal control RAM functions as a work area and a buffer memory.

  With these configurations, the liquid crystal control board 52 generates various image data based on the effect control command from the effect control board 51, and outputs it to the main liquid crystal display device 32M and the sub liquid crystal display device 32S. As a result, various effect images are displayed on the main liquid crystal display device 32M and the sub liquid crystal display device 32S.

The production control unit 51 controls the light production and the sound production. For this reason, a frame driver unit 61, a panel driver unit 62, and a sound source IC (Integrated Circuit) 59 are connected to the effect control unit 51.
The frame driver unit 61 performs light emission driving for the LEDs of the decorative lamp unit 63 on the frame side. Note that the decorative lamp portion 63 is a general view of the decorative lamp 20w provided on the frame side as shown in FIG.
The panel driver unit 62 performs light emission driving for the LEDs of the decorative lamp unit 64 on the panel side. In addition, the decorative lamp part 64 is a general view of the decorative lamp 20b provided on the panel side as shown in FIG.
The panel driver unit 62 also drives the motor of the movable body accessory motor unit 65. The movable body accessory motor 65 generally represents one or more motors that drive one or more movable body accessories formed on the board side. For example, a stepping motor is used as the motor of the movable body accessory motor unit 65.

  In this example, the panel driver unit 62 also drives the motor of the movable body accessory motor unit 65 that drives the movable body accessory formed on the panel side. The driver unit that drives the light emission and the driver unit that drives the motor of the movable body accessory motor unit 65 may be provided separately.

As the movable body accessory motor unit 65, for example, a plurality of motors (for example, stepping motors) are provided corresponding to the plurality of accessories.
Each motor has a specified origin position. The origin position is, for example, a position where an accessory does not normally appear on the board surface of FIG.
Each motor is provided with an origin switch 68 so that it can be confirmed on the side of the effect control board 51 whether or not the motor is at the origin position. For example, a photo interrupter is used. The information of the origin switch 68 is configured to be detected by the effect control CPU 200.

Further, the effect control unit 51 controls the sound source IC 59 so that the speaker 25 outputs a desired sound. A sound data ROM 69 is connected to the sound source IC 59, and the sound source IC 59 acquires necessary sound data (sound data of a phrase to be reproduced) from the sound data ROM 69 and outputs a sound signal.
The sound source IC 59 mixes phrases of a plurality of channels (a sound channel aCH described later) to obtain a predetermined number (number of channels) of audio signals. As shown in FIG. 1, in the case of this example, since a plurality of speakers 25 are provided, the number of output channels of the sound source IC 59 can be, for example, two channels of Lch and Rch (stereo output). Through the above mixing, phrases of a plurality of channels instructed to be reproduced from the effect control unit 51 can be reproduced simultaneously.
The sound source IC 59 performs sound control for the phrase instructed as a control target in accordance with the instruction from the effect control unit 51. Specifically, the production control unit 51 gives information related to an instruction to give a sound effect such as a volume change instruction or fade-in reproduction / fade-out reproduction to the sound source IC 59, and the sound source IC 59 is designated as a control target according to the information. Controls playback of the phrase that is played.

The output audio signal from the sound source IC 59 is amplified by the amplifier unit 67 and then given to the speaker 25.
In FIG. 3, for convenience of illustration, the number of output channels of the sound source IC 59 is one. However, in reality, the amplifier unit 67 and the speaker 25 are provided with output channels corresponding to, for example, Lch and Rch, respectively, and stereo sound Playback is possible.

  In the above description, the sound source IC 59 is provided separately from the effect control board 51. However, the sound source IC 59 may be provided integrally on the same board as the effect control board 51.

The effect control unit 51 is connected to an operation unit 60 that can be operated by the player, and can receive an operation detection signal from the operation unit 60. The operation unit 60 is the patrol switch 11, the effect button 12, the cross key 13, and the operation detection mechanism described above with reference to FIG.
The effect control unit 51 can perform various effect controls according to the operation detection signal from the operation unit 60.

  The production control unit 51 determines a production pattern by lottery or uniquely from a plurality of types of production patterns prepared in advance based on the production control command sent from the main control unit 50, and performs various productions at necessary timing. Control means. Thereby, the display of the effect image by the main / sub liquid crystal display devices 32M and 32S corresponding to the effect pattern, the sound reproduction from the speaker 25, the lighting and blinking driving of the LEDs in the decoration lamp parts 63 and 64 (decoration lamps 20w and 20b) The operation of the movable body accessory by the motor of the movable body accessory motor unit 65 is realized, and various effect patterns are developed in time series. Thereby, the “production scenario” is realized.

The effect control command defines a function by a 2-byte structure consisting of a 1-byte length mode (MODE) and a 1-byte length event (EVENT).
In order to distinguish between MODE and EVENT, MODE Bit 7 is ON, and EVENT Bit 7 is OFF.

<3. Configuration of main control unit>

FIG. 4 is a block diagram showing an internal configuration of the main control unit 50.
The main control unit 50 includes an internal bus 103 to which the main control CPU 100, the main control ROM 101 and the main control RAM 102 are connected, a random number circuit 104 connected to the internal bus 103, an interrupt controller 105, a timer circuit 106, Each unit includes a counter circuit 107, a reset controller 108, an external bus I / F (interface) 109, a clock circuit 110, a parallel input circuit 111, a serial communication circuit 112, an address decoding circuit 113, and an arithmetic circuit 114.
In the case of this example, each part which comprises these main control parts 50 is mounted on the same board | substrate. That is, the microcomputer as the main control unit 50 is a so-called one-chip microcomputer.

The random number circuit 104 is a circuit that generates a random number value according to a predetermined rule. In this example, the random number circuit 104 can generate two systems (two channels) of 16-bit pseudorandom numbers. The random number circuit 104 can selectively set a random value start value and an update method.
In the case of this example, the random number (hardware random number) of the random number circuit 104 is used for determination of big hit / small hit / loss. Note that other random numbers such as a special symbol random number and a normal symbol random number described later are software random numbers updated by a program.

The interrupt controller 105 receives an external interrupt request made via a predetermined signal input terminal DTi of the parallel input circuit 111, a circuit in the main control unit 50, particularly a serial communication circuit 112, a random number circuit 104, a timer circuit. 106 is a circuit for controlling an interrupt request from 106.
The interrupt controller 105 can control two types of interrupts, a non-maskable interrupt and a maskable interrupt. The non-maskable interrupt is an interrupt that should be unconditionally accepted even when the main control CPU 100 is in an interrupt disabled state, and a predetermined signal is input to a predetermined signal input terminal DTi among the signal input terminals DTi of the parallel input circuit 111. Occurs.
The maskable interrupt is an interrupt that can permit / prohibit acceptance of an interrupt request by a setting instruction of the main control CPU 100. For maskable interrupts, it is possible to set priorities for each type in advance, and it is possible to mask low priority interrupts.
There are two types of maskable interrupts: external maskable interrupts and internal maskable interrupts. The external maskable interrupt is an interrupt generated when a predetermined signal is input to a predetermined signal input terminal DTi among the signal input terminals DTi of the parallel input circuit 111.
An internal maskable interrupt is an interrupt generated due to the following interrupt generation factors. That is, the timer circuit 106 times out, the serial communication circuit 112 receives data, the serial communication circuit 112 transmits data, and the random number circuit 104 fetches random numbers.

  The timer circuit 106 is a programmable timer, and a real-time interrupt request and time measurement can be performed by setting a user program. In this example, the timer circuit 106 has three channels of 8-bit timers.

  The counter circuit 107 is a programmable counter and can measure time by setting a user program. In this example, the counter circuit 107 has four channels of 8-bit counters.

The reset controller 108 is a circuit that controls various resets and internal resets.
Here, there are two types of resetting of the pachinko gaming machine 1: system reset and user reset. The system reset is a reset in which all the internal circuits of the main control unit 50 including the main control CPU 100 are initialized, and is executed in response to the system reset signal SRST being input to the reset terminal TRS.
Here, with regard to the system reset, it is possible to select whether to shift to the security mode or the PROM mode after the initialization is executed. In the security mode, a security check is performed after the initialization is executed, and if the result is OK, the mode is shifted to the user mode (mode in which the user program is executed from the reset address), and if the result is NG, the main control CPU 100 is stopped. It is an operation mode. The PROM mode is an operation mode for reading / writing the main control ROM 101. Whether to shift to the security mode / PROM mode after initialization can be selected according to the level of the program signal PRG input to the setting terminal TPR (for example, LOW level / High level).
The user reset is a reset in which only a predetermined circuit in the main control unit 50 is selectively initialized and shifts to the user mode after the initialization. The circuits initialized by the user reset are, for example, the main control CPU 100, the interrupt controller 105, the timer circuit 106, the counter circuit 107, the parallel input circuit 111, the serial communication circuit 112, and the arithmetic circuit 114. The user reset is generated in response to a time-out signal Sto described later by a WDT (watchdog timer) circuit 120 provided in the reset controller 108.

The external bus I / F 109 is a bus interface that reinforces the address bus, the data bus, the direction control of each control signal, and the driving capability. Data communication with predetermined external devices such as the effect control unit 51, the liquid crystal I / F board 66, and the sound source IC 59 shown in FIG. 1 is performed via the external bus I / F 109.
The external bus I / F 109 can transmit / receive a plurality of bits (8 bits in this example) via the data input / output terminal DT and a plurality of bits (16 bits in this example) via the address data output terminal. Bit address data can be output. Further, the external bus I / F 109 can output signals accompanying data exchange such as various request signals and signals indicating cycles via a plurality of signal output terminals STo.

The clock circuit 110 receives a first external clock and a second external clock from the outside, and supplies a system clock to internal circuits of the main control unit 50 including the main control CPU 100 based on the first external clock. At the same time, the second external clock is supplied to the random number circuit 104. The clock circuit 110 can supply a system clock to an external device via a clock terminal (not shown).
In the case of this example, the clock circuit 110 divides a clock input from the outside by two to generate a system clock.

The parallel input circuit 111 is a parallel input port dedicated to input, and a plurality of systems of signals can be input in parallel from an external device via a plurality of signal input terminals DTi. The parallel input circuit 111 can send a parallel input signal to the internal bus 103. Further, the parallel input circuit 111 can supply a signal input to a predetermined signal input terminal DTi among the signal input terminals DTi to the random number circuit 104.
The parallel input circuit 111 interrupts the interrupt request signal for the non-maskable interrupt or the external maskable interrupt described above in response to the input of the predetermined signal to the predetermined signal input terminal DTi among the signal input terminals DTi. Output to the embedded controller 105.

The serial communication circuit 112 transmits / receives data to / from an external device by serial data communication. In the case of this example, data transmission and reception of command signals and the like between the main control CPU 100 and the payout control board 53 and the effect control board 51 are performed via the serial communication circuit 112.
The serial communication circuit 112 transmits transmission data to the external device via the data transmission terminal TX. On the other hand, data reception can be performed using one predetermined signal input terminal DTi among the signal input terminals DTi of the parallel input circuit 111.
Further, the serial communication circuit 112 outputs an interrupt request signal corresponding to the data transmission to the interrupt controller 105.
A detailed configuration example in the serial communication circuit 112 will be described later.
Here, the case where only one data transmission terminal TX of the serial communication circuit 112 is provided, that is, the case where the transmission system is only one system is illustrated, but the transmission system by the serial communication circuit 112 is two or more systems. You can also.
In addition, an example has been given in which the serial communication circuit 112 uses the predetermined signal input terminal DTi of the parallel input circuit 111 to receive data, but a terminal for the serial communication circuit 112 to receive data may be provided separately. it can.

The address decoding circuit 113 is an address decoding circuit for an external device of the user program. The address decoding circuit 113 of this example is compatible with both the memory mapped I / O method and the I / O mapped I / O method, and decodes the address data included in the read / write command to the main control RAM 102. A chip select signal CS of the external device can be generated and output to the external device. The generated chip select signal CS can be sent to an external device via a chip select signal output terminal (not shown). In this example, the chip select signal CS can be output via the data communication terminal TX of the serial communication circuit 112 by setting.
In the pachinko gaming machine 1 of this example, it is possible to perform selection without using the chip select signal CS by setting.

The arithmetic circuit 114 includes a multiplication circuit and a division circuit, and can perform multiplication and division. In this example, the multiplication circuit is an 8-bit × 8-bit multiplication circuit, and the division circuit is a 16-bit ÷ 16-bit division circuit.

<4. Configuration of serial communication circuit>

FIG. 5 is a block diagram showing the internal configuration of the serial communication circuit 112.
The serial communication circuit 112 includes a transmission / reception unit 150, a data register 151, a baud rate register 152, a baud rate generation circuit 153, a command register 154, a transmission trigger level setting register 155, a status register 156, a FIFO status register 157, an interrupt control register 158, a communication A setting register 159 is provided.

  The data register 151 temporarily stores transmission / reception data. In other words, the control command and other transmission data are set by the main control CPU 100 via the internal bus 103, and the reception data received by the serial communication circuit 112 is temporarily stored during transfer via the internal bus 103. It is a register.

The transmission / reception unit 150 performs serial data transmission from the data transmission terminal TX and serial data reception from the data reception terminal RX (a predetermined signal input terminal DTi of the parallel input circuit 111 in the example of FIG. 4). Therefore, the transmission / reception unit 150 includes a transmission shift register 160, a transmission data register 161, a parity generation unit 162, an interrupt control circuit 163, a reception data register 164, a parity check unit 165, and a reception shift register 166.
First, regarding the transmission system, the transmission data register 161 is configured as a 64-byte FIFO memory, for example. For the sake of explanation, the transmission data register 161 is also expressed as “transmission FIFO 161”.
Transmission data such as a control command set in the data register 151 by the main control CPU 100 is written in the transmission FIFO 161. For example, if a control command is transmitted in a 2-byte data format, a maximum of 32 control commands can be temporarily stored in the 64-byte transmission FIFO 161.
One or more pieces of transmission data written in the transmission FIFO 161 are sequentially transferred to the transmission shift register 160 and serially transmitted and output from the transmission shift register 160.
Note that by providing the parity generation unit 162, it is possible to add a parity bit to the transmission data.

As a reception system, the reception data register 164 is configured as, for example, an 8-byte FIFO memory. For the sake of explanation, the reception data register 164 is also expressed as “reception FIFO 164”.
The reception data by serial communication is taken in by the reception shift register 166 and transferred to the reception FIFO 164.
When the received data includes a parity bit, the parity check unit 165 performs a data error check on the received data written in the reception FIFO 164.
Since the reception FIFO 164 is 8 bytes, it is possible to continuously capture reception data for 8 bytes.
The reception data temporarily stored in the reception FIFO 164 is transferred to the data register 151 and then read out by the main control CPU 100.

  The interrupt control circuit 163 controls interrupt processing related to transmission / reception data. Therefore, flag writing to the status register 156 and the FIFO status register 157 and transmission of the data transmission interrupt signal TX0I and the data reception interrupt signal RX0I to the interrupt controller 105 are performed.

The communication data format transmitted / received by the transmission / reception unit 150 as described above is, for example, as shown in FIGS.
FIG. 6A is an example in which one frame is constituted by a start bit STA, 8-bit transmission / reception data of bits b0 to b7, and a stop bit STP.
The idle line before transmission / reception is at a high level (logic “1”). The start bit STA is at a low level (logic “0”) to indicate the start of one frame. In 8-bit transmission / reception data, transmission / reception is performed in order from the least significant bit b0 (LSB). A high level (logic “1”) stop bit STP indicates the completion of one frame.
FIG. 6B shows an example in which a parity bit PR is added. The serial communication circuit 112 can select use / unuse of parity. When used, a parity bit PR is added by the parity generation unit 162 to 8-bit (1 byte) transmission data during transmission. At the time of reception, a checksum process is performed by the parity check unit 165 on the received 1-byte received data.

Returning to FIG. 5, the baud rate register 152 is used for baud rate control. Baud rate setting data is written into the baud rate register 152 by the main control CPU 100.
The baud rate generation circuit 153 generates the transmission clock TCK and the reception clock RCK based on the internal clock SCLK according to the baud rate setting data written in the baud rate register 152. The transmission shift register 160 performs a transmission operation based on the transmission clock TCK, and the reception shift register 166 performs a reception data sampling operation based on the reception clock RCK.
In the case of the present embodiment, the maximum number of commands that may be transmitted in the timer interrupt process executed at intervals of 4 ms (more specifically, the total number of frames including all commands to be transmitted × frame bits) Set the baud rate within the interval of interrupt processing. For example, as will be described later, it is assumed that a maximum of seven payout control commands (7 frames including 1-byte command data) are transmitted to the payout control unit 53 in one interrupt process, and a maximum of 15 effect controls. Assuming that a command (2 frames × 15 = 30 frames for a 2-byte production control command) is transmitted to the production control unit 51, transmission of 37 frames (370 bits if 1 frame = 10 bits) is within 4 ms. Set the baud rate as possible.

The communication setting register 159 is a register for setting the communication format and operation mode of the serial communication circuit 112.
For example, a bit that temporarily disables the transmission function, a bit that temporarily disables the reception function, a bit that selects the normal mode and the FIFO mode as the operation mode, a bit that sets the data length of transmission / reception data, and a parity function Bits for setting whether to use or not, bits for setting parity type (even parity / odd parity), and the like are prepared.
In this embodiment, the FIFO mode is selected as the operation mode.

The command register 154 is a register for clearing the serial communication circuit 112 by software and transmitting a break code (“0” of one frame or more).
When the main control CPU 100 writes a predetermined bit of the command register 154, the serial communication circuit 112 clears the transmission FIFO 161, clears the reception FIFO 164, transmits a break code, and the like.

The transmission trigger level setting register 155 is a register for setting the trigger level of the transmission FIFO 161. The main control CPU 100 can set a trigger level of 1 byte to 64 bytes from “00h” to “3Fh” using 6 bits in the transmission trigger level setting register 155.
When the number of bytes of one or a plurality of transmission data written in the transmission FIFO 161 is less than the number of bytes as a set trigger level, a write status flag indicating a transmission data writing status is described in a status register 156 described later. Set to indicate the empty state of the transmit FIFO 161.

The status register 156 is a register for confirming the transmission / reception state of the serial communication circuit 112. The status register 156 includes a bit indicating a transmission completion flag, a bit indicating various states in the normal mode, and a bit indicating various states in the FIFO mode.
The transmission completion flag is a flag that is set when the data transfer from the transmission shift register 160 is completed in both the normal mode and the FIFO mode.
Bits indicating various states in the normal mode include a bit indicating transmission data empty, a bit indicating a reception data full flag set depending on whether or not the value of the reception shift register 166 has been transferred to the reception FIFO 164, and reception Bit indicating noise flag according to noise detection in the system, bit indicating overrun flag according to detection of overrun in the reception system, bit indicating break code detection flag according to detection of break code in the reception system, stop code There are a bit indicating a framing error flag and a bit indicating a parity error flag in accordance with the presence or absence of detection.
The bits indicating the various states of the FIFO mode include a bit indicating the transmission FIFO trigger level, a bit indicating the reception FIFO trigger level, a bit indicating the reception FIFO timeout error flag, and the reception data at the head of the reception FIFO 164 are a break code and a framing error , A bit indicating a reception FIFO head error flag that is set in the case of a parity error, and a reception FIFO data error flag that is set when reception data including a break code, a framing error, and a parity error exists in the reception FIFO 164 , A bit indicating a reception FIFO noise flag that is set when there is reception data including noise in the reception FIFO 164, and a reception F that is set when there is at least one reception data in the reception FIFO There is a bit that indicates the FO ready.

The transmission completion flag set in the status register 156 is a flag that is set to “1” when the data transfer from the transmission shift register 160 is completed. When transmission data is written to the data register 151, it is set to “0”. The transmission completion flag can be set to “1” by writing “1” to a predetermined bit of the command register 154. However, in this case, if there is data being transmitted, it is set to “1” after the transmission is completed.
The bit indicating the transmission FIFO trigger level is set to “1” when the data written in the transmission FIFO 161 becomes less than the transmission FIFO trigger level set in the transmission trigger level setting register 155. The bit indicating the transmission FIFO trigger level being “1” indicates that there is an empty space in the transmission FIFO 161 that has not reached the transmission FIFO trigger level. When the transmission data is transferred to the transmission FIFO 161 and the stored data amount becomes equal to or higher than the transmission FIFO trigger level, it is set to “0”.

  The FIFO status register 157 is a register for confirming the reception state in the FIFO mode. The FIFO status register 157 indicates that the received data at the head of the reception FIFO 164 includes a bit indicating noise, a bit indicating a break code, a bit indicating a framing error, and a parity error. There are bits to show.

The interrupt control register 158 is a register for setting permission / prohibition of the interrupt request of the serial communication circuit 112.
A part of the interrupt control register 158 is used for a bit for setting the number of bytes of the trigger level of the reception FIFO 164.

<5. Control processing of embodiment>
[5-1: Main processing]

Hereinafter, the control process of this Embodiment is demonstrated.
FIG. 7 is a flowchart showing main processing of the main control unit 50.
The main process is started when a system reset occurs and when a user reset occurs.

  In the main process on the main control side shown in FIG. 7, the main control CPU 100 first sets itself to an interrupt disabled state (interrupt mode 2) in step S11. In subsequent step S12, the internal register values including the respective units in the main control unit 50 are initialized (various initial settings).

Next, the main control CPU 100 activates the hard random number circuit in step S13. That is, the random number circuit 104 is activated.
Then, the main control CPU 100 reads a RAM clear signal in step S14. The RAM clear signal means an output signal of a RAM clear switch that is input via an input port (not shown).

Further, the main control CPU 100 performs a start-up waiting process for the peripheral board in step S15. The peripheral board here means a board that is communicably connected to the main controller 50, such as an effect control board 51, a liquid crystal control board 52, and the like.
Note that the standby time for waiting for activation is appropriately determined based on the program configuration and circuit configuration of the peripheral board.

The main control CPU 100 waits until the power supply abnormality signal is turned off in step S16 after performing the activation waiting process in step S15. The power supply abnormality signal is a signal input from the power supply board 58 through an input port (not shown), and “1” represents an ON state (that is, an abnormal state) and “0” represents an OFF state (that is, a normal state). .
Since a sufficient waiting time is ensured in the waiting process of the previous step S15, the waiting in step S16 does not actually occur.
If it is confirmed that the power supply abnormality signal is in the OFF state, the main control CPU 100 transmits a standby screen display command to the peripheral board in step S17.

  Next, the main control CPU 100 stands by until the power-on signal is turned on in step S18. The power-on signal is input from the payout control board 53, and “1” represents an ON state (that is, a power-on state) and “0” represents an OFF state (that is, a power-off state).

  In response to confirming that the power-on signal is in the ON state, the main control CPU 100 determines the state (ON / OFF) of the RAM clear signal in step S19. The RAM clear signal is a signal that determines whether or not to initialize (zero clear) the entire area of the main control RAM 102. The RAM clear signal usually has a value corresponding to the ON / OFF state of the RAM clear switch (operated by a pachinko store clerk). At the time of recovery from the power failure state, since the RAM clear switch is in the OFF state, the RAM clear signal is in the OFF state. If the RAM clear switch is in the ON state, the RAM clear signal is also in the ON state.

When the RAM clear signal is in the ON state, the main control CPU 100 advances the process from step S19 to S22, and performs zero clear of all areas of the main control RAM 102 (RAM initialization). In the RAM initialization, only a predetermined use area in the main control RAM 102 may be cleared to zero.
Subsequently, in step S23, the main control CPU 100 transmits a “RAM clear display command” for notifying that the main control RAM 102 is cleared to zero to the peripheral board as an initialization command. In step S24, for example, 30s is stored in the RAM clear notification timer as a time for notifying that the RAM is cleared (RAM clear information setting process).
The operation state of the pachinko gaming machine 1 is returned to the initial state by the processing of steps S22 to S24 described above.
The main control CPU 100 advances the process to step S25 in response to executing the process of step S24.

If it is determined in step S19 that the RAM clear signal is not in the ON state, the main control CPU 100 determines whether the backup data in the main control RAM 102 is valid in step S20. Whether the backup data is valid is determined based on a so-called backup flag or checksum value. The backup data is stored in the main control RAM 102 by the backup process executed in the power supply abnormality check process (S51) of FIG.
If it is determined in step S20 that the backup data is not valid, the main control CPU 100 proceeds to step S22 described above to perform the RAM initialization process, and then transmits a command for RAM clear display command transmission ( S23) and RAM clear information setting processing (S24) are executed to return the operation state of the pachinko gaming machine 1 to the initial state.

On the other hand, when the determination result that the backup data is valid is obtained in step S20, the main control CPU 100 transmits a command for performing power failure recovery to the peripheral board in step S21.
The main control CPU 100 advances the process to step S25 in response to performing the command transmission process of step S21.
Here, the process of step S21 corresponds to a backup recovery process for performing a recovery control based on the backup data.

In step S25, the main control CPU 100 initializes the CTC (timer circuit 106) in order to start the timer interrupt operation, and sets the main control CPU 100 to the interrupt permitting state.
Next, the main control CPU 100 performs processing for starting the WDT circuit 120 in step S26. That is, the WDT circuit 120 is activated by setting values for instructing the operation permission and the timeout time. As a result, in the WDT circuit 120, the clock is selected according to the timeout time and the count operation is started.
In this example, 4 ms is set as the timeout time, for example.

After starting the WDT circuit 120 in step S26, the main control CPU 100 repeats the interrupt disabled state and the interrupt permitted state until an interrupt occurs as the processing of steps S27, S28, and S29. Various random number update processing is executed.
Specifically, in the various random number update processing in step S28, the random number used for changing the initial value (start value) of various random numbers used for the special symbol variation display and the normal symbol variation display, and the variation pattern are used. The random number for the variation pattern to be updated is updated. That is, a special symbol initial value random number for changing an initial value of a special symbol random number, a normal symbol initial value random number for changing an initial value of a normal symbol random number, a variation pattern random number 1, and a variation pattern Random number 2.
Here, the special symbol random number is a random number used for the determination of probability variation / non-probability variation, and the normal symbol random number is a random number used for determination of whether or not to release the ordinary electric accessory (so-called electric Chu). . The special symbol random number, the special symbol initial value random number, the ordinary symbol random number, the ordinary symbol initial value random number, the variation pattern random number 1, and the variation pattern random number 2 are software random numbers counted by the program.

The main control RAM 102 has storage areas for storing the count values of these software random numbers. These storage areas can be said to be counters for generating corresponding random numbers in software.
In the various random number update processing in step S28, the counter for generating the above-described special symbol initial value random number, normal symbol initial value random number, variation pattern random number 1, and variation pattern random number 2 is performed. For example, if the numerical value range that can be taken as the counter for the variation pattern random number 1 is 0 to 238, the value is acquired from the storage area for generating the value of the variation pattern random number 1 in the main control RAM 102, and the acquired value is 1 Are stored in the original storage area. At this time, if the result of adding 1 to the acquired value is 239, 0 is stored in the original storage area. The update process is similarly performed for the other random number 2 for the variation pattern, the initial value random number for the special symbol, and the initial value random number for the normal symbol.
The main control CPU 100 repeatedly executes the various random number update processes described above by the loop process in steps S27 to S29 except during the timer interrupt process that is executed intermittently.
The loop process of steps S27 to S29 is an infinite loop process in which a predetermined process is repeatedly executed except for a period for executing the timer interrupt process.

[5-2: Timer interrupt processing]

Next, a timer interrupt process (hereinafter referred to as “main control timer interrupt process”) of the main control CPU 100 will be described with reference to FIG. The main control timer interrupt process is activated by interruption every predetermined time (about 4 ms) from the CTC, and is interrupted and executed during execution of the main process described above. Specifically, the main control timer interrupt process is executed after the interrupt permission state is set in step S29.

  When a timer interrupt occurs, the main control CPU 100 saves the contents of the register in the stack area, and first performs a power supply abnormality check process for monitoring the power supply state from the power supply board 58 in step S51 of FIG. In this power failure check process, a power failure signal from the power supply board 58 is mainly monitored. Here, for example, when an abnormality such as a power interruption occurs, backup processing for storing predetermined game information at the time of power interruption in the main control RAM 102 is performed so that the game can be restored without any trouble when the power is restored. .

  In step S52, the main control CPU 100 performs a timer management process for managing a timer used for gaming operation control. Timer values of various timers (for example, special symbol accessory operation timer) used for game operation control of the pachinko gaming machine 1 are managed (updated) by this processing.

In step S53, the main control CPU 100 performs input management processing. In this input management process, information detected by various sensors provided in the pachinko gaming machine 1 is stored in the winning counter. Here, the detection information by the various sensors includes, for example, an upper start opening sensor 71, a lower start opening sensor 72, a gate sensor (ordinary symbol start opening sensor) 73, a first big prize opening sensor 75, and a second big prize opening sensor. 76, ON / OFF information (winning detection information) of a switch signal output from a winning detection switch such as the general winning opening sensor 74.
Through the processing in step S53, it is monitored for each interrupt whether or not a winning is detected (winning has occurred) at each winning opening. The “winning counter” is a counter that counts the number of game balls (winning balls) won in each winning opening. In the present embodiment, a plurality of winning counters corresponding to the types of prize balls are provided in a predetermined area of the main control RAM 102.
Further, in this input management process, it is also monitored whether or not there is an illegal prize based on whether or not the detection information from the prize detection switch has won a prize during a period in which the prize should be allowed. For example, when the first and second big prize opening sensors 75 and 76 detect a game ball even though the big hit game is not being played, the prize detection information is invalidated by invalidating the prize detection information. In order to notify the outside of the fact, a predetermined error process is performed in an error management process in step S55 described later.
Details of the process in step S53 will be described later.

In step S54, the main control CPU 100 performs a timer interrupt random number management process for periodically updating the software random number. In this periodic random number update process, update of the random number 1 for the fluctuation pattern and the random number 2 for the fluctuation pattern is not executed. Perform the update.
Here, the update process for the special symbol random number and the normal symbol random number includes a process of incrementing the corresponding counter value of the main control RAM 102 for each interrupt, and the count value becomes the upper limit value of the counter. A process of changing the start value (initial value) of the counter is performed every time it reaches (that is, every time the counter makes one round). For example, the value of the special symbol random number counter is updated (added by +1) within a predetermined range, and each time the special symbol random number counter makes one round, the value of the special symbol initial value random number counter is read and the value is Store in special design random number counter. The normal symbol random number is similarly processed using the normal symbol initial value random number.
As a result, the count values of the special symbol random numbers and the normal symbol random numbers become random while the update cycle is constant.

In step S55, the main control CPU 100 performs an error management process for monitoring whether or not there is an abnormality in the gaming operation state. In this error management process, as abnormalities in the game operation state, these operational abnormalities (errors) occur, for example, by monitoring whether or not there is a disconnection between the boards or whether there has been an illegal prize. If so, predetermined error processing corresponding to the error is performed.
As the error processing, for example, the progress of a predetermined game operation (for example, a game ball payout operation or a game ball launch operation) is stopped, or an error notification command is transmitted to the effect control unit 51, To notify that an error has occurred.

In step S56, the main control CPU 100 performs prize ball management processing. In this prize ball management process, the data stored in the input management process in step S53 is grasped, the above-mentioned prize counter is confirmed, and if there is a prize, a payout control command for designating the number of prize balls is issued. Transmit to the substrate 53.
Upon receiving this payout control command, the payout control board 53 controls the game ball payout device 55 to perform a payout operation for the designated number of prize balls. Thereby, the number of winning balls corresponding to each winning opening is paid out. The number of winning balls corresponding to a winning opening is the predetermined number of winning balls per winning ball set for each winning opening × the number of winning balls corresponding to the value of the winning counter.
Details of the processing in step S56 will be described later.

  In step S57, the main control CPU 100 performs normal symbol management processing. In this normal symbol management process, a lottery per auxiliary in the normal symbol variation display is performed, and based on the lottery result, the variation pattern of the normal symbol and the stop display mode of the normal symbol are determined, or the blinking is repeated every predetermined time. Create symbol data (data for LED blinking display during normal symbol variation), or create data for stop display (data for LED blinking display during normal symbol stop display) if normal symbol is not varying Or

  In step S <b> 58, the main control CPU 100 performs a normal electric accessory management process. In this ordinary electric accessory management process, generation of an excitation signal for solenoid control for the ordinary electric accessory solenoid 77 and its data (solenoid control data) based on the lottery result of the auxiliary symbol lottery in the normal symbol management process in step S57. Set up. Based on the data set here, an excitation signal is output to the ordinary electric utility solenoid 77 in a solenoid management process in step S64 described later, whereby the operation of the movable blade piece 42b is controlled.

In step S59, the main control CPU 100 performs special symbol management processing. In this special symbol management process, the big hit lottery in the special symbol variation display is mainly performed, and based on the lottery result, the variation pattern of the special symbol (look-ahead variation pattern, variation pattern at the start of variation), the special stop symbol, etc. decide.
In step S60, the main control CPU 100 performs a special electric accessory management process. In this special electric utility management process, when the big hit lottery result is “big hit” or “small win”, a setting process necessary to execute and control the hit game corresponding to the win is performed.

In step S61, the main control CPU 100 performs a right-handed notification information management process. In this right-handed notification information management process, for example, a right-handed instruction is given in situations where right-handed is advantageous, such as when the first and second big prize winning holes 45a and 46a are opened or when the movable blade piece 42b is driven. A process for making a “launch position guidance effect (right-handed notification effect)” for performing the notification appears. Specifically, the right-handed instruction is an effect operation instructing the player to aim at the right game area 3c. For example, an image prompting the player to “right-hand” is displayed on the main liquid crystal display device 32M. Or a right-handed message sound is generated from the speaker 25.
When a right-handed notification effect is performed, in this right-handed notification information management process, a “right-handed instruction command” instructing execution of a right-handed notification effect is transmitted to the effect control unit 51 as an effect control command. Then, the production control unit 51 performs execution control of right-handed notification using an image or sound.

  In step S62, the main control CPU 100 performs LED management processing. This LED management process is a process of outputting display data for normal symbol display and first and second special symbol displays to the symbol display unit 33. By this processing, normal symbol and special symbol change display and stop display are performed. The normal symbol display data created in the normal symbol management process in step S57 and the special symbol display data created in the special symbol display data update process in the special symbol management process in step S59 are the LED management process. Is output.

  In step S63, the main control CPU 100 performs an external terminal management process. In this external terminal management process, the operation state information of the pachinko gaming machine 1 is output to an external device such as a hall computer or an island lamp through the frame external terminal board 57. The operating state information includes that a big hit game has occurred (condition device has been activated), that a small hit game has occurred, that a symbol variation display has been executed (a special symbol variation display game has started or ended) , Information such as winning information (information indicating that the player has won a winning opening or a big winning opening and information on the number of winning balls) is included.

  In step S64, the main control CPU 100 performs solenoid management processing. In this solenoid management process, an excitation signal output process for the ordinary electric accessory solenoid 77 based on the solenoid control data created in the ordinary electric accessory management process in step S58, or a special electric accessory management process in step S60. Excitation signal output processing for the first and second big prize opening solenoids 78 and 79 based on the solenoid control data is performed. Thereby, the movable wing piece 42b and the open doors 45b and 46b operate in a predetermined pattern, and the lower start port 42a and the big winning ports 45a and 46b are opened and closed.

After completing the above steps S51 to S64, the main control CPU 100 restores the saved register contents and sets the interrupt permitted state in step S65. As a result, the timer interrupt process is terminated, the process returns to the main process on the main control side in FIG. 6 before the interruption, and the loop process of steps S27 to S29 is performed until the next timer interruption occurs.

[5-3: Processing related to command transmission]

Processing related to command transmission such as payout control command transmission and effect control command transmission performed in the above-described main control timer interrupt processing for each predetermined time will be described.
First, the payout control command transmission will be described.
Processing relating to the payout control of prize balls is mainly performed as input management processing in step S53 and prize ball management processing in step S56 in FIG.

The input management process in step S53 will be described in detail with reference to FIG.
In step S5301 of FIG. 9, the main control CPU 100 acquires level data of each input port, creates edge data based on the level data, and stores it in the work area. That is, this process includes an upper start opening sensor 71, a lower start opening sensor 72, a gate sensor (normal symbol start opening sensor) 73, a first large winning opening sensor 75, a second large winning opening sensor 76, a general winning opening sensor 74, and the like. This is processing for confirming ON / OFF information (winning detection information) of the switch signal output from the winning detection switch. The edge data is the level difference data of L and H of the detection signal for each of these sensors, that is, the edge data is data indicating the presence of detection.

  In step S5302, the main control CPU 100 performs a winning invalidation process. Here, for example, a process of detecting an illegal winning with respect to the upper start opening 41, the lower start opening 42a, the first big winning opening 45a, the second big winning opening 46a, and the like is performed.

  In step S5303, the main control CPU 100 confirms the presence or absence of edge data. If the edge data is not stored in step S5301 described above, the process ends because there is no winning.

If edge data exists, the process advances to step S5304 to increment the winning counter corresponding to each number of winning balls by one.
As the winning counter, a plurality of winning counters corresponding to the types of the number of winning balls are provided. For example, assume that the number of prize balls is determined as follows.
・ Upper start opening 41 and lower start opening 42a: 3 prize balls ・ General prize opening 43: Upper left prize opening, lower left prize opening, right prize opening all 10 prize balls ・ First big prize opening 45a: 11 prizes Ball / second big prize opening 46a: 15 prize balls In such a case, four prize counters (NCT1, NCT2, NCT3, corresponding to the types of 3, 10, 11, and 15 prize balls) NCT4) is provided.
In step S5304, a count value is added to each of the four winning counters according to the number of edge data.
Although it is an extreme example for explanation to the last, there is a game in all of the upper start opening 41, the lower start opening 42a, the three general winning openings 43, 43, 43, the first big winning opening 45a, and the second big winning opening 46a. Suppose a ball enters at the same time. In this case, the winning counter NCT1 corresponding to the winning opening of three prize balls is +2, the winning counter CT2 corresponding to the winning opening of ten winning balls is +3, and the winning counter CT3 corresponding to the winning opening of eleven prize balls is obtained. Is incremented by 1, and the winning counter CT4 corresponding to the winning opening of 15 prize balls is incremented by 1.

The processing of the winning counter for payout control is as described above, but the number of winning balls for each winning mouth is also notified to the hall computer. This is because the hall computer can grasp the number of prize balls in real time even when the payout is delayed due to, for example, a ball jam.
For this purpose, in step S5305, the number of winning balls corresponding to the winning winning opening is added to the winning ball number counter. In step S5306, if the added value exceeds the maximum value, the addition result is changed to the maximum value. In step S5307, the addition result is set in the work area.
The value of the prize ball number counter is transmitted to the hall computer in step S63 of FIG.

  As described above, in the input management process, with respect to a winning ball, the winning ball counter is incremented in response to the detection of a ball entering the winning opening.

The prize ball management process in step S56 of FIG. 8 is performed as shown in FIG.
In step S5601, the main control CPU 100 sets the total number of types of winning counters in the variable N. When four winning counters (NCT1, NCT2, NCT3, NCT4) are provided as in the above example, N = 4.
In step S5602, the main control CPU 100 sets the loop control variable X = 1.

In step S5603, the main control CPU 100 confirms the value of the winning counter NCT (X). Therefore, first, the value of the winning counter NCT1 corresponding to the winning opening of three winning balls is confirmed.
If the winning counter NCT1 = 0, no payout control command for three prize balls is generated, and the process proceeds to step S5608.
If the winning counter NCT1 ≠ 0, one or more three winning ball payout control commands are generated. In this case, the main control CPU 100 proceeds to step S5604 and generates payout control command data for the number of prize balls R (X). The number of winning balls R1 = 3. That is, a payout control command for three prize balls is generated. In step S5605, command transmission processing (described later in FIG. 11) is performed.

The main control CPU 100 decrements the value of the winning counter NCT (X) in step S5606, and checks whether or not the winning counter NCT (X) = 0 in step S5607. If it is “0”, processing of the payout control command for the winning counter NCT (X) has already been completed, and the process proceeds to step S5608. On the other hand, if it is not “0”, the process returns to step S5604. That is, as many payout control commands as the number of winning counters NCT (X) are generated.
For example, if the winning counter NCT1 = 2 at the start of the winning ball management process, first, a payout control command for three winning balls is generated in step S5604. Thereafter, the decrement in step S5606 results in a winning counter NCT1 = 1. In this case, the process returns to step S5604 to generate a payout control command for three prize balls again, and a command transmission process is performed in step S5605.
Thereafter, the winning counter NCT1 = 0 is set by decrementing in step S5606, and the process proceeds from step S5607 to S5608.

In step S5608, it is confirmed whether or not the loop control variable X = N. If X = N is not satisfied, the loop control variable X is incremented in step S5609, and the process returns to step S5603. That is, the processing of steps S5603 to S5607 is performed on the winning counter NTC2 in the same manner as described above. In this case, if the value of the winning counter NCT2 is “1” or more, one or more payout control commands for five prize balls are generated, and command transmission processing is performed.
Thereafter, the same processing is performed for the winning counters NCT3 and NCT4.
As described above, a payout control command for designating the number of prize balls corresponding to each prize ball indicated by the four winning counters (NCT1, NCT2, NCT3, NCT4) is generated and command transmission processing is performed.

At the time of step S5605 described above, the main control CPU 100 calls and executes a command transmission process as shown in FIG. 11A or FIG. 11B.
In the case of FIG. 11A, the main control CPU 100 confirms transmission capability in the serial communication circuit 112 in step S201. In this case, a necessary flag of the status register 156 of the serial communication circuit 112 operating in the FIFO mode is confirmed. For example, a bit indicating the transmission FIFO trigger level is checked to check whether there is a vacancy in the transmission FIFO 161. Further, it may be confirmed whether or not an error that hinders command transmission has occurred.
For example, if the transmission FIFO trigger level is set to the maximum 64 bytes, if the bit indicating the transmission FIFO trigger level is “0”, the payout control command is transferred to the data register 151. However, it cannot be transferred to the transmission FIFO 161. In such a case, the process returns from step S202 to S201 and waits. However, in practice, the transmission FIFO trigger level may be set to 1 byte, 2 bytes, or the like, and the above is not assumed at first.
When transmission is possible (for example, the bit indicating the transmission FIFO trigger level is “1”), the process proceeds to step S 203, and the payout control command is written in the data register 151.

The payout control command is a command for instructing the payout control unit 53 of the number of prize balls, and is composed of 8 bits (1 byte).
Since the maximum number of award balls in a pachinko machine is 15, 4 bits become award ball information of 0 to 15, and the remaining 4 bits are used for unused or error information.
In step S203, this 1-byte payout control command is written in the data register 151.
In the serial communication circuit 112, the payout control command written in the data register 151 is transferred to the transmission FIFO 161, transferred from the transmission FIFO 161 to the transmission shift register 160, and serial transmission to the payout control unit 53 is executed.

Here, as described above, consider that the transmission FIFO 161 has a capacity of 64 bytes. Then, when the payout control command is transmitted, it can be said that the fact that there is no space in the transmission FIFO 161 does not actually occur.
For example, as shown in the above example, the winning opening for generating a winning ball is the upper starting opening 41, the lower starting opening 42a, the three general winning openings 43, 43, 43, the first large winning opening 45a, and the second large winning opening 46a. Suppose that it is a piece. The payout control command has an 8-bit (1 byte) structure. Then, at the maximum, the number of payout control commands transmitted in one interrupt process is 7, that is, 7 bytes.
Even if one payout control command is transmitted twice, it is only 14 bytes.

In this case, in actuality, even if the payout control command for all prize balls detected at that time is transmitted in the course of one timer interruption process, the transmission FIFO 161 will become full. Absent.
Therefore, even if processing for confirming the availability of the transmission FIFO 161 is performed as the processing for confirming the transmission capability in step S201, it can be said that waiting in step S202 (waiting for the availability of the transmission FIFO 161) does not actually occur. Therefore, the command transmission process can be executed efficiently.

Furthermore, if the process for confirming the transmission capability in step S201 is a process that only confirms the availability of the transmission FIFO 161 (when no other error confirmation is performed for transmission), the processes in steps S201 and S202 are unnecessary in the first place. It can also be.
The process of FIG. 11B is an example in which transmission confirmation is not performed. For example, the main control CPU 100 does not perform processing for confirming a bit indicating the transmission FIFO trigger level of the status register 156. The main control CPU 100 executes the command transmission process only by writing a payout control command in the data register 151 in step S251.
In response to this, the serial communication circuit 112 transfers the payout control command written in the data register 151 to the transmission FIFO 161, transfers it from the transmission FIFO 161 to the transmission shift register 160, and executes serial transmission to the payout control unit 53. .
According to the processing of FIG. 11B, the payout control command transmission processing is further streamlined.

Subsequently, the process related to the control command performed in the main control timer interrupt process performed as the scheduled process as shown in FIG. 8 will be described in addition to the payout control command and the effect control command.
In the course of the main control timer interrupt process of FIG. 8 described above, the main control unit 50 may transmit a power-off command, for example, in a power supply abnormality check process (S51). Further, a control command related to random number abnormality may be transmitted in the timer interrupt random number management process (S54). In addition, a control command related to an error may be transmitted to the effect control unit 51 (and the liquid crystal control board 52 via the effect control unit 51) or the payout control unit 53 in the error management process (S55). In addition, a payout control command may be transmitted to the payout control unit 53 in the prize ball management process (S56). In addition, control commands related to effects and display may be transmitted to the effect control unit 51 in the special symbol management process (S59), the special electric accessory management process (S60), and the right-handed notification information management process (S61).
However, the number of control commands to be transmitted in one main control timer interrupt process varies depending on the model of the pachinko gaming machine, but is a maximum of 10 to 15 commands.

  In these cases, when the condition for command transmission occurs, the main control CPU 100 generates command data according to the generation condition as step S101 shown in FIG. In step S102, the command transmission process is called.

For example, the main control CPU 100 calls and executes a command transmission process as shown in FIG.
In the case of the example of FIG. 13, the main control CPU 100 confirms transmission capability in the serial communication circuit 112 in step S <b> 301. As in step S201 of FIG. 11 described above, each flag of the status register 156 of the serial communication circuit 112 operating in the FIFO mode is confirmed. For example, a bit indicating the transmission FIFO trigger level is checked to check whether there is a vacancy in the transmission FIFO 161. Further, it may be confirmed whether or not an error that hinders command transmission has occurred.
If the bit indicating the transmission FIFO trigger level is “0”, even if a control command is transferred to the data register 151, it cannot be transferred to the transmission FIFO 161. In such a case, the process returns from step S302 to S301 and waits.
When transmission is possible (for example, the bit indicating the transmission FIFO trigger level is “1”), the process proceeds to step S303, and the upper byte of command data is written in the data register 151.
In addition, the main control CPU 100 confirms transmission again in step S304. If standby is required, the process waits as steps S305 → S304. When it is confirmed that transmission is possible, the process proceeds to step S306, and the lower byte of the command data is written in the data register 151.

  In the serial communication circuit 112, the control command written in the data register 151 as described above is sequentially transferred to the transmission FIFO 161, transferred from the transmission FIFO 161 to the transmission shift register 160, and serial transmission to the effect control unit 51 is executed, for example. To do.

As described above, the effect control command for the effect control unit 51 has a 2-byte configuration including a 1-byte length mode (MODE) and an event (EVENT) that is also 1-byte length. In the case of such a 2-byte configuration, the processing of steps S 3 03 and S 3 06 means that the upper byte and the lower byte are written in the data register 151, respectively.
If the payout control command for dispensing the controller 53 as described above has to be 1 byte configuration, when the commands transmitted the entire command data of the one byte as described above in step S 3 03 of FIG. 11 The command transmission process may be terminated by writing to the data register 151.

Here, it is considered that the transmission FIFO 161 has a capacity of 64 bytes as described above. Then, when the control command is transmitted, it can be said that the fact that there is no space in the transmission FIFO 161 does not actually occur.
The maximum number of control commands to be transmitted in one main control timer interrupt process is 10 to 15 commands as described above. Even if all commands have a 2-byte configuration, the maximum command data to be transmitted is 30 bytes of 2 × 15, which is about half the capacity of the 64-byte transmission FIFO 161.

Therefore, in practice, command data is not written as the capacity of the transmission FIFO 161 becomes full in the course of one timer interruption process.
Therefore, even if processing for confirming the availability of the transmission FIFO 161 is performed as the processing for confirming the transmission capability in steps S301 and S304, there is actually no standby (waiting for the availability of the transmission FIFO 161) in step S302 or S305. I can say that. Therefore, the command transmission process can be executed efficiently.

Furthermore, if the process of confirming the transmission capability in steps S301 and S304 is a process that only confirms the availability of the transmission FIFO 161 (when no other error confirmation or the like is performed regarding transmission), steps S301, S302, and The processing of S304 and S305 can be made unnecessary.
The process of FIG. 14 is an example in which transmission confirmation is not performed. For example, the main control CPU 100 does not perform processing for confirming a bit indicating the transmission FIFO trigger level of the status register 156. As the command transmission process, the main control CPU 100 executes only writing the upper byte of the control command in the data register 151 in step S351 and writing the lower byte of the control command in the data register 151 in step S352.
In accordance with these processes, the serial communication circuit 112 sequentially transfers the upper byte and lower byte of the control command written in the data register 151 to the transmission FIFO 161, and from the transmission FIFO 161 to the transmission shift register 160, thereby giving out control. Serial transmission to the unit 53 is executed.
According to the process of FIG. 14, the command transmission process is further streamlined.

<6. Summary and Modification>

As described above, in the pachinko gaming machine 1 according to the present embodiment, the efficiency of the control process of the main control unit 50 and the processing burden caused by the configuration and each process described with reference to FIGS. Mitigation is realized.

The pachinko gaming machine 1 according to the present embodiment includes n (for example, seven) winning holes, and gives a game value in response to a game ball entering the winning hole. Then, the overall control of the gaming operation is performed, and a main control unit 50 (main control means) that outputs a control command related to the gaming operation, and m bits (for example, 8) for designating the number of winning balls from the main control unit 50. A payout control unit 53 (payout control means) for assigning a game value based on a payout control command of (bit) and a winning ball entrance detection signal provided corresponding to each winning opening, and the main control And a plurality of sensor means (for example, an upper start opening sensor 71, a lower start opening sensor 72, a first large winning opening sensor 75, a second large winning opening sensor 76, and a general winning opening sensor 74).
The main control unit 50 receives a transmission FIFO 161 (transmission data storage unit) having a capacity of at least (n × m: for example, 7 × 8) bits (for example, a capacity of 64 bytes) and transmission data transferred from the transmission FIFO 161. A serial communication circuit 112 having a transmission shift register 160 for serial transmission output is provided.
Then, the main control unit 50 including the serial communication circuit 112 performs one or more payouts corresponding to detection signals from the plurality of sensor means for each prize ball management process executed at predetermined time intervals such as timer interruption. A control command is written in the transmission FIFO 161, and the payout control commands written in the transmission FIFO 161 are sequentially transferred to the transmission shift register 160 and serially transmitted to the payout control unit 53.
As described above, the transmission FIFO 161 having a sufficient capacity of (n × m) bits or more is provided in the serial communication circuit 112, so that it is assumed that a game ball has entered all the winning holes at the same time. A payout control command corresponding to each entry can be set in the serial communication circuit and transmitted. Therefore, in the payout control command transmission, standby processing such as waiting for the transmission FIFO 161 to be free substantially does not occur, and more efficient processing is realized.

In addition, the pachinko gaming machine 1 according to the present embodiment controls the game operation in an integrated manner and outputs a control command related to the game operation (main control means) and the main control unit 50. Sub-control means (for example, an effect control unit 51) that performs a control operation based on the control command. Further, the maximum value of the number of control commands to be transmitted to the sub-control means in one timed process (main control timer interrupt process) executed by the main control unit 50 at a predetermined interval is x (for example, x = 15), and the bit of the control command When the number is y (for example, y = 16 bits: 2 bytes), the main control means includes a transmission FIFO 161 (transmission data storage unit) having a capacity of at least (x × y) bits (for example, a capacity of 64 bytes). ) And a transmission shift register 160 that serially transmits and outputs transmission data transferred from the transmission FIFO 161.
The main control unit 50 including the serial communication circuit 112 writes one or a plurality of control commands to be transmitted to the sub-control means in one scheduled processing (for example, main control timer interrupt processing) in the transmission FIFO 161, and The written control commands are sequentially transferred to the transmission shift register 160 and serially transmitted to the sub-control means.
Assuming that the transmission FIFO 161 having a sufficient capacity of (x × y) bits or more is provided in the serial communication circuit 112 in this way, it is assumed that the maximum number of control command transmissions occur in one timed process. However, each control command can be set and transmitted to the serial communication circuit without any problem. Therefore, in the command transmission, the standby process such as waiting for the transmission FIFO 161 to be free substantially does not occur, and an efficient process is realized.

  Further, by adopting a queue structure as a FIFO memory, for example, as a transmission data buffer (transmission data storage unit), the transmission data is sequentially transferred to the transmission shift register 160 as the transmission data is written. No complicated control is required for transfer.

  Further, assuming the effect control unit 51 having the most control command transmission opportunities as the sub control means, that is, assuming the maximum number x of the number of effect control commands, the usefulness of the present embodiment is enhanced.

In serial communication circuit 112, a write status flag indicating the transmission data write status to the transmission data storage unit (transmission FIFO 161) is set. That is, this bit indicates the transmission FIFO trigger level in the status register 156.
In this case, the main control CPU 100 writes the control command to the data register 151 (that is, transfers it to the transmission FIFO 161) without performing the write status flag recognition process as shown in FIG. 11B or FIG. It can also be executed. This eliminates the need for confirmation processing at the time of command writing, reduces the processing load, and realizes more efficient processing.

Note that the present invention is not limited to the examples given in the embodiment, and various modifications and application examples are conceivable.
Although the transmission FIFO 161 has been described as an example of the transmission data storage unit that functions as a transmission data buffer, it is not necessarily required to be a FIFO type memory. By preparing a capacity of n × m bits or more, at least a waiting time is not required for writing the payout control command to the serial communication circuit 112, and the processing is executed efficiently.
In addition, although the example in which the payout control command is transmitted in the main control timer interruption process every 4 ms is given, it is not limited thereto. For example, a processing example in which a prize ball flag or a prize ball counter is set in the input management process (S53), is confirmed in the main loop, and a payout control command is transmitted can be considered. For example, all or part of the prize ball management process (S56) is performed between steps S27 and S29 in FIG.

  Further, in the above, an example in which the present invention is applied to a ball game machine such as the pachinko gaming machine 1 has been shown, but the present invention can also be applied to a revolving game machine (so-called slot machine). In other words, the serial transmission method of the present invention can be applied to command transmission for paying out and counting game medals as game value addition and transmission processing of effect control commands.

1 Pachinko machine 2 Front frame 3 Game board 50 Main control board (main control part)
51 Production control board (production control unit)
52 liquid crystal control board 53 payout control board (payout control unit)
54 Launch Control Board 58 Power Supply Board 100 CPU (Main Control CPU)
112 Serial communication circuit

Claims (1)

Main control means for overall control of game operations and outputting control commands related to game operations;
Sub-control means for performing a control operation based on a control command output from the main control means;
With
The main control means includes a main control CPU and performs a series of processes having a generation opportunity of a plurality of control commands as a scheduled process executed at a predetermined interval.
When the maximum value of the number of control commands transmitted by the main control means in one timed process is x and the number of bits of the control command is y, the main control means has at least (x × y) bits or more. A transmission data storage unit having a capacity of, and serial transmission means for serial transmission output of transmission data for each transmission unit transferred from the transmission data storage unit,
One control command is composed of a data amount in which command transmission is completed by transmission of a plurality of transmission units.
The main control means generates a control command each time a command transmission generation condition is met during the scheduled processing, and whether the generated control command can be transmitted from the serial transmission means for each transmission unit. If the data can be transmitted after confirmation, the process is written in the transmission data storage unit, the control commands written in the transmission data storage unit are sequentially transferred to the serial transmission unit, and serially transmitted to the sub-control unit Do a gaming machine.

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